1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/sysbus.h" 25 #include "qemu/timer.h" 26 #include "hw/sparc/sun4m.h" 27 #include "hw/timer/m48t59.h" 28 #include "hw/sparc/sparc32_dma.h" 29 #include "hw/block/fdc.h" 30 #include "sysemu/sysemu.h" 31 #include "net/net.h" 32 #include "hw/boards.h" 33 #include "hw/nvram/openbios_firmware_abi.h" 34 #include "hw/scsi/esp.h" 35 #include "hw/i386/pc.h" 36 #include "hw/isa/isa.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/char/escc.h" 39 #include "hw/empty_slot.h" 40 #include "hw/loader.h" 41 #include "elf.h" 42 #include "sysemu/blockdev.h" 43 #include "trace.h" 44 45 /* 46 * Sun4m architecture was used in the following machines: 47 * 48 * SPARCserver 6xxMP/xx 49 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 50 * SPARCclassic X (4/10) 51 * SPARCstation LX/ZX (4/30) 52 * SPARCstation Voyager 53 * SPARCstation 10/xx, SPARCserver 10/xx 54 * SPARCstation 5, SPARCserver 5 55 * SPARCstation 20/xx, SPARCserver 20 56 * SPARCstation 4 57 * 58 * See for example: http://www.sunhelp.org/faq/sunref1.html 59 */ 60 61 #define KERNEL_LOAD_ADDR 0x00004000 62 #define CMDLINE_ADDR 0x007ff000 63 #define INITRD_LOAD_ADDR 0x00800000 64 #define PROM_SIZE_MAX (1024 * 1024) 65 #define PROM_VADDR 0xffd00000 66 #define PROM_FILENAME "openbios-sparc32" 67 #define CFG_ADDR 0xd00000510ULL 68 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 69 70 #define MAX_CPUS 16 71 #define MAX_PILS 16 72 #define MAX_VSIMMS 4 73 74 #define ESCC_CLOCK 4915200 75 76 struct sun4m_hwdef { 77 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 78 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 79 hwaddr serial_base, fd_base; 80 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 81 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 82 hwaddr bpp_base, dbri_base, sx_base; 83 struct { 84 hwaddr reg_base, vram_base; 85 } vsimm[MAX_VSIMMS]; 86 hwaddr ecc_base; 87 uint64_t max_mem; 88 const char * const default_cpu_model; 89 uint32_t ecc_version; 90 uint32_t iommu_version; 91 uint16_t machine_id; 92 uint8_t nvram_machine_id; 93 }; 94 95 int DMA_get_channel_mode (int nchan) 96 { 97 return 0; 98 } 99 int DMA_read_memory (int nchan, void *buf, int pos, int size) 100 { 101 return 0; 102 } 103 int DMA_write_memory (int nchan, void *buf, int pos, int size) 104 { 105 return 0; 106 } 107 void DMA_hold_DREQ (int nchan) {} 108 void DMA_release_DREQ (int nchan) {} 109 void DMA_schedule(int nchan) {} 110 111 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) 112 { 113 } 114 115 void DMA_register_channel (int nchan, 116 DMA_transfer_handler transfer_handler, 117 void *opaque) 118 { 119 } 120 121 static int fw_cfg_boot_set(void *opaque, const char *boot_device) 122 { 123 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 124 return 0; 125 } 126 127 static void nvram_init(M48t59State *nvram, uint8_t *macaddr, 128 const char *cmdline, const char *boot_devices, 129 ram_addr_t RAM_size, uint32_t kernel_size, 130 int width, int height, int depth, 131 int nvram_machine_id, const char *arch) 132 { 133 unsigned int i; 134 uint32_t start, end; 135 uint8_t image[0x1ff0]; 136 struct OpenBIOS_nvpart_v1 *part_header; 137 138 memset(image, '\0', sizeof(image)); 139 140 start = 0; 141 142 // OpenBIOS nvram variables 143 // Variable partition 144 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 145 part_header->signature = OPENBIOS_PART_SYSTEM; 146 pstrcpy(part_header->name, sizeof(part_header->name), "system"); 147 148 end = start + sizeof(struct OpenBIOS_nvpart_v1); 149 for (i = 0; i < nb_prom_envs; i++) 150 end = OpenBIOS_set_var(image, end, prom_envs[i]); 151 152 // End marker 153 image[end++] = '\0'; 154 155 end = start + ((end - start + 15) & ~15); 156 OpenBIOS_finish_partition(part_header, end - start); 157 158 // free partition 159 start = end; 160 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 161 part_header->signature = OPENBIOS_PART_FREE; 162 pstrcpy(part_header->name, sizeof(part_header->name), "free"); 163 164 end = 0x1fd0; 165 OpenBIOS_finish_partition(part_header, end - start); 166 167 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 168 nvram_machine_id); 169 170 for (i = 0; i < sizeof(image); i++) 171 m48t59_write(nvram, i, image[i]); 172 } 173 174 static DeviceState *slavio_intctl; 175 176 void sun4m_pic_info(Monitor *mon, const QDict *qdict) 177 { 178 if (slavio_intctl) 179 slavio_pic_info(mon, slavio_intctl); 180 } 181 182 void sun4m_irq_info(Monitor *mon, const QDict *qdict) 183 { 184 if (slavio_intctl) 185 slavio_irq_info(mon, slavio_intctl); 186 } 187 188 void cpu_check_irqs(CPUSPARCState *env) 189 { 190 CPUState *cs; 191 192 if (env->pil_in && (env->interrupt_index == 0 || 193 (env->interrupt_index & ~15) == TT_EXTINT)) { 194 unsigned int i; 195 196 for (i = 15; i > 0; i--) { 197 if (env->pil_in & (1 << i)) { 198 int old_interrupt = env->interrupt_index; 199 200 env->interrupt_index = TT_EXTINT | i; 201 if (old_interrupt != env->interrupt_index) { 202 cs = CPU(sparc_env_get_cpu(env)); 203 trace_sun4m_cpu_interrupt(i); 204 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 205 } 206 break; 207 } 208 } 209 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 210 cs = CPU(sparc_env_get_cpu(env)); 211 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 212 env->interrupt_index = 0; 213 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 214 } 215 } 216 217 static void cpu_kick_irq(SPARCCPU *cpu) 218 { 219 CPUSPARCState *env = &cpu->env; 220 CPUState *cs = CPU(cpu); 221 222 cs->halted = 0; 223 cpu_check_irqs(env); 224 qemu_cpu_kick(cs); 225 } 226 227 static void cpu_set_irq(void *opaque, int irq, int level) 228 { 229 SPARCCPU *cpu = opaque; 230 CPUSPARCState *env = &cpu->env; 231 232 if (level) { 233 trace_sun4m_cpu_set_irq_raise(irq); 234 env->pil_in |= 1 << irq; 235 cpu_kick_irq(cpu); 236 } else { 237 trace_sun4m_cpu_set_irq_lower(irq); 238 env->pil_in &= ~(1 << irq); 239 cpu_check_irqs(env); 240 } 241 } 242 243 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 244 { 245 } 246 247 static void main_cpu_reset(void *opaque) 248 { 249 SPARCCPU *cpu = opaque; 250 CPUState *cs = CPU(cpu); 251 252 cpu_reset(cs); 253 cs->halted = 0; 254 } 255 256 static void secondary_cpu_reset(void *opaque) 257 { 258 SPARCCPU *cpu = opaque; 259 CPUState *cs = CPU(cpu); 260 261 cpu_reset(cs); 262 cs->halted = 1; 263 } 264 265 static void cpu_halt_signal(void *opaque, int irq, int level) 266 { 267 if (level && cpu_single_env) { 268 cpu_interrupt(CPU(sparc_env_get_cpu(cpu_single_env)), 269 CPU_INTERRUPT_HALT); 270 } 271 } 272 273 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 274 { 275 return addr - 0xf0000000ULL; 276 } 277 278 static unsigned long sun4m_load_kernel(const char *kernel_filename, 279 const char *initrd_filename, 280 ram_addr_t RAM_size) 281 { 282 int linux_boot; 283 unsigned int i; 284 long initrd_size, kernel_size; 285 uint8_t *ptr; 286 287 linux_boot = (kernel_filename != NULL); 288 289 kernel_size = 0; 290 if (linux_boot) { 291 int bswap_needed; 292 293 #ifdef BSWAP_NEEDED 294 bswap_needed = 1; 295 #else 296 bswap_needed = 0; 297 #endif 298 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 299 NULL, NULL, NULL, 1, ELF_MACHINE, 0); 300 if (kernel_size < 0) 301 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 302 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 303 TARGET_PAGE_SIZE); 304 if (kernel_size < 0) 305 kernel_size = load_image_targphys(kernel_filename, 306 KERNEL_LOAD_ADDR, 307 RAM_size - KERNEL_LOAD_ADDR); 308 if (kernel_size < 0) { 309 fprintf(stderr, "qemu: could not load kernel '%s'\n", 310 kernel_filename); 311 exit(1); 312 } 313 314 /* load initrd */ 315 initrd_size = 0; 316 if (initrd_filename) { 317 initrd_size = load_image_targphys(initrd_filename, 318 INITRD_LOAD_ADDR, 319 RAM_size - INITRD_LOAD_ADDR); 320 if (initrd_size < 0) { 321 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 322 initrd_filename); 323 exit(1); 324 } 325 } 326 if (initrd_size > 0) { 327 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 328 ptr = rom_ptr(KERNEL_LOAD_ADDR + i); 329 if (ldl_p(ptr) == 0x48647253) { // HdrS 330 stl_p(ptr + 16, INITRD_LOAD_ADDR); 331 stl_p(ptr + 20, initrd_size); 332 break; 333 } 334 } 335 } 336 } 337 return kernel_size; 338 } 339 340 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 341 { 342 DeviceState *dev; 343 SysBusDevice *s; 344 345 dev = qdev_create(NULL, "iommu"); 346 qdev_prop_set_uint32(dev, "version", version); 347 qdev_init_nofail(dev); 348 s = SYS_BUS_DEVICE(dev); 349 sysbus_connect_irq(s, 0, irq); 350 sysbus_mmio_map(s, 0, addr); 351 352 return s; 353 } 354 355 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq, 356 void *iommu, qemu_irq *dev_irq, int is_ledma) 357 { 358 DeviceState *dev; 359 SysBusDevice *s; 360 361 dev = qdev_create(NULL, "sparc32_dma"); 362 qdev_prop_set_ptr(dev, "iommu_opaque", iommu); 363 qdev_prop_set_uint32(dev, "is_ledma", is_ledma); 364 qdev_init_nofail(dev); 365 s = SYS_BUS_DEVICE(dev); 366 sysbus_connect_irq(s, 0, parent_irq); 367 *dev_irq = qdev_get_gpio_in(dev, 0); 368 sysbus_mmio_map(s, 0, daddr); 369 370 return s; 371 } 372 373 static void lance_init(NICInfo *nd, hwaddr leaddr, 374 void *dma_opaque, qemu_irq irq) 375 { 376 DeviceState *dev; 377 SysBusDevice *s; 378 qemu_irq reset; 379 380 qemu_check_nic_model(&nd_table[0], "lance"); 381 382 dev = qdev_create(NULL, "lance"); 383 qdev_set_nic_properties(dev, nd); 384 qdev_prop_set_ptr(dev, "dma", dma_opaque); 385 qdev_init_nofail(dev); 386 s = SYS_BUS_DEVICE(dev); 387 sysbus_mmio_map(s, 0, leaddr); 388 sysbus_connect_irq(s, 0, irq); 389 reset = qdev_get_gpio_in(dev, 0); 390 qdev_connect_gpio_out(dma_opaque, 0, reset); 391 } 392 393 static DeviceState *slavio_intctl_init(hwaddr addr, 394 hwaddr addrg, 395 qemu_irq **parent_irq) 396 { 397 DeviceState *dev; 398 SysBusDevice *s; 399 unsigned int i, j; 400 401 dev = qdev_create(NULL, "slavio_intctl"); 402 qdev_init_nofail(dev); 403 404 s = SYS_BUS_DEVICE(dev); 405 406 for (i = 0; i < MAX_CPUS; i++) { 407 for (j = 0; j < MAX_PILS; j++) { 408 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 409 } 410 } 411 sysbus_mmio_map(s, 0, addrg); 412 for (i = 0; i < MAX_CPUS; i++) { 413 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 414 } 415 416 return dev; 417 } 418 419 #define SYS_TIMER_OFFSET 0x10000ULL 420 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 421 422 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 423 qemu_irq *cpu_irqs, unsigned int num_cpus) 424 { 425 DeviceState *dev; 426 SysBusDevice *s; 427 unsigned int i; 428 429 dev = qdev_create(NULL, "slavio_timer"); 430 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 431 qdev_init_nofail(dev); 432 s = SYS_BUS_DEVICE(dev); 433 sysbus_connect_irq(s, 0, master_irq); 434 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 435 436 for (i = 0; i < MAX_CPUS; i++) { 437 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 438 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 439 } 440 } 441 442 static qemu_irq slavio_system_powerdown; 443 444 static void slavio_powerdown_req(Notifier *n, void *opaque) 445 { 446 qemu_irq_raise(slavio_system_powerdown); 447 } 448 449 static Notifier slavio_system_powerdown_notifier = { 450 .notify = slavio_powerdown_req 451 }; 452 453 #define MISC_LEDS 0x01600000 454 #define MISC_CFG 0x01800000 455 #define MISC_DIAG 0x01a00000 456 #define MISC_MDM 0x01b00000 457 #define MISC_SYS 0x01f00000 458 459 static void slavio_misc_init(hwaddr base, 460 hwaddr aux1_base, 461 hwaddr aux2_base, qemu_irq irq, 462 qemu_irq fdc_tc) 463 { 464 DeviceState *dev; 465 SysBusDevice *s; 466 467 dev = qdev_create(NULL, "slavio_misc"); 468 qdev_init_nofail(dev); 469 s = SYS_BUS_DEVICE(dev); 470 if (base) { 471 /* 8 bit registers */ 472 /* Slavio control */ 473 sysbus_mmio_map(s, 0, base + MISC_CFG); 474 /* Diagnostics */ 475 sysbus_mmio_map(s, 1, base + MISC_DIAG); 476 /* Modem control */ 477 sysbus_mmio_map(s, 2, base + MISC_MDM); 478 /* 16 bit registers */ 479 /* ss600mp diag LEDs */ 480 sysbus_mmio_map(s, 3, base + MISC_LEDS); 481 /* 32 bit registers */ 482 /* System control */ 483 sysbus_mmio_map(s, 4, base + MISC_SYS); 484 } 485 if (aux1_base) { 486 /* AUX 1 (Misc System Functions) */ 487 sysbus_mmio_map(s, 5, aux1_base); 488 } 489 if (aux2_base) { 490 /* AUX 2 (Software Powerdown Control) */ 491 sysbus_mmio_map(s, 6, aux2_base); 492 } 493 sysbus_connect_irq(s, 0, irq); 494 sysbus_connect_irq(s, 1, fdc_tc); 495 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 496 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 497 } 498 499 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 500 { 501 DeviceState *dev; 502 SysBusDevice *s; 503 504 dev = qdev_create(NULL, "eccmemctl"); 505 qdev_prop_set_uint32(dev, "version", version); 506 qdev_init_nofail(dev); 507 s = SYS_BUS_DEVICE(dev); 508 sysbus_connect_irq(s, 0, irq); 509 sysbus_mmio_map(s, 0, base); 510 if (version == 0) { // SS-600MP only 511 sysbus_mmio_map(s, 1, base + 0x1000); 512 } 513 } 514 515 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 516 { 517 DeviceState *dev; 518 SysBusDevice *s; 519 520 dev = qdev_create(NULL, "apc"); 521 qdev_init_nofail(dev); 522 s = SYS_BUS_DEVICE(dev); 523 /* Power management (APC) XXX: not a Slavio device */ 524 sysbus_mmio_map(s, 0, power_base); 525 sysbus_connect_irq(s, 0, cpu_halt); 526 } 527 528 static void tcx_init(hwaddr addr, int vram_size, int width, 529 int height, int depth) 530 { 531 DeviceState *dev; 532 SysBusDevice *s; 533 534 dev = qdev_create(NULL, "SUNW,tcx"); 535 qdev_prop_set_uint32(dev, "vram_size", vram_size); 536 qdev_prop_set_uint16(dev, "width", width); 537 qdev_prop_set_uint16(dev, "height", height); 538 qdev_prop_set_uint16(dev, "depth", depth); 539 qdev_init_nofail(dev); 540 s = SYS_BUS_DEVICE(dev); 541 /* 8-bit plane */ 542 sysbus_mmio_map(s, 0, addr + 0x00800000ULL); 543 /* DAC */ 544 sysbus_mmio_map(s, 1, addr + 0x00200000ULL); 545 /* TEC (dummy) */ 546 sysbus_mmio_map(s, 2, addr + 0x00700000ULL); 547 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */ 548 sysbus_mmio_map(s, 3, addr + 0x00301000ULL); 549 if (depth == 24) { 550 /* 24-bit plane */ 551 sysbus_mmio_map(s, 4, addr + 0x02000000ULL); 552 /* Control plane */ 553 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL); 554 } else { 555 /* THC 8 bit (dummy) */ 556 sysbus_mmio_map(s, 4, addr + 0x00300000ULL); 557 } 558 } 559 560 /* NCR89C100/MACIO Internal ID register */ 561 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 562 563 static void idreg_init(hwaddr addr) 564 { 565 DeviceState *dev; 566 SysBusDevice *s; 567 568 dev = qdev_create(NULL, "macio_idreg"); 569 qdev_init_nofail(dev); 570 s = SYS_BUS_DEVICE(dev); 571 572 sysbus_mmio_map(s, 0, addr); 573 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data)); 574 } 575 576 typedef struct IDRegState { 577 SysBusDevice busdev; 578 MemoryRegion mem; 579 } IDRegState; 580 581 static int idreg_init1(SysBusDevice *dev) 582 { 583 IDRegState *s = FROM_SYSBUS(IDRegState, dev); 584 585 memory_region_init_ram(&s->mem, OBJECT(s), 586 "sun4m.idreg", sizeof(idreg_data)); 587 vmstate_register_ram_global(&s->mem); 588 memory_region_set_readonly(&s->mem, true); 589 sysbus_init_mmio(dev, &s->mem); 590 return 0; 591 } 592 593 static void idreg_class_init(ObjectClass *klass, void *data) 594 { 595 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 596 597 k->init = idreg_init1; 598 } 599 600 static const TypeInfo idreg_info = { 601 .name = "macio_idreg", 602 .parent = TYPE_SYS_BUS_DEVICE, 603 .instance_size = sizeof(IDRegState), 604 .class_init = idreg_class_init, 605 }; 606 607 typedef struct AFXState { 608 SysBusDevice busdev; 609 MemoryRegion mem; 610 } AFXState; 611 612 /* SS-5 TCX AFX register */ 613 static void afx_init(hwaddr addr) 614 { 615 DeviceState *dev; 616 SysBusDevice *s; 617 618 dev = qdev_create(NULL, "tcx_afx"); 619 qdev_init_nofail(dev); 620 s = SYS_BUS_DEVICE(dev); 621 622 sysbus_mmio_map(s, 0, addr); 623 } 624 625 static int afx_init1(SysBusDevice *dev) 626 { 627 AFXState *s = FROM_SYSBUS(AFXState, dev); 628 629 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4); 630 vmstate_register_ram_global(&s->mem); 631 sysbus_init_mmio(dev, &s->mem); 632 return 0; 633 } 634 635 static void afx_class_init(ObjectClass *klass, void *data) 636 { 637 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 638 639 k->init = afx_init1; 640 } 641 642 static const TypeInfo afx_info = { 643 .name = "tcx_afx", 644 .parent = TYPE_SYS_BUS_DEVICE, 645 .instance_size = sizeof(AFXState), 646 .class_init = afx_class_init, 647 }; 648 649 typedef struct PROMState { 650 SysBusDevice busdev; 651 MemoryRegion prom; 652 } PROMState; 653 654 /* Boot PROM (OpenBIOS) */ 655 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 656 { 657 hwaddr *base_addr = (hwaddr *)opaque; 658 return addr + *base_addr - PROM_VADDR; 659 } 660 661 static void prom_init(hwaddr addr, const char *bios_name) 662 { 663 DeviceState *dev; 664 SysBusDevice *s; 665 char *filename; 666 int ret; 667 668 dev = qdev_create(NULL, "openprom"); 669 qdev_init_nofail(dev); 670 s = SYS_BUS_DEVICE(dev); 671 672 sysbus_mmio_map(s, 0, addr); 673 674 /* load boot prom */ 675 if (bios_name == NULL) { 676 bios_name = PROM_FILENAME; 677 } 678 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 679 if (filename) { 680 ret = load_elf(filename, translate_prom_address, &addr, NULL, 681 NULL, NULL, 1, ELF_MACHINE, 0); 682 if (ret < 0 || ret > PROM_SIZE_MAX) { 683 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 684 } 685 g_free(filename); 686 } else { 687 ret = -1; 688 } 689 if (ret < 0 || ret > PROM_SIZE_MAX) { 690 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 691 exit(1); 692 } 693 } 694 695 static int prom_init1(SysBusDevice *dev) 696 { 697 PROMState *s = FROM_SYSBUS(PROMState, dev); 698 699 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX); 700 vmstate_register_ram_global(&s->prom); 701 memory_region_set_readonly(&s->prom, true); 702 sysbus_init_mmio(dev, &s->prom); 703 return 0; 704 } 705 706 static Property prom_properties[] = { 707 {/* end of property list */}, 708 }; 709 710 static void prom_class_init(ObjectClass *klass, void *data) 711 { 712 DeviceClass *dc = DEVICE_CLASS(klass); 713 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 714 715 k->init = prom_init1; 716 dc->props = prom_properties; 717 } 718 719 static const TypeInfo prom_info = { 720 .name = "openprom", 721 .parent = TYPE_SYS_BUS_DEVICE, 722 .instance_size = sizeof(PROMState), 723 .class_init = prom_class_init, 724 }; 725 726 typedef struct RamDevice 727 { 728 SysBusDevice busdev; 729 MemoryRegion ram; 730 uint64_t size; 731 } RamDevice; 732 733 /* System RAM */ 734 static int ram_init1(SysBusDevice *dev) 735 { 736 RamDevice *d = FROM_SYSBUS(RamDevice, dev); 737 738 memory_region_init_ram(&d->ram, OBJECT(d), "sun4m.ram", d->size); 739 vmstate_register_ram_global(&d->ram); 740 sysbus_init_mmio(dev, &d->ram); 741 return 0; 742 } 743 744 static void ram_init(hwaddr addr, ram_addr_t RAM_size, 745 uint64_t max_mem) 746 { 747 DeviceState *dev; 748 SysBusDevice *s; 749 RamDevice *d; 750 751 /* allocate RAM */ 752 if ((uint64_t)RAM_size > max_mem) { 753 fprintf(stderr, 754 "qemu: Too much memory for this machine: %d, maximum %d\n", 755 (unsigned int)(RAM_size / (1024 * 1024)), 756 (unsigned int)(max_mem / (1024 * 1024))); 757 exit(1); 758 } 759 dev = qdev_create(NULL, "memory"); 760 s = SYS_BUS_DEVICE(dev); 761 762 d = FROM_SYSBUS(RamDevice, s); 763 d->size = RAM_size; 764 qdev_init_nofail(dev); 765 766 sysbus_mmio_map(s, 0, addr); 767 } 768 769 static Property ram_properties[] = { 770 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 771 DEFINE_PROP_END_OF_LIST(), 772 }; 773 774 static void ram_class_init(ObjectClass *klass, void *data) 775 { 776 DeviceClass *dc = DEVICE_CLASS(klass); 777 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 778 779 k->init = ram_init1; 780 dc->props = ram_properties; 781 } 782 783 static const TypeInfo ram_info = { 784 .name = "memory", 785 .parent = TYPE_SYS_BUS_DEVICE, 786 .instance_size = sizeof(RamDevice), 787 .class_init = ram_class_init, 788 }; 789 790 static void cpu_devinit(const char *cpu_model, unsigned int id, 791 uint64_t prom_addr, qemu_irq **cpu_irqs) 792 { 793 CPUState *cs; 794 SPARCCPU *cpu; 795 CPUSPARCState *env; 796 797 cpu = cpu_sparc_init(cpu_model); 798 if (cpu == NULL) { 799 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); 800 exit(1); 801 } 802 env = &cpu->env; 803 804 cpu_sparc_set_id(env, id); 805 if (id == 0) { 806 qemu_register_reset(main_cpu_reset, cpu); 807 } else { 808 qemu_register_reset(secondary_cpu_reset, cpu); 809 cs = CPU(cpu); 810 cs->halted = 1; 811 } 812 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 813 env->prom_addr = prom_addr; 814 } 815 816 static void dummy_fdc_tc(void *opaque, int irq, int level) 817 { 818 } 819 820 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, 821 const char *boot_device, 822 const char *kernel_filename, 823 const char *kernel_cmdline, 824 const char *initrd_filename, const char *cpu_model) 825 { 826 unsigned int i; 827 void *iommu, *espdma, *ledma, *nvram; 828 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS], 829 espdma_irq, ledma_irq; 830 qemu_irq esp_reset, dma_enable; 831 qemu_irq fdc_tc; 832 qemu_irq *cpu_halt; 833 unsigned long kernel_size; 834 DriveInfo *fd[MAX_FD]; 835 FWCfgState *fw_cfg; 836 unsigned int num_vsimms; 837 838 /* init CPUs */ 839 if (!cpu_model) 840 cpu_model = hwdef->default_cpu_model; 841 842 for(i = 0; i < smp_cpus; i++) { 843 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); 844 } 845 846 for (i = smp_cpus; i < MAX_CPUS; i++) 847 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 848 849 850 /* set up devices */ 851 ram_init(0, RAM_size, hwdef->max_mem); 852 /* models without ECC don't trap when missing ram is accessed */ 853 if (!hwdef->ecc_base) { 854 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size); 855 } 856 857 prom_init(hwdef->slavio_base, bios_name); 858 859 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 860 hwdef->intctl_base + 0x10000ULL, 861 cpu_irqs); 862 863 for (i = 0; i < 32; i++) { 864 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 865 } 866 for (i = 0; i < MAX_CPUS; i++) { 867 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 868 } 869 870 if (hwdef->idreg_base) { 871 idreg_init(hwdef->idreg_base); 872 } 873 874 if (hwdef->afx_base) { 875 afx_init(hwdef->afx_base); 876 } 877 878 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, 879 slavio_irq[30]); 880 881 if (hwdef->iommu_pad_base) { 882 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 883 Software shouldn't use aliased addresses, neither should it crash 884 when does. Using empty_slot instead of aliasing can help with 885 debugging such accesses */ 886 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); 887 } 888 889 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18], 890 iommu, &espdma_irq, 0); 891 892 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, 893 slavio_irq[16], iommu, &ledma_irq, 1); 894 895 if (graphic_depth != 8 && graphic_depth != 24) { 896 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); 897 exit (1); 898 } 899 num_vsimms = 0; 900 if (num_vsimms == 0) { 901 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height, 902 graphic_depth); 903 } 904 905 for (i = num_vsimms; i < MAX_VSIMMS; i++) { 906 /* vsimm registers probed by OBP */ 907 if (hwdef->vsimm[i].reg_base) { 908 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); 909 } 910 } 911 912 if (hwdef->sx_base) { 913 empty_slot_init(hwdef->sx_base, 0x2000); 914 } 915 916 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq); 917 918 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8); 919 920 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 921 922 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14], 923 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1); 924 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 925 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 926 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], 927 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); 928 929 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); 930 if (hwdef->apc_base) { 931 apc_init(hwdef->apc_base, cpu_halt[0]); 932 } 933 934 if (hwdef->fd_base) { 935 /* there is zero or one floppy drive */ 936 memset(fd, 0, sizeof(fd)); 937 fd[0] = drive_get(IF_FLOPPY, 0, 0); 938 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 939 &fdc_tc); 940 } else { 941 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1); 942 } 943 944 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 945 slavio_irq[30], fdc_tc); 946 947 if (drive_get_max_bus(IF_SCSI) > 0) { 948 fprintf(stderr, "qemu: too many SCSI bus\n"); 949 exit(1); 950 } 951 952 esp_init(hwdef->esp_base, 2, 953 espdma_memory_read, espdma_memory_write, 954 espdma, espdma_irq, &esp_reset, &dma_enable); 955 956 qdev_connect_gpio_out(espdma, 0, esp_reset); 957 qdev_connect_gpio_out(espdma, 1, dma_enable); 958 959 if (hwdef->cs_base) { 960 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, 961 slavio_irq[5]); 962 } 963 964 if (hwdef->dbri_base) { 965 /* ISDN chip with attached CS4215 audio codec */ 966 /* prom space */ 967 empty_slot_init(hwdef->dbri_base+0x1000, 0x30); 968 /* reg space */ 969 empty_slot_init(hwdef->dbri_base+0x10000, 0x100); 970 } 971 972 if (hwdef->bpp_base) { 973 /* parallel port */ 974 empty_slot_init(hwdef->bpp_base, 0x20); 975 } 976 977 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, 978 RAM_size); 979 980 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, 981 boot_device, RAM_size, kernel_size, graphic_width, 982 graphic_height, graphic_depth, hwdef->nvram_machine_id, 983 "Sun4m"); 984 985 if (hwdef->ecc_base) 986 ecc_init(hwdef->ecc_base, slavio_irq[28], 987 hwdef->ecc_version); 988 989 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); 990 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 991 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 992 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 993 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 994 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 995 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 996 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 997 if (kernel_cmdline) { 998 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 999 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); 1000 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1001 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1002 strlen(kernel_cmdline) + 1); 1003 } else { 1004 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1005 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1006 } 1007 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1008 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used 1009 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]); 1010 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1011 } 1012 1013 enum { 1014 ss5_id = 32, 1015 vger_id, 1016 lx_id, 1017 ss4_id, 1018 scls_id, 1019 sbook_id, 1020 ss10_id = 64, 1021 ss20_id, 1022 ss600mp_id, 1023 }; 1024 1025 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1026 /* SS-5 */ 1027 { 1028 .iommu_base = 0x10000000, 1029 .iommu_pad_base = 0x10004000, 1030 .iommu_pad_len = 0x0fffb000, 1031 .tcx_base = 0x50000000, 1032 .cs_base = 0x6c000000, 1033 .slavio_base = 0x70000000, 1034 .ms_kb_base = 0x71000000, 1035 .serial_base = 0x71100000, 1036 .nvram_base = 0x71200000, 1037 .fd_base = 0x71400000, 1038 .counter_base = 0x71d00000, 1039 .intctl_base = 0x71e00000, 1040 .idreg_base = 0x78000000, 1041 .dma_base = 0x78400000, 1042 .esp_base = 0x78800000, 1043 .le_base = 0x78c00000, 1044 .apc_base = 0x6a000000, 1045 .afx_base = 0x6e000000, 1046 .aux1_base = 0x71900000, 1047 .aux2_base = 0x71910000, 1048 .nvram_machine_id = 0x80, 1049 .machine_id = ss5_id, 1050 .iommu_version = 0x05000000, 1051 .max_mem = 0x10000000, 1052 .default_cpu_model = "Fujitsu MB86904", 1053 }, 1054 /* SS-10 */ 1055 { 1056 .iommu_base = 0xfe0000000ULL, 1057 .tcx_base = 0xe20000000ULL, 1058 .slavio_base = 0xff0000000ULL, 1059 .ms_kb_base = 0xff1000000ULL, 1060 .serial_base = 0xff1100000ULL, 1061 .nvram_base = 0xff1200000ULL, 1062 .fd_base = 0xff1700000ULL, 1063 .counter_base = 0xff1300000ULL, 1064 .intctl_base = 0xff1400000ULL, 1065 .idreg_base = 0xef0000000ULL, 1066 .dma_base = 0xef0400000ULL, 1067 .esp_base = 0xef0800000ULL, 1068 .le_base = 0xef0c00000ULL, 1069 .apc_base = 0xefa000000ULL, // XXX should not exist 1070 .aux1_base = 0xff1800000ULL, 1071 .aux2_base = 0xff1a01000ULL, 1072 .ecc_base = 0xf00000000ULL, 1073 .ecc_version = 0x10000000, // version 0, implementation 1 1074 .nvram_machine_id = 0x72, 1075 .machine_id = ss10_id, 1076 .iommu_version = 0x03000000, 1077 .max_mem = 0xf00000000ULL, 1078 .default_cpu_model = "TI SuperSparc II", 1079 }, 1080 /* SS-600MP */ 1081 { 1082 .iommu_base = 0xfe0000000ULL, 1083 .tcx_base = 0xe20000000ULL, 1084 .slavio_base = 0xff0000000ULL, 1085 .ms_kb_base = 0xff1000000ULL, 1086 .serial_base = 0xff1100000ULL, 1087 .nvram_base = 0xff1200000ULL, 1088 .counter_base = 0xff1300000ULL, 1089 .intctl_base = 0xff1400000ULL, 1090 .dma_base = 0xef0081000ULL, 1091 .esp_base = 0xef0080000ULL, 1092 .le_base = 0xef0060000ULL, 1093 .apc_base = 0xefa000000ULL, // XXX should not exist 1094 .aux1_base = 0xff1800000ULL, 1095 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1096 .ecc_base = 0xf00000000ULL, 1097 .ecc_version = 0x00000000, // version 0, implementation 0 1098 .nvram_machine_id = 0x71, 1099 .machine_id = ss600mp_id, 1100 .iommu_version = 0x01000000, 1101 .max_mem = 0xf00000000ULL, 1102 .default_cpu_model = "TI SuperSparc II", 1103 }, 1104 /* SS-20 */ 1105 { 1106 .iommu_base = 0xfe0000000ULL, 1107 .tcx_base = 0xe20000000ULL, 1108 .slavio_base = 0xff0000000ULL, 1109 .ms_kb_base = 0xff1000000ULL, 1110 .serial_base = 0xff1100000ULL, 1111 .nvram_base = 0xff1200000ULL, 1112 .fd_base = 0xff1700000ULL, 1113 .counter_base = 0xff1300000ULL, 1114 .intctl_base = 0xff1400000ULL, 1115 .idreg_base = 0xef0000000ULL, 1116 .dma_base = 0xef0400000ULL, 1117 .esp_base = 0xef0800000ULL, 1118 .le_base = 0xef0c00000ULL, 1119 .bpp_base = 0xef4800000ULL, 1120 .apc_base = 0xefa000000ULL, // XXX should not exist 1121 .aux1_base = 0xff1800000ULL, 1122 .aux2_base = 0xff1a01000ULL, 1123 .dbri_base = 0xee0000000ULL, 1124 .sx_base = 0xf80000000ULL, 1125 .vsimm = { 1126 { 1127 .reg_base = 0x9c000000ULL, 1128 .vram_base = 0xfc000000ULL 1129 }, { 1130 .reg_base = 0x90000000ULL, 1131 .vram_base = 0xf0000000ULL 1132 }, { 1133 .reg_base = 0x94000000ULL 1134 }, { 1135 .reg_base = 0x98000000ULL 1136 } 1137 }, 1138 .ecc_base = 0xf00000000ULL, 1139 .ecc_version = 0x20000000, // version 0, implementation 2 1140 .nvram_machine_id = 0x72, 1141 .machine_id = ss20_id, 1142 .iommu_version = 0x13000000, 1143 .max_mem = 0xf00000000ULL, 1144 .default_cpu_model = "TI SuperSparc II", 1145 }, 1146 /* Voyager */ 1147 { 1148 .iommu_base = 0x10000000, 1149 .tcx_base = 0x50000000, 1150 .slavio_base = 0x70000000, 1151 .ms_kb_base = 0x71000000, 1152 .serial_base = 0x71100000, 1153 .nvram_base = 0x71200000, 1154 .fd_base = 0x71400000, 1155 .counter_base = 0x71d00000, 1156 .intctl_base = 0x71e00000, 1157 .idreg_base = 0x78000000, 1158 .dma_base = 0x78400000, 1159 .esp_base = 0x78800000, 1160 .le_base = 0x78c00000, 1161 .apc_base = 0x71300000, // pmc 1162 .aux1_base = 0x71900000, 1163 .aux2_base = 0x71910000, 1164 .nvram_machine_id = 0x80, 1165 .machine_id = vger_id, 1166 .iommu_version = 0x05000000, 1167 .max_mem = 0x10000000, 1168 .default_cpu_model = "Fujitsu MB86904", 1169 }, 1170 /* LX */ 1171 { 1172 .iommu_base = 0x10000000, 1173 .iommu_pad_base = 0x10004000, 1174 .iommu_pad_len = 0x0fffb000, 1175 .tcx_base = 0x50000000, 1176 .slavio_base = 0x70000000, 1177 .ms_kb_base = 0x71000000, 1178 .serial_base = 0x71100000, 1179 .nvram_base = 0x71200000, 1180 .fd_base = 0x71400000, 1181 .counter_base = 0x71d00000, 1182 .intctl_base = 0x71e00000, 1183 .idreg_base = 0x78000000, 1184 .dma_base = 0x78400000, 1185 .esp_base = 0x78800000, 1186 .le_base = 0x78c00000, 1187 .aux1_base = 0x71900000, 1188 .aux2_base = 0x71910000, 1189 .nvram_machine_id = 0x80, 1190 .machine_id = lx_id, 1191 .iommu_version = 0x04000000, 1192 .max_mem = 0x10000000, 1193 .default_cpu_model = "TI MicroSparc I", 1194 }, 1195 /* SS-4 */ 1196 { 1197 .iommu_base = 0x10000000, 1198 .tcx_base = 0x50000000, 1199 .cs_base = 0x6c000000, 1200 .slavio_base = 0x70000000, 1201 .ms_kb_base = 0x71000000, 1202 .serial_base = 0x71100000, 1203 .nvram_base = 0x71200000, 1204 .fd_base = 0x71400000, 1205 .counter_base = 0x71d00000, 1206 .intctl_base = 0x71e00000, 1207 .idreg_base = 0x78000000, 1208 .dma_base = 0x78400000, 1209 .esp_base = 0x78800000, 1210 .le_base = 0x78c00000, 1211 .apc_base = 0x6a000000, 1212 .aux1_base = 0x71900000, 1213 .aux2_base = 0x71910000, 1214 .nvram_machine_id = 0x80, 1215 .machine_id = ss4_id, 1216 .iommu_version = 0x05000000, 1217 .max_mem = 0x10000000, 1218 .default_cpu_model = "Fujitsu MB86904", 1219 }, 1220 /* SPARCClassic */ 1221 { 1222 .iommu_base = 0x10000000, 1223 .tcx_base = 0x50000000, 1224 .slavio_base = 0x70000000, 1225 .ms_kb_base = 0x71000000, 1226 .serial_base = 0x71100000, 1227 .nvram_base = 0x71200000, 1228 .fd_base = 0x71400000, 1229 .counter_base = 0x71d00000, 1230 .intctl_base = 0x71e00000, 1231 .idreg_base = 0x78000000, 1232 .dma_base = 0x78400000, 1233 .esp_base = 0x78800000, 1234 .le_base = 0x78c00000, 1235 .apc_base = 0x6a000000, 1236 .aux1_base = 0x71900000, 1237 .aux2_base = 0x71910000, 1238 .nvram_machine_id = 0x80, 1239 .machine_id = scls_id, 1240 .iommu_version = 0x05000000, 1241 .max_mem = 0x10000000, 1242 .default_cpu_model = "TI MicroSparc I", 1243 }, 1244 /* SPARCbook */ 1245 { 1246 .iommu_base = 0x10000000, 1247 .tcx_base = 0x50000000, // XXX 1248 .slavio_base = 0x70000000, 1249 .ms_kb_base = 0x71000000, 1250 .serial_base = 0x71100000, 1251 .nvram_base = 0x71200000, 1252 .fd_base = 0x71400000, 1253 .counter_base = 0x71d00000, 1254 .intctl_base = 0x71e00000, 1255 .idreg_base = 0x78000000, 1256 .dma_base = 0x78400000, 1257 .esp_base = 0x78800000, 1258 .le_base = 0x78c00000, 1259 .apc_base = 0x6a000000, 1260 .aux1_base = 0x71900000, 1261 .aux2_base = 0x71910000, 1262 .nvram_machine_id = 0x80, 1263 .machine_id = sbook_id, 1264 .iommu_version = 0x05000000, 1265 .max_mem = 0x10000000, 1266 .default_cpu_model = "TI MicroSparc I", 1267 }, 1268 }; 1269 1270 /* SPARCstation 5 hardware initialisation */ 1271 static void ss5_init(QEMUMachineInitArgs *args) 1272 { 1273 ram_addr_t RAM_size = args->ram_size; 1274 const char *cpu_model = args->cpu_model; 1275 const char *kernel_filename = args->kernel_filename; 1276 const char *kernel_cmdline = args->kernel_cmdline; 1277 const char *initrd_filename = args->initrd_filename; 1278 const char *boot_device = args->boot_device; 1279 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename, 1280 kernel_cmdline, initrd_filename, cpu_model); 1281 } 1282 1283 /* SPARCstation 10 hardware initialisation */ 1284 static void ss10_init(QEMUMachineInitArgs *args) 1285 { 1286 ram_addr_t RAM_size = args->ram_size; 1287 const char *cpu_model = args->cpu_model; 1288 const char *kernel_filename = args->kernel_filename; 1289 const char *kernel_cmdline = args->kernel_cmdline; 1290 const char *initrd_filename = args->initrd_filename; 1291 const char *boot_device = args->boot_device; 1292 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename, 1293 kernel_cmdline, initrd_filename, cpu_model); 1294 } 1295 1296 /* SPARCserver 600MP hardware initialisation */ 1297 static void ss600mp_init(QEMUMachineInitArgs *args) 1298 { 1299 ram_addr_t RAM_size = args->ram_size; 1300 const char *cpu_model = args->cpu_model; 1301 const char *kernel_filename = args->kernel_filename; 1302 const char *kernel_cmdline = args->kernel_cmdline; 1303 const char *initrd_filename = args->initrd_filename; 1304 const char *boot_device = args->boot_device; 1305 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename, 1306 kernel_cmdline, initrd_filename, cpu_model); 1307 } 1308 1309 /* SPARCstation 20 hardware initialisation */ 1310 static void ss20_init(QEMUMachineInitArgs *args) 1311 { 1312 ram_addr_t RAM_size = args->ram_size; 1313 const char *cpu_model = args->cpu_model; 1314 const char *kernel_filename = args->kernel_filename; 1315 const char *kernel_cmdline = args->kernel_cmdline; 1316 const char *initrd_filename = args->initrd_filename; 1317 const char *boot_device = args->boot_device; 1318 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename, 1319 kernel_cmdline, initrd_filename, cpu_model); 1320 } 1321 1322 /* SPARCstation Voyager hardware initialisation */ 1323 static void vger_init(QEMUMachineInitArgs *args) 1324 { 1325 ram_addr_t RAM_size = args->ram_size; 1326 const char *cpu_model = args->cpu_model; 1327 const char *kernel_filename = args->kernel_filename; 1328 const char *kernel_cmdline = args->kernel_cmdline; 1329 const char *initrd_filename = args->initrd_filename; 1330 const char *boot_device = args->boot_device; 1331 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename, 1332 kernel_cmdline, initrd_filename, cpu_model); 1333 } 1334 1335 /* SPARCstation LX hardware initialisation */ 1336 static void ss_lx_init(QEMUMachineInitArgs *args) 1337 { 1338 ram_addr_t RAM_size = args->ram_size; 1339 const char *cpu_model = args->cpu_model; 1340 const char *kernel_filename = args->kernel_filename; 1341 const char *kernel_cmdline = args->kernel_cmdline; 1342 const char *initrd_filename = args->initrd_filename; 1343 const char *boot_device = args->boot_device; 1344 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename, 1345 kernel_cmdline, initrd_filename, cpu_model); 1346 } 1347 1348 /* SPARCstation 4 hardware initialisation */ 1349 static void ss4_init(QEMUMachineInitArgs *args) 1350 { 1351 ram_addr_t RAM_size = args->ram_size; 1352 const char *cpu_model = args->cpu_model; 1353 const char *kernel_filename = args->kernel_filename; 1354 const char *kernel_cmdline = args->kernel_cmdline; 1355 const char *initrd_filename = args->initrd_filename; 1356 const char *boot_device = args->boot_device; 1357 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename, 1358 kernel_cmdline, initrd_filename, cpu_model); 1359 } 1360 1361 /* SPARCClassic hardware initialisation */ 1362 static void scls_init(QEMUMachineInitArgs *args) 1363 { 1364 ram_addr_t RAM_size = args->ram_size; 1365 const char *cpu_model = args->cpu_model; 1366 const char *kernel_filename = args->kernel_filename; 1367 const char *kernel_cmdline = args->kernel_cmdline; 1368 const char *initrd_filename = args->initrd_filename; 1369 const char *boot_device = args->boot_device; 1370 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename, 1371 kernel_cmdline, initrd_filename, cpu_model); 1372 } 1373 1374 /* SPARCbook hardware initialisation */ 1375 static void sbook_init(QEMUMachineInitArgs *args) 1376 { 1377 ram_addr_t RAM_size = args->ram_size; 1378 const char *cpu_model = args->cpu_model; 1379 const char *kernel_filename = args->kernel_filename; 1380 const char *kernel_cmdline = args->kernel_cmdline; 1381 const char *initrd_filename = args->initrd_filename; 1382 const char *boot_device = args->boot_device; 1383 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename, 1384 kernel_cmdline, initrd_filename, cpu_model); 1385 } 1386 1387 static QEMUMachine ss5_machine = { 1388 .name = "SS-5", 1389 .desc = "Sun4m platform, SPARCstation 5", 1390 .init = ss5_init, 1391 .block_default_type = IF_SCSI, 1392 .is_default = 1, 1393 DEFAULT_MACHINE_OPTIONS, 1394 }; 1395 1396 static QEMUMachine ss10_machine = { 1397 .name = "SS-10", 1398 .desc = "Sun4m platform, SPARCstation 10", 1399 .init = ss10_init, 1400 .block_default_type = IF_SCSI, 1401 .max_cpus = 4, 1402 DEFAULT_MACHINE_OPTIONS, 1403 }; 1404 1405 static QEMUMachine ss600mp_machine = { 1406 .name = "SS-600MP", 1407 .desc = "Sun4m platform, SPARCserver 600MP", 1408 .init = ss600mp_init, 1409 .block_default_type = IF_SCSI, 1410 .max_cpus = 4, 1411 DEFAULT_MACHINE_OPTIONS, 1412 }; 1413 1414 static QEMUMachine ss20_machine = { 1415 .name = "SS-20", 1416 .desc = "Sun4m platform, SPARCstation 20", 1417 .init = ss20_init, 1418 .block_default_type = IF_SCSI, 1419 .max_cpus = 4, 1420 DEFAULT_MACHINE_OPTIONS, 1421 }; 1422 1423 static QEMUMachine voyager_machine = { 1424 .name = "Voyager", 1425 .desc = "Sun4m platform, SPARCstation Voyager", 1426 .init = vger_init, 1427 .block_default_type = IF_SCSI, 1428 DEFAULT_MACHINE_OPTIONS, 1429 }; 1430 1431 static QEMUMachine ss_lx_machine = { 1432 .name = "LX", 1433 .desc = "Sun4m platform, SPARCstation LX", 1434 .init = ss_lx_init, 1435 .block_default_type = IF_SCSI, 1436 DEFAULT_MACHINE_OPTIONS, 1437 }; 1438 1439 static QEMUMachine ss4_machine = { 1440 .name = "SS-4", 1441 .desc = "Sun4m platform, SPARCstation 4", 1442 .init = ss4_init, 1443 .block_default_type = IF_SCSI, 1444 DEFAULT_MACHINE_OPTIONS, 1445 }; 1446 1447 static QEMUMachine scls_machine = { 1448 .name = "SPARCClassic", 1449 .desc = "Sun4m platform, SPARCClassic", 1450 .init = scls_init, 1451 .block_default_type = IF_SCSI, 1452 DEFAULT_MACHINE_OPTIONS, 1453 }; 1454 1455 static QEMUMachine sbook_machine = { 1456 .name = "SPARCbook", 1457 .desc = "Sun4m platform, SPARCbook", 1458 .init = sbook_init, 1459 .block_default_type = IF_SCSI, 1460 DEFAULT_MACHINE_OPTIONS, 1461 }; 1462 1463 static void sun4m_register_types(void) 1464 { 1465 type_register_static(&idreg_info); 1466 type_register_static(&afx_info); 1467 type_register_static(&prom_info); 1468 type_register_static(&ram_info); 1469 } 1470 1471 static void sun4m_machine_init(void) 1472 { 1473 qemu_register_machine(&ss5_machine); 1474 qemu_register_machine(&ss10_machine); 1475 qemu_register_machine(&ss600mp_machine); 1476 qemu_register_machine(&ss20_machine); 1477 qemu_register_machine(&voyager_machine); 1478 qemu_register_machine(&ss_lx_machine); 1479 qemu_register_machine(&ss4_machine); 1480 qemu_register_machine(&scls_machine); 1481 qemu_register_machine(&sbook_machine); 1482 } 1483 1484 type_init(sun4m_register_types) 1485 machine_init(sun4m_machine_init); 1486