xref: /openbmc/qemu/hw/sparc/sun4m.c (revision db725815985654007ade0fd53590d613fd657208)
1 /*
2  * QEMU Sun4m & Sun4d & Sun4c System Emulator
3  *
4  * Copyright (c) 2003-2005 Fabrice Bellard
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
28 #include "qemu-common.h"
29 #include "cpu.h"
30 #include "hw/sysbus.h"
31 #include "qemu/error-report.h"
32 #include "qemu/timer.h"
33 #include "hw/sparc/sun4m_iommu.h"
34 #include "hw/timer/m48t59.h"
35 #include "migration/vmstate.h"
36 #include "hw/sparc/sparc32_dma.h"
37 #include "hw/block/fdc.h"
38 #include "sysemu/reset.h"
39 #include "sysemu/sysemu.h"
40 #include "net/net.h"
41 #include "hw/boards.h"
42 #include "hw/scsi/esp.h"
43 #include "hw/nvram/sun_nvram.h"
44 #include "hw/nvram/chrp_nvram.h"
45 #include "hw/nvram/fw_cfg.h"
46 #include "hw/char/escc.h"
47 #include "hw/empty_slot.h"
48 #include "hw/irq.h"
49 #include "hw/loader.h"
50 #include "elf.h"
51 #include "trace.h"
52 
53 /*
54  * Sun4m architecture was used in the following machines:
55  *
56  * SPARCserver 6xxMP/xx
57  * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
58  * SPARCclassic X (4/10)
59  * SPARCstation LX/ZX (4/30)
60  * SPARCstation Voyager
61  * SPARCstation 10/xx, SPARCserver 10/xx
62  * SPARCstation 5, SPARCserver 5
63  * SPARCstation 20/xx, SPARCserver 20
64  * SPARCstation 4
65  *
66  * See for example: http://www.sunhelp.org/faq/sunref1.html
67  */
68 
69 #define KERNEL_LOAD_ADDR     0x00004000
70 #define CMDLINE_ADDR         0x007ff000
71 #define INITRD_LOAD_ADDR     0x00800000
72 #define PROM_SIZE_MAX        (1 * MiB)
73 #define PROM_VADDR           0xffd00000
74 #define PROM_FILENAME        "openbios-sparc32"
75 #define CFG_ADDR             0xd00000510ULL
76 #define FW_CFG_SUN4M_DEPTH   (FW_CFG_ARCH_LOCAL + 0x00)
77 #define FW_CFG_SUN4M_WIDTH   (FW_CFG_ARCH_LOCAL + 0x01)
78 #define FW_CFG_SUN4M_HEIGHT  (FW_CFG_ARCH_LOCAL + 0x02)
79 
80 #define MAX_CPUS 16
81 #define MAX_PILS 16
82 #define MAX_VSIMMS 4
83 
84 #define ESCC_CLOCK 4915200
85 
86 struct sun4m_hwdef {
87     hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
88     hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
89     hwaddr serial_base, fd_base;
90     hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
91     hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
92     hwaddr bpp_base, dbri_base, sx_base;
93     struct {
94         hwaddr reg_base, vram_base;
95     } vsimm[MAX_VSIMMS];
96     hwaddr ecc_base;
97     uint64_t max_mem;
98     uint32_t ecc_version;
99     uint32_t iommu_version;
100     uint16_t machine_id;
101     uint8_t nvram_machine_id;
102 };
103 
104 const char *fw_cfg_arch_key_name(uint16_t key)
105 {
106     static const struct {
107         uint16_t key;
108         const char *name;
109     } fw_cfg_arch_wellknown_keys[] = {
110         {FW_CFG_SUN4M_DEPTH, "depth"},
111         {FW_CFG_SUN4M_WIDTH, "width"},
112         {FW_CFG_SUN4M_HEIGHT, "height"},
113     };
114 
115     for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
116         if (fw_cfg_arch_wellknown_keys[i].key == key) {
117             return fw_cfg_arch_wellknown_keys[i].name;
118         }
119     }
120     return NULL;
121 }
122 
123 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
124                             Error **errp)
125 {
126     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
127 }
128 
129 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
130                        const char *cmdline, const char *boot_devices,
131                        ram_addr_t RAM_size, uint32_t kernel_size,
132                        int width, int height, int depth,
133                        int nvram_machine_id, const char *arch)
134 {
135     unsigned int i;
136     int sysp_end;
137     uint8_t image[0x1ff0];
138     NvramClass *k = NVRAM_GET_CLASS(nvram);
139 
140     memset(image, '\0', sizeof(image));
141 
142     /* OpenBIOS nvram variables partition */
143     sysp_end = chrp_nvram_create_system_partition(image, 0);
144 
145     /* Free space partition */
146     chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
147 
148     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
149                     nvram_machine_id);
150 
151     for (i = 0; i < sizeof(image); i++) {
152         (k->write)(nvram, i, image[i]);
153     }
154 }
155 
156 void cpu_check_irqs(CPUSPARCState *env)
157 {
158     CPUState *cs;
159 
160     /* We should be holding the BQL before we mess with IRQs */
161     g_assert(qemu_mutex_iothread_locked());
162 
163     if (env->pil_in && (env->interrupt_index == 0 ||
164                         (env->interrupt_index & ~15) == TT_EXTINT)) {
165         unsigned int i;
166 
167         for (i = 15; i > 0; i--) {
168             if (env->pil_in & (1 << i)) {
169                 int old_interrupt = env->interrupt_index;
170 
171                 env->interrupt_index = TT_EXTINT | i;
172                 if (old_interrupt != env->interrupt_index) {
173                     cs = env_cpu(env);
174                     trace_sun4m_cpu_interrupt(i);
175                     cpu_interrupt(cs, CPU_INTERRUPT_HARD);
176                 }
177                 break;
178             }
179         }
180     } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
181         cs = env_cpu(env);
182         trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
183         env->interrupt_index = 0;
184         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
185     }
186 }
187 
188 static void cpu_kick_irq(SPARCCPU *cpu)
189 {
190     CPUSPARCState *env = &cpu->env;
191     CPUState *cs = CPU(cpu);
192 
193     cs->halted = 0;
194     cpu_check_irqs(env);
195     qemu_cpu_kick(cs);
196 }
197 
198 static void cpu_set_irq(void *opaque, int irq, int level)
199 {
200     SPARCCPU *cpu = opaque;
201     CPUSPARCState *env = &cpu->env;
202 
203     if (level) {
204         trace_sun4m_cpu_set_irq_raise(irq);
205         env->pil_in |= 1 << irq;
206         cpu_kick_irq(cpu);
207     } else {
208         trace_sun4m_cpu_set_irq_lower(irq);
209         env->pil_in &= ~(1 << irq);
210         cpu_check_irqs(env);
211     }
212 }
213 
214 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
215 {
216 }
217 
218 static void main_cpu_reset(void *opaque)
219 {
220     SPARCCPU *cpu = opaque;
221     CPUState *cs = CPU(cpu);
222 
223     cpu_reset(cs);
224     cs->halted = 0;
225 }
226 
227 static void secondary_cpu_reset(void *opaque)
228 {
229     SPARCCPU *cpu = opaque;
230     CPUState *cs = CPU(cpu);
231 
232     cpu_reset(cs);
233     cs->halted = 1;
234 }
235 
236 static void cpu_halt_signal(void *opaque, int irq, int level)
237 {
238     if (level && current_cpu) {
239         cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
240     }
241 }
242 
243 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
244 {
245     return addr - 0xf0000000ULL;
246 }
247 
248 static unsigned long sun4m_load_kernel(const char *kernel_filename,
249                                        const char *initrd_filename,
250                                        ram_addr_t RAM_size,
251                                        uint32_t *initrd_size)
252 {
253     int linux_boot;
254     unsigned int i;
255     long kernel_size;
256     uint8_t *ptr;
257 
258     linux_boot = (kernel_filename != NULL);
259 
260     kernel_size = 0;
261     if (linux_boot) {
262         int bswap_needed;
263 
264 #ifdef BSWAP_NEEDED
265         bswap_needed = 1;
266 #else
267         bswap_needed = 0;
268 #endif
269         kernel_size = load_elf(kernel_filename, NULL,
270                                translate_kernel_address, NULL,
271                                NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
272         if (kernel_size < 0)
273             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
274                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
275                                     TARGET_PAGE_SIZE);
276         if (kernel_size < 0)
277             kernel_size = load_image_targphys(kernel_filename,
278                                               KERNEL_LOAD_ADDR,
279                                               RAM_size - KERNEL_LOAD_ADDR);
280         if (kernel_size < 0) {
281             error_report("could not load kernel '%s'", kernel_filename);
282             exit(1);
283         }
284 
285         /* load initrd */
286         *initrd_size = 0;
287         if (initrd_filename) {
288             *initrd_size = load_image_targphys(initrd_filename,
289                                                INITRD_LOAD_ADDR,
290                                                RAM_size - INITRD_LOAD_ADDR);
291             if ((int)*initrd_size < 0) {
292                 error_report("could not load initial ram disk '%s'",
293                              initrd_filename);
294                 exit(1);
295             }
296         }
297         if (*initrd_size > 0) {
298             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
299                 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24);
300                 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */
301                     stl_p(ptr + 16, INITRD_LOAD_ADDR);
302                     stl_p(ptr + 20, *initrd_size);
303                     break;
304                 }
305             }
306         }
307     }
308     return kernel_size;
309 }
310 
311 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
312 {
313     DeviceState *dev;
314     SysBusDevice *s;
315 
316     dev = qdev_create(NULL, TYPE_SUN4M_IOMMU);
317     qdev_prop_set_uint32(dev, "version", version);
318     qdev_init_nofail(dev);
319     s = SYS_BUS_DEVICE(dev);
320     sysbus_connect_irq(s, 0, irq);
321     sysbus_mmio_map(s, 0, addr);
322 
323     return s;
324 }
325 
326 static void *sparc32_dma_init(hwaddr dma_base,
327                               hwaddr esp_base, qemu_irq espdma_irq,
328                               hwaddr le_base, qemu_irq ledma_irq)
329 {
330     DeviceState *dma;
331     ESPDMADeviceState *espdma;
332     LEDMADeviceState *ledma;
333     SysBusESPState *esp;
334     SysBusPCNetState *lance;
335 
336     dma = qdev_create(NULL, TYPE_SPARC32_DMA);
337     qdev_init_nofail(dma);
338     sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
339 
340     espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
341                                    OBJECT(dma), "espdma"));
342     sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
343 
344     esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp"));
345     sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
346     scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
347 
348     ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
349                                  OBJECT(dma), "ledma"));
350     sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
351 
352     lance = SYSBUS_PCNET(object_resolve_path_component(
353                          OBJECT(ledma), "lance"));
354     sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
355 
356     return dma;
357 }
358 
359 static DeviceState *slavio_intctl_init(hwaddr addr,
360                                        hwaddr addrg,
361                                        qemu_irq **parent_irq)
362 {
363     DeviceState *dev;
364     SysBusDevice *s;
365     unsigned int i, j;
366 
367     dev = qdev_create(NULL, "slavio_intctl");
368     qdev_init_nofail(dev);
369 
370     s = SYS_BUS_DEVICE(dev);
371 
372     for (i = 0; i < MAX_CPUS; i++) {
373         for (j = 0; j < MAX_PILS; j++) {
374             sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
375         }
376     }
377     sysbus_mmio_map(s, 0, addrg);
378     for (i = 0; i < MAX_CPUS; i++) {
379         sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
380     }
381 
382     return dev;
383 }
384 
385 #define SYS_TIMER_OFFSET      0x10000ULL
386 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
387 
388 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
389                                   qemu_irq *cpu_irqs, unsigned int num_cpus)
390 {
391     DeviceState *dev;
392     SysBusDevice *s;
393     unsigned int i;
394 
395     dev = qdev_create(NULL, "slavio_timer");
396     qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
397     qdev_init_nofail(dev);
398     s = SYS_BUS_DEVICE(dev);
399     sysbus_connect_irq(s, 0, master_irq);
400     sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
401 
402     for (i = 0; i < MAX_CPUS; i++) {
403         sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
404         sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
405     }
406 }
407 
408 static qemu_irq  slavio_system_powerdown;
409 
410 static void slavio_powerdown_req(Notifier *n, void *opaque)
411 {
412     qemu_irq_raise(slavio_system_powerdown);
413 }
414 
415 static Notifier slavio_system_powerdown_notifier = {
416     .notify = slavio_powerdown_req
417 };
418 
419 #define MISC_LEDS 0x01600000
420 #define MISC_CFG  0x01800000
421 #define MISC_DIAG 0x01a00000
422 #define MISC_MDM  0x01b00000
423 #define MISC_SYS  0x01f00000
424 
425 static void slavio_misc_init(hwaddr base,
426                              hwaddr aux1_base,
427                              hwaddr aux2_base, qemu_irq irq,
428                              qemu_irq fdc_tc)
429 {
430     DeviceState *dev;
431     SysBusDevice *s;
432 
433     dev = qdev_create(NULL, "slavio_misc");
434     qdev_init_nofail(dev);
435     s = SYS_BUS_DEVICE(dev);
436     if (base) {
437         /* 8 bit registers */
438         /* Slavio control */
439         sysbus_mmio_map(s, 0, base + MISC_CFG);
440         /* Diagnostics */
441         sysbus_mmio_map(s, 1, base + MISC_DIAG);
442         /* Modem control */
443         sysbus_mmio_map(s, 2, base + MISC_MDM);
444         /* 16 bit registers */
445         /* ss600mp diag LEDs */
446         sysbus_mmio_map(s, 3, base + MISC_LEDS);
447         /* 32 bit registers */
448         /* System control */
449         sysbus_mmio_map(s, 4, base + MISC_SYS);
450     }
451     if (aux1_base) {
452         /* AUX 1 (Misc System Functions) */
453         sysbus_mmio_map(s, 5, aux1_base);
454     }
455     if (aux2_base) {
456         /* AUX 2 (Software Powerdown Control) */
457         sysbus_mmio_map(s, 6, aux2_base);
458     }
459     sysbus_connect_irq(s, 0, irq);
460     sysbus_connect_irq(s, 1, fdc_tc);
461     slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
462     qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
463 }
464 
465 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
466 {
467     DeviceState *dev;
468     SysBusDevice *s;
469 
470     dev = qdev_create(NULL, "eccmemctl");
471     qdev_prop_set_uint32(dev, "version", version);
472     qdev_init_nofail(dev);
473     s = SYS_BUS_DEVICE(dev);
474     sysbus_connect_irq(s, 0, irq);
475     sysbus_mmio_map(s, 0, base);
476     if (version == 0) { // SS-600MP only
477         sysbus_mmio_map(s, 1, base + 0x1000);
478     }
479 }
480 
481 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
482 {
483     DeviceState *dev;
484     SysBusDevice *s;
485 
486     dev = qdev_create(NULL, "apc");
487     qdev_init_nofail(dev);
488     s = SYS_BUS_DEVICE(dev);
489     /* Power management (APC) XXX: not a Slavio device */
490     sysbus_mmio_map(s, 0, power_base);
491     sysbus_connect_irq(s, 0, cpu_halt);
492 }
493 
494 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
495                      int height, int depth)
496 {
497     DeviceState *dev;
498     SysBusDevice *s;
499 
500     dev = qdev_create(NULL, "SUNW,tcx");
501     qdev_prop_set_uint32(dev, "vram_size", vram_size);
502     qdev_prop_set_uint16(dev, "width", width);
503     qdev_prop_set_uint16(dev, "height", height);
504     qdev_prop_set_uint16(dev, "depth", depth);
505     qdev_init_nofail(dev);
506     s = SYS_BUS_DEVICE(dev);
507 
508     /* 10/ROM : FCode ROM */
509     sysbus_mmio_map(s, 0, addr);
510     /* 2/STIP : Stipple */
511     sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
512     /* 3/BLIT : Blitter */
513     sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
514     /* 5/RSTIP : Raw Stipple */
515     sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
516     /* 6/RBLIT : Raw Blitter */
517     sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
518     /* 7/TEC : Transform Engine */
519     sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
520     /* 8/CMAP  : DAC */
521     sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
522     /* 9/THC : */
523     if (depth == 8) {
524         sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
525     } else {
526         sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
527     }
528     /* 11/DHC : */
529     sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
530     /* 12/ALT : */
531     sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
532     /* 0/DFB8 : 8-bit plane */
533     sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
534     /* 1/DFB24 : 24bit plane */
535     sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
536     /* 4/RDFB32: Raw framebuffer. Control plane */
537     sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
538     /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
539     if (depth == 8) {
540         sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
541     }
542 
543     sysbus_connect_irq(s, 0, irq);
544 }
545 
546 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
547                      int height, int depth)
548 {
549     DeviceState *dev;
550     SysBusDevice *s;
551 
552     dev = qdev_create(NULL, "cgthree");
553     qdev_prop_set_uint32(dev, "vram-size", vram_size);
554     qdev_prop_set_uint16(dev, "width", width);
555     qdev_prop_set_uint16(dev, "height", height);
556     qdev_prop_set_uint16(dev, "depth", depth);
557     qdev_init_nofail(dev);
558     s = SYS_BUS_DEVICE(dev);
559 
560     /* FCode ROM */
561     sysbus_mmio_map(s, 0, addr);
562     /* DAC */
563     sysbus_mmio_map(s, 1, addr + 0x400000ULL);
564     /* 8-bit plane */
565     sysbus_mmio_map(s, 2, addr + 0x800000ULL);
566 
567     sysbus_connect_irq(s, 0, irq);
568 }
569 
570 /* NCR89C100/MACIO Internal ID register */
571 
572 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
573 
574 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
575 
576 static void idreg_init(hwaddr addr)
577 {
578     DeviceState *dev;
579     SysBusDevice *s;
580 
581     dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
582     qdev_init_nofail(dev);
583     s = SYS_BUS_DEVICE(dev);
584 
585     sysbus_mmio_map(s, 0, addr);
586     address_space_write_rom(&address_space_memory, addr,
587                             MEMTXATTRS_UNSPECIFIED,
588                             idreg_data, sizeof(idreg_data));
589 }
590 
591 #define MACIO_ID_REGISTER(obj) \
592     OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
593 
594 typedef struct IDRegState {
595     SysBusDevice parent_obj;
596 
597     MemoryRegion mem;
598 } IDRegState;
599 
600 static void idreg_realize(DeviceState *ds, Error **errp)
601 {
602     IDRegState *s = MACIO_ID_REGISTER(ds);
603     SysBusDevice *dev = SYS_BUS_DEVICE(ds);
604     Error *local_err = NULL;
605 
606     memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
607                                      sizeof(idreg_data), &local_err);
608     if (local_err) {
609         error_propagate(errp, local_err);
610         return;
611     }
612 
613     vmstate_register_ram_global(&s->mem);
614     memory_region_set_readonly(&s->mem, true);
615     sysbus_init_mmio(dev, &s->mem);
616 }
617 
618 static void idreg_class_init(ObjectClass *oc, void *data)
619 {
620     DeviceClass *dc = DEVICE_CLASS(oc);
621 
622     dc->realize = idreg_realize;
623 }
624 
625 static const TypeInfo idreg_info = {
626     .name          = TYPE_MACIO_ID_REGISTER,
627     .parent        = TYPE_SYS_BUS_DEVICE,
628     .instance_size = sizeof(IDRegState),
629     .class_init    = idreg_class_init,
630 };
631 
632 #define TYPE_TCX_AFX "tcx_afx"
633 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
634 
635 typedef struct AFXState {
636     SysBusDevice parent_obj;
637 
638     MemoryRegion mem;
639 } AFXState;
640 
641 /* SS-5 TCX AFX register */
642 static void afx_init(hwaddr addr)
643 {
644     DeviceState *dev;
645     SysBusDevice *s;
646 
647     dev = qdev_create(NULL, TYPE_TCX_AFX);
648     qdev_init_nofail(dev);
649     s = SYS_BUS_DEVICE(dev);
650 
651     sysbus_mmio_map(s, 0, addr);
652 }
653 
654 static void afx_realize(DeviceState *ds, Error **errp)
655 {
656     AFXState *s = TCX_AFX(ds);
657     SysBusDevice *dev = SYS_BUS_DEVICE(ds);
658     Error *local_err = NULL;
659 
660     memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4,
661                                      &local_err);
662     if (local_err) {
663         error_propagate(errp, local_err);
664         return;
665     }
666 
667     vmstate_register_ram_global(&s->mem);
668     sysbus_init_mmio(dev, &s->mem);
669 }
670 
671 static void afx_class_init(ObjectClass *oc, void *data)
672 {
673     DeviceClass *dc = DEVICE_CLASS(oc);
674 
675     dc->realize = afx_realize;
676 }
677 
678 static const TypeInfo afx_info = {
679     .name          = TYPE_TCX_AFX,
680     .parent        = TYPE_SYS_BUS_DEVICE,
681     .instance_size = sizeof(AFXState),
682     .class_init    = afx_class_init,
683 };
684 
685 #define TYPE_OPENPROM "openprom"
686 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
687 
688 typedef struct PROMState {
689     SysBusDevice parent_obj;
690 
691     MemoryRegion prom;
692 } PROMState;
693 
694 /* Boot PROM (OpenBIOS) */
695 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
696 {
697     hwaddr *base_addr = (hwaddr *)opaque;
698     return addr + *base_addr - PROM_VADDR;
699 }
700 
701 static void prom_init(hwaddr addr, const char *bios_name)
702 {
703     DeviceState *dev;
704     SysBusDevice *s;
705     char *filename;
706     int ret;
707 
708     dev = qdev_create(NULL, TYPE_OPENPROM);
709     qdev_init_nofail(dev);
710     s = SYS_BUS_DEVICE(dev);
711 
712     sysbus_mmio_map(s, 0, addr);
713 
714     /* load boot prom */
715     if (bios_name == NULL) {
716         bios_name = PROM_FILENAME;
717     }
718     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
719     if (filename) {
720         ret = load_elf(filename, NULL,
721                        translate_prom_address, &addr, NULL,
722                        NULL, NULL, 1, EM_SPARC, 0, 0);
723         if (ret < 0 || ret > PROM_SIZE_MAX) {
724             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
725         }
726         g_free(filename);
727     } else {
728         ret = -1;
729     }
730     if (ret < 0 || ret > PROM_SIZE_MAX) {
731         error_report("could not load prom '%s'", bios_name);
732         exit(1);
733     }
734 }
735 
736 static void prom_realize(DeviceState *ds, Error **errp)
737 {
738     PROMState *s = OPENPROM(ds);
739     SysBusDevice *dev = SYS_BUS_DEVICE(ds);
740     Error *local_err = NULL;
741 
742     memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
743                                      PROM_SIZE_MAX, &local_err);
744     if (local_err) {
745         error_propagate(errp, local_err);
746         return;
747     }
748 
749     vmstate_register_ram_global(&s->prom);
750     memory_region_set_readonly(&s->prom, true);
751     sysbus_init_mmio(dev, &s->prom);
752 }
753 
754 static Property prom_properties[] = {
755     {/* end of property list */},
756 };
757 
758 static void prom_class_init(ObjectClass *klass, void *data)
759 {
760     DeviceClass *dc = DEVICE_CLASS(klass);
761 
762     dc->props = prom_properties;
763     dc->realize = prom_realize;
764 }
765 
766 static const TypeInfo prom_info = {
767     .name          = TYPE_OPENPROM,
768     .parent        = TYPE_SYS_BUS_DEVICE,
769     .instance_size = sizeof(PROMState),
770     .class_init    = prom_class_init,
771 };
772 
773 #define TYPE_SUN4M_MEMORY "memory"
774 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
775 
776 typedef struct RamDevice {
777     SysBusDevice parent_obj;
778 
779     MemoryRegion ram;
780     uint64_t size;
781 } RamDevice;
782 
783 /* System RAM */
784 static void ram_realize(DeviceState *dev, Error **errp)
785 {
786     RamDevice *d = SUN4M_RAM(dev);
787     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
788 
789     memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
790                                          d->size);
791     sysbus_init_mmio(sbd, &d->ram);
792 }
793 
794 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
795                      uint64_t max_mem)
796 {
797     DeviceState *dev;
798     SysBusDevice *s;
799     RamDevice *d;
800 
801     /* allocate RAM */
802     if ((uint64_t)RAM_size > max_mem) {
803         error_report("Too much memory for this machine: %" PRId64 ","
804                      " maximum %" PRId64,
805                      RAM_size / MiB, max_mem / MiB);
806         exit(1);
807     }
808     dev = qdev_create(NULL, "memory");
809     s = SYS_BUS_DEVICE(dev);
810 
811     d = SUN4M_RAM(dev);
812     d->size = RAM_size;
813     qdev_init_nofail(dev);
814 
815     sysbus_mmio_map(s, 0, addr);
816 }
817 
818 static Property ram_properties[] = {
819     DEFINE_PROP_UINT64("size", RamDevice, size, 0),
820     DEFINE_PROP_END_OF_LIST(),
821 };
822 
823 static void ram_class_init(ObjectClass *klass, void *data)
824 {
825     DeviceClass *dc = DEVICE_CLASS(klass);
826 
827     dc->realize = ram_realize;
828     dc->props = ram_properties;
829 }
830 
831 static const TypeInfo ram_info = {
832     .name          = TYPE_SUN4M_MEMORY,
833     .parent        = TYPE_SYS_BUS_DEVICE,
834     .instance_size = sizeof(RamDevice),
835     .class_init    = ram_class_init,
836 };
837 
838 static void cpu_devinit(const char *cpu_type, unsigned int id,
839                         uint64_t prom_addr, qemu_irq **cpu_irqs)
840 {
841     CPUState *cs;
842     SPARCCPU *cpu;
843     CPUSPARCState *env;
844 
845     cpu = SPARC_CPU(cpu_create(cpu_type));
846     env = &cpu->env;
847 
848     cpu_sparc_set_id(env, id);
849     if (id == 0) {
850         qemu_register_reset(main_cpu_reset, cpu);
851     } else {
852         qemu_register_reset(secondary_cpu_reset, cpu);
853         cs = CPU(cpu);
854         cs->halted = 1;
855     }
856     *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
857     env->prom_addr = prom_addr;
858 }
859 
860 static void dummy_fdc_tc(void *opaque, int irq, int level)
861 {
862 }
863 
864 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
865                           MachineState *machine)
866 {
867     DeviceState *slavio_intctl;
868     unsigned int i;
869     void *nvram;
870     qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
871     qemu_irq fdc_tc;
872     unsigned long kernel_size;
873     uint32_t initrd_size;
874     DriveInfo *fd[MAX_FD];
875     FWCfgState *fw_cfg;
876     DeviceState *dev;
877     SysBusDevice *s;
878     unsigned int smp_cpus = machine->smp.cpus;
879     unsigned int max_cpus = machine->smp.max_cpus;
880 
881     /* init CPUs */
882     for(i = 0; i < smp_cpus; i++) {
883         cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
884     }
885 
886     for (i = smp_cpus; i < MAX_CPUS; i++)
887         cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
888 
889 
890     /* set up devices */
891     ram_init(0, machine->ram_size, hwdef->max_mem);
892     /* models without ECC don't trap when missing ram is accessed */
893     if (!hwdef->ecc_base) {
894         empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
895     }
896 
897     prom_init(hwdef->slavio_base, bios_name);
898 
899     slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
900                                        hwdef->intctl_base + 0x10000ULL,
901                                        cpu_irqs);
902 
903     for (i = 0; i < 32; i++) {
904         slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
905     }
906     for (i = 0; i < MAX_CPUS; i++) {
907         slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
908     }
909 
910     if (hwdef->idreg_base) {
911         idreg_init(hwdef->idreg_base);
912     }
913 
914     if (hwdef->afx_base) {
915         afx_init(hwdef->afx_base);
916     }
917 
918     iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
919 
920     if (hwdef->iommu_pad_base) {
921         /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
922            Software shouldn't use aliased addresses, neither should it crash
923            when does. Using empty_slot instead of aliasing can help with
924            debugging such accesses */
925         empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
926     }
927 
928     sparc32_dma_init(hwdef->dma_base,
929                      hwdef->esp_base, slavio_irq[18],
930                      hwdef->le_base, slavio_irq[16]);
931 
932     if (graphic_depth != 8 && graphic_depth != 24) {
933         error_report("Unsupported depth: %d", graphic_depth);
934         exit (1);
935     }
936     if (vga_interface_type != VGA_NONE) {
937         if (vga_interface_type == VGA_CG3) {
938             if (graphic_depth != 8) {
939                 error_report("Unsupported depth: %d", graphic_depth);
940                 exit(1);
941             }
942 
943             if (!(graphic_width == 1024 && graphic_height == 768) &&
944                 !(graphic_width == 1152 && graphic_height == 900)) {
945                 error_report("Unsupported resolution: %d x %d", graphic_width,
946                              graphic_height);
947                 exit(1);
948             }
949 
950             /* sbus irq 5 */
951             cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
952                      graphic_width, graphic_height, graphic_depth);
953         } else {
954             /* If no display specified, default to TCX */
955             if (graphic_depth != 8 && graphic_depth != 24) {
956                 error_report("Unsupported depth: %d", graphic_depth);
957                 exit(1);
958             }
959 
960             if (!(graphic_width == 1024 && graphic_height == 768)) {
961                 error_report("Unsupported resolution: %d x %d",
962                              graphic_width, graphic_height);
963                 exit(1);
964             }
965 
966             tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
967                      graphic_width, graphic_height, graphic_depth);
968         }
969     }
970 
971     for (i = 0; i < MAX_VSIMMS; i++) {
972         /* vsimm registers probed by OBP */
973         if (hwdef->vsimm[i].reg_base) {
974             empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
975         }
976     }
977 
978     if (hwdef->sx_base) {
979         empty_slot_init(hwdef->sx_base, 0x2000);
980     }
981 
982     nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
983 
984     slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
985 
986     /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
987        Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
988     dev = qdev_create(NULL, TYPE_ESCC);
989     qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
990     qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
991     qdev_prop_set_uint32(dev, "it_shift", 1);
992     qdev_prop_set_chr(dev, "chrB", NULL);
993     qdev_prop_set_chr(dev, "chrA", NULL);
994     qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
995     qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
996     qdev_init_nofail(dev);
997     s = SYS_BUS_DEVICE(dev);
998     sysbus_connect_irq(s, 0, slavio_irq[14]);
999     sysbus_connect_irq(s, 1, slavio_irq[14]);
1000     sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
1001 
1002     dev = qdev_create(NULL, TYPE_ESCC);
1003     qdev_prop_set_uint32(dev, "disabled", 0);
1004     qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
1005     qdev_prop_set_uint32(dev, "it_shift", 1);
1006     qdev_prop_set_chr(dev, "chrB", serial_hd(1));
1007     qdev_prop_set_chr(dev, "chrA", serial_hd(0));
1008     qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
1009     qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
1010     qdev_init_nofail(dev);
1011 
1012     s = SYS_BUS_DEVICE(dev);
1013     sysbus_connect_irq(s, 0, slavio_irq[15]);
1014     sysbus_connect_irq(s, 1,  slavio_irq[15]);
1015     sysbus_mmio_map(s, 0, hwdef->serial_base);
1016 
1017     if (hwdef->apc_base) {
1018         apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
1019     }
1020 
1021     if (hwdef->fd_base) {
1022         /* there is zero or one floppy drive */
1023         memset(fd, 0, sizeof(fd));
1024         fd[0] = drive_get(IF_FLOPPY, 0, 0);
1025         sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1026                           &fdc_tc);
1027     } else {
1028         fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1029     }
1030 
1031     slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1032                      slavio_irq[30], fdc_tc);
1033 
1034     if (hwdef->cs_base) {
1035         sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1036                              slavio_irq[5]);
1037     }
1038 
1039     if (hwdef->dbri_base) {
1040         /* ISDN chip with attached CS4215 audio codec */
1041         /* prom space */
1042         empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1043         /* reg space */
1044         empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1045     }
1046 
1047     if (hwdef->bpp_base) {
1048         /* parallel port */
1049         empty_slot_init(hwdef->bpp_base, 0x20);
1050     }
1051 
1052     initrd_size = 0;
1053     kernel_size = sun4m_load_kernel(machine->kernel_filename,
1054                                     machine->initrd_filename,
1055                                     machine->ram_size, &initrd_size);
1056 
1057     nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1058                machine->boot_order, machine->ram_size, kernel_size,
1059                graphic_width, graphic_height, graphic_depth,
1060                hwdef->nvram_machine_id, "Sun4m");
1061 
1062     if (hwdef->ecc_base)
1063         ecc_init(hwdef->ecc_base, slavio_irq[28],
1064                  hwdef->ecc_version);
1065 
1066     dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
1067     fw_cfg = FW_CFG(dev);
1068     qdev_prop_set_uint32(dev, "data_width", 1);
1069     qdev_prop_set_bit(dev, "dma_enabled", false);
1070     object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1071                               OBJECT(fw_cfg), NULL);
1072     qdev_init_nofail(dev);
1073     s = SYS_BUS_DEVICE(dev);
1074     sysbus_mmio_map(s, 0, CFG_ADDR);
1075     sysbus_mmio_map(s, 1, CFG_ADDR + 2);
1076 
1077     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1078     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1079     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1080     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1081     fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1082     fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1083     fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1084     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1085     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1086     if (machine->kernel_cmdline) {
1087         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1088         pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1089                          machine->kernel_cmdline);
1090         fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1091         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1092                        strlen(machine->kernel_cmdline) + 1);
1093     } else {
1094         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1095         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1096     }
1097     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1098     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1099     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1100     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1101 }
1102 
1103 enum {
1104     ss5_id = 32,
1105     vger_id,
1106     lx_id,
1107     ss4_id,
1108     scls_id,
1109     sbook_id,
1110     ss10_id = 64,
1111     ss20_id,
1112     ss600mp_id,
1113 };
1114 
1115 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1116     /* SS-5 */
1117     {
1118         .iommu_base   = 0x10000000,
1119         .iommu_pad_base = 0x10004000,
1120         .iommu_pad_len  = 0x0fffb000,
1121         .tcx_base     = 0x50000000,
1122         .cs_base      = 0x6c000000,
1123         .slavio_base  = 0x70000000,
1124         .ms_kb_base   = 0x71000000,
1125         .serial_base  = 0x71100000,
1126         .nvram_base   = 0x71200000,
1127         .fd_base      = 0x71400000,
1128         .counter_base = 0x71d00000,
1129         .intctl_base  = 0x71e00000,
1130         .idreg_base   = 0x78000000,
1131         .dma_base     = 0x78400000,
1132         .esp_base     = 0x78800000,
1133         .le_base      = 0x78c00000,
1134         .apc_base     = 0x6a000000,
1135         .afx_base     = 0x6e000000,
1136         .aux1_base    = 0x71900000,
1137         .aux2_base    = 0x71910000,
1138         .nvram_machine_id = 0x80,
1139         .machine_id = ss5_id,
1140         .iommu_version = 0x05000000,
1141         .max_mem = 0x10000000,
1142     },
1143     /* SS-10 */
1144     {
1145         .iommu_base   = 0xfe0000000ULL,
1146         .tcx_base     = 0xe20000000ULL,
1147         .slavio_base  = 0xff0000000ULL,
1148         .ms_kb_base   = 0xff1000000ULL,
1149         .serial_base  = 0xff1100000ULL,
1150         .nvram_base   = 0xff1200000ULL,
1151         .fd_base      = 0xff1700000ULL,
1152         .counter_base = 0xff1300000ULL,
1153         .intctl_base  = 0xff1400000ULL,
1154         .idreg_base   = 0xef0000000ULL,
1155         .dma_base     = 0xef0400000ULL,
1156         .esp_base     = 0xef0800000ULL,
1157         .le_base      = 0xef0c00000ULL,
1158         .apc_base     = 0xefa000000ULL, // XXX should not exist
1159         .aux1_base    = 0xff1800000ULL,
1160         .aux2_base    = 0xff1a01000ULL,
1161         .ecc_base     = 0xf00000000ULL,
1162         .ecc_version  = 0x10000000, // version 0, implementation 1
1163         .nvram_machine_id = 0x72,
1164         .machine_id = ss10_id,
1165         .iommu_version = 0x03000000,
1166         .max_mem = 0xf00000000ULL,
1167     },
1168     /* SS-600MP */
1169     {
1170         .iommu_base   = 0xfe0000000ULL,
1171         .tcx_base     = 0xe20000000ULL,
1172         .slavio_base  = 0xff0000000ULL,
1173         .ms_kb_base   = 0xff1000000ULL,
1174         .serial_base  = 0xff1100000ULL,
1175         .nvram_base   = 0xff1200000ULL,
1176         .counter_base = 0xff1300000ULL,
1177         .intctl_base  = 0xff1400000ULL,
1178         .dma_base     = 0xef0081000ULL,
1179         .esp_base     = 0xef0080000ULL,
1180         .le_base      = 0xef0060000ULL,
1181         .apc_base     = 0xefa000000ULL, // XXX should not exist
1182         .aux1_base    = 0xff1800000ULL,
1183         .aux2_base    = 0xff1a01000ULL, // XXX should not exist
1184         .ecc_base     = 0xf00000000ULL,
1185         .ecc_version  = 0x00000000, // version 0, implementation 0
1186         .nvram_machine_id = 0x71,
1187         .machine_id = ss600mp_id,
1188         .iommu_version = 0x01000000,
1189         .max_mem = 0xf00000000ULL,
1190     },
1191     /* SS-20 */
1192     {
1193         .iommu_base   = 0xfe0000000ULL,
1194         .tcx_base     = 0xe20000000ULL,
1195         .slavio_base  = 0xff0000000ULL,
1196         .ms_kb_base   = 0xff1000000ULL,
1197         .serial_base  = 0xff1100000ULL,
1198         .nvram_base   = 0xff1200000ULL,
1199         .fd_base      = 0xff1700000ULL,
1200         .counter_base = 0xff1300000ULL,
1201         .intctl_base  = 0xff1400000ULL,
1202         .idreg_base   = 0xef0000000ULL,
1203         .dma_base     = 0xef0400000ULL,
1204         .esp_base     = 0xef0800000ULL,
1205         .le_base      = 0xef0c00000ULL,
1206         .bpp_base     = 0xef4800000ULL,
1207         .apc_base     = 0xefa000000ULL, // XXX should not exist
1208         .aux1_base    = 0xff1800000ULL,
1209         .aux2_base    = 0xff1a01000ULL,
1210         .dbri_base    = 0xee0000000ULL,
1211         .sx_base      = 0xf80000000ULL,
1212         .vsimm        = {
1213             {
1214                 .reg_base  = 0x9c000000ULL,
1215                 .vram_base = 0xfc000000ULL
1216             }, {
1217                 .reg_base  = 0x90000000ULL,
1218                 .vram_base = 0xf0000000ULL
1219             }, {
1220                 .reg_base  = 0x94000000ULL
1221             }, {
1222                 .reg_base  = 0x98000000ULL
1223             }
1224         },
1225         .ecc_base     = 0xf00000000ULL,
1226         .ecc_version  = 0x20000000, // version 0, implementation 2
1227         .nvram_machine_id = 0x72,
1228         .machine_id = ss20_id,
1229         .iommu_version = 0x13000000,
1230         .max_mem = 0xf00000000ULL,
1231     },
1232     /* Voyager */
1233     {
1234         .iommu_base   = 0x10000000,
1235         .tcx_base     = 0x50000000,
1236         .slavio_base  = 0x70000000,
1237         .ms_kb_base   = 0x71000000,
1238         .serial_base  = 0x71100000,
1239         .nvram_base   = 0x71200000,
1240         .fd_base      = 0x71400000,
1241         .counter_base = 0x71d00000,
1242         .intctl_base  = 0x71e00000,
1243         .idreg_base   = 0x78000000,
1244         .dma_base     = 0x78400000,
1245         .esp_base     = 0x78800000,
1246         .le_base      = 0x78c00000,
1247         .apc_base     = 0x71300000, // pmc
1248         .aux1_base    = 0x71900000,
1249         .aux2_base    = 0x71910000,
1250         .nvram_machine_id = 0x80,
1251         .machine_id = vger_id,
1252         .iommu_version = 0x05000000,
1253         .max_mem = 0x10000000,
1254     },
1255     /* LX */
1256     {
1257         .iommu_base   = 0x10000000,
1258         .iommu_pad_base = 0x10004000,
1259         .iommu_pad_len  = 0x0fffb000,
1260         .tcx_base     = 0x50000000,
1261         .slavio_base  = 0x70000000,
1262         .ms_kb_base   = 0x71000000,
1263         .serial_base  = 0x71100000,
1264         .nvram_base   = 0x71200000,
1265         .fd_base      = 0x71400000,
1266         .counter_base = 0x71d00000,
1267         .intctl_base  = 0x71e00000,
1268         .idreg_base   = 0x78000000,
1269         .dma_base     = 0x78400000,
1270         .esp_base     = 0x78800000,
1271         .le_base      = 0x78c00000,
1272         .aux1_base    = 0x71900000,
1273         .aux2_base    = 0x71910000,
1274         .nvram_machine_id = 0x80,
1275         .machine_id = lx_id,
1276         .iommu_version = 0x04000000,
1277         .max_mem = 0x10000000,
1278     },
1279     /* SS-4 */
1280     {
1281         .iommu_base   = 0x10000000,
1282         .tcx_base     = 0x50000000,
1283         .cs_base      = 0x6c000000,
1284         .slavio_base  = 0x70000000,
1285         .ms_kb_base   = 0x71000000,
1286         .serial_base  = 0x71100000,
1287         .nvram_base   = 0x71200000,
1288         .fd_base      = 0x71400000,
1289         .counter_base = 0x71d00000,
1290         .intctl_base  = 0x71e00000,
1291         .idreg_base   = 0x78000000,
1292         .dma_base     = 0x78400000,
1293         .esp_base     = 0x78800000,
1294         .le_base      = 0x78c00000,
1295         .apc_base     = 0x6a000000,
1296         .aux1_base    = 0x71900000,
1297         .aux2_base    = 0x71910000,
1298         .nvram_machine_id = 0x80,
1299         .machine_id = ss4_id,
1300         .iommu_version = 0x05000000,
1301         .max_mem = 0x10000000,
1302     },
1303     /* SPARCClassic */
1304     {
1305         .iommu_base   = 0x10000000,
1306         .tcx_base     = 0x50000000,
1307         .slavio_base  = 0x70000000,
1308         .ms_kb_base   = 0x71000000,
1309         .serial_base  = 0x71100000,
1310         .nvram_base   = 0x71200000,
1311         .fd_base      = 0x71400000,
1312         .counter_base = 0x71d00000,
1313         .intctl_base  = 0x71e00000,
1314         .idreg_base   = 0x78000000,
1315         .dma_base     = 0x78400000,
1316         .esp_base     = 0x78800000,
1317         .le_base      = 0x78c00000,
1318         .apc_base     = 0x6a000000,
1319         .aux1_base    = 0x71900000,
1320         .aux2_base    = 0x71910000,
1321         .nvram_machine_id = 0x80,
1322         .machine_id = scls_id,
1323         .iommu_version = 0x05000000,
1324         .max_mem = 0x10000000,
1325     },
1326     /* SPARCbook */
1327     {
1328         .iommu_base   = 0x10000000,
1329         .tcx_base     = 0x50000000, // XXX
1330         .slavio_base  = 0x70000000,
1331         .ms_kb_base   = 0x71000000,
1332         .serial_base  = 0x71100000,
1333         .nvram_base   = 0x71200000,
1334         .fd_base      = 0x71400000,
1335         .counter_base = 0x71d00000,
1336         .intctl_base  = 0x71e00000,
1337         .idreg_base   = 0x78000000,
1338         .dma_base     = 0x78400000,
1339         .esp_base     = 0x78800000,
1340         .le_base      = 0x78c00000,
1341         .apc_base     = 0x6a000000,
1342         .aux1_base    = 0x71900000,
1343         .aux2_base    = 0x71910000,
1344         .nvram_machine_id = 0x80,
1345         .machine_id = sbook_id,
1346         .iommu_version = 0x05000000,
1347         .max_mem = 0x10000000,
1348     },
1349 };
1350 
1351 /* SPARCstation 5 hardware initialisation */
1352 static void ss5_init(MachineState *machine)
1353 {
1354     sun4m_hw_init(&sun4m_hwdefs[0], machine);
1355 }
1356 
1357 /* SPARCstation 10 hardware initialisation */
1358 static void ss10_init(MachineState *machine)
1359 {
1360     sun4m_hw_init(&sun4m_hwdefs[1], machine);
1361 }
1362 
1363 /* SPARCserver 600MP hardware initialisation */
1364 static void ss600mp_init(MachineState *machine)
1365 {
1366     sun4m_hw_init(&sun4m_hwdefs[2], machine);
1367 }
1368 
1369 /* SPARCstation 20 hardware initialisation */
1370 static void ss20_init(MachineState *machine)
1371 {
1372     sun4m_hw_init(&sun4m_hwdefs[3], machine);
1373 }
1374 
1375 /* SPARCstation Voyager hardware initialisation */
1376 static void vger_init(MachineState *machine)
1377 {
1378     sun4m_hw_init(&sun4m_hwdefs[4], machine);
1379 }
1380 
1381 /* SPARCstation LX hardware initialisation */
1382 static void ss_lx_init(MachineState *machine)
1383 {
1384     sun4m_hw_init(&sun4m_hwdefs[5], machine);
1385 }
1386 
1387 /* SPARCstation 4 hardware initialisation */
1388 static void ss4_init(MachineState *machine)
1389 {
1390     sun4m_hw_init(&sun4m_hwdefs[6], machine);
1391 }
1392 
1393 /* SPARCClassic hardware initialisation */
1394 static void scls_init(MachineState *machine)
1395 {
1396     sun4m_hw_init(&sun4m_hwdefs[7], machine);
1397 }
1398 
1399 /* SPARCbook hardware initialisation */
1400 static void sbook_init(MachineState *machine)
1401 {
1402     sun4m_hw_init(&sun4m_hwdefs[8], machine);
1403 }
1404 
1405 static void ss5_class_init(ObjectClass *oc, void *data)
1406 {
1407     MachineClass *mc = MACHINE_CLASS(oc);
1408 
1409     mc->desc = "Sun4m platform, SPARCstation 5";
1410     mc->init = ss5_init;
1411     mc->block_default_type = IF_SCSI;
1412     mc->is_default = 1;
1413     mc->default_boot_order = "c";
1414     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1415     mc->default_display = "tcx";
1416 }
1417 
1418 static const TypeInfo ss5_type = {
1419     .name = MACHINE_TYPE_NAME("SS-5"),
1420     .parent = TYPE_MACHINE,
1421     .class_init = ss5_class_init,
1422 };
1423 
1424 static void ss10_class_init(ObjectClass *oc, void *data)
1425 {
1426     MachineClass *mc = MACHINE_CLASS(oc);
1427 
1428     mc->desc = "Sun4m platform, SPARCstation 10";
1429     mc->init = ss10_init;
1430     mc->block_default_type = IF_SCSI;
1431     mc->max_cpus = 4;
1432     mc->default_boot_order = "c";
1433     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1434     mc->default_display = "tcx";
1435 }
1436 
1437 static const TypeInfo ss10_type = {
1438     .name = MACHINE_TYPE_NAME("SS-10"),
1439     .parent = TYPE_MACHINE,
1440     .class_init = ss10_class_init,
1441 };
1442 
1443 static void ss600mp_class_init(ObjectClass *oc, void *data)
1444 {
1445     MachineClass *mc = MACHINE_CLASS(oc);
1446 
1447     mc->desc = "Sun4m platform, SPARCserver 600MP";
1448     mc->init = ss600mp_init;
1449     mc->block_default_type = IF_SCSI;
1450     mc->max_cpus = 4;
1451     mc->default_boot_order = "c";
1452     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1453     mc->default_display = "tcx";
1454 }
1455 
1456 static const TypeInfo ss600mp_type = {
1457     .name = MACHINE_TYPE_NAME("SS-600MP"),
1458     .parent = TYPE_MACHINE,
1459     .class_init = ss600mp_class_init,
1460 };
1461 
1462 static void ss20_class_init(ObjectClass *oc, void *data)
1463 {
1464     MachineClass *mc = MACHINE_CLASS(oc);
1465 
1466     mc->desc = "Sun4m platform, SPARCstation 20";
1467     mc->init = ss20_init;
1468     mc->block_default_type = IF_SCSI;
1469     mc->max_cpus = 4;
1470     mc->default_boot_order = "c";
1471     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1472     mc->default_display = "tcx";
1473 }
1474 
1475 static const TypeInfo ss20_type = {
1476     .name = MACHINE_TYPE_NAME("SS-20"),
1477     .parent = TYPE_MACHINE,
1478     .class_init = ss20_class_init,
1479 };
1480 
1481 static void voyager_class_init(ObjectClass *oc, void *data)
1482 {
1483     MachineClass *mc = MACHINE_CLASS(oc);
1484 
1485     mc->desc = "Sun4m platform, SPARCstation Voyager";
1486     mc->init = vger_init;
1487     mc->block_default_type = IF_SCSI;
1488     mc->default_boot_order = "c";
1489     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1490     mc->default_display = "tcx";
1491 }
1492 
1493 static const TypeInfo voyager_type = {
1494     .name = MACHINE_TYPE_NAME("Voyager"),
1495     .parent = TYPE_MACHINE,
1496     .class_init = voyager_class_init,
1497 };
1498 
1499 static void ss_lx_class_init(ObjectClass *oc, void *data)
1500 {
1501     MachineClass *mc = MACHINE_CLASS(oc);
1502 
1503     mc->desc = "Sun4m platform, SPARCstation LX";
1504     mc->init = ss_lx_init;
1505     mc->block_default_type = IF_SCSI;
1506     mc->default_boot_order = "c";
1507     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1508     mc->default_display = "tcx";
1509 }
1510 
1511 static const TypeInfo ss_lx_type = {
1512     .name = MACHINE_TYPE_NAME("LX"),
1513     .parent = TYPE_MACHINE,
1514     .class_init = ss_lx_class_init,
1515 };
1516 
1517 static void ss4_class_init(ObjectClass *oc, void *data)
1518 {
1519     MachineClass *mc = MACHINE_CLASS(oc);
1520 
1521     mc->desc = "Sun4m platform, SPARCstation 4";
1522     mc->init = ss4_init;
1523     mc->block_default_type = IF_SCSI;
1524     mc->default_boot_order = "c";
1525     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1526     mc->default_display = "tcx";
1527 }
1528 
1529 static const TypeInfo ss4_type = {
1530     .name = MACHINE_TYPE_NAME("SS-4"),
1531     .parent = TYPE_MACHINE,
1532     .class_init = ss4_class_init,
1533 };
1534 
1535 static void scls_class_init(ObjectClass *oc, void *data)
1536 {
1537     MachineClass *mc = MACHINE_CLASS(oc);
1538 
1539     mc->desc = "Sun4m platform, SPARCClassic";
1540     mc->init = scls_init;
1541     mc->block_default_type = IF_SCSI;
1542     mc->default_boot_order = "c";
1543     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1544     mc->default_display = "tcx";
1545 }
1546 
1547 static const TypeInfo scls_type = {
1548     .name = MACHINE_TYPE_NAME("SPARCClassic"),
1549     .parent = TYPE_MACHINE,
1550     .class_init = scls_class_init,
1551 };
1552 
1553 static void sbook_class_init(ObjectClass *oc, void *data)
1554 {
1555     MachineClass *mc = MACHINE_CLASS(oc);
1556 
1557     mc->desc = "Sun4m platform, SPARCbook";
1558     mc->init = sbook_init;
1559     mc->block_default_type = IF_SCSI;
1560     mc->default_boot_order = "c";
1561     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1562     mc->default_display = "tcx";
1563 }
1564 
1565 static const TypeInfo sbook_type = {
1566     .name = MACHINE_TYPE_NAME("SPARCbook"),
1567     .parent = TYPE_MACHINE,
1568     .class_init = sbook_class_init,
1569 };
1570 
1571 static void sun4m_register_types(void)
1572 {
1573     type_register_static(&idreg_info);
1574     type_register_static(&afx_info);
1575     type_register_static(&prom_info);
1576     type_register_static(&ram_info);
1577 
1578     type_register_static(&ss5_type);
1579     type_register_static(&ss10_type);
1580     type_register_static(&ss600mp_type);
1581     type_register_static(&ss20_type);
1582     type_register_static(&voyager_type);
1583     type_register_static(&ss_lx_type);
1584     type_register_static(&ss4_type);
1585     type_register_static(&scls_type);
1586     type_register_static(&sbook_type);
1587 }
1588 
1589 type_init(sun4m_register_types)
1590