1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/sysbus.h" 29 #include "qemu/error-report.h" 30 #include "qemu/timer.h" 31 #include "hw/sparc/sun4m.h" 32 #include "hw/timer/m48t59.h" 33 #include "hw/sparc/sparc32_dma.h" 34 #include "hw/block/fdc.h" 35 #include "sysemu/sysemu.h" 36 #include "net/net.h" 37 #include "hw/boards.h" 38 #include "hw/scsi/esp.h" 39 #include "hw/isa/isa.h" 40 #include "hw/nvram/sun_nvram.h" 41 #include "hw/nvram/chrp_nvram.h" 42 #include "hw/nvram/fw_cfg.h" 43 #include "hw/char/escc.h" 44 #include "hw/empty_slot.h" 45 #include "hw/loader.h" 46 #include "elf.h" 47 #include "sysemu/block-backend.h" 48 #include "trace.h" 49 #include "qemu/cutils.h" 50 51 /* 52 * Sun4m architecture was used in the following machines: 53 * 54 * SPARCserver 6xxMP/xx 55 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 56 * SPARCclassic X (4/10) 57 * SPARCstation LX/ZX (4/30) 58 * SPARCstation Voyager 59 * SPARCstation 10/xx, SPARCserver 10/xx 60 * SPARCstation 5, SPARCserver 5 61 * SPARCstation 20/xx, SPARCserver 20 62 * SPARCstation 4 63 * 64 * See for example: http://www.sunhelp.org/faq/sunref1.html 65 */ 66 67 #define KERNEL_LOAD_ADDR 0x00004000 68 #define CMDLINE_ADDR 0x007ff000 69 #define INITRD_LOAD_ADDR 0x00800000 70 #define PROM_SIZE_MAX (1024 * 1024) 71 #define PROM_VADDR 0xffd00000 72 #define PROM_FILENAME "openbios-sparc32" 73 #define CFG_ADDR 0xd00000510ULL 74 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 75 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 76 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 77 78 #define MAX_CPUS 16 79 #define MAX_PILS 16 80 #define MAX_VSIMMS 4 81 82 #define ESCC_CLOCK 4915200 83 84 struct sun4m_hwdef { 85 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 86 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 87 hwaddr serial_base, fd_base; 88 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 89 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 90 hwaddr bpp_base, dbri_base, sx_base; 91 struct { 92 hwaddr reg_base, vram_base; 93 } vsimm[MAX_VSIMMS]; 94 hwaddr ecc_base; 95 uint64_t max_mem; 96 uint32_t ecc_version; 97 uint32_t iommu_version; 98 uint16_t machine_id; 99 uint8_t nvram_machine_id; 100 }; 101 102 void DMA_init(ISABus *bus, int high_page_enable) 103 { 104 } 105 106 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 107 Error **errp) 108 { 109 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 110 } 111 112 static void nvram_init(Nvram *nvram, uint8_t *macaddr, 113 const char *cmdline, const char *boot_devices, 114 ram_addr_t RAM_size, uint32_t kernel_size, 115 int width, int height, int depth, 116 int nvram_machine_id, const char *arch) 117 { 118 unsigned int i; 119 int sysp_end; 120 uint8_t image[0x1ff0]; 121 NvramClass *k = NVRAM_GET_CLASS(nvram); 122 123 memset(image, '\0', sizeof(image)); 124 125 /* OpenBIOS nvram variables partition */ 126 sysp_end = chrp_nvram_create_system_partition(image, 0); 127 128 /* Free space partition */ 129 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 130 131 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 132 nvram_machine_id); 133 134 for (i = 0; i < sizeof(image); i++) { 135 (k->write)(nvram, i, image[i]); 136 } 137 } 138 139 void cpu_check_irqs(CPUSPARCState *env) 140 { 141 CPUState *cs; 142 143 /* We should be holding the BQL before we mess with IRQs */ 144 g_assert(qemu_mutex_iothread_locked()); 145 146 if (env->pil_in && (env->interrupt_index == 0 || 147 (env->interrupt_index & ~15) == TT_EXTINT)) { 148 unsigned int i; 149 150 for (i = 15; i > 0; i--) { 151 if (env->pil_in & (1 << i)) { 152 int old_interrupt = env->interrupt_index; 153 154 env->interrupt_index = TT_EXTINT | i; 155 if (old_interrupt != env->interrupt_index) { 156 cs = CPU(sparc_env_get_cpu(env)); 157 trace_sun4m_cpu_interrupt(i); 158 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 159 } 160 break; 161 } 162 } 163 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 164 cs = CPU(sparc_env_get_cpu(env)); 165 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 166 env->interrupt_index = 0; 167 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 168 } 169 } 170 171 static void cpu_kick_irq(SPARCCPU *cpu) 172 { 173 CPUSPARCState *env = &cpu->env; 174 CPUState *cs = CPU(cpu); 175 176 cs->halted = 0; 177 cpu_check_irqs(env); 178 qemu_cpu_kick(cs); 179 } 180 181 static void cpu_set_irq(void *opaque, int irq, int level) 182 { 183 SPARCCPU *cpu = opaque; 184 CPUSPARCState *env = &cpu->env; 185 186 if (level) { 187 trace_sun4m_cpu_set_irq_raise(irq); 188 env->pil_in |= 1 << irq; 189 cpu_kick_irq(cpu); 190 } else { 191 trace_sun4m_cpu_set_irq_lower(irq); 192 env->pil_in &= ~(1 << irq); 193 cpu_check_irqs(env); 194 } 195 } 196 197 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 198 { 199 } 200 201 static void main_cpu_reset(void *opaque) 202 { 203 SPARCCPU *cpu = opaque; 204 CPUState *cs = CPU(cpu); 205 206 cpu_reset(cs); 207 cs->halted = 0; 208 } 209 210 static void secondary_cpu_reset(void *opaque) 211 { 212 SPARCCPU *cpu = opaque; 213 CPUState *cs = CPU(cpu); 214 215 cpu_reset(cs); 216 cs->halted = 1; 217 } 218 219 static void cpu_halt_signal(void *opaque, int irq, int level) 220 { 221 if (level && current_cpu) { 222 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 223 } 224 } 225 226 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 227 { 228 return addr - 0xf0000000ULL; 229 } 230 231 static unsigned long sun4m_load_kernel(const char *kernel_filename, 232 const char *initrd_filename, 233 ram_addr_t RAM_size) 234 { 235 int linux_boot; 236 unsigned int i; 237 long initrd_size, kernel_size; 238 uint8_t *ptr; 239 240 linux_boot = (kernel_filename != NULL); 241 242 kernel_size = 0; 243 if (linux_boot) { 244 int bswap_needed; 245 246 #ifdef BSWAP_NEEDED 247 bswap_needed = 1; 248 #else 249 bswap_needed = 0; 250 #endif 251 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 252 NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 253 if (kernel_size < 0) 254 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 255 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 256 TARGET_PAGE_SIZE); 257 if (kernel_size < 0) 258 kernel_size = load_image_targphys(kernel_filename, 259 KERNEL_LOAD_ADDR, 260 RAM_size - KERNEL_LOAD_ADDR); 261 if (kernel_size < 0) { 262 fprintf(stderr, "qemu: could not load kernel '%s'\n", 263 kernel_filename); 264 exit(1); 265 } 266 267 /* load initrd */ 268 initrd_size = 0; 269 if (initrd_filename) { 270 initrd_size = load_image_targphys(initrd_filename, 271 INITRD_LOAD_ADDR, 272 RAM_size - INITRD_LOAD_ADDR); 273 if (initrd_size < 0) { 274 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 275 initrd_filename); 276 exit(1); 277 } 278 } 279 if (initrd_size > 0) { 280 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 281 ptr = rom_ptr(KERNEL_LOAD_ADDR + i); 282 if (ldl_p(ptr) == 0x48647253) { // HdrS 283 stl_p(ptr + 16, INITRD_LOAD_ADDR); 284 stl_p(ptr + 20, initrd_size); 285 break; 286 } 287 } 288 } 289 } 290 return kernel_size; 291 } 292 293 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 294 { 295 DeviceState *dev; 296 SysBusDevice *s; 297 298 dev = qdev_create(NULL, TYPE_SUN4M_IOMMU); 299 qdev_prop_set_uint32(dev, "version", version); 300 qdev_init_nofail(dev); 301 s = SYS_BUS_DEVICE(dev); 302 sysbus_connect_irq(s, 0, irq); 303 sysbus_mmio_map(s, 0, addr); 304 305 return s; 306 } 307 308 static void *sparc32_dma_init(hwaddr dma_base, 309 hwaddr esp_base, qemu_irq espdma_irq, 310 hwaddr le_base, qemu_irq ledma_irq) 311 { 312 DeviceState *dma; 313 ESPDMADeviceState *espdma; 314 LEDMADeviceState *ledma; 315 SysBusESPState *esp; 316 SysBusPCNetState *lance; 317 318 dma = qdev_create(NULL, TYPE_SPARC32_DMA); 319 qdev_init_nofail(dma); 320 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); 321 322 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( 323 OBJECT(dma), "espdma")); 324 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); 325 326 esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp")); 327 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base); 328 329 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( 330 OBJECT(dma), "ledma")); 331 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq); 332 333 lance = SYSBUS_PCNET(object_resolve_path_component( 334 OBJECT(ledma), "lance")); 335 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base); 336 337 return dma; 338 } 339 340 static DeviceState *slavio_intctl_init(hwaddr addr, 341 hwaddr addrg, 342 qemu_irq **parent_irq) 343 { 344 DeviceState *dev; 345 SysBusDevice *s; 346 unsigned int i, j; 347 348 dev = qdev_create(NULL, "slavio_intctl"); 349 qdev_init_nofail(dev); 350 351 s = SYS_BUS_DEVICE(dev); 352 353 for (i = 0; i < MAX_CPUS; i++) { 354 for (j = 0; j < MAX_PILS; j++) { 355 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 356 } 357 } 358 sysbus_mmio_map(s, 0, addrg); 359 for (i = 0; i < MAX_CPUS; i++) { 360 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 361 } 362 363 return dev; 364 } 365 366 #define SYS_TIMER_OFFSET 0x10000ULL 367 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 368 369 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 370 qemu_irq *cpu_irqs, unsigned int num_cpus) 371 { 372 DeviceState *dev; 373 SysBusDevice *s; 374 unsigned int i; 375 376 dev = qdev_create(NULL, "slavio_timer"); 377 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 378 qdev_init_nofail(dev); 379 s = SYS_BUS_DEVICE(dev); 380 sysbus_connect_irq(s, 0, master_irq); 381 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 382 383 for (i = 0; i < MAX_CPUS; i++) { 384 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 385 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 386 } 387 } 388 389 static qemu_irq slavio_system_powerdown; 390 391 static void slavio_powerdown_req(Notifier *n, void *opaque) 392 { 393 qemu_irq_raise(slavio_system_powerdown); 394 } 395 396 static Notifier slavio_system_powerdown_notifier = { 397 .notify = slavio_powerdown_req 398 }; 399 400 #define MISC_LEDS 0x01600000 401 #define MISC_CFG 0x01800000 402 #define MISC_DIAG 0x01a00000 403 #define MISC_MDM 0x01b00000 404 #define MISC_SYS 0x01f00000 405 406 static void slavio_misc_init(hwaddr base, 407 hwaddr aux1_base, 408 hwaddr aux2_base, qemu_irq irq, 409 qemu_irq fdc_tc) 410 { 411 DeviceState *dev; 412 SysBusDevice *s; 413 414 dev = qdev_create(NULL, "slavio_misc"); 415 qdev_init_nofail(dev); 416 s = SYS_BUS_DEVICE(dev); 417 if (base) { 418 /* 8 bit registers */ 419 /* Slavio control */ 420 sysbus_mmio_map(s, 0, base + MISC_CFG); 421 /* Diagnostics */ 422 sysbus_mmio_map(s, 1, base + MISC_DIAG); 423 /* Modem control */ 424 sysbus_mmio_map(s, 2, base + MISC_MDM); 425 /* 16 bit registers */ 426 /* ss600mp diag LEDs */ 427 sysbus_mmio_map(s, 3, base + MISC_LEDS); 428 /* 32 bit registers */ 429 /* System control */ 430 sysbus_mmio_map(s, 4, base + MISC_SYS); 431 } 432 if (aux1_base) { 433 /* AUX 1 (Misc System Functions) */ 434 sysbus_mmio_map(s, 5, aux1_base); 435 } 436 if (aux2_base) { 437 /* AUX 2 (Software Powerdown Control) */ 438 sysbus_mmio_map(s, 6, aux2_base); 439 } 440 sysbus_connect_irq(s, 0, irq); 441 sysbus_connect_irq(s, 1, fdc_tc); 442 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 443 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 444 } 445 446 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 447 { 448 DeviceState *dev; 449 SysBusDevice *s; 450 451 dev = qdev_create(NULL, "eccmemctl"); 452 qdev_prop_set_uint32(dev, "version", version); 453 qdev_init_nofail(dev); 454 s = SYS_BUS_DEVICE(dev); 455 sysbus_connect_irq(s, 0, irq); 456 sysbus_mmio_map(s, 0, base); 457 if (version == 0) { // SS-600MP only 458 sysbus_mmio_map(s, 1, base + 0x1000); 459 } 460 } 461 462 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 463 { 464 DeviceState *dev; 465 SysBusDevice *s; 466 467 dev = qdev_create(NULL, "apc"); 468 qdev_init_nofail(dev); 469 s = SYS_BUS_DEVICE(dev); 470 /* Power management (APC) XXX: not a Slavio device */ 471 sysbus_mmio_map(s, 0, power_base); 472 sysbus_connect_irq(s, 0, cpu_halt); 473 } 474 475 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 476 int height, int depth) 477 { 478 DeviceState *dev; 479 SysBusDevice *s; 480 481 dev = qdev_create(NULL, "SUNW,tcx"); 482 qdev_prop_set_uint32(dev, "vram_size", vram_size); 483 qdev_prop_set_uint16(dev, "width", width); 484 qdev_prop_set_uint16(dev, "height", height); 485 qdev_prop_set_uint16(dev, "depth", depth); 486 qdev_init_nofail(dev); 487 s = SYS_BUS_DEVICE(dev); 488 489 /* 10/ROM : FCode ROM */ 490 sysbus_mmio_map(s, 0, addr); 491 /* 2/STIP : Stipple */ 492 sysbus_mmio_map(s, 1, addr + 0x04000000ULL); 493 /* 3/BLIT : Blitter */ 494 sysbus_mmio_map(s, 2, addr + 0x06000000ULL); 495 /* 5/RSTIP : Raw Stipple */ 496 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); 497 /* 6/RBLIT : Raw Blitter */ 498 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); 499 /* 7/TEC : Transform Engine */ 500 sysbus_mmio_map(s, 5, addr + 0x00700000ULL); 501 /* 8/CMAP : DAC */ 502 sysbus_mmio_map(s, 6, addr + 0x00200000ULL); 503 /* 9/THC : */ 504 if (depth == 8) { 505 sysbus_mmio_map(s, 7, addr + 0x00300000ULL); 506 } else { 507 sysbus_mmio_map(s, 7, addr + 0x00301000ULL); 508 } 509 /* 11/DHC : */ 510 sysbus_mmio_map(s, 8, addr + 0x00240000ULL); 511 /* 12/ALT : */ 512 sysbus_mmio_map(s, 9, addr + 0x00280000ULL); 513 /* 0/DFB8 : 8-bit plane */ 514 sysbus_mmio_map(s, 10, addr + 0x00800000ULL); 515 /* 1/DFB24 : 24bit plane */ 516 sysbus_mmio_map(s, 11, addr + 0x02000000ULL); 517 /* 4/RDFB32: Raw framebuffer. Control plane */ 518 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); 519 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 520 if (depth == 8) { 521 sysbus_mmio_map(s, 13, addr + 0x00301000ULL); 522 } 523 524 sysbus_connect_irq(s, 0, irq); 525 } 526 527 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 528 int height, int depth) 529 { 530 DeviceState *dev; 531 SysBusDevice *s; 532 533 dev = qdev_create(NULL, "cgthree"); 534 qdev_prop_set_uint32(dev, "vram-size", vram_size); 535 qdev_prop_set_uint16(dev, "width", width); 536 qdev_prop_set_uint16(dev, "height", height); 537 qdev_prop_set_uint16(dev, "depth", depth); 538 qdev_init_nofail(dev); 539 s = SYS_BUS_DEVICE(dev); 540 541 /* FCode ROM */ 542 sysbus_mmio_map(s, 0, addr); 543 /* DAC */ 544 sysbus_mmio_map(s, 1, addr + 0x400000ULL); 545 /* 8-bit plane */ 546 sysbus_mmio_map(s, 2, addr + 0x800000ULL); 547 548 sysbus_connect_irq(s, 0, irq); 549 } 550 551 /* NCR89C100/MACIO Internal ID register */ 552 553 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 554 555 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 556 557 static void idreg_init(hwaddr addr) 558 { 559 DeviceState *dev; 560 SysBusDevice *s; 561 562 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER); 563 qdev_init_nofail(dev); 564 s = SYS_BUS_DEVICE(dev); 565 566 sysbus_mmio_map(s, 0, addr); 567 cpu_physical_memory_write_rom(&address_space_memory, 568 addr, idreg_data, sizeof(idreg_data)); 569 } 570 571 #define MACIO_ID_REGISTER(obj) \ 572 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER) 573 574 typedef struct IDRegState { 575 SysBusDevice parent_obj; 576 577 MemoryRegion mem; 578 } IDRegState; 579 580 static void idreg_init1(Object *obj) 581 { 582 IDRegState *s = MACIO_ID_REGISTER(obj); 583 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 584 585 memory_region_init_ram_nomigrate(&s->mem, obj, 586 "sun4m.idreg", sizeof(idreg_data), &error_fatal); 587 vmstate_register_ram_global(&s->mem); 588 memory_region_set_readonly(&s->mem, true); 589 sysbus_init_mmio(dev, &s->mem); 590 } 591 592 static const TypeInfo idreg_info = { 593 .name = TYPE_MACIO_ID_REGISTER, 594 .parent = TYPE_SYS_BUS_DEVICE, 595 .instance_size = sizeof(IDRegState), 596 .instance_init = idreg_init1, 597 }; 598 599 #define TYPE_TCX_AFX "tcx_afx" 600 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX) 601 602 typedef struct AFXState { 603 SysBusDevice parent_obj; 604 605 MemoryRegion mem; 606 } AFXState; 607 608 /* SS-5 TCX AFX register */ 609 static void afx_init(hwaddr addr) 610 { 611 DeviceState *dev; 612 SysBusDevice *s; 613 614 dev = qdev_create(NULL, TYPE_TCX_AFX); 615 qdev_init_nofail(dev); 616 s = SYS_BUS_DEVICE(dev); 617 618 sysbus_mmio_map(s, 0, addr); 619 } 620 621 static void afx_init1(Object *obj) 622 { 623 AFXState *s = TCX_AFX(obj); 624 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 625 626 memory_region_init_ram_nomigrate(&s->mem, obj, "sun4m.afx", 4, &error_fatal); 627 vmstate_register_ram_global(&s->mem); 628 sysbus_init_mmio(dev, &s->mem); 629 } 630 631 static const TypeInfo afx_info = { 632 .name = TYPE_TCX_AFX, 633 .parent = TYPE_SYS_BUS_DEVICE, 634 .instance_size = sizeof(AFXState), 635 .instance_init = afx_init1, 636 }; 637 638 #define TYPE_OPENPROM "openprom" 639 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 640 641 typedef struct PROMState { 642 SysBusDevice parent_obj; 643 644 MemoryRegion prom; 645 } PROMState; 646 647 /* Boot PROM (OpenBIOS) */ 648 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 649 { 650 hwaddr *base_addr = (hwaddr *)opaque; 651 return addr + *base_addr - PROM_VADDR; 652 } 653 654 static void prom_init(hwaddr addr, const char *bios_name) 655 { 656 DeviceState *dev; 657 SysBusDevice *s; 658 char *filename; 659 int ret; 660 661 dev = qdev_create(NULL, TYPE_OPENPROM); 662 qdev_init_nofail(dev); 663 s = SYS_BUS_DEVICE(dev); 664 665 sysbus_mmio_map(s, 0, addr); 666 667 /* load boot prom */ 668 if (bios_name == NULL) { 669 bios_name = PROM_FILENAME; 670 } 671 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 672 if (filename) { 673 ret = load_elf(filename, translate_prom_address, &addr, NULL, 674 NULL, NULL, 1, EM_SPARC, 0, 0); 675 if (ret < 0 || ret > PROM_SIZE_MAX) { 676 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 677 } 678 g_free(filename); 679 } else { 680 ret = -1; 681 } 682 if (ret < 0 || ret > PROM_SIZE_MAX) { 683 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 684 exit(1); 685 } 686 } 687 688 static void prom_init1(Object *obj) 689 { 690 PROMState *s = OPENPROM(obj); 691 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 692 693 memory_region_init_ram_nomigrate(&s->prom, obj, "sun4m.prom", PROM_SIZE_MAX, 694 &error_fatal); 695 vmstate_register_ram_global(&s->prom); 696 memory_region_set_readonly(&s->prom, true); 697 sysbus_init_mmio(dev, &s->prom); 698 } 699 700 static Property prom_properties[] = { 701 {/* end of property list */}, 702 }; 703 704 static void prom_class_init(ObjectClass *klass, void *data) 705 { 706 DeviceClass *dc = DEVICE_CLASS(klass); 707 708 dc->props = prom_properties; 709 } 710 711 static const TypeInfo prom_info = { 712 .name = TYPE_OPENPROM, 713 .parent = TYPE_SYS_BUS_DEVICE, 714 .instance_size = sizeof(PROMState), 715 .class_init = prom_class_init, 716 .instance_init = prom_init1, 717 }; 718 719 #define TYPE_SUN4M_MEMORY "memory" 720 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY) 721 722 typedef struct RamDevice { 723 SysBusDevice parent_obj; 724 725 MemoryRegion ram; 726 uint64_t size; 727 } RamDevice; 728 729 /* System RAM */ 730 static void ram_realize(DeviceState *dev, Error **errp) 731 { 732 RamDevice *d = SUN4M_RAM(dev); 733 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 734 735 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram", 736 d->size); 737 sysbus_init_mmio(sbd, &d->ram); 738 } 739 740 static void ram_init(hwaddr addr, ram_addr_t RAM_size, 741 uint64_t max_mem) 742 { 743 DeviceState *dev; 744 SysBusDevice *s; 745 RamDevice *d; 746 747 /* allocate RAM */ 748 if ((uint64_t)RAM_size > max_mem) { 749 fprintf(stderr, 750 "qemu: Too much memory for this machine: %d, maximum %d\n", 751 (unsigned int)(RAM_size / (1024 * 1024)), 752 (unsigned int)(max_mem / (1024 * 1024))); 753 exit(1); 754 } 755 dev = qdev_create(NULL, "memory"); 756 s = SYS_BUS_DEVICE(dev); 757 758 d = SUN4M_RAM(dev); 759 d->size = RAM_size; 760 qdev_init_nofail(dev); 761 762 sysbus_mmio_map(s, 0, addr); 763 } 764 765 static Property ram_properties[] = { 766 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 767 DEFINE_PROP_END_OF_LIST(), 768 }; 769 770 static void ram_class_init(ObjectClass *klass, void *data) 771 { 772 DeviceClass *dc = DEVICE_CLASS(klass); 773 774 dc->realize = ram_realize; 775 dc->props = ram_properties; 776 } 777 778 static const TypeInfo ram_info = { 779 .name = TYPE_SUN4M_MEMORY, 780 .parent = TYPE_SYS_BUS_DEVICE, 781 .instance_size = sizeof(RamDevice), 782 .class_init = ram_class_init, 783 }; 784 785 static void cpu_devinit(const char *cpu_type, unsigned int id, 786 uint64_t prom_addr, qemu_irq **cpu_irqs) 787 { 788 CPUState *cs; 789 SPARCCPU *cpu; 790 CPUSPARCState *env; 791 792 cpu = SPARC_CPU(cpu_create(cpu_type)); 793 env = &cpu->env; 794 795 cpu_sparc_set_id(env, id); 796 if (id == 0) { 797 qemu_register_reset(main_cpu_reset, cpu); 798 } else { 799 qemu_register_reset(secondary_cpu_reset, cpu); 800 cs = CPU(cpu); 801 cs->halted = 1; 802 } 803 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 804 env->prom_addr = prom_addr; 805 } 806 807 static void dummy_fdc_tc(void *opaque, int irq, int level) 808 { 809 } 810 811 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, 812 MachineState *machine) 813 { 814 DeviceState *slavio_intctl; 815 unsigned int i; 816 void *nvram; 817 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; 818 qemu_irq fdc_tc; 819 unsigned long kernel_size; 820 DriveInfo *fd[MAX_FD]; 821 FWCfgState *fw_cfg; 822 unsigned int num_vsimms; 823 824 /* init CPUs */ 825 for(i = 0; i < smp_cpus; i++) { 826 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); 827 } 828 829 for (i = smp_cpus; i < MAX_CPUS; i++) 830 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 831 832 833 /* set up devices */ 834 ram_init(0, machine->ram_size, hwdef->max_mem); 835 /* models without ECC don't trap when missing ram is accessed */ 836 if (!hwdef->ecc_base) { 837 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size); 838 } 839 840 prom_init(hwdef->slavio_base, bios_name); 841 842 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 843 hwdef->intctl_base + 0x10000ULL, 844 cpu_irqs); 845 846 for (i = 0; i < 32; i++) { 847 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 848 } 849 for (i = 0; i < MAX_CPUS; i++) { 850 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 851 } 852 853 if (hwdef->idreg_base) { 854 idreg_init(hwdef->idreg_base); 855 } 856 857 if (hwdef->afx_base) { 858 afx_init(hwdef->afx_base); 859 } 860 861 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]); 862 863 if (hwdef->iommu_pad_base) { 864 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 865 Software shouldn't use aliased addresses, neither should it crash 866 when does. Using empty_slot instead of aliasing can help with 867 debugging such accesses */ 868 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); 869 } 870 871 sparc32_dma_init(hwdef->dma_base, 872 hwdef->esp_base, slavio_irq[18], 873 hwdef->le_base, slavio_irq[16]); 874 875 if (graphic_depth != 8 && graphic_depth != 24) { 876 error_report("Unsupported depth: %d", graphic_depth); 877 exit (1); 878 } 879 num_vsimms = 0; 880 if (num_vsimms == 0) { 881 if (vga_interface_type == VGA_CG3) { 882 if (graphic_depth != 8) { 883 error_report("Unsupported depth: %d", graphic_depth); 884 exit(1); 885 } 886 887 if (!(graphic_width == 1024 && graphic_height == 768) && 888 !(graphic_width == 1152 && graphic_height == 900)) { 889 error_report("Unsupported resolution: %d x %d", graphic_width, 890 graphic_height); 891 exit(1); 892 } 893 894 /* sbus irq 5 */ 895 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 896 graphic_width, graphic_height, graphic_depth); 897 } else { 898 /* If no display specified, default to TCX */ 899 if (graphic_depth != 8 && graphic_depth != 24) { 900 error_report("Unsupported depth: %d", graphic_depth); 901 exit(1); 902 } 903 904 if (!(graphic_width == 1024 && graphic_height == 768)) { 905 error_report("Unsupported resolution: %d x %d", 906 graphic_width, graphic_height); 907 exit(1); 908 } 909 910 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 911 graphic_width, graphic_height, graphic_depth); 912 } 913 } 914 915 for (i = num_vsimms; i < MAX_VSIMMS; i++) { 916 /* vsimm registers probed by OBP */ 917 if (hwdef->vsimm[i].reg_base) { 918 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); 919 } 920 } 921 922 if (hwdef->sx_base) { 923 empty_slot_init(hwdef->sx_base, 0x2000); 924 } 925 926 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8); 927 928 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 929 930 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14], 931 !machine->enable_graphics, ESCC_CLOCK, 1); 932 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 933 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 934 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], 935 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); 936 937 if (hwdef->apc_base) { 938 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); 939 } 940 941 if (hwdef->fd_base) { 942 /* there is zero or one floppy drive */ 943 memset(fd, 0, sizeof(fd)); 944 fd[0] = drive_get(IF_FLOPPY, 0, 0); 945 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 946 &fdc_tc); 947 } else { 948 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); 949 } 950 951 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 952 slavio_irq[30], fdc_tc); 953 954 if (hwdef->cs_base) { 955 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, 956 slavio_irq[5]); 957 } 958 959 if (hwdef->dbri_base) { 960 /* ISDN chip with attached CS4215 audio codec */ 961 /* prom space */ 962 empty_slot_init(hwdef->dbri_base+0x1000, 0x30); 963 /* reg space */ 964 empty_slot_init(hwdef->dbri_base+0x10000, 0x100); 965 } 966 967 if (hwdef->bpp_base) { 968 /* parallel port */ 969 empty_slot_init(hwdef->bpp_base, 0x20); 970 } 971 972 kernel_size = sun4m_load_kernel(machine->kernel_filename, 973 machine->initrd_filename, 974 machine->ram_size); 975 976 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline, 977 machine->boot_order, machine->ram_size, kernel_size, 978 graphic_width, graphic_height, graphic_depth, 979 hwdef->nvram_machine_id, "Sun4m"); 980 981 if (hwdef->ecc_base) 982 ecc_init(hwdef->ecc_base, slavio_irq[28], 983 hwdef->ecc_version); 984 985 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 986 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 987 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 988 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 989 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 990 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 991 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 992 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 993 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 994 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 995 if (machine->kernel_cmdline) { 996 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 997 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 998 machine->kernel_cmdline); 999 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 1000 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1001 strlen(machine->kernel_cmdline) + 1); 1002 } else { 1003 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1004 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1005 } 1006 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1007 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used 1008 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 1009 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1010 } 1011 1012 enum { 1013 ss5_id = 32, 1014 vger_id, 1015 lx_id, 1016 ss4_id, 1017 scls_id, 1018 sbook_id, 1019 ss10_id = 64, 1020 ss20_id, 1021 ss600mp_id, 1022 }; 1023 1024 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1025 /* SS-5 */ 1026 { 1027 .iommu_base = 0x10000000, 1028 .iommu_pad_base = 0x10004000, 1029 .iommu_pad_len = 0x0fffb000, 1030 .tcx_base = 0x50000000, 1031 .cs_base = 0x6c000000, 1032 .slavio_base = 0x70000000, 1033 .ms_kb_base = 0x71000000, 1034 .serial_base = 0x71100000, 1035 .nvram_base = 0x71200000, 1036 .fd_base = 0x71400000, 1037 .counter_base = 0x71d00000, 1038 .intctl_base = 0x71e00000, 1039 .idreg_base = 0x78000000, 1040 .dma_base = 0x78400000, 1041 .esp_base = 0x78800000, 1042 .le_base = 0x78c00000, 1043 .apc_base = 0x6a000000, 1044 .afx_base = 0x6e000000, 1045 .aux1_base = 0x71900000, 1046 .aux2_base = 0x71910000, 1047 .nvram_machine_id = 0x80, 1048 .machine_id = ss5_id, 1049 .iommu_version = 0x05000000, 1050 .max_mem = 0x10000000, 1051 }, 1052 /* SS-10 */ 1053 { 1054 .iommu_base = 0xfe0000000ULL, 1055 .tcx_base = 0xe20000000ULL, 1056 .slavio_base = 0xff0000000ULL, 1057 .ms_kb_base = 0xff1000000ULL, 1058 .serial_base = 0xff1100000ULL, 1059 .nvram_base = 0xff1200000ULL, 1060 .fd_base = 0xff1700000ULL, 1061 .counter_base = 0xff1300000ULL, 1062 .intctl_base = 0xff1400000ULL, 1063 .idreg_base = 0xef0000000ULL, 1064 .dma_base = 0xef0400000ULL, 1065 .esp_base = 0xef0800000ULL, 1066 .le_base = 0xef0c00000ULL, 1067 .apc_base = 0xefa000000ULL, // XXX should not exist 1068 .aux1_base = 0xff1800000ULL, 1069 .aux2_base = 0xff1a01000ULL, 1070 .ecc_base = 0xf00000000ULL, 1071 .ecc_version = 0x10000000, // version 0, implementation 1 1072 .nvram_machine_id = 0x72, 1073 .machine_id = ss10_id, 1074 .iommu_version = 0x03000000, 1075 .max_mem = 0xf00000000ULL, 1076 }, 1077 /* SS-600MP */ 1078 { 1079 .iommu_base = 0xfe0000000ULL, 1080 .tcx_base = 0xe20000000ULL, 1081 .slavio_base = 0xff0000000ULL, 1082 .ms_kb_base = 0xff1000000ULL, 1083 .serial_base = 0xff1100000ULL, 1084 .nvram_base = 0xff1200000ULL, 1085 .counter_base = 0xff1300000ULL, 1086 .intctl_base = 0xff1400000ULL, 1087 .dma_base = 0xef0081000ULL, 1088 .esp_base = 0xef0080000ULL, 1089 .le_base = 0xef0060000ULL, 1090 .apc_base = 0xefa000000ULL, // XXX should not exist 1091 .aux1_base = 0xff1800000ULL, 1092 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1093 .ecc_base = 0xf00000000ULL, 1094 .ecc_version = 0x00000000, // version 0, implementation 0 1095 .nvram_machine_id = 0x71, 1096 .machine_id = ss600mp_id, 1097 .iommu_version = 0x01000000, 1098 .max_mem = 0xf00000000ULL, 1099 }, 1100 /* SS-20 */ 1101 { 1102 .iommu_base = 0xfe0000000ULL, 1103 .tcx_base = 0xe20000000ULL, 1104 .slavio_base = 0xff0000000ULL, 1105 .ms_kb_base = 0xff1000000ULL, 1106 .serial_base = 0xff1100000ULL, 1107 .nvram_base = 0xff1200000ULL, 1108 .fd_base = 0xff1700000ULL, 1109 .counter_base = 0xff1300000ULL, 1110 .intctl_base = 0xff1400000ULL, 1111 .idreg_base = 0xef0000000ULL, 1112 .dma_base = 0xef0400000ULL, 1113 .esp_base = 0xef0800000ULL, 1114 .le_base = 0xef0c00000ULL, 1115 .bpp_base = 0xef4800000ULL, 1116 .apc_base = 0xefa000000ULL, // XXX should not exist 1117 .aux1_base = 0xff1800000ULL, 1118 .aux2_base = 0xff1a01000ULL, 1119 .dbri_base = 0xee0000000ULL, 1120 .sx_base = 0xf80000000ULL, 1121 .vsimm = { 1122 { 1123 .reg_base = 0x9c000000ULL, 1124 .vram_base = 0xfc000000ULL 1125 }, { 1126 .reg_base = 0x90000000ULL, 1127 .vram_base = 0xf0000000ULL 1128 }, { 1129 .reg_base = 0x94000000ULL 1130 }, { 1131 .reg_base = 0x98000000ULL 1132 } 1133 }, 1134 .ecc_base = 0xf00000000ULL, 1135 .ecc_version = 0x20000000, // version 0, implementation 2 1136 .nvram_machine_id = 0x72, 1137 .machine_id = ss20_id, 1138 .iommu_version = 0x13000000, 1139 .max_mem = 0xf00000000ULL, 1140 }, 1141 /* Voyager */ 1142 { 1143 .iommu_base = 0x10000000, 1144 .tcx_base = 0x50000000, 1145 .slavio_base = 0x70000000, 1146 .ms_kb_base = 0x71000000, 1147 .serial_base = 0x71100000, 1148 .nvram_base = 0x71200000, 1149 .fd_base = 0x71400000, 1150 .counter_base = 0x71d00000, 1151 .intctl_base = 0x71e00000, 1152 .idreg_base = 0x78000000, 1153 .dma_base = 0x78400000, 1154 .esp_base = 0x78800000, 1155 .le_base = 0x78c00000, 1156 .apc_base = 0x71300000, // pmc 1157 .aux1_base = 0x71900000, 1158 .aux2_base = 0x71910000, 1159 .nvram_machine_id = 0x80, 1160 .machine_id = vger_id, 1161 .iommu_version = 0x05000000, 1162 .max_mem = 0x10000000, 1163 }, 1164 /* LX */ 1165 { 1166 .iommu_base = 0x10000000, 1167 .iommu_pad_base = 0x10004000, 1168 .iommu_pad_len = 0x0fffb000, 1169 .tcx_base = 0x50000000, 1170 .slavio_base = 0x70000000, 1171 .ms_kb_base = 0x71000000, 1172 .serial_base = 0x71100000, 1173 .nvram_base = 0x71200000, 1174 .fd_base = 0x71400000, 1175 .counter_base = 0x71d00000, 1176 .intctl_base = 0x71e00000, 1177 .idreg_base = 0x78000000, 1178 .dma_base = 0x78400000, 1179 .esp_base = 0x78800000, 1180 .le_base = 0x78c00000, 1181 .aux1_base = 0x71900000, 1182 .aux2_base = 0x71910000, 1183 .nvram_machine_id = 0x80, 1184 .machine_id = lx_id, 1185 .iommu_version = 0x04000000, 1186 .max_mem = 0x10000000, 1187 }, 1188 /* SS-4 */ 1189 { 1190 .iommu_base = 0x10000000, 1191 .tcx_base = 0x50000000, 1192 .cs_base = 0x6c000000, 1193 .slavio_base = 0x70000000, 1194 .ms_kb_base = 0x71000000, 1195 .serial_base = 0x71100000, 1196 .nvram_base = 0x71200000, 1197 .fd_base = 0x71400000, 1198 .counter_base = 0x71d00000, 1199 .intctl_base = 0x71e00000, 1200 .idreg_base = 0x78000000, 1201 .dma_base = 0x78400000, 1202 .esp_base = 0x78800000, 1203 .le_base = 0x78c00000, 1204 .apc_base = 0x6a000000, 1205 .aux1_base = 0x71900000, 1206 .aux2_base = 0x71910000, 1207 .nvram_machine_id = 0x80, 1208 .machine_id = ss4_id, 1209 .iommu_version = 0x05000000, 1210 .max_mem = 0x10000000, 1211 }, 1212 /* SPARCClassic */ 1213 { 1214 .iommu_base = 0x10000000, 1215 .tcx_base = 0x50000000, 1216 .slavio_base = 0x70000000, 1217 .ms_kb_base = 0x71000000, 1218 .serial_base = 0x71100000, 1219 .nvram_base = 0x71200000, 1220 .fd_base = 0x71400000, 1221 .counter_base = 0x71d00000, 1222 .intctl_base = 0x71e00000, 1223 .idreg_base = 0x78000000, 1224 .dma_base = 0x78400000, 1225 .esp_base = 0x78800000, 1226 .le_base = 0x78c00000, 1227 .apc_base = 0x6a000000, 1228 .aux1_base = 0x71900000, 1229 .aux2_base = 0x71910000, 1230 .nvram_machine_id = 0x80, 1231 .machine_id = scls_id, 1232 .iommu_version = 0x05000000, 1233 .max_mem = 0x10000000, 1234 }, 1235 /* SPARCbook */ 1236 { 1237 .iommu_base = 0x10000000, 1238 .tcx_base = 0x50000000, // XXX 1239 .slavio_base = 0x70000000, 1240 .ms_kb_base = 0x71000000, 1241 .serial_base = 0x71100000, 1242 .nvram_base = 0x71200000, 1243 .fd_base = 0x71400000, 1244 .counter_base = 0x71d00000, 1245 .intctl_base = 0x71e00000, 1246 .idreg_base = 0x78000000, 1247 .dma_base = 0x78400000, 1248 .esp_base = 0x78800000, 1249 .le_base = 0x78c00000, 1250 .apc_base = 0x6a000000, 1251 .aux1_base = 0x71900000, 1252 .aux2_base = 0x71910000, 1253 .nvram_machine_id = 0x80, 1254 .machine_id = sbook_id, 1255 .iommu_version = 0x05000000, 1256 .max_mem = 0x10000000, 1257 }, 1258 }; 1259 1260 /* SPARCstation 5 hardware initialisation */ 1261 static void ss5_init(MachineState *machine) 1262 { 1263 sun4m_hw_init(&sun4m_hwdefs[0], machine); 1264 } 1265 1266 /* SPARCstation 10 hardware initialisation */ 1267 static void ss10_init(MachineState *machine) 1268 { 1269 sun4m_hw_init(&sun4m_hwdefs[1], machine); 1270 } 1271 1272 /* SPARCserver 600MP hardware initialisation */ 1273 static void ss600mp_init(MachineState *machine) 1274 { 1275 sun4m_hw_init(&sun4m_hwdefs[2], machine); 1276 } 1277 1278 /* SPARCstation 20 hardware initialisation */ 1279 static void ss20_init(MachineState *machine) 1280 { 1281 sun4m_hw_init(&sun4m_hwdefs[3], machine); 1282 } 1283 1284 /* SPARCstation Voyager hardware initialisation */ 1285 static void vger_init(MachineState *machine) 1286 { 1287 sun4m_hw_init(&sun4m_hwdefs[4], machine); 1288 } 1289 1290 /* SPARCstation LX hardware initialisation */ 1291 static void ss_lx_init(MachineState *machine) 1292 { 1293 sun4m_hw_init(&sun4m_hwdefs[5], machine); 1294 } 1295 1296 /* SPARCstation 4 hardware initialisation */ 1297 static void ss4_init(MachineState *machine) 1298 { 1299 sun4m_hw_init(&sun4m_hwdefs[6], machine); 1300 } 1301 1302 /* SPARCClassic hardware initialisation */ 1303 static void scls_init(MachineState *machine) 1304 { 1305 sun4m_hw_init(&sun4m_hwdefs[7], machine); 1306 } 1307 1308 /* SPARCbook hardware initialisation */ 1309 static void sbook_init(MachineState *machine) 1310 { 1311 sun4m_hw_init(&sun4m_hwdefs[8], machine); 1312 } 1313 1314 static void ss5_class_init(ObjectClass *oc, void *data) 1315 { 1316 MachineClass *mc = MACHINE_CLASS(oc); 1317 1318 mc->desc = "Sun4m platform, SPARCstation 5"; 1319 mc->init = ss5_init; 1320 mc->block_default_type = IF_SCSI; 1321 mc->is_default = 1; 1322 mc->default_boot_order = "c"; 1323 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1324 } 1325 1326 static const TypeInfo ss5_type = { 1327 .name = MACHINE_TYPE_NAME("SS-5"), 1328 .parent = TYPE_MACHINE, 1329 .class_init = ss5_class_init, 1330 }; 1331 1332 static void ss10_class_init(ObjectClass *oc, void *data) 1333 { 1334 MachineClass *mc = MACHINE_CLASS(oc); 1335 1336 mc->desc = "Sun4m platform, SPARCstation 10"; 1337 mc->init = ss10_init; 1338 mc->block_default_type = IF_SCSI; 1339 mc->max_cpus = 4; 1340 mc->default_boot_order = "c"; 1341 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1342 } 1343 1344 static const TypeInfo ss10_type = { 1345 .name = MACHINE_TYPE_NAME("SS-10"), 1346 .parent = TYPE_MACHINE, 1347 .class_init = ss10_class_init, 1348 }; 1349 1350 static void ss600mp_class_init(ObjectClass *oc, void *data) 1351 { 1352 MachineClass *mc = MACHINE_CLASS(oc); 1353 1354 mc->desc = "Sun4m platform, SPARCserver 600MP"; 1355 mc->init = ss600mp_init; 1356 mc->block_default_type = IF_SCSI; 1357 mc->max_cpus = 4; 1358 mc->default_boot_order = "c"; 1359 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1360 } 1361 1362 static const TypeInfo ss600mp_type = { 1363 .name = MACHINE_TYPE_NAME("SS-600MP"), 1364 .parent = TYPE_MACHINE, 1365 .class_init = ss600mp_class_init, 1366 }; 1367 1368 static void ss20_class_init(ObjectClass *oc, void *data) 1369 { 1370 MachineClass *mc = MACHINE_CLASS(oc); 1371 1372 mc->desc = "Sun4m platform, SPARCstation 20"; 1373 mc->init = ss20_init; 1374 mc->block_default_type = IF_SCSI; 1375 mc->max_cpus = 4; 1376 mc->default_boot_order = "c"; 1377 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1378 } 1379 1380 static const TypeInfo ss20_type = { 1381 .name = MACHINE_TYPE_NAME("SS-20"), 1382 .parent = TYPE_MACHINE, 1383 .class_init = ss20_class_init, 1384 }; 1385 1386 static void voyager_class_init(ObjectClass *oc, void *data) 1387 { 1388 MachineClass *mc = MACHINE_CLASS(oc); 1389 1390 mc->desc = "Sun4m platform, SPARCstation Voyager"; 1391 mc->init = vger_init; 1392 mc->block_default_type = IF_SCSI; 1393 mc->default_boot_order = "c"; 1394 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1395 } 1396 1397 static const TypeInfo voyager_type = { 1398 .name = MACHINE_TYPE_NAME("Voyager"), 1399 .parent = TYPE_MACHINE, 1400 .class_init = voyager_class_init, 1401 }; 1402 1403 static void ss_lx_class_init(ObjectClass *oc, void *data) 1404 { 1405 MachineClass *mc = MACHINE_CLASS(oc); 1406 1407 mc->desc = "Sun4m platform, SPARCstation LX"; 1408 mc->init = ss_lx_init; 1409 mc->block_default_type = IF_SCSI; 1410 mc->default_boot_order = "c"; 1411 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1412 } 1413 1414 static const TypeInfo ss_lx_type = { 1415 .name = MACHINE_TYPE_NAME("LX"), 1416 .parent = TYPE_MACHINE, 1417 .class_init = ss_lx_class_init, 1418 }; 1419 1420 static void ss4_class_init(ObjectClass *oc, void *data) 1421 { 1422 MachineClass *mc = MACHINE_CLASS(oc); 1423 1424 mc->desc = "Sun4m platform, SPARCstation 4"; 1425 mc->init = ss4_init; 1426 mc->block_default_type = IF_SCSI; 1427 mc->default_boot_order = "c"; 1428 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1429 } 1430 1431 static const TypeInfo ss4_type = { 1432 .name = MACHINE_TYPE_NAME("SS-4"), 1433 .parent = TYPE_MACHINE, 1434 .class_init = ss4_class_init, 1435 }; 1436 1437 static void scls_class_init(ObjectClass *oc, void *data) 1438 { 1439 MachineClass *mc = MACHINE_CLASS(oc); 1440 1441 mc->desc = "Sun4m platform, SPARCClassic"; 1442 mc->init = scls_init; 1443 mc->block_default_type = IF_SCSI; 1444 mc->default_boot_order = "c"; 1445 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1446 } 1447 1448 static const TypeInfo scls_type = { 1449 .name = MACHINE_TYPE_NAME("SPARCClassic"), 1450 .parent = TYPE_MACHINE, 1451 .class_init = scls_class_init, 1452 }; 1453 1454 static void sbook_class_init(ObjectClass *oc, void *data) 1455 { 1456 MachineClass *mc = MACHINE_CLASS(oc); 1457 1458 mc->desc = "Sun4m platform, SPARCbook"; 1459 mc->init = sbook_init; 1460 mc->block_default_type = IF_SCSI; 1461 mc->default_boot_order = "c"; 1462 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1463 } 1464 1465 static const TypeInfo sbook_type = { 1466 .name = MACHINE_TYPE_NAME("SPARCbook"), 1467 .parent = TYPE_MACHINE, 1468 .class_init = sbook_class_init, 1469 }; 1470 1471 static void sun4m_register_types(void) 1472 { 1473 type_register_static(&idreg_info); 1474 type_register_static(&afx_info); 1475 type_register_static(&prom_info); 1476 type_register_static(&ram_info); 1477 1478 type_register_static(&ss5_type); 1479 type_register_static(&ss10_type); 1480 type_register_static(&ss600mp_type); 1481 type_register_static(&ss20_type); 1482 type_register_static(&voyager_type); 1483 type_register_static(&ss_lx_type); 1484 type_register_static(&ss4_type); 1485 type_register_static(&scls_type); 1486 type_register_static(&sbook_type); 1487 } 1488 1489 type_init(sun4m_register_types) 1490