1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/sysbus.h" 25 #include "qemu/timer.h" 26 #include "hw/sparc/sun4m.h" 27 #include "hw/timer/m48t59.h" 28 #include "hw/sparc/sparc32_dma.h" 29 #include "hw/block/fdc.h" 30 #include "sysemu/sysemu.h" 31 #include "net/net.h" 32 #include "hw/boards.h" 33 #include "hw/nvram/openbios_firmware_abi.h" 34 #include "hw/scsi/esp.h" 35 #include "hw/i386/pc.h" 36 #include "hw/isa/isa.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/char/escc.h" 39 #include "hw/empty_slot.h" 40 #include "hw/loader.h" 41 #include "elf.h" 42 #include "sysemu/blockdev.h" 43 #include "trace.h" 44 45 /* 46 * Sun4m architecture was used in the following machines: 47 * 48 * SPARCserver 6xxMP/xx 49 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 50 * SPARCclassic X (4/10) 51 * SPARCstation LX/ZX (4/30) 52 * SPARCstation Voyager 53 * SPARCstation 10/xx, SPARCserver 10/xx 54 * SPARCstation 5, SPARCserver 5 55 * SPARCstation 20/xx, SPARCserver 20 56 * SPARCstation 4 57 * 58 * See for example: http://www.sunhelp.org/faq/sunref1.html 59 */ 60 61 #define KERNEL_LOAD_ADDR 0x00004000 62 #define CMDLINE_ADDR 0x007ff000 63 #define INITRD_LOAD_ADDR 0x00800000 64 #define PROM_SIZE_MAX (1024 * 1024) 65 #define PROM_VADDR 0xffd00000 66 #define PROM_FILENAME "openbios-sparc32" 67 #define CFG_ADDR 0xd00000510ULL 68 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 69 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 70 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 71 72 #define MAX_CPUS 16 73 #define MAX_PILS 16 74 #define MAX_VSIMMS 4 75 76 #define ESCC_CLOCK 4915200 77 78 struct sun4m_hwdef { 79 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 80 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 81 hwaddr serial_base, fd_base; 82 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 83 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 84 hwaddr bpp_base, dbri_base, sx_base; 85 struct { 86 hwaddr reg_base, vram_base; 87 } vsimm[MAX_VSIMMS]; 88 hwaddr ecc_base; 89 uint64_t max_mem; 90 const char * const default_cpu_model; 91 uint32_t ecc_version; 92 uint32_t iommu_version; 93 uint16_t machine_id; 94 uint8_t nvram_machine_id; 95 }; 96 97 int DMA_get_channel_mode (int nchan) 98 { 99 return 0; 100 } 101 int DMA_read_memory (int nchan, void *buf, int pos, int size) 102 { 103 return 0; 104 } 105 int DMA_write_memory (int nchan, void *buf, int pos, int size) 106 { 107 return 0; 108 } 109 void DMA_hold_DREQ (int nchan) {} 110 void DMA_release_DREQ (int nchan) {} 111 void DMA_schedule(int nchan) {} 112 113 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) 114 { 115 } 116 117 void DMA_register_channel (int nchan, 118 DMA_transfer_handler transfer_handler, 119 void *opaque) 120 { 121 } 122 123 static int fw_cfg_boot_set(void *opaque, const char *boot_device) 124 { 125 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 126 return 0; 127 } 128 129 static void nvram_init(M48t59State *nvram, uint8_t *macaddr, 130 const char *cmdline, const char *boot_devices, 131 ram_addr_t RAM_size, uint32_t kernel_size, 132 int width, int height, int depth, 133 int nvram_machine_id, const char *arch) 134 { 135 unsigned int i; 136 uint32_t start, end; 137 uint8_t image[0x1ff0]; 138 struct OpenBIOS_nvpart_v1 *part_header; 139 140 memset(image, '\0', sizeof(image)); 141 142 start = 0; 143 144 // OpenBIOS nvram variables 145 // Variable partition 146 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 147 part_header->signature = OPENBIOS_PART_SYSTEM; 148 pstrcpy(part_header->name, sizeof(part_header->name), "system"); 149 150 end = start + sizeof(struct OpenBIOS_nvpart_v1); 151 for (i = 0; i < nb_prom_envs; i++) 152 end = OpenBIOS_set_var(image, end, prom_envs[i]); 153 154 // End marker 155 image[end++] = '\0'; 156 157 end = start + ((end - start + 15) & ~15); 158 OpenBIOS_finish_partition(part_header, end - start); 159 160 // free partition 161 start = end; 162 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 163 part_header->signature = OPENBIOS_PART_FREE; 164 pstrcpy(part_header->name, sizeof(part_header->name), "free"); 165 166 end = 0x1fd0; 167 OpenBIOS_finish_partition(part_header, end - start); 168 169 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 170 nvram_machine_id); 171 172 for (i = 0; i < sizeof(image); i++) 173 m48t59_write(nvram, i, image[i]); 174 } 175 176 static DeviceState *slavio_intctl; 177 178 void sun4m_pic_info(Monitor *mon, const QDict *qdict) 179 { 180 if (slavio_intctl) 181 slavio_pic_info(mon, slavio_intctl); 182 } 183 184 void sun4m_irq_info(Monitor *mon, const QDict *qdict) 185 { 186 if (slavio_intctl) 187 slavio_irq_info(mon, slavio_intctl); 188 } 189 190 void cpu_check_irqs(CPUSPARCState *env) 191 { 192 CPUState *cs; 193 194 if (env->pil_in && (env->interrupt_index == 0 || 195 (env->interrupt_index & ~15) == TT_EXTINT)) { 196 unsigned int i; 197 198 for (i = 15; i > 0; i--) { 199 if (env->pil_in & (1 << i)) { 200 int old_interrupt = env->interrupt_index; 201 202 env->interrupt_index = TT_EXTINT | i; 203 if (old_interrupt != env->interrupt_index) { 204 cs = CPU(sparc_env_get_cpu(env)); 205 trace_sun4m_cpu_interrupt(i); 206 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 207 } 208 break; 209 } 210 } 211 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 212 cs = CPU(sparc_env_get_cpu(env)); 213 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 214 env->interrupt_index = 0; 215 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 216 } 217 } 218 219 static void cpu_kick_irq(SPARCCPU *cpu) 220 { 221 CPUSPARCState *env = &cpu->env; 222 CPUState *cs = CPU(cpu); 223 224 cs->halted = 0; 225 cpu_check_irqs(env); 226 qemu_cpu_kick(cs); 227 } 228 229 static void cpu_set_irq(void *opaque, int irq, int level) 230 { 231 SPARCCPU *cpu = opaque; 232 CPUSPARCState *env = &cpu->env; 233 234 if (level) { 235 trace_sun4m_cpu_set_irq_raise(irq); 236 env->pil_in |= 1 << irq; 237 cpu_kick_irq(cpu); 238 } else { 239 trace_sun4m_cpu_set_irq_lower(irq); 240 env->pil_in &= ~(1 << irq); 241 cpu_check_irqs(env); 242 } 243 } 244 245 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 246 { 247 } 248 249 static void main_cpu_reset(void *opaque) 250 { 251 SPARCCPU *cpu = opaque; 252 CPUState *cs = CPU(cpu); 253 254 cpu_reset(cs); 255 cs->halted = 0; 256 } 257 258 static void secondary_cpu_reset(void *opaque) 259 { 260 SPARCCPU *cpu = opaque; 261 CPUState *cs = CPU(cpu); 262 263 cpu_reset(cs); 264 cs->halted = 1; 265 } 266 267 static void cpu_halt_signal(void *opaque, int irq, int level) 268 { 269 if (level && current_cpu) { 270 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 271 } 272 } 273 274 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 275 { 276 return addr - 0xf0000000ULL; 277 } 278 279 static unsigned long sun4m_load_kernel(const char *kernel_filename, 280 const char *initrd_filename, 281 ram_addr_t RAM_size) 282 { 283 int linux_boot; 284 unsigned int i; 285 long initrd_size, kernel_size; 286 uint8_t *ptr; 287 288 linux_boot = (kernel_filename != NULL); 289 290 kernel_size = 0; 291 if (linux_boot) { 292 int bswap_needed; 293 294 #ifdef BSWAP_NEEDED 295 bswap_needed = 1; 296 #else 297 bswap_needed = 0; 298 #endif 299 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 300 NULL, NULL, NULL, 1, ELF_MACHINE, 0); 301 if (kernel_size < 0) 302 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 303 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 304 TARGET_PAGE_SIZE); 305 if (kernel_size < 0) 306 kernel_size = load_image_targphys(kernel_filename, 307 KERNEL_LOAD_ADDR, 308 RAM_size - KERNEL_LOAD_ADDR); 309 if (kernel_size < 0) { 310 fprintf(stderr, "qemu: could not load kernel '%s'\n", 311 kernel_filename); 312 exit(1); 313 } 314 315 /* load initrd */ 316 initrd_size = 0; 317 if (initrd_filename) { 318 initrd_size = load_image_targphys(initrd_filename, 319 INITRD_LOAD_ADDR, 320 RAM_size - INITRD_LOAD_ADDR); 321 if (initrd_size < 0) { 322 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 323 initrd_filename); 324 exit(1); 325 } 326 } 327 if (initrd_size > 0) { 328 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 329 ptr = rom_ptr(KERNEL_LOAD_ADDR + i); 330 if (ldl_p(ptr) == 0x48647253) { // HdrS 331 stl_p(ptr + 16, INITRD_LOAD_ADDR); 332 stl_p(ptr + 20, initrd_size); 333 break; 334 } 335 } 336 } 337 } 338 return kernel_size; 339 } 340 341 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 342 { 343 DeviceState *dev; 344 SysBusDevice *s; 345 346 dev = qdev_create(NULL, "iommu"); 347 qdev_prop_set_uint32(dev, "version", version); 348 qdev_init_nofail(dev); 349 s = SYS_BUS_DEVICE(dev); 350 sysbus_connect_irq(s, 0, irq); 351 sysbus_mmio_map(s, 0, addr); 352 353 return s; 354 } 355 356 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq, 357 void *iommu, qemu_irq *dev_irq, int is_ledma) 358 { 359 DeviceState *dev; 360 SysBusDevice *s; 361 362 dev = qdev_create(NULL, "sparc32_dma"); 363 qdev_prop_set_ptr(dev, "iommu_opaque", iommu); 364 qdev_prop_set_uint32(dev, "is_ledma", is_ledma); 365 qdev_init_nofail(dev); 366 s = SYS_BUS_DEVICE(dev); 367 sysbus_connect_irq(s, 0, parent_irq); 368 *dev_irq = qdev_get_gpio_in(dev, 0); 369 sysbus_mmio_map(s, 0, daddr); 370 371 return s; 372 } 373 374 static void lance_init(NICInfo *nd, hwaddr leaddr, 375 void *dma_opaque, qemu_irq irq) 376 { 377 DeviceState *dev; 378 SysBusDevice *s; 379 qemu_irq reset; 380 381 qemu_check_nic_model(&nd_table[0], "lance"); 382 383 dev = qdev_create(NULL, "lance"); 384 qdev_set_nic_properties(dev, nd); 385 qdev_prop_set_ptr(dev, "dma", dma_opaque); 386 qdev_init_nofail(dev); 387 s = SYS_BUS_DEVICE(dev); 388 sysbus_mmio_map(s, 0, leaddr); 389 sysbus_connect_irq(s, 0, irq); 390 reset = qdev_get_gpio_in(dev, 0); 391 qdev_connect_gpio_out(dma_opaque, 0, reset); 392 } 393 394 static DeviceState *slavio_intctl_init(hwaddr addr, 395 hwaddr addrg, 396 qemu_irq **parent_irq) 397 { 398 DeviceState *dev; 399 SysBusDevice *s; 400 unsigned int i, j; 401 402 dev = qdev_create(NULL, "slavio_intctl"); 403 qdev_init_nofail(dev); 404 405 s = SYS_BUS_DEVICE(dev); 406 407 for (i = 0; i < MAX_CPUS; i++) { 408 for (j = 0; j < MAX_PILS; j++) { 409 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 410 } 411 } 412 sysbus_mmio_map(s, 0, addrg); 413 for (i = 0; i < MAX_CPUS; i++) { 414 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 415 } 416 417 return dev; 418 } 419 420 #define SYS_TIMER_OFFSET 0x10000ULL 421 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 422 423 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 424 qemu_irq *cpu_irqs, unsigned int num_cpus) 425 { 426 DeviceState *dev; 427 SysBusDevice *s; 428 unsigned int i; 429 430 dev = qdev_create(NULL, "slavio_timer"); 431 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 432 qdev_init_nofail(dev); 433 s = SYS_BUS_DEVICE(dev); 434 sysbus_connect_irq(s, 0, master_irq); 435 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 436 437 for (i = 0; i < MAX_CPUS; i++) { 438 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 439 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 440 } 441 } 442 443 static qemu_irq slavio_system_powerdown; 444 445 static void slavio_powerdown_req(Notifier *n, void *opaque) 446 { 447 qemu_irq_raise(slavio_system_powerdown); 448 } 449 450 static Notifier slavio_system_powerdown_notifier = { 451 .notify = slavio_powerdown_req 452 }; 453 454 #define MISC_LEDS 0x01600000 455 #define MISC_CFG 0x01800000 456 #define MISC_DIAG 0x01a00000 457 #define MISC_MDM 0x01b00000 458 #define MISC_SYS 0x01f00000 459 460 static void slavio_misc_init(hwaddr base, 461 hwaddr aux1_base, 462 hwaddr aux2_base, qemu_irq irq, 463 qemu_irq fdc_tc) 464 { 465 DeviceState *dev; 466 SysBusDevice *s; 467 468 dev = qdev_create(NULL, "slavio_misc"); 469 qdev_init_nofail(dev); 470 s = SYS_BUS_DEVICE(dev); 471 if (base) { 472 /* 8 bit registers */ 473 /* Slavio control */ 474 sysbus_mmio_map(s, 0, base + MISC_CFG); 475 /* Diagnostics */ 476 sysbus_mmio_map(s, 1, base + MISC_DIAG); 477 /* Modem control */ 478 sysbus_mmio_map(s, 2, base + MISC_MDM); 479 /* 16 bit registers */ 480 /* ss600mp diag LEDs */ 481 sysbus_mmio_map(s, 3, base + MISC_LEDS); 482 /* 32 bit registers */ 483 /* System control */ 484 sysbus_mmio_map(s, 4, base + MISC_SYS); 485 } 486 if (aux1_base) { 487 /* AUX 1 (Misc System Functions) */ 488 sysbus_mmio_map(s, 5, aux1_base); 489 } 490 if (aux2_base) { 491 /* AUX 2 (Software Powerdown Control) */ 492 sysbus_mmio_map(s, 6, aux2_base); 493 } 494 sysbus_connect_irq(s, 0, irq); 495 sysbus_connect_irq(s, 1, fdc_tc); 496 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 497 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 498 } 499 500 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 501 { 502 DeviceState *dev; 503 SysBusDevice *s; 504 505 dev = qdev_create(NULL, "eccmemctl"); 506 qdev_prop_set_uint32(dev, "version", version); 507 qdev_init_nofail(dev); 508 s = SYS_BUS_DEVICE(dev); 509 sysbus_connect_irq(s, 0, irq); 510 sysbus_mmio_map(s, 0, base); 511 if (version == 0) { // SS-600MP only 512 sysbus_mmio_map(s, 1, base + 0x1000); 513 } 514 } 515 516 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 517 { 518 DeviceState *dev; 519 SysBusDevice *s; 520 521 dev = qdev_create(NULL, "apc"); 522 qdev_init_nofail(dev); 523 s = SYS_BUS_DEVICE(dev); 524 /* Power management (APC) XXX: not a Slavio device */ 525 sysbus_mmio_map(s, 0, power_base); 526 sysbus_connect_irq(s, 0, cpu_halt); 527 } 528 529 static void tcx_init(hwaddr addr, int vram_size, int width, 530 int height, int depth) 531 { 532 DeviceState *dev; 533 SysBusDevice *s; 534 535 dev = qdev_create(NULL, "SUNW,tcx"); 536 qdev_prop_set_uint32(dev, "vram_size", vram_size); 537 qdev_prop_set_uint16(dev, "width", width); 538 qdev_prop_set_uint16(dev, "height", height); 539 qdev_prop_set_uint16(dev, "depth", depth); 540 qdev_prop_set_uint64(dev, "prom_addr", addr); 541 qdev_init_nofail(dev); 542 s = SYS_BUS_DEVICE(dev); 543 /* FCode ROM */ 544 sysbus_mmio_map(s, 0, addr); 545 /* 8-bit plane */ 546 sysbus_mmio_map(s, 1, addr + 0x00800000ULL); 547 /* DAC */ 548 sysbus_mmio_map(s, 2, addr + 0x00200000ULL); 549 /* TEC (dummy) */ 550 sysbus_mmio_map(s, 3, addr + 0x00700000ULL); 551 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */ 552 sysbus_mmio_map(s, 4, addr + 0x00301000ULL); 553 if (depth == 24) { 554 /* 24-bit plane */ 555 sysbus_mmio_map(s, 5, addr + 0x02000000ULL); 556 /* Control plane */ 557 sysbus_mmio_map(s, 6, addr + 0x0a000000ULL); 558 } else { 559 /* THC 8 bit (dummy) */ 560 sysbus_mmio_map(s, 5, addr + 0x00300000ULL); 561 } 562 } 563 564 /* NCR89C100/MACIO Internal ID register */ 565 566 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 567 568 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 569 570 static void idreg_init(hwaddr addr) 571 { 572 DeviceState *dev; 573 SysBusDevice *s; 574 575 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER); 576 qdev_init_nofail(dev); 577 s = SYS_BUS_DEVICE(dev); 578 579 sysbus_mmio_map(s, 0, addr); 580 cpu_physical_memory_write_rom(&address_space_memory, 581 addr, idreg_data, sizeof(idreg_data)); 582 } 583 584 #define MACIO_ID_REGISTER(obj) \ 585 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER) 586 587 typedef struct IDRegState { 588 SysBusDevice parent_obj; 589 590 MemoryRegion mem; 591 } IDRegState; 592 593 static int idreg_init1(SysBusDevice *dev) 594 { 595 IDRegState *s = MACIO_ID_REGISTER(dev); 596 597 memory_region_init_ram(&s->mem, OBJECT(s), 598 "sun4m.idreg", sizeof(idreg_data)); 599 vmstate_register_ram_global(&s->mem); 600 memory_region_set_readonly(&s->mem, true); 601 sysbus_init_mmio(dev, &s->mem); 602 return 0; 603 } 604 605 static void idreg_class_init(ObjectClass *klass, void *data) 606 { 607 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 608 609 k->init = idreg_init1; 610 } 611 612 static const TypeInfo idreg_info = { 613 .name = TYPE_MACIO_ID_REGISTER, 614 .parent = TYPE_SYS_BUS_DEVICE, 615 .instance_size = sizeof(IDRegState), 616 .class_init = idreg_class_init, 617 }; 618 619 #define TYPE_TCX_AFX "tcx_afx" 620 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX) 621 622 typedef struct AFXState { 623 SysBusDevice parent_obj; 624 625 MemoryRegion mem; 626 } AFXState; 627 628 /* SS-5 TCX AFX register */ 629 static void afx_init(hwaddr addr) 630 { 631 DeviceState *dev; 632 SysBusDevice *s; 633 634 dev = qdev_create(NULL, TYPE_TCX_AFX); 635 qdev_init_nofail(dev); 636 s = SYS_BUS_DEVICE(dev); 637 638 sysbus_mmio_map(s, 0, addr); 639 } 640 641 static int afx_init1(SysBusDevice *dev) 642 { 643 AFXState *s = TCX_AFX(dev); 644 645 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4); 646 vmstate_register_ram_global(&s->mem); 647 sysbus_init_mmio(dev, &s->mem); 648 return 0; 649 } 650 651 static void afx_class_init(ObjectClass *klass, void *data) 652 { 653 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 654 655 k->init = afx_init1; 656 } 657 658 static const TypeInfo afx_info = { 659 .name = TYPE_TCX_AFX, 660 .parent = TYPE_SYS_BUS_DEVICE, 661 .instance_size = sizeof(AFXState), 662 .class_init = afx_class_init, 663 }; 664 665 #define TYPE_OPENPROM "openprom" 666 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 667 668 typedef struct PROMState { 669 SysBusDevice parent_obj; 670 671 MemoryRegion prom; 672 } PROMState; 673 674 /* Boot PROM (OpenBIOS) */ 675 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 676 { 677 hwaddr *base_addr = (hwaddr *)opaque; 678 return addr + *base_addr - PROM_VADDR; 679 } 680 681 static void prom_init(hwaddr addr, const char *bios_name) 682 { 683 DeviceState *dev; 684 SysBusDevice *s; 685 char *filename; 686 int ret; 687 688 dev = qdev_create(NULL, TYPE_OPENPROM); 689 qdev_init_nofail(dev); 690 s = SYS_BUS_DEVICE(dev); 691 692 sysbus_mmio_map(s, 0, addr); 693 694 /* load boot prom */ 695 if (bios_name == NULL) { 696 bios_name = PROM_FILENAME; 697 } 698 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 699 if (filename) { 700 ret = load_elf(filename, translate_prom_address, &addr, NULL, 701 NULL, NULL, 1, ELF_MACHINE, 0); 702 if (ret < 0 || ret > PROM_SIZE_MAX) { 703 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 704 } 705 g_free(filename); 706 } else { 707 ret = -1; 708 } 709 if (ret < 0 || ret > PROM_SIZE_MAX) { 710 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 711 exit(1); 712 } 713 } 714 715 static int prom_init1(SysBusDevice *dev) 716 { 717 PROMState *s = OPENPROM(dev); 718 719 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX); 720 vmstate_register_ram_global(&s->prom); 721 memory_region_set_readonly(&s->prom, true); 722 sysbus_init_mmio(dev, &s->prom); 723 return 0; 724 } 725 726 static Property prom_properties[] = { 727 {/* end of property list */}, 728 }; 729 730 static void prom_class_init(ObjectClass *klass, void *data) 731 { 732 DeviceClass *dc = DEVICE_CLASS(klass); 733 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 734 735 k->init = prom_init1; 736 dc->props = prom_properties; 737 } 738 739 static const TypeInfo prom_info = { 740 .name = TYPE_OPENPROM, 741 .parent = TYPE_SYS_BUS_DEVICE, 742 .instance_size = sizeof(PROMState), 743 .class_init = prom_class_init, 744 }; 745 746 #define TYPE_SUN4M_MEMORY "memory" 747 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY) 748 749 typedef struct RamDevice { 750 SysBusDevice parent_obj; 751 752 MemoryRegion ram; 753 uint64_t size; 754 } RamDevice; 755 756 /* System RAM */ 757 static int ram_init1(SysBusDevice *dev) 758 { 759 RamDevice *d = SUN4M_RAM(dev); 760 761 memory_region_init_ram(&d->ram, OBJECT(d), "sun4m.ram", d->size); 762 vmstate_register_ram_global(&d->ram); 763 sysbus_init_mmio(dev, &d->ram); 764 return 0; 765 } 766 767 static void ram_init(hwaddr addr, ram_addr_t RAM_size, 768 uint64_t max_mem) 769 { 770 DeviceState *dev; 771 SysBusDevice *s; 772 RamDevice *d; 773 774 /* allocate RAM */ 775 if ((uint64_t)RAM_size > max_mem) { 776 fprintf(stderr, 777 "qemu: Too much memory for this machine: %d, maximum %d\n", 778 (unsigned int)(RAM_size / (1024 * 1024)), 779 (unsigned int)(max_mem / (1024 * 1024))); 780 exit(1); 781 } 782 dev = qdev_create(NULL, "memory"); 783 s = SYS_BUS_DEVICE(dev); 784 785 d = SUN4M_RAM(dev); 786 d->size = RAM_size; 787 qdev_init_nofail(dev); 788 789 sysbus_mmio_map(s, 0, addr); 790 } 791 792 static Property ram_properties[] = { 793 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 794 DEFINE_PROP_END_OF_LIST(), 795 }; 796 797 static void ram_class_init(ObjectClass *klass, void *data) 798 { 799 DeviceClass *dc = DEVICE_CLASS(klass); 800 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 801 802 k->init = ram_init1; 803 dc->props = ram_properties; 804 } 805 806 static const TypeInfo ram_info = { 807 .name = TYPE_SUN4M_MEMORY, 808 .parent = TYPE_SYS_BUS_DEVICE, 809 .instance_size = sizeof(RamDevice), 810 .class_init = ram_class_init, 811 }; 812 813 static void cpu_devinit(const char *cpu_model, unsigned int id, 814 uint64_t prom_addr, qemu_irq **cpu_irqs) 815 { 816 CPUState *cs; 817 SPARCCPU *cpu; 818 CPUSPARCState *env; 819 820 cpu = cpu_sparc_init(cpu_model); 821 if (cpu == NULL) { 822 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); 823 exit(1); 824 } 825 env = &cpu->env; 826 827 cpu_sparc_set_id(env, id); 828 if (id == 0) { 829 qemu_register_reset(main_cpu_reset, cpu); 830 } else { 831 qemu_register_reset(secondary_cpu_reset, cpu); 832 cs = CPU(cpu); 833 cs->halted = 1; 834 } 835 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 836 env->prom_addr = prom_addr; 837 } 838 839 static void dummy_fdc_tc(void *opaque, int irq, int level) 840 { 841 } 842 843 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, 844 QEMUMachineInitArgs *args) 845 { 846 const char *cpu_model = args->cpu_model; 847 unsigned int i; 848 void *iommu, *espdma, *ledma, *nvram; 849 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS], 850 espdma_irq, ledma_irq; 851 qemu_irq esp_reset, dma_enable; 852 qemu_irq fdc_tc; 853 qemu_irq *cpu_halt; 854 unsigned long kernel_size; 855 DriveInfo *fd[MAX_FD]; 856 FWCfgState *fw_cfg; 857 unsigned int num_vsimms; 858 859 /* init CPUs */ 860 if (!cpu_model) 861 cpu_model = hwdef->default_cpu_model; 862 863 for(i = 0; i < smp_cpus; i++) { 864 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); 865 } 866 867 for (i = smp_cpus; i < MAX_CPUS; i++) 868 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 869 870 871 /* set up devices */ 872 ram_init(0, args->ram_size, hwdef->max_mem); 873 /* models without ECC don't trap when missing ram is accessed */ 874 if (!hwdef->ecc_base) { 875 empty_slot_init(args->ram_size, hwdef->max_mem - args->ram_size); 876 } 877 878 prom_init(hwdef->slavio_base, bios_name); 879 880 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 881 hwdef->intctl_base + 0x10000ULL, 882 cpu_irqs); 883 884 for (i = 0; i < 32; i++) { 885 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 886 } 887 for (i = 0; i < MAX_CPUS; i++) { 888 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 889 } 890 891 if (hwdef->idreg_base) { 892 idreg_init(hwdef->idreg_base); 893 } 894 895 if (hwdef->afx_base) { 896 afx_init(hwdef->afx_base); 897 } 898 899 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, 900 slavio_irq[30]); 901 902 if (hwdef->iommu_pad_base) { 903 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 904 Software shouldn't use aliased addresses, neither should it crash 905 when does. Using empty_slot instead of aliasing can help with 906 debugging such accesses */ 907 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); 908 } 909 910 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18], 911 iommu, &espdma_irq, 0); 912 913 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, 914 slavio_irq[16], iommu, &ledma_irq, 1); 915 916 if (graphic_depth != 8 && graphic_depth != 24) { 917 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); 918 exit (1); 919 } 920 num_vsimms = 0; 921 if (num_vsimms == 0) { 922 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height, 923 graphic_depth); 924 } 925 926 for (i = num_vsimms; i < MAX_VSIMMS; i++) { 927 /* vsimm registers probed by OBP */ 928 if (hwdef->vsimm[i].reg_base) { 929 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); 930 } 931 } 932 933 if (hwdef->sx_base) { 934 empty_slot_init(hwdef->sx_base, 0x2000); 935 } 936 937 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq); 938 939 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8); 940 941 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 942 943 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14], 944 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1); 945 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 946 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 947 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], 948 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); 949 950 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); 951 if (hwdef->apc_base) { 952 apc_init(hwdef->apc_base, cpu_halt[0]); 953 } 954 955 if (hwdef->fd_base) { 956 /* there is zero or one floppy drive */ 957 memset(fd, 0, sizeof(fd)); 958 fd[0] = drive_get(IF_FLOPPY, 0, 0); 959 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 960 &fdc_tc); 961 } else { 962 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1); 963 } 964 965 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 966 slavio_irq[30], fdc_tc); 967 968 if (drive_get_max_bus(IF_SCSI) > 0) { 969 fprintf(stderr, "qemu: too many SCSI bus\n"); 970 exit(1); 971 } 972 973 esp_init(hwdef->esp_base, 2, 974 espdma_memory_read, espdma_memory_write, 975 espdma, espdma_irq, &esp_reset, &dma_enable); 976 977 qdev_connect_gpio_out(espdma, 0, esp_reset); 978 qdev_connect_gpio_out(espdma, 1, dma_enable); 979 980 if (hwdef->cs_base) { 981 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, 982 slavio_irq[5]); 983 } 984 985 if (hwdef->dbri_base) { 986 /* ISDN chip with attached CS4215 audio codec */ 987 /* prom space */ 988 empty_slot_init(hwdef->dbri_base+0x1000, 0x30); 989 /* reg space */ 990 empty_slot_init(hwdef->dbri_base+0x10000, 0x100); 991 } 992 993 if (hwdef->bpp_base) { 994 /* parallel port */ 995 empty_slot_init(hwdef->bpp_base, 0x20); 996 } 997 998 kernel_size = sun4m_load_kernel(args->kernel_filename, 999 args->initrd_filename, 1000 args->ram_size); 1001 1002 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, args->kernel_cmdline, 1003 args->boot_order, args->ram_size, kernel_size, graphic_width, 1004 graphic_height, graphic_depth, hwdef->nvram_machine_id, 1005 "Sun4m"); 1006 1007 if (hwdef->ecc_base) 1008 ecc_init(hwdef->ecc_base, slavio_irq[28], 1009 hwdef->ecc_version); 1010 1011 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); 1012 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1013 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 1014 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1015 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1016 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1017 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1018 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1019 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1020 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1021 if (args->kernel_cmdline) { 1022 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1023 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1024 args->kernel_cmdline); 1025 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, args->kernel_cmdline); 1026 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1027 strlen(args->kernel_cmdline) + 1); 1028 } else { 1029 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1030 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1031 } 1032 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1033 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used 1034 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, args->boot_order[0]); 1035 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1036 } 1037 1038 enum { 1039 ss5_id = 32, 1040 vger_id, 1041 lx_id, 1042 ss4_id, 1043 scls_id, 1044 sbook_id, 1045 ss10_id = 64, 1046 ss20_id, 1047 ss600mp_id, 1048 }; 1049 1050 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1051 /* SS-5 */ 1052 { 1053 .iommu_base = 0x10000000, 1054 .iommu_pad_base = 0x10004000, 1055 .iommu_pad_len = 0x0fffb000, 1056 .tcx_base = 0x50000000, 1057 .cs_base = 0x6c000000, 1058 .slavio_base = 0x70000000, 1059 .ms_kb_base = 0x71000000, 1060 .serial_base = 0x71100000, 1061 .nvram_base = 0x71200000, 1062 .fd_base = 0x71400000, 1063 .counter_base = 0x71d00000, 1064 .intctl_base = 0x71e00000, 1065 .idreg_base = 0x78000000, 1066 .dma_base = 0x78400000, 1067 .esp_base = 0x78800000, 1068 .le_base = 0x78c00000, 1069 .apc_base = 0x6a000000, 1070 .afx_base = 0x6e000000, 1071 .aux1_base = 0x71900000, 1072 .aux2_base = 0x71910000, 1073 .nvram_machine_id = 0x80, 1074 .machine_id = ss5_id, 1075 .iommu_version = 0x05000000, 1076 .max_mem = 0x10000000, 1077 .default_cpu_model = "Fujitsu MB86904", 1078 }, 1079 /* SS-10 */ 1080 { 1081 .iommu_base = 0xfe0000000ULL, 1082 .tcx_base = 0xe20000000ULL, 1083 .slavio_base = 0xff0000000ULL, 1084 .ms_kb_base = 0xff1000000ULL, 1085 .serial_base = 0xff1100000ULL, 1086 .nvram_base = 0xff1200000ULL, 1087 .fd_base = 0xff1700000ULL, 1088 .counter_base = 0xff1300000ULL, 1089 .intctl_base = 0xff1400000ULL, 1090 .idreg_base = 0xef0000000ULL, 1091 .dma_base = 0xef0400000ULL, 1092 .esp_base = 0xef0800000ULL, 1093 .le_base = 0xef0c00000ULL, 1094 .apc_base = 0xefa000000ULL, // XXX should not exist 1095 .aux1_base = 0xff1800000ULL, 1096 .aux2_base = 0xff1a01000ULL, 1097 .ecc_base = 0xf00000000ULL, 1098 .ecc_version = 0x10000000, // version 0, implementation 1 1099 .nvram_machine_id = 0x72, 1100 .machine_id = ss10_id, 1101 .iommu_version = 0x03000000, 1102 .max_mem = 0xf00000000ULL, 1103 .default_cpu_model = "TI SuperSparc II", 1104 }, 1105 /* SS-600MP */ 1106 { 1107 .iommu_base = 0xfe0000000ULL, 1108 .tcx_base = 0xe20000000ULL, 1109 .slavio_base = 0xff0000000ULL, 1110 .ms_kb_base = 0xff1000000ULL, 1111 .serial_base = 0xff1100000ULL, 1112 .nvram_base = 0xff1200000ULL, 1113 .counter_base = 0xff1300000ULL, 1114 .intctl_base = 0xff1400000ULL, 1115 .dma_base = 0xef0081000ULL, 1116 .esp_base = 0xef0080000ULL, 1117 .le_base = 0xef0060000ULL, 1118 .apc_base = 0xefa000000ULL, // XXX should not exist 1119 .aux1_base = 0xff1800000ULL, 1120 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1121 .ecc_base = 0xf00000000ULL, 1122 .ecc_version = 0x00000000, // version 0, implementation 0 1123 .nvram_machine_id = 0x71, 1124 .machine_id = ss600mp_id, 1125 .iommu_version = 0x01000000, 1126 .max_mem = 0xf00000000ULL, 1127 .default_cpu_model = "TI SuperSparc II", 1128 }, 1129 /* SS-20 */ 1130 { 1131 .iommu_base = 0xfe0000000ULL, 1132 .tcx_base = 0xe20000000ULL, 1133 .slavio_base = 0xff0000000ULL, 1134 .ms_kb_base = 0xff1000000ULL, 1135 .serial_base = 0xff1100000ULL, 1136 .nvram_base = 0xff1200000ULL, 1137 .fd_base = 0xff1700000ULL, 1138 .counter_base = 0xff1300000ULL, 1139 .intctl_base = 0xff1400000ULL, 1140 .idreg_base = 0xef0000000ULL, 1141 .dma_base = 0xef0400000ULL, 1142 .esp_base = 0xef0800000ULL, 1143 .le_base = 0xef0c00000ULL, 1144 .bpp_base = 0xef4800000ULL, 1145 .apc_base = 0xefa000000ULL, // XXX should not exist 1146 .aux1_base = 0xff1800000ULL, 1147 .aux2_base = 0xff1a01000ULL, 1148 .dbri_base = 0xee0000000ULL, 1149 .sx_base = 0xf80000000ULL, 1150 .vsimm = { 1151 { 1152 .reg_base = 0x9c000000ULL, 1153 .vram_base = 0xfc000000ULL 1154 }, { 1155 .reg_base = 0x90000000ULL, 1156 .vram_base = 0xf0000000ULL 1157 }, { 1158 .reg_base = 0x94000000ULL 1159 }, { 1160 .reg_base = 0x98000000ULL 1161 } 1162 }, 1163 .ecc_base = 0xf00000000ULL, 1164 .ecc_version = 0x20000000, // version 0, implementation 2 1165 .nvram_machine_id = 0x72, 1166 .machine_id = ss20_id, 1167 .iommu_version = 0x13000000, 1168 .max_mem = 0xf00000000ULL, 1169 .default_cpu_model = "TI SuperSparc II", 1170 }, 1171 /* Voyager */ 1172 { 1173 .iommu_base = 0x10000000, 1174 .tcx_base = 0x50000000, 1175 .slavio_base = 0x70000000, 1176 .ms_kb_base = 0x71000000, 1177 .serial_base = 0x71100000, 1178 .nvram_base = 0x71200000, 1179 .fd_base = 0x71400000, 1180 .counter_base = 0x71d00000, 1181 .intctl_base = 0x71e00000, 1182 .idreg_base = 0x78000000, 1183 .dma_base = 0x78400000, 1184 .esp_base = 0x78800000, 1185 .le_base = 0x78c00000, 1186 .apc_base = 0x71300000, // pmc 1187 .aux1_base = 0x71900000, 1188 .aux2_base = 0x71910000, 1189 .nvram_machine_id = 0x80, 1190 .machine_id = vger_id, 1191 .iommu_version = 0x05000000, 1192 .max_mem = 0x10000000, 1193 .default_cpu_model = "Fujitsu MB86904", 1194 }, 1195 /* LX */ 1196 { 1197 .iommu_base = 0x10000000, 1198 .iommu_pad_base = 0x10004000, 1199 .iommu_pad_len = 0x0fffb000, 1200 .tcx_base = 0x50000000, 1201 .slavio_base = 0x70000000, 1202 .ms_kb_base = 0x71000000, 1203 .serial_base = 0x71100000, 1204 .nvram_base = 0x71200000, 1205 .fd_base = 0x71400000, 1206 .counter_base = 0x71d00000, 1207 .intctl_base = 0x71e00000, 1208 .idreg_base = 0x78000000, 1209 .dma_base = 0x78400000, 1210 .esp_base = 0x78800000, 1211 .le_base = 0x78c00000, 1212 .aux1_base = 0x71900000, 1213 .aux2_base = 0x71910000, 1214 .nvram_machine_id = 0x80, 1215 .machine_id = lx_id, 1216 .iommu_version = 0x04000000, 1217 .max_mem = 0x10000000, 1218 .default_cpu_model = "TI MicroSparc I", 1219 }, 1220 /* SS-4 */ 1221 { 1222 .iommu_base = 0x10000000, 1223 .tcx_base = 0x50000000, 1224 .cs_base = 0x6c000000, 1225 .slavio_base = 0x70000000, 1226 .ms_kb_base = 0x71000000, 1227 .serial_base = 0x71100000, 1228 .nvram_base = 0x71200000, 1229 .fd_base = 0x71400000, 1230 .counter_base = 0x71d00000, 1231 .intctl_base = 0x71e00000, 1232 .idreg_base = 0x78000000, 1233 .dma_base = 0x78400000, 1234 .esp_base = 0x78800000, 1235 .le_base = 0x78c00000, 1236 .apc_base = 0x6a000000, 1237 .aux1_base = 0x71900000, 1238 .aux2_base = 0x71910000, 1239 .nvram_machine_id = 0x80, 1240 .machine_id = ss4_id, 1241 .iommu_version = 0x05000000, 1242 .max_mem = 0x10000000, 1243 .default_cpu_model = "Fujitsu MB86904", 1244 }, 1245 /* SPARCClassic */ 1246 { 1247 .iommu_base = 0x10000000, 1248 .tcx_base = 0x50000000, 1249 .slavio_base = 0x70000000, 1250 .ms_kb_base = 0x71000000, 1251 .serial_base = 0x71100000, 1252 .nvram_base = 0x71200000, 1253 .fd_base = 0x71400000, 1254 .counter_base = 0x71d00000, 1255 .intctl_base = 0x71e00000, 1256 .idreg_base = 0x78000000, 1257 .dma_base = 0x78400000, 1258 .esp_base = 0x78800000, 1259 .le_base = 0x78c00000, 1260 .apc_base = 0x6a000000, 1261 .aux1_base = 0x71900000, 1262 .aux2_base = 0x71910000, 1263 .nvram_machine_id = 0x80, 1264 .machine_id = scls_id, 1265 .iommu_version = 0x05000000, 1266 .max_mem = 0x10000000, 1267 .default_cpu_model = "TI MicroSparc I", 1268 }, 1269 /* SPARCbook */ 1270 { 1271 .iommu_base = 0x10000000, 1272 .tcx_base = 0x50000000, // XXX 1273 .slavio_base = 0x70000000, 1274 .ms_kb_base = 0x71000000, 1275 .serial_base = 0x71100000, 1276 .nvram_base = 0x71200000, 1277 .fd_base = 0x71400000, 1278 .counter_base = 0x71d00000, 1279 .intctl_base = 0x71e00000, 1280 .idreg_base = 0x78000000, 1281 .dma_base = 0x78400000, 1282 .esp_base = 0x78800000, 1283 .le_base = 0x78c00000, 1284 .apc_base = 0x6a000000, 1285 .aux1_base = 0x71900000, 1286 .aux2_base = 0x71910000, 1287 .nvram_machine_id = 0x80, 1288 .machine_id = sbook_id, 1289 .iommu_version = 0x05000000, 1290 .max_mem = 0x10000000, 1291 .default_cpu_model = "TI MicroSparc I", 1292 }, 1293 }; 1294 1295 /* SPARCstation 5 hardware initialisation */ 1296 static void ss5_init(QEMUMachineInitArgs *args) 1297 { 1298 sun4m_hw_init(&sun4m_hwdefs[0], args); 1299 } 1300 1301 /* SPARCstation 10 hardware initialisation */ 1302 static void ss10_init(QEMUMachineInitArgs *args) 1303 { 1304 sun4m_hw_init(&sun4m_hwdefs[1], args); 1305 } 1306 1307 /* SPARCserver 600MP hardware initialisation */ 1308 static void ss600mp_init(QEMUMachineInitArgs *args) 1309 { 1310 sun4m_hw_init(&sun4m_hwdefs[2], args); 1311 } 1312 1313 /* SPARCstation 20 hardware initialisation */ 1314 static void ss20_init(QEMUMachineInitArgs *args) 1315 { 1316 sun4m_hw_init(&sun4m_hwdefs[3], args); 1317 } 1318 1319 /* SPARCstation Voyager hardware initialisation */ 1320 static void vger_init(QEMUMachineInitArgs *args) 1321 { 1322 sun4m_hw_init(&sun4m_hwdefs[4], args); 1323 } 1324 1325 /* SPARCstation LX hardware initialisation */ 1326 static void ss_lx_init(QEMUMachineInitArgs *args) 1327 { 1328 sun4m_hw_init(&sun4m_hwdefs[5], args); 1329 } 1330 1331 /* SPARCstation 4 hardware initialisation */ 1332 static void ss4_init(QEMUMachineInitArgs *args) 1333 { 1334 sun4m_hw_init(&sun4m_hwdefs[6], args); 1335 } 1336 1337 /* SPARCClassic hardware initialisation */ 1338 static void scls_init(QEMUMachineInitArgs *args) 1339 { 1340 sun4m_hw_init(&sun4m_hwdefs[7], args); 1341 } 1342 1343 /* SPARCbook hardware initialisation */ 1344 static void sbook_init(QEMUMachineInitArgs *args) 1345 { 1346 sun4m_hw_init(&sun4m_hwdefs[8], args); 1347 } 1348 1349 static QEMUMachine ss5_machine = { 1350 .name = "SS-5", 1351 .desc = "Sun4m platform, SPARCstation 5", 1352 .init = ss5_init, 1353 .block_default_type = IF_SCSI, 1354 .is_default = 1, 1355 .default_boot_order = "c", 1356 }; 1357 1358 static QEMUMachine ss10_machine = { 1359 .name = "SS-10", 1360 .desc = "Sun4m platform, SPARCstation 10", 1361 .init = ss10_init, 1362 .block_default_type = IF_SCSI, 1363 .max_cpus = 4, 1364 .default_boot_order = "c", 1365 }; 1366 1367 static QEMUMachine ss600mp_machine = { 1368 .name = "SS-600MP", 1369 .desc = "Sun4m platform, SPARCserver 600MP", 1370 .init = ss600mp_init, 1371 .block_default_type = IF_SCSI, 1372 .max_cpus = 4, 1373 .default_boot_order = "c", 1374 }; 1375 1376 static QEMUMachine ss20_machine = { 1377 .name = "SS-20", 1378 .desc = "Sun4m platform, SPARCstation 20", 1379 .init = ss20_init, 1380 .block_default_type = IF_SCSI, 1381 .max_cpus = 4, 1382 .default_boot_order = "c", 1383 }; 1384 1385 static QEMUMachine voyager_machine = { 1386 .name = "Voyager", 1387 .desc = "Sun4m platform, SPARCstation Voyager", 1388 .init = vger_init, 1389 .block_default_type = IF_SCSI, 1390 .default_boot_order = "c", 1391 }; 1392 1393 static QEMUMachine ss_lx_machine = { 1394 .name = "LX", 1395 .desc = "Sun4m platform, SPARCstation LX", 1396 .init = ss_lx_init, 1397 .block_default_type = IF_SCSI, 1398 .default_boot_order = "c", 1399 }; 1400 1401 static QEMUMachine ss4_machine = { 1402 .name = "SS-4", 1403 .desc = "Sun4m platform, SPARCstation 4", 1404 .init = ss4_init, 1405 .block_default_type = IF_SCSI, 1406 .default_boot_order = "c", 1407 }; 1408 1409 static QEMUMachine scls_machine = { 1410 .name = "SPARCClassic", 1411 .desc = "Sun4m platform, SPARCClassic", 1412 .init = scls_init, 1413 .block_default_type = IF_SCSI, 1414 .default_boot_order = "c", 1415 }; 1416 1417 static QEMUMachine sbook_machine = { 1418 .name = "SPARCbook", 1419 .desc = "Sun4m platform, SPARCbook", 1420 .init = sbook_init, 1421 .block_default_type = IF_SCSI, 1422 .default_boot_order = "c", 1423 }; 1424 1425 static void sun4m_register_types(void) 1426 { 1427 type_register_static(&idreg_info); 1428 type_register_static(&afx_info); 1429 type_register_static(&prom_info); 1430 type_register_static(&ram_info); 1431 } 1432 1433 static void sun4m_machine_init(void) 1434 { 1435 qemu_register_machine(&ss5_machine); 1436 qemu_register_machine(&ss10_machine); 1437 qemu_register_machine(&ss600mp_machine); 1438 qemu_register_machine(&ss20_machine); 1439 qemu_register_machine(&voyager_machine); 1440 qemu_register_machine(&ss_lx_machine); 1441 qemu_register_machine(&ss4_machine); 1442 qemu_register_machine(&scls_machine); 1443 qemu_register_machine(&sbook_machine); 1444 } 1445 1446 type_init(sun4m_register_types) 1447 machine_init(sun4m_machine_init); 1448