1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "qemu-common.h" 29 #include "cpu.h" 30 #include "hw/sysbus.h" 31 #include "qemu/error-report.h" 32 #include "qemu/timer.h" 33 #include "hw/sparc/sun4m_iommu.h" 34 #include "hw/timer/m48t59.h" 35 #include "migration/vmstate.h" 36 #include "hw/sparc/sparc32_dma.h" 37 #include "hw/block/fdc.h" 38 #include "sysemu/reset.h" 39 #include "sysemu/sysemu.h" 40 #include "net/net.h" 41 #include "hw/boards.h" 42 #include "hw/scsi/esp.h" 43 #include "hw/nvram/sun_nvram.h" 44 #include "hw/qdev-properties.h" 45 #include "hw/nvram/chrp_nvram.h" 46 #include "hw/nvram/fw_cfg.h" 47 #include "hw/char/escc.h" 48 #include "hw/empty_slot.h" 49 #include "hw/irq.h" 50 #include "hw/loader.h" 51 #include "elf.h" 52 #include "trace.h" 53 54 /* 55 * Sun4m architecture was used in the following machines: 56 * 57 * SPARCserver 6xxMP/xx 58 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 59 * SPARCclassic X (4/10) 60 * SPARCstation LX/ZX (4/30) 61 * SPARCstation Voyager 62 * SPARCstation 10/xx, SPARCserver 10/xx 63 * SPARCstation 5, SPARCserver 5 64 * SPARCstation 20/xx, SPARCserver 20 65 * SPARCstation 4 66 * 67 * See for example: http://www.sunhelp.org/faq/sunref1.html 68 */ 69 70 #define KERNEL_LOAD_ADDR 0x00004000 71 #define CMDLINE_ADDR 0x007ff000 72 #define INITRD_LOAD_ADDR 0x00800000 73 #define PROM_SIZE_MAX (1 * MiB) 74 #define PROM_VADDR 0xffd00000 75 #define PROM_FILENAME "openbios-sparc32" 76 #define CFG_ADDR 0xd00000510ULL 77 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 78 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 79 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 80 81 #define MAX_CPUS 16 82 #define MAX_PILS 16 83 #define MAX_VSIMMS 4 84 85 #define ESCC_CLOCK 4915200 86 87 struct sun4m_hwdef { 88 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 89 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 90 hwaddr serial_base, fd_base; 91 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 92 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 93 hwaddr bpp_base, dbri_base, sx_base; 94 struct { 95 hwaddr reg_base, vram_base; 96 } vsimm[MAX_VSIMMS]; 97 hwaddr ecc_base; 98 uint64_t max_mem; 99 uint32_t ecc_version; 100 uint32_t iommu_version; 101 uint16_t machine_id; 102 uint8_t nvram_machine_id; 103 }; 104 105 const char *fw_cfg_arch_key_name(uint16_t key) 106 { 107 static const struct { 108 uint16_t key; 109 const char *name; 110 } fw_cfg_arch_wellknown_keys[] = { 111 {FW_CFG_SUN4M_DEPTH, "depth"}, 112 {FW_CFG_SUN4M_WIDTH, "width"}, 113 {FW_CFG_SUN4M_HEIGHT, "height"}, 114 }; 115 116 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { 117 if (fw_cfg_arch_wellknown_keys[i].key == key) { 118 return fw_cfg_arch_wellknown_keys[i].name; 119 } 120 } 121 return NULL; 122 } 123 124 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 125 Error **errp) 126 { 127 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 128 } 129 130 static void nvram_init(Nvram *nvram, uint8_t *macaddr, 131 const char *cmdline, const char *boot_devices, 132 ram_addr_t RAM_size, uint32_t kernel_size, 133 int width, int height, int depth, 134 int nvram_machine_id, const char *arch) 135 { 136 unsigned int i; 137 int sysp_end; 138 uint8_t image[0x1ff0]; 139 NvramClass *k = NVRAM_GET_CLASS(nvram); 140 141 memset(image, '\0', sizeof(image)); 142 143 /* OpenBIOS nvram variables partition */ 144 sysp_end = chrp_nvram_create_system_partition(image, 0); 145 146 /* Free space partition */ 147 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 148 149 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 150 nvram_machine_id); 151 152 for (i = 0; i < sizeof(image); i++) { 153 (k->write)(nvram, i, image[i]); 154 } 155 } 156 157 void cpu_check_irqs(CPUSPARCState *env) 158 { 159 CPUState *cs; 160 161 /* We should be holding the BQL before we mess with IRQs */ 162 g_assert(qemu_mutex_iothread_locked()); 163 164 if (env->pil_in && (env->interrupt_index == 0 || 165 (env->interrupt_index & ~15) == TT_EXTINT)) { 166 unsigned int i; 167 168 for (i = 15; i > 0; i--) { 169 if (env->pil_in & (1 << i)) { 170 int old_interrupt = env->interrupt_index; 171 172 env->interrupt_index = TT_EXTINT | i; 173 if (old_interrupt != env->interrupt_index) { 174 cs = env_cpu(env); 175 trace_sun4m_cpu_interrupt(i); 176 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 177 } 178 break; 179 } 180 } 181 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 182 cs = env_cpu(env); 183 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 184 env->interrupt_index = 0; 185 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 186 } 187 } 188 189 static void cpu_kick_irq(SPARCCPU *cpu) 190 { 191 CPUSPARCState *env = &cpu->env; 192 CPUState *cs = CPU(cpu); 193 194 cs->halted = 0; 195 cpu_check_irqs(env); 196 qemu_cpu_kick(cs); 197 } 198 199 static void cpu_set_irq(void *opaque, int irq, int level) 200 { 201 SPARCCPU *cpu = opaque; 202 CPUSPARCState *env = &cpu->env; 203 204 if (level) { 205 trace_sun4m_cpu_set_irq_raise(irq); 206 env->pil_in |= 1 << irq; 207 cpu_kick_irq(cpu); 208 } else { 209 trace_sun4m_cpu_set_irq_lower(irq); 210 env->pil_in &= ~(1 << irq); 211 cpu_check_irqs(env); 212 } 213 } 214 215 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 216 { 217 } 218 219 static void main_cpu_reset(void *opaque) 220 { 221 SPARCCPU *cpu = opaque; 222 CPUState *cs = CPU(cpu); 223 224 cpu_reset(cs); 225 cs->halted = 0; 226 } 227 228 static void secondary_cpu_reset(void *opaque) 229 { 230 SPARCCPU *cpu = opaque; 231 CPUState *cs = CPU(cpu); 232 233 cpu_reset(cs); 234 cs->halted = 1; 235 } 236 237 static void cpu_halt_signal(void *opaque, int irq, int level) 238 { 239 if (level && current_cpu) { 240 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 241 } 242 } 243 244 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 245 { 246 return addr - 0xf0000000ULL; 247 } 248 249 static unsigned long sun4m_load_kernel(const char *kernel_filename, 250 const char *initrd_filename, 251 ram_addr_t RAM_size, 252 uint32_t *initrd_size) 253 { 254 int linux_boot; 255 unsigned int i; 256 long kernel_size; 257 uint8_t *ptr; 258 259 linux_boot = (kernel_filename != NULL); 260 261 kernel_size = 0; 262 if (linux_boot) { 263 int bswap_needed; 264 265 #ifdef BSWAP_NEEDED 266 bswap_needed = 1; 267 #else 268 bswap_needed = 0; 269 #endif 270 kernel_size = load_elf(kernel_filename, NULL, 271 translate_kernel_address, NULL, 272 NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 273 if (kernel_size < 0) 274 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 275 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 276 TARGET_PAGE_SIZE); 277 if (kernel_size < 0) 278 kernel_size = load_image_targphys(kernel_filename, 279 KERNEL_LOAD_ADDR, 280 RAM_size - KERNEL_LOAD_ADDR); 281 if (kernel_size < 0) { 282 error_report("could not load kernel '%s'", kernel_filename); 283 exit(1); 284 } 285 286 /* load initrd */ 287 *initrd_size = 0; 288 if (initrd_filename) { 289 *initrd_size = load_image_targphys(initrd_filename, 290 INITRD_LOAD_ADDR, 291 RAM_size - INITRD_LOAD_ADDR); 292 if ((int)*initrd_size < 0) { 293 error_report("could not load initial ram disk '%s'", 294 initrd_filename); 295 exit(1); 296 } 297 } 298 if (*initrd_size > 0) { 299 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 300 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24); 301 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */ 302 stl_p(ptr + 16, INITRD_LOAD_ADDR); 303 stl_p(ptr + 20, *initrd_size); 304 break; 305 } 306 } 307 } 308 } 309 return kernel_size; 310 } 311 312 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 313 { 314 DeviceState *dev; 315 SysBusDevice *s; 316 317 dev = qdev_create(NULL, TYPE_SUN4M_IOMMU); 318 qdev_prop_set_uint32(dev, "version", version); 319 qdev_init_nofail(dev); 320 s = SYS_BUS_DEVICE(dev); 321 sysbus_connect_irq(s, 0, irq); 322 sysbus_mmio_map(s, 0, addr); 323 324 return s; 325 } 326 327 static void *sparc32_dma_init(hwaddr dma_base, 328 hwaddr esp_base, qemu_irq espdma_irq, 329 hwaddr le_base, qemu_irq ledma_irq) 330 { 331 DeviceState *dma; 332 ESPDMADeviceState *espdma; 333 LEDMADeviceState *ledma; 334 SysBusESPState *esp; 335 SysBusPCNetState *lance; 336 337 dma = qdev_create(NULL, TYPE_SPARC32_DMA); 338 qdev_init_nofail(dma); 339 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); 340 341 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( 342 OBJECT(dma), "espdma")); 343 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); 344 345 esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp")); 346 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base); 347 scsi_bus_legacy_handle_cmdline(&esp->esp.bus); 348 349 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( 350 OBJECT(dma), "ledma")); 351 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq); 352 353 lance = SYSBUS_PCNET(object_resolve_path_component( 354 OBJECT(ledma), "lance")); 355 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base); 356 357 return dma; 358 } 359 360 static DeviceState *slavio_intctl_init(hwaddr addr, 361 hwaddr addrg, 362 qemu_irq **parent_irq) 363 { 364 DeviceState *dev; 365 SysBusDevice *s; 366 unsigned int i, j; 367 368 dev = qdev_create(NULL, "slavio_intctl"); 369 qdev_init_nofail(dev); 370 371 s = SYS_BUS_DEVICE(dev); 372 373 for (i = 0; i < MAX_CPUS; i++) { 374 for (j = 0; j < MAX_PILS; j++) { 375 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 376 } 377 } 378 sysbus_mmio_map(s, 0, addrg); 379 for (i = 0; i < MAX_CPUS; i++) { 380 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 381 } 382 383 return dev; 384 } 385 386 #define SYS_TIMER_OFFSET 0x10000ULL 387 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 388 389 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 390 qemu_irq *cpu_irqs, unsigned int num_cpus) 391 { 392 DeviceState *dev; 393 SysBusDevice *s; 394 unsigned int i; 395 396 dev = qdev_create(NULL, "slavio_timer"); 397 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 398 qdev_init_nofail(dev); 399 s = SYS_BUS_DEVICE(dev); 400 sysbus_connect_irq(s, 0, master_irq); 401 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 402 403 for (i = 0; i < MAX_CPUS; i++) { 404 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 405 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 406 } 407 } 408 409 static qemu_irq slavio_system_powerdown; 410 411 static void slavio_powerdown_req(Notifier *n, void *opaque) 412 { 413 qemu_irq_raise(slavio_system_powerdown); 414 } 415 416 static Notifier slavio_system_powerdown_notifier = { 417 .notify = slavio_powerdown_req 418 }; 419 420 #define MISC_LEDS 0x01600000 421 #define MISC_CFG 0x01800000 422 #define MISC_DIAG 0x01a00000 423 #define MISC_MDM 0x01b00000 424 #define MISC_SYS 0x01f00000 425 426 static void slavio_misc_init(hwaddr base, 427 hwaddr aux1_base, 428 hwaddr aux2_base, qemu_irq irq, 429 qemu_irq fdc_tc) 430 { 431 DeviceState *dev; 432 SysBusDevice *s; 433 434 dev = qdev_create(NULL, "slavio_misc"); 435 qdev_init_nofail(dev); 436 s = SYS_BUS_DEVICE(dev); 437 if (base) { 438 /* 8 bit registers */ 439 /* Slavio control */ 440 sysbus_mmio_map(s, 0, base + MISC_CFG); 441 /* Diagnostics */ 442 sysbus_mmio_map(s, 1, base + MISC_DIAG); 443 /* Modem control */ 444 sysbus_mmio_map(s, 2, base + MISC_MDM); 445 /* 16 bit registers */ 446 /* ss600mp diag LEDs */ 447 sysbus_mmio_map(s, 3, base + MISC_LEDS); 448 /* 32 bit registers */ 449 /* System control */ 450 sysbus_mmio_map(s, 4, base + MISC_SYS); 451 } 452 if (aux1_base) { 453 /* AUX 1 (Misc System Functions) */ 454 sysbus_mmio_map(s, 5, aux1_base); 455 } 456 if (aux2_base) { 457 /* AUX 2 (Software Powerdown Control) */ 458 sysbus_mmio_map(s, 6, aux2_base); 459 } 460 sysbus_connect_irq(s, 0, irq); 461 sysbus_connect_irq(s, 1, fdc_tc); 462 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 463 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 464 } 465 466 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 467 { 468 DeviceState *dev; 469 SysBusDevice *s; 470 471 dev = qdev_create(NULL, "eccmemctl"); 472 qdev_prop_set_uint32(dev, "version", version); 473 qdev_init_nofail(dev); 474 s = SYS_BUS_DEVICE(dev); 475 sysbus_connect_irq(s, 0, irq); 476 sysbus_mmio_map(s, 0, base); 477 if (version == 0) { // SS-600MP only 478 sysbus_mmio_map(s, 1, base + 0x1000); 479 } 480 } 481 482 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 483 { 484 DeviceState *dev; 485 SysBusDevice *s; 486 487 dev = qdev_create(NULL, "apc"); 488 qdev_init_nofail(dev); 489 s = SYS_BUS_DEVICE(dev); 490 /* Power management (APC) XXX: not a Slavio device */ 491 sysbus_mmio_map(s, 0, power_base); 492 sysbus_connect_irq(s, 0, cpu_halt); 493 } 494 495 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 496 int height, int depth) 497 { 498 DeviceState *dev; 499 SysBusDevice *s; 500 501 dev = qdev_create(NULL, "SUNW,tcx"); 502 qdev_prop_set_uint32(dev, "vram_size", vram_size); 503 qdev_prop_set_uint16(dev, "width", width); 504 qdev_prop_set_uint16(dev, "height", height); 505 qdev_prop_set_uint16(dev, "depth", depth); 506 qdev_init_nofail(dev); 507 s = SYS_BUS_DEVICE(dev); 508 509 /* 10/ROM : FCode ROM */ 510 sysbus_mmio_map(s, 0, addr); 511 /* 2/STIP : Stipple */ 512 sysbus_mmio_map(s, 1, addr + 0x04000000ULL); 513 /* 3/BLIT : Blitter */ 514 sysbus_mmio_map(s, 2, addr + 0x06000000ULL); 515 /* 5/RSTIP : Raw Stipple */ 516 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); 517 /* 6/RBLIT : Raw Blitter */ 518 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); 519 /* 7/TEC : Transform Engine */ 520 sysbus_mmio_map(s, 5, addr + 0x00700000ULL); 521 /* 8/CMAP : DAC */ 522 sysbus_mmio_map(s, 6, addr + 0x00200000ULL); 523 /* 9/THC : */ 524 if (depth == 8) { 525 sysbus_mmio_map(s, 7, addr + 0x00300000ULL); 526 } else { 527 sysbus_mmio_map(s, 7, addr + 0x00301000ULL); 528 } 529 /* 11/DHC : */ 530 sysbus_mmio_map(s, 8, addr + 0x00240000ULL); 531 /* 12/ALT : */ 532 sysbus_mmio_map(s, 9, addr + 0x00280000ULL); 533 /* 0/DFB8 : 8-bit plane */ 534 sysbus_mmio_map(s, 10, addr + 0x00800000ULL); 535 /* 1/DFB24 : 24bit plane */ 536 sysbus_mmio_map(s, 11, addr + 0x02000000ULL); 537 /* 4/RDFB32: Raw framebuffer. Control plane */ 538 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); 539 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 540 if (depth == 8) { 541 sysbus_mmio_map(s, 13, addr + 0x00301000ULL); 542 } 543 544 sysbus_connect_irq(s, 0, irq); 545 } 546 547 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 548 int height, int depth) 549 { 550 DeviceState *dev; 551 SysBusDevice *s; 552 553 dev = qdev_create(NULL, "cgthree"); 554 qdev_prop_set_uint32(dev, "vram-size", vram_size); 555 qdev_prop_set_uint16(dev, "width", width); 556 qdev_prop_set_uint16(dev, "height", height); 557 qdev_prop_set_uint16(dev, "depth", depth); 558 qdev_init_nofail(dev); 559 s = SYS_BUS_DEVICE(dev); 560 561 /* FCode ROM */ 562 sysbus_mmio_map(s, 0, addr); 563 /* DAC */ 564 sysbus_mmio_map(s, 1, addr + 0x400000ULL); 565 /* 8-bit plane */ 566 sysbus_mmio_map(s, 2, addr + 0x800000ULL); 567 568 sysbus_connect_irq(s, 0, irq); 569 } 570 571 /* NCR89C100/MACIO Internal ID register */ 572 573 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 574 575 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 576 577 static void idreg_init(hwaddr addr) 578 { 579 DeviceState *dev; 580 SysBusDevice *s; 581 582 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER); 583 qdev_init_nofail(dev); 584 s = SYS_BUS_DEVICE(dev); 585 586 sysbus_mmio_map(s, 0, addr); 587 address_space_write_rom(&address_space_memory, addr, 588 MEMTXATTRS_UNSPECIFIED, 589 idreg_data, sizeof(idreg_data)); 590 } 591 592 #define MACIO_ID_REGISTER(obj) \ 593 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER) 594 595 typedef struct IDRegState { 596 SysBusDevice parent_obj; 597 598 MemoryRegion mem; 599 } IDRegState; 600 601 static void idreg_realize(DeviceState *ds, Error **errp) 602 { 603 IDRegState *s = MACIO_ID_REGISTER(ds); 604 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 605 Error *local_err = NULL; 606 607 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg", 608 sizeof(idreg_data), &local_err); 609 if (local_err) { 610 error_propagate(errp, local_err); 611 return; 612 } 613 614 vmstate_register_ram_global(&s->mem); 615 memory_region_set_readonly(&s->mem, true); 616 sysbus_init_mmio(dev, &s->mem); 617 } 618 619 static void idreg_class_init(ObjectClass *oc, void *data) 620 { 621 DeviceClass *dc = DEVICE_CLASS(oc); 622 623 dc->realize = idreg_realize; 624 } 625 626 static const TypeInfo idreg_info = { 627 .name = TYPE_MACIO_ID_REGISTER, 628 .parent = TYPE_SYS_BUS_DEVICE, 629 .instance_size = sizeof(IDRegState), 630 .class_init = idreg_class_init, 631 }; 632 633 #define TYPE_TCX_AFX "tcx_afx" 634 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX) 635 636 typedef struct AFXState { 637 SysBusDevice parent_obj; 638 639 MemoryRegion mem; 640 } AFXState; 641 642 /* SS-5 TCX AFX register */ 643 static void afx_init(hwaddr addr) 644 { 645 DeviceState *dev; 646 SysBusDevice *s; 647 648 dev = qdev_create(NULL, TYPE_TCX_AFX); 649 qdev_init_nofail(dev); 650 s = SYS_BUS_DEVICE(dev); 651 652 sysbus_mmio_map(s, 0, addr); 653 } 654 655 static void afx_realize(DeviceState *ds, Error **errp) 656 { 657 AFXState *s = TCX_AFX(ds); 658 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 659 Error *local_err = NULL; 660 661 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4, 662 &local_err); 663 if (local_err) { 664 error_propagate(errp, local_err); 665 return; 666 } 667 668 vmstate_register_ram_global(&s->mem); 669 sysbus_init_mmio(dev, &s->mem); 670 } 671 672 static void afx_class_init(ObjectClass *oc, void *data) 673 { 674 DeviceClass *dc = DEVICE_CLASS(oc); 675 676 dc->realize = afx_realize; 677 } 678 679 static const TypeInfo afx_info = { 680 .name = TYPE_TCX_AFX, 681 .parent = TYPE_SYS_BUS_DEVICE, 682 .instance_size = sizeof(AFXState), 683 .class_init = afx_class_init, 684 }; 685 686 #define TYPE_OPENPROM "openprom" 687 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 688 689 typedef struct PROMState { 690 SysBusDevice parent_obj; 691 692 MemoryRegion prom; 693 } PROMState; 694 695 /* Boot PROM (OpenBIOS) */ 696 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 697 { 698 hwaddr *base_addr = (hwaddr *)opaque; 699 return addr + *base_addr - PROM_VADDR; 700 } 701 702 static void prom_init(hwaddr addr, const char *bios_name) 703 { 704 DeviceState *dev; 705 SysBusDevice *s; 706 char *filename; 707 int ret; 708 709 dev = qdev_create(NULL, TYPE_OPENPROM); 710 qdev_init_nofail(dev); 711 s = SYS_BUS_DEVICE(dev); 712 713 sysbus_mmio_map(s, 0, addr); 714 715 /* load boot prom */ 716 if (bios_name == NULL) { 717 bios_name = PROM_FILENAME; 718 } 719 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 720 if (filename) { 721 ret = load_elf(filename, NULL, 722 translate_prom_address, &addr, NULL, 723 NULL, NULL, 1, EM_SPARC, 0, 0); 724 if (ret < 0 || ret > PROM_SIZE_MAX) { 725 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 726 } 727 g_free(filename); 728 } else { 729 ret = -1; 730 } 731 if (ret < 0 || ret > PROM_SIZE_MAX) { 732 error_report("could not load prom '%s'", bios_name); 733 exit(1); 734 } 735 } 736 737 static void prom_realize(DeviceState *ds, Error **errp) 738 { 739 PROMState *s = OPENPROM(ds); 740 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 741 Error *local_err = NULL; 742 743 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom", 744 PROM_SIZE_MAX, &local_err); 745 if (local_err) { 746 error_propagate(errp, local_err); 747 return; 748 } 749 750 vmstate_register_ram_global(&s->prom); 751 memory_region_set_readonly(&s->prom, true); 752 sysbus_init_mmio(dev, &s->prom); 753 } 754 755 static Property prom_properties[] = { 756 {/* end of property list */}, 757 }; 758 759 static void prom_class_init(ObjectClass *klass, void *data) 760 { 761 DeviceClass *dc = DEVICE_CLASS(klass); 762 763 dc->props = prom_properties; 764 dc->realize = prom_realize; 765 } 766 767 static const TypeInfo prom_info = { 768 .name = TYPE_OPENPROM, 769 .parent = TYPE_SYS_BUS_DEVICE, 770 .instance_size = sizeof(PROMState), 771 .class_init = prom_class_init, 772 }; 773 774 #define TYPE_SUN4M_MEMORY "memory" 775 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY) 776 777 typedef struct RamDevice { 778 SysBusDevice parent_obj; 779 780 MemoryRegion ram; 781 uint64_t size; 782 } RamDevice; 783 784 /* System RAM */ 785 static void ram_realize(DeviceState *dev, Error **errp) 786 { 787 RamDevice *d = SUN4M_RAM(dev); 788 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 789 790 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram", 791 d->size); 792 sysbus_init_mmio(sbd, &d->ram); 793 } 794 795 static void ram_init(hwaddr addr, ram_addr_t RAM_size, 796 uint64_t max_mem) 797 { 798 DeviceState *dev; 799 SysBusDevice *s; 800 RamDevice *d; 801 802 /* allocate RAM */ 803 if ((uint64_t)RAM_size > max_mem) { 804 error_report("Too much memory for this machine: %" PRId64 "," 805 " maximum %" PRId64, 806 RAM_size / MiB, max_mem / MiB); 807 exit(1); 808 } 809 dev = qdev_create(NULL, "memory"); 810 s = SYS_BUS_DEVICE(dev); 811 812 d = SUN4M_RAM(dev); 813 d->size = RAM_size; 814 qdev_init_nofail(dev); 815 816 sysbus_mmio_map(s, 0, addr); 817 } 818 819 static Property ram_properties[] = { 820 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 821 DEFINE_PROP_END_OF_LIST(), 822 }; 823 824 static void ram_class_init(ObjectClass *klass, void *data) 825 { 826 DeviceClass *dc = DEVICE_CLASS(klass); 827 828 dc->realize = ram_realize; 829 dc->props = ram_properties; 830 } 831 832 static const TypeInfo ram_info = { 833 .name = TYPE_SUN4M_MEMORY, 834 .parent = TYPE_SYS_BUS_DEVICE, 835 .instance_size = sizeof(RamDevice), 836 .class_init = ram_class_init, 837 }; 838 839 static void cpu_devinit(const char *cpu_type, unsigned int id, 840 uint64_t prom_addr, qemu_irq **cpu_irqs) 841 { 842 CPUState *cs; 843 SPARCCPU *cpu; 844 CPUSPARCState *env; 845 846 cpu = SPARC_CPU(cpu_create(cpu_type)); 847 env = &cpu->env; 848 849 cpu_sparc_set_id(env, id); 850 if (id == 0) { 851 qemu_register_reset(main_cpu_reset, cpu); 852 } else { 853 qemu_register_reset(secondary_cpu_reset, cpu); 854 cs = CPU(cpu); 855 cs->halted = 1; 856 } 857 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 858 env->prom_addr = prom_addr; 859 } 860 861 static void dummy_fdc_tc(void *opaque, int irq, int level) 862 { 863 } 864 865 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, 866 MachineState *machine) 867 { 868 DeviceState *slavio_intctl; 869 unsigned int i; 870 void *nvram; 871 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; 872 qemu_irq fdc_tc; 873 unsigned long kernel_size; 874 uint32_t initrd_size; 875 DriveInfo *fd[MAX_FD]; 876 FWCfgState *fw_cfg; 877 DeviceState *dev; 878 SysBusDevice *s; 879 unsigned int smp_cpus = machine->smp.cpus; 880 unsigned int max_cpus = machine->smp.max_cpus; 881 882 /* init CPUs */ 883 for(i = 0; i < smp_cpus; i++) { 884 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); 885 } 886 887 for (i = smp_cpus; i < MAX_CPUS; i++) 888 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 889 890 891 /* set up devices */ 892 ram_init(0, machine->ram_size, hwdef->max_mem); 893 /* models without ECC don't trap when missing ram is accessed */ 894 if (!hwdef->ecc_base) { 895 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size); 896 } 897 898 prom_init(hwdef->slavio_base, bios_name); 899 900 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 901 hwdef->intctl_base + 0x10000ULL, 902 cpu_irqs); 903 904 for (i = 0; i < 32; i++) { 905 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 906 } 907 for (i = 0; i < MAX_CPUS; i++) { 908 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 909 } 910 911 if (hwdef->idreg_base) { 912 idreg_init(hwdef->idreg_base); 913 } 914 915 if (hwdef->afx_base) { 916 afx_init(hwdef->afx_base); 917 } 918 919 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]); 920 921 if (hwdef->iommu_pad_base) { 922 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 923 Software shouldn't use aliased addresses, neither should it crash 924 when does. Using empty_slot instead of aliasing can help with 925 debugging such accesses */ 926 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); 927 } 928 929 sparc32_dma_init(hwdef->dma_base, 930 hwdef->esp_base, slavio_irq[18], 931 hwdef->le_base, slavio_irq[16]); 932 933 if (graphic_depth != 8 && graphic_depth != 24) { 934 error_report("Unsupported depth: %d", graphic_depth); 935 exit (1); 936 } 937 if (vga_interface_type != VGA_NONE) { 938 if (vga_interface_type == VGA_CG3) { 939 if (graphic_depth != 8) { 940 error_report("Unsupported depth: %d", graphic_depth); 941 exit(1); 942 } 943 944 if (!(graphic_width == 1024 && graphic_height == 768) && 945 !(graphic_width == 1152 && graphic_height == 900)) { 946 error_report("Unsupported resolution: %d x %d", graphic_width, 947 graphic_height); 948 exit(1); 949 } 950 951 /* sbus irq 5 */ 952 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 953 graphic_width, graphic_height, graphic_depth); 954 } else { 955 /* If no display specified, default to TCX */ 956 if (graphic_depth != 8 && graphic_depth != 24) { 957 error_report("Unsupported depth: %d", graphic_depth); 958 exit(1); 959 } 960 961 if (!(graphic_width == 1024 && graphic_height == 768)) { 962 error_report("Unsupported resolution: %d x %d", 963 graphic_width, graphic_height); 964 exit(1); 965 } 966 967 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 968 graphic_width, graphic_height, graphic_depth); 969 } 970 } 971 972 for (i = 0; i < MAX_VSIMMS; i++) { 973 /* vsimm registers probed by OBP */ 974 if (hwdef->vsimm[i].reg_base) { 975 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); 976 } 977 } 978 979 if (hwdef->sx_base) { 980 empty_slot_init(hwdef->sx_base, 0x2000); 981 } 982 983 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8); 984 985 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 986 987 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 988 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 989 dev = qdev_create(NULL, TYPE_ESCC); 990 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics); 991 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 992 qdev_prop_set_uint32(dev, "it_shift", 1); 993 qdev_prop_set_chr(dev, "chrB", NULL); 994 qdev_prop_set_chr(dev, "chrA", NULL); 995 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse); 996 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd); 997 qdev_init_nofail(dev); 998 s = SYS_BUS_DEVICE(dev); 999 sysbus_connect_irq(s, 0, slavio_irq[14]); 1000 sysbus_connect_irq(s, 1, slavio_irq[14]); 1001 sysbus_mmio_map(s, 0, hwdef->ms_kb_base); 1002 1003 dev = qdev_create(NULL, TYPE_ESCC); 1004 qdev_prop_set_uint32(dev, "disabled", 0); 1005 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 1006 qdev_prop_set_uint32(dev, "it_shift", 1); 1007 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 1008 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 1009 qdev_prop_set_uint32(dev, "chnBtype", escc_serial); 1010 qdev_prop_set_uint32(dev, "chnAtype", escc_serial); 1011 qdev_init_nofail(dev); 1012 1013 s = SYS_BUS_DEVICE(dev); 1014 sysbus_connect_irq(s, 0, slavio_irq[15]); 1015 sysbus_connect_irq(s, 1, slavio_irq[15]); 1016 sysbus_mmio_map(s, 0, hwdef->serial_base); 1017 1018 if (hwdef->apc_base) { 1019 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); 1020 } 1021 1022 if (hwdef->fd_base) { 1023 /* there is zero or one floppy drive */ 1024 memset(fd, 0, sizeof(fd)); 1025 fd[0] = drive_get(IF_FLOPPY, 0, 0); 1026 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 1027 &fdc_tc); 1028 } else { 1029 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); 1030 } 1031 1032 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 1033 slavio_irq[30], fdc_tc); 1034 1035 if (hwdef->cs_base) { 1036 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, 1037 slavio_irq[5]); 1038 } 1039 1040 if (hwdef->dbri_base) { 1041 /* ISDN chip with attached CS4215 audio codec */ 1042 /* prom space */ 1043 empty_slot_init(hwdef->dbri_base+0x1000, 0x30); 1044 /* reg space */ 1045 empty_slot_init(hwdef->dbri_base+0x10000, 0x100); 1046 } 1047 1048 if (hwdef->bpp_base) { 1049 /* parallel port */ 1050 empty_slot_init(hwdef->bpp_base, 0x20); 1051 } 1052 1053 initrd_size = 0; 1054 kernel_size = sun4m_load_kernel(machine->kernel_filename, 1055 machine->initrd_filename, 1056 machine->ram_size, &initrd_size); 1057 1058 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline, 1059 machine->boot_order, machine->ram_size, kernel_size, 1060 graphic_width, graphic_height, graphic_depth, 1061 hwdef->nvram_machine_id, "Sun4m"); 1062 1063 if (hwdef->ecc_base) 1064 ecc_init(hwdef->ecc_base, slavio_irq[28], 1065 hwdef->ecc_version); 1066 1067 dev = qdev_create(NULL, TYPE_FW_CFG_MEM); 1068 fw_cfg = FW_CFG(dev); 1069 qdev_prop_set_uint32(dev, "data_width", 1); 1070 qdev_prop_set_bit(dev, "dma_enabled", false); 1071 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1072 OBJECT(fw_cfg), NULL); 1073 qdev_init_nofail(dev); 1074 s = SYS_BUS_DEVICE(dev); 1075 sysbus_mmio_map(s, 0, CFG_ADDR); 1076 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 1077 1078 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 1079 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1080 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1081 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1082 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1083 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1084 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1085 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1086 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1087 if (machine->kernel_cmdline) { 1088 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1089 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1090 machine->kernel_cmdline); 1091 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 1092 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1093 strlen(machine->kernel_cmdline) + 1); 1094 } else { 1095 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1096 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1097 } 1098 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1099 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1100 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 1101 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1102 } 1103 1104 enum { 1105 ss5_id = 32, 1106 vger_id, 1107 lx_id, 1108 ss4_id, 1109 scls_id, 1110 sbook_id, 1111 ss10_id = 64, 1112 ss20_id, 1113 ss600mp_id, 1114 }; 1115 1116 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1117 /* SS-5 */ 1118 { 1119 .iommu_base = 0x10000000, 1120 .iommu_pad_base = 0x10004000, 1121 .iommu_pad_len = 0x0fffb000, 1122 .tcx_base = 0x50000000, 1123 .cs_base = 0x6c000000, 1124 .slavio_base = 0x70000000, 1125 .ms_kb_base = 0x71000000, 1126 .serial_base = 0x71100000, 1127 .nvram_base = 0x71200000, 1128 .fd_base = 0x71400000, 1129 .counter_base = 0x71d00000, 1130 .intctl_base = 0x71e00000, 1131 .idreg_base = 0x78000000, 1132 .dma_base = 0x78400000, 1133 .esp_base = 0x78800000, 1134 .le_base = 0x78c00000, 1135 .apc_base = 0x6a000000, 1136 .afx_base = 0x6e000000, 1137 .aux1_base = 0x71900000, 1138 .aux2_base = 0x71910000, 1139 .nvram_machine_id = 0x80, 1140 .machine_id = ss5_id, 1141 .iommu_version = 0x05000000, 1142 .max_mem = 0x10000000, 1143 }, 1144 /* SS-10 */ 1145 { 1146 .iommu_base = 0xfe0000000ULL, 1147 .tcx_base = 0xe20000000ULL, 1148 .slavio_base = 0xff0000000ULL, 1149 .ms_kb_base = 0xff1000000ULL, 1150 .serial_base = 0xff1100000ULL, 1151 .nvram_base = 0xff1200000ULL, 1152 .fd_base = 0xff1700000ULL, 1153 .counter_base = 0xff1300000ULL, 1154 .intctl_base = 0xff1400000ULL, 1155 .idreg_base = 0xef0000000ULL, 1156 .dma_base = 0xef0400000ULL, 1157 .esp_base = 0xef0800000ULL, 1158 .le_base = 0xef0c00000ULL, 1159 .apc_base = 0xefa000000ULL, // XXX should not exist 1160 .aux1_base = 0xff1800000ULL, 1161 .aux2_base = 0xff1a01000ULL, 1162 .ecc_base = 0xf00000000ULL, 1163 .ecc_version = 0x10000000, // version 0, implementation 1 1164 .nvram_machine_id = 0x72, 1165 .machine_id = ss10_id, 1166 .iommu_version = 0x03000000, 1167 .max_mem = 0xf00000000ULL, 1168 }, 1169 /* SS-600MP */ 1170 { 1171 .iommu_base = 0xfe0000000ULL, 1172 .tcx_base = 0xe20000000ULL, 1173 .slavio_base = 0xff0000000ULL, 1174 .ms_kb_base = 0xff1000000ULL, 1175 .serial_base = 0xff1100000ULL, 1176 .nvram_base = 0xff1200000ULL, 1177 .counter_base = 0xff1300000ULL, 1178 .intctl_base = 0xff1400000ULL, 1179 .dma_base = 0xef0081000ULL, 1180 .esp_base = 0xef0080000ULL, 1181 .le_base = 0xef0060000ULL, 1182 .apc_base = 0xefa000000ULL, // XXX should not exist 1183 .aux1_base = 0xff1800000ULL, 1184 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1185 .ecc_base = 0xf00000000ULL, 1186 .ecc_version = 0x00000000, // version 0, implementation 0 1187 .nvram_machine_id = 0x71, 1188 .machine_id = ss600mp_id, 1189 .iommu_version = 0x01000000, 1190 .max_mem = 0xf00000000ULL, 1191 }, 1192 /* SS-20 */ 1193 { 1194 .iommu_base = 0xfe0000000ULL, 1195 .tcx_base = 0xe20000000ULL, 1196 .slavio_base = 0xff0000000ULL, 1197 .ms_kb_base = 0xff1000000ULL, 1198 .serial_base = 0xff1100000ULL, 1199 .nvram_base = 0xff1200000ULL, 1200 .fd_base = 0xff1700000ULL, 1201 .counter_base = 0xff1300000ULL, 1202 .intctl_base = 0xff1400000ULL, 1203 .idreg_base = 0xef0000000ULL, 1204 .dma_base = 0xef0400000ULL, 1205 .esp_base = 0xef0800000ULL, 1206 .le_base = 0xef0c00000ULL, 1207 .bpp_base = 0xef4800000ULL, 1208 .apc_base = 0xefa000000ULL, // XXX should not exist 1209 .aux1_base = 0xff1800000ULL, 1210 .aux2_base = 0xff1a01000ULL, 1211 .dbri_base = 0xee0000000ULL, 1212 .sx_base = 0xf80000000ULL, 1213 .vsimm = { 1214 { 1215 .reg_base = 0x9c000000ULL, 1216 .vram_base = 0xfc000000ULL 1217 }, { 1218 .reg_base = 0x90000000ULL, 1219 .vram_base = 0xf0000000ULL 1220 }, { 1221 .reg_base = 0x94000000ULL 1222 }, { 1223 .reg_base = 0x98000000ULL 1224 } 1225 }, 1226 .ecc_base = 0xf00000000ULL, 1227 .ecc_version = 0x20000000, // version 0, implementation 2 1228 .nvram_machine_id = 0x72, 1229 .machine_id = ss20_id, 1230 .iommu_version = 0x13000000, 1231 .max_mem = 0xf00000000ULL, 1232 }, 1233 /* Voyager */ 1234 { 1235 .iommu_base = 0x10000000, 1236 .tcx_base = 0x50000000, 1237 .slavio_base = 0x70000000, 1238 .ms_kb_base = 0x71000000, 1239 .serial_base = 0x71100000, 1240 .nvram_base = 0x71200000, 1241 .fd_base = 0x71400000, 1242 .counter_base = 0x71d00000, 1243 .intctl_base = 0x71e00000, 1244 .idreg_base = 0x78000000, 1245 .dma_base = 0x78400000, 1246 .esp_base = 0x78800000, 1247 .le_base = 0x78c00000, 1248 .apc_base = 0x71300000, // pmc 1249 .aux1_base = 0x71900000, 1250 .aux2_base = 0x71910000, 1251 .nvram_machine_id = 0x80, 1252 .machine_id = vger_id, 1253 .iommu_version = 0x05000000, 1254 .max_mem = 0x10000000, 1255 }, 1256 /* LX */ 1257 { 1258 .iommu_base = 0x10000000, 1259 .iommu_pad_base = 0x10004000, 1260 .iommu_pad_len = 0x0fffb000, 1261 .tcx_base = 0x50000000, 1262 .slavio_base = 0x70000000, 1263 .ms_kb_base = 0x71000000, 1264 .serial_base = 0x71100000, 1265 .nvram_base = 0x71200000, 1266 .fd_base = 0x71400000, 1267 .counter_base = 0x71d00000, 1268 .intctl_base = 0x71e00000, 1269 .idreg_base = 0x78000000, 1270 .dma_base = 0x78400000, 1271 .esp_base = 0x78800000, 1272 .le_base = 0x78c00000, 1273 .aux1_base = 0x71900000, 1274 .aux2_base = 0x71910000, 1275 .nvram_machine_id = 0x80, 1276 .machine_id = lx_id, 1277 .iommu_version = 0x04000000, 1278 .max_mem = 0x10000000, 1279 }, 1280 /* SS-4 */ 1281 { 1282 .iommu_base = 0x10000000, 1283 .tcx_base = 0x50000000, 1284 .cs_base = 0x6c000000, 1285 .slavio_base = 0x70000000, 1286 .ms_kb_base = 0x71000000, 1287 .serial_base = 0x71100000, 1288 .nvram_base = 0x71200000, 1289 .fd_base = 0x71400000, 1290 .counter_base = 0x71d00000, 1291 .intctl_base = 0x71e00000, 1292 .idreg_base = 0x78000000, 1293 .dma_base = 0x78400000, 1294 .esp_base = 0x78800000, 1295 .le_base = 0x78c00000, 1296 .apc_base = 0x6a000000, 1297 .aux1_base = 0x71900000, 1298 .aux2_base = 0x71910000, 1299 .nvram_machine_id = 0x80, 1300 .machine_id = ss4_id, 1301 .iommu_version = 0x05000000, 1302 .max_mem = 0x10000000, 1303 }, 1304 /* SPARCClassic */ 1305 { 1306 .iommu_base = 0x10000000, 1307 .tcx_base = 0x50000000, 1308 .slavio_base = 0x70000000, 1309 .ms_kb_base = 0x71000000, 1310 .serial_base = 0x71100000, 1311 .nvram_base = 0x71200000, 1312 .fd_base = 0x71400000, 1313 .counter_base = 0x71d00000, 1314 .intctl_base = 0x71e00000, 1315 .idreg_base = 0x78000000, 1316 .dma_base = 0x78400000, 1317 .esp_base = 0x78800000, 1318 .le_base = 0x78c00000, 1319 .apc_base = 0x6a000000, 1320 .aux1_base = 0x71900000, 1321 .aux2_base = 0x71910000, 1322 .nvram_machine_id = 0x80, 1323 .machine_id = scls_id, 1324 .iommu_version = 0x05000000, 1325 .max_mem = 0x10000000, 1326 }, 1327 /* SPARCbook */ 1328 { 1329 .iommu_base = 0x10000000, 1330 .tcx_base = 0x50000000, // XXX 1331 .slavio_base = 0x70000000, 1332 .ms_kb_base = 0x71000000, 1333 .serial_base = 0x71100000, 1334 .nvram_base = 0x71200000, 1335 .fd_base = 0x71400000, 1336 .counter_base = 0x71d00000, 1337 .intctl_base = 0x71e00000, 1338 .idreg_base = 0x78000000, 1339 .dma_base = 0x78400000, 1340 .esp_base = 0x78800000, 1341 .le_base = 0x78c00000, 1342 .apc_base = 0x6a000000, 1343 .aux1_base = 0x71900000, 1344 .aux2_base = 0x71910000, 1345 .nvram_machine_id = 0x80, 1346 .machine_id = sbook_id, 1347 .iommu_version = 0x05000000, 1348 .max_mem = 0x10000000, 1349 }, 1350 }; 1351 1352 /* SPARCstation 5 hardware initialisation */ 1353 static void ss5_init(MachineState *machine) 1354 { 1355 sun4m_hw_init(&sun4m_hwdefs[0], machine); 1356 } 1357 1358 /* SPARCstation 10 hardware initialisation */ 1359 static void ss10_init(MachineState *machine) 1360 { 1361 sun4m_hw_init(&sun4m_hwdefs[1], machine); 1362 } 1363 1364 /* SPARCserver 600MP hardware initialisation */ 1365 static void ss600mp_init(MachineState *machine) 1366 { 1367 sun4m_hw_init(&sun4m_hwdefs[2], machine); 1368 } 1369 1370 /* SPARCstation 20 hardware initialisation */ 1371 static void ss20_init(MachineState *machine) 1372 { 1373 sun4m_hw_init(&sun4m_hwdefs[3], machine); 1374 } 1375 1376 /* SPARCstation Voyager hardware initialisation */ 1377 static void vger_init(MachineState *machine) 1378 { 1379 sun4m_hw_init(&sun4m_hwdefs[4], machine); 1380 } 1381 1382 /* SPARCstation LX hardware initialisation */ 1383 static void ss_lx_init(MachineState *machine) 1384 { 1385 sun4m_hw_init(&sun4m_hwdefs[5], machine); 1386 } 1387 1388 /* SPARCstation 4 hardware initialisation */ 1389 static void ss4_init(MachineState *machine) 1390 { 1391 sun4m_hw_init(&sun4m_hwdefs[6], machine); 1392 } 1393 1394 /* SPARCClassic hardware initialisation */ 1395 static void scls_init(MachineState *machine) 1396 { 1397 sun4m_hw_init(&sun4m_hwdefs[7], machine); 1398 } 1399 1400 /* SPARCbook hardware initialisation */ 1401 static void sbook_init(MachineState *machine) 1402 { 1403 sun4m_hw_init(&sun4m_hwdefs[8], machine); 1404 } 1405 1406 static void ss5_class_init(ObjectClass *oc, void *data) 1407 { 1408 MachineClass *mc = MACHINE_CLASS(oc); 1409 1410 mc->desc = "Sun4m platform, SPARCstation 5"; 1411 mc->init = ss5_init; 1412 mc->block_default_type = IF_SCSI; 1413 mc->is_default = 1; 1414 mc->default_boot_order = "c"; 1415 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1416 mc->default_display = "tcx"; 1417 } 1418 1419 static const TypeInfo ss5_type = { 1420 .name = MACHINE_TYPE_NAME("SS-5"), 1421 .parent = TYPE_MACHINE, 1422 .class_init = ss5_class_init, 1423 }; 1424 1425 static void ss10_class_init(ObjectClass *oc, void *data) 1426 { 1427 MachineClass *mc = MACHINE_CLASS(oc); 1428 1429 mc->desc = "Sun4m platform, SPARCstation 10"; 1430 mc->init = ss10_init; 1431 mc->block_default_type = IF_SCSI; 1432 mc->max_cpus = 4; 1433 mc->default_boot_order = "c"; 1434 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1435 mc->default_display = "tcx"; 1436 } 1437 1438 static const TypeInfo ss10_type = { 1439 .name = MACHINE_TYPE_NAME("SS-10"), 1440 .parent = TYPE_MACHINE, 1441 .class_init = ss10_class_init, 1442 }; 1443 1444 static void ss600mp_class_init(ObjectClass *oc, void *data) 1445 { 1446 MachineClass *mc = MACHINE_CLASS(oc); 1447 1448 mc->desc = "Sun4m platform, SPARCserver 600MP"; 1449 mc->init = ss600mp_init; 1450 mc->block_default_type = IF_SCSI; 1451 mc->max_cpus = 4; 1452 mc->default_boot_order = "c"; 1453 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1454 mc->default_display = "tcx"; 1455 } 1456 1457 static const TypeInfo ss600mp_type = { 1458 .name = MACHINE_TYPE_NAME("SS-600MP"), 1459 .parent = TYPE_MACHINE, 1460 .class_init = ss600mp_class_init, 1461 }; 1462 1463 static void ss20_class_init(ObjectClass *oc, void *data) 1464 { 1465 MachineClass *mc = MACHINE_CLASS(oc); 1466 1467 mc->desc = "Sun4m platform, SPARCstation 20"; 1468 mc->init = ss20_init; 1469 mc->block_default_type = IF_SCSI; 1470 mc->max_cpus = 4; 1471 mc->default_boot_order = "c"; 1472 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1473 mc->default_display = "tcx"; 1474 } 1475 1476 static const TypeInfo ss20_type = { 1477 .name = MACHINE_TYPE_NAME("SS-20"), 1478 .parent = TYPE_MACHINE, 1479 .class_init = ss20_class_init, 1480 }; 1481 1482 static void voyager_class_init(ObjectClass *oc, void *data) 1483 { 1484 MachineClass *mc = MACHINE_CLASS(oc); 1485 1486 mc->desc = "Sun4m platform, SPARCstation Voyager"; 1487 mc->init = vger_init; 1488 mc->block_default_type = IF_SCSI; 1489 mc->default_boot_order = "c"; 1490 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1491 mc->default_display = "tcx"; 1492 } 1493 1494 static const TypeInfo voyager_type = { 1495 .name = MACHINE_TYPE_NAME("Voyager"), 1496 .parent = TYPE_MACHINE, 1497 .class_init = voyager_class_init, 1498 }; 1499 1500 static void ss_lx_class_init(ObjectClass *oc, void *data) 1501 { 1502 MachineClass *mc = MACHINE_CLASS(oc); 1503 1504 mc->desc = "Sun4m platform, SPARCstation LX"; 1505 mc->init = ss_lx_init; 1506 mc->block_default_type = IF_SCSI; 1507 mc->default_boot_order = "c"; 1508 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1509 mc->default_display = "tcx"; 1510 } 1511 1512 static const TypeInfo ss_lx_type = { 1513 .name = MACHINE_TYPE_NAME("LX"), 1514 .parent = TYPE_MACHINE, 1515 .class_init = ss_lx_class_init, 1516 }; 1517 1518 static void ss4_class_init(ObjectClass *oc, void *data) 1519 { 1520 MachineClass *mc = MACHINE_CLASS(oc); 1521 1522 mc->desc = "Sun4m platform, SPARCstation 4"; 1523 mc->init = ss4_init; 1524 mc->block_default_type = IF_SCSI; 1525 mc->default_boot_order = "c"; 1526 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1527 mc->default_display = "tcx"; 1528 } 1529 1530 static const TypeInfo ss4_type = { 1531 .name = MACHINE_TYPE_NAME("SS-4"), 1532 .parent = TYPE_MACHINE, 1533 .class_init = ss4_class_init, 1534 }; 1535 1536 static void scls_class_init(ObjectClass *oc, void *data) 1537 { 1538 MachineClass *mc = MACHINE_CLASS(oc); 1539 1540 mc->desc = "Sun4m platform, SPARCClassic"; 1541 mc->init = scls_init; 1542 mc->block_default_type = IF_SCSI; 1543 mc->default_boot_order = "c"; 1544 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1545 mc->default_display = "tcx"; 1546 } 1547 1548 static const TypeInfo scls_type = { 1549 .name = MACHINE_TYPE_NAME("SPARCClassic"), 1550 .parent = TYPE_MACHINE, 1551 .class_init = scls_class_init, 1552 }; 1553 1554 static void sbook_class_init(ObjectClass *oc, void *data) 1555 { 1556 MachineClass *mc = MACHINE_CLASS(oc); 1557 1558 mc->desc = "Sun4m platform, SPARCbook"; 1559 mc->init = sbook_init; 1560 mc->block_default_type = IF_SCSI; 1561 mc->default_boot_order = "c"; 1562 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1563 mc->default_display = "tcx"; 1564 } 1565 1566 static const TypeInfo sbook_type = { 1567 .name = MACHINE_TYPE_NAME("SPARCbook"), 1568 .parent = TYPE_MACHINE, 1569 .class_init = sbook_class_init, 1570 }; 1571 1572 static void sun4m_register_types(void) 1573 { 1574 type_register_static(&idreg_info); 1575 type_register_static(&afx_info); 1576 type_register_static(&prom_info); 1577 type_register_static(&ram_info); 1578 1579 type_register_static(&ss5_type); 1580 type_register_static(&ss10_type); 1581 type_register_static(&ss600mp_type); 1582 type_register_static(&ss20_type); 1583 type_register_static(&voyager_type); 1584 type_register_static(&ss_lx_type); 1585 type_register_static(&ss4_type); 1586 type_register_static(&scls_type); 1587 type_register_static(&sbook_type); 1588 } 1589 1590 type_init(sun4m_register_types) 1591