1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/sysbus.h" 29 #include "qemu/error-report.h" 30 #include "qemu/timer.h" 31 #include "hw/sparc/sun4m_iommu.h" 32 #include "hw/timer/m48t59.h" 33 #include "hw/sparc/sparc32_dma.h" 34 #include "hw/block/fdc.h" 35 #include "sysemu/sysemu.h" 36 #include "net/net.h" 37 #include "hw/boards.h" 38 #include "hw/scsi/esp.h" 39 #include "hw/isa/isa.h" 40 #include "hw/nvram/sun_nvram.h" 41 #include "hw/nvram/chrp_nvram.h" 42 #include "hw/nvram/fw_cfg.h" 43 #include "hw/char/escc.h" 44 #include "hw/empty_slot.h" 45 #include "hw/loader.h" 46 #include "elf.h" 47 #include "trace.h" 48 #include "qemu/cutils.h" 49 50 /* 51 * Sun4m architecture was used in the following machines: 52 * 53 * SPARCserver 6xxMP/xx 54 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 55 * SPARCclassic X (4/10) 56 * SPARCstation LX/ZX (4/30) 57 * SPARCstation Voyager 58 * SPARCstation 10/xx, SPARCserver 10/xx 59 * SPARCstation 5, SPARCserver 5 60 * SPARCstation 20/xx, SPARCserver 20 61 * SPARCstation 4 62 * 63 * See for example: http://www.sunhelp.org/faq/sunref1.html 64 */ 65 66 #define KERNEL_LOAD_ADDR 0x00004000 67 #define CMDLINE_ADDR 0x007ff000 68 #define INITRD_LOAD_ADDR 0x00800000 69 #define PROM_SIZE_MAX (1024 * 1024) 70 #define PROM_VADDR 0xffd00000 71 #define PROM_FILENAME "openbios-sparc32" 72 #define CFG_ADDR 0xd00000510ULL 73 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 74 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 75 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 76 77 #define MAX_CPUS 16 78 #define MAX_PILS 16 79 #define MAX_VSIMMS 4 80 81 #define ESCC_CLOCK 4915200 82 83 struct sun4m_hwdef { 84 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 85 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 86 hwaddr serial_base, fd_base; 87 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 88 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 89 hwaddr bpp_base, dbri_base, sx_base; 90 struct { 91 hwaddr reg_base, vram_base; 92 } vsimm[MAX_VSIMMS]; 93 hwaddr ecc_base; 94 uint64_t max_mem; 95 uint32_t ecc_version; 96 uint32_t iommu_version; 97 uint16_t machine_id; 98 uint8_t nvram_machine_id; 99 }; 100 101 void DMA_init(ISABus *bus, int high_page_enable) 102 { 103 } 104 105 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 106 Error **errp) 107 { 108 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 109 } 110 111 static void nvram_init(Nvram *nvram, uint8_t *macaddr, 112 const char *cmdline, const char *boot_devices, 113 ram_addr_t RAM_size, uint32_t kernel_size, 114 int width, int height, int depth, 115 int nvram_machine_id, const char *arch) 116 { 117 unsigned int i; 118 int sysp_end; 119 uint8_t image[0x1ff0]; 120 NvramClass *k = NVRAM_GET_CLASS(nvram); 121 122 memset(image, '\0', sizeof(image)); 123 124 /* OpenBIOS nvram variables partition */ 125 sysp_end = chrp_nvram_create_system_partition(image, 0); 126 127 /* Free space partition */ 128 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 129 130 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 131 nvram_machine_id); 132 133 for (i = 0; i < sizeof(image); i++) { 134 (k->write)(nvram, i, image[i]); 135 } 136 } 137 138 void cpu_check_irqs(CPUSPARCState *env) 139 { 140 CPUState *cs; 141 142 /* We should be holding the BQL before we mess with IRQs */ 143 g_assert(qemu_mutex_iothread_locked()); 144 145 if (env->pil_in && (env->interrupt_index == 0 || 146 (env->interrupt_index & ~15) == TT_EXTINT)) { 147 unsigned int i; 148 149 for (i = 15; i > 0; i--) { 150 if (env->pil_in & (1 << i)) { 151 int old_interrupt = env->interrupt_index; 152 153 env->interrupt_index = TT_EXTINT | i; 154 if (old_interrupt != env->interrupt_index) { 155 cs = CPU(sparc_env_get_cpu(env)); 156 trace_sun4m_cpu_interrupt(i); 157 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 158 } 159 break; 160 } 161 } 162 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 163 cs = CPU(sparc_env_get_cpu(env)); 164 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 165 env->interrupt_index = 0; 166 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 167 } 168 } 169 170 static void cpu_kick_irq(SPARCCPU *cpu) 171 { 172 CPUSPARCState *env = &cpu->env; 173 CPUState *cs = CPU(cpu); 174 175 cs->halted = 0; 176 cpu_check_irqs(env); 177 qemu_cpu_kick(cs); 178 } 179 180 static void cpu_set_irq(void *opaque, int irq, int level) 181 { 182 SPARCCPU *cpu = opaque; 183 CPUSPARCState *env = &cpu->env; 184 185 if (level) { 186 trace_sun4m_cpu_set_irq_raise(irq); 187 env->pil_in |= 1 << irq; 188 cpu_kick_irq(cpu); 189 } else { 190 trace_sun4m_cpu_set_irq_lower(irq); 191 env->pil_in &= ~(1 << irq); 192 cpu_check_irqs(env); 193 } 194 } 195 196 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 197 { 198 } 199 200 static void main_cpu_reset(void *opaque) 201 { 202 SPARCCPU *cpu = opaque; 203 CPUState *cs = CPU(cpu); 204 205 cpu_reset(cs); 206 cs->halted = 0; 207 } 208 209 static void secondary_cpu_reset(void *opaque) 210 { 211 SPARCCPU *cpu = opaque; 212 CPUState *cs = CPU(cpu); 213 214 cpu_reset(cs); 215 cs->halted = 1; 216 } 217 218 static void cpu_halt_signal(void *opaque, int irq, int level) 219 { 220 if (level && current_cpu) { 221 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 222 } 223 } 224 225 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 226 { 227 return addr - 0xf0000000ULL; 228 } 229 230 static unsigned long sun4m_load_kernel(const char *kernel_filename, 231 const char *initrd_filename, 232 ram_addr_t RAM_size) 233 { 234 int linux_boot; 235 unsigned int i; 236 long initrd_size, kernel_size; 237 uint8_t *ptr; 238 239 linux_boot = (kernel_filename != NULL); 240 241 kernel_size = 0; 242 if (linux_boot) { 243 int bswap_needed; 244 245 #ifdef BSWAP_NEEDED 246 bswap_needed = 1; 247 #else 248 bswap_needed = 0; 249 #endif 250 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 251 NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 252 if (kernel_size < 0) 253 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 254 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 255 TARGET_PAGE_SIZE); 256 if (kernel_size < 0) 257 kernel_size = load_image_targphys(kernel_filename, 258 KERNEL_LOAD_ADDR, 259 RAM_size - KERNEL_LOAD_ADDR); 260 if (kernel_size < 0) { 261 error_report("could not load kernel '%s'", kernel_filename); 262 exit(1); 263 } 264 265 /* load initrd */ 266 initrd_size = 0; 267 if (initrd_filename) { 268 initrd_size = load_image_targphys(initrd_filename, 269 INITRD_LOAD_ADDR, 270 RAM_size - INITRD_LOAD_ADDR); 271 if (initrd_size < 0) { 272 error_report("could not load initial ram disk '%s'", 273 initrd_filename); 274 exit(1); 275 } 276 } 277 if (initrd_size > 0) { 278 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 279 ptr = rom_ptr(KERNEL_LOAD_ADDR + i); 280 if (ldl_p(ptr) == 0x48647253) { // HdrS 281 stl_p(ptr + 16, INITRD_LOAD_ADDR); 282 stl_p(ptr + 20, initrd_size); 283 break; 284 } 285 } 286 } 287 } 288 return kernel_size; 289 } 290 291 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 292 { 293 DeviceState *dev; 294 SysBusDevice *s; 295 296 dev = qdev_create(NULL, TYPE_SUN4M_IOMMU); 297 qdev_prop_set_uint32(dev, "version", version); 298 qdev_init_nofail(dev); 299 s = SYS_BUS_DEVICE(dev); 300 sysbus_connect_irq(s, 0, irq); 301 sysbus_mmio_map(s, 0, addr); 302 303 return s; 304 } 305 306 static void *sparc32_dma_init(hwaddr dma_base, 307 hwaddr esp_base, qemu_irq espdma_irq, 308 hwaddr le_base, qemu_irq ledma_irq) 309 { 310 DeviceState *dma; 311 ESPDMADeviceState *espdma; 312 LEDMADeviceState *ledma; 313 SysBusESPState *esp; 314 SysBusPCNetState *lance; 315 316 dma = qdev_create(NULL, TYPE_SPARC32_DMA); 317 qdev_init_nofail(dma); 318 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); 319 320 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( 321 OBJECT(dma), "espdma")); 322 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); 323 324 esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp")); 325 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base); 326 scsi_bus_legacy_handle_cmdline(&esp->esp.bus); 327 328 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( 329 OBJECT(dma), "ledma")); 330 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq); 331 332 lance = SYSBUS_PCNET(object_resolve_path_component( 333 OBJECT(ledma), "lance")); 334 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base); 335 336 return dma; 337 } 338 339 static DeviceState *slavio_intctl_init(hwaddr addr, 340 hwaddr addrg, 341 qemu_irq **parent_irq) 342 { 343 DeviceState *dev; 344 SysBusDevice *s; 345 unsigned int i, j; 346 347 dev = qdev_create(NULL, "slavio_intctl"); 348 qdev_init_nofail(dev); 349 350 s = SYS_BUS_DEVICE(dev); 351 352 for (i = 0; i < MAX_CPUS; i++) { 353 for (j = 0; j < MAX_PILS; j++) { 354 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 355 } 356 } 357 sysbus_mmio_map(s, 0, addrg); 358 for (i = 0; i < MAX_CPUS; i++) { 359 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 360 } 361 362 return dev; 363 } 364 365 #define SYS_TIMER_OFFSET 0x10000ULL 366 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 367 368 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 369 qemu_irq *cpu_irqs, unsigned int num_cpus) 370 { 371 DeviceState *dev; 372 SysBusDevice *s; 373 unsigned int i; 374 375 dev = qdev_create(NULL, "slavio_timer"); 376 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 377 qdev_init_nofail(dev); 378 s = SYS_BUS_DEVICE(dev); 379 sysbus_connect_irq(s, 0, master_irq); 380 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 381 382 for (i = 0; i < MAX_CPUS; i++) { 383 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 384 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 385 } 386 } 387 388 static qemu_irq slavio_system_powerdown; 389 390 static void slavio_powerdown_req(Notifier *n, void *opaque) 391 { 392 qemu_irq_raise(slavio_system_powerdown); 393 } 394 395 static Notifier slavio_system_powerdown_notifier = { 396 .notify = slavio_powerdown_req 397 }; 398 399 #define MISC_LEDS 0x01600000 400 #define MISC_CFG 0x01800000 401 #define MISC_DIAG 0x01a00000 402 #define MISC_MDM 0x01b00000 403 #define MISC_SYS 0x01f00000 404 405 static void slavio_misc_init(hwaddr base, 406 hwaddr aux1_base, 407 hwaddr aux2_base, qemu_irq irq, 408 qemu_irq fdc_tc) 409 { 410 DeviceState *dev; 411 SysBusDevice *s; 412 413 dev = qdev_create(NULL, "slavio_misc"); 414 qdev_init_nofail(dev); 415 s = SYS_BUS_DEVICE(dev); 416 if (base) { 417 /* 8 bit registers */ 418 /* Slavio control */ 419 sysbus_mmio_map(s, 0, base + MISC_CFG); 420 /* Diagnostics */ 421 sysbus_mmio_map(s, 1, base + MISC_DIAG); 422 /* Modem control */ 423 sysbus_mmio_map(s, 2, base + MISC_MDM); 424 /* 16 bit registers */ 425 /* ss600mp diag LEDs */ 426 sysbus_mmio_map(s, 3, base + MISC_LEDS); 427 /* 32 bit registers */ 428 /* System control */ 429 sysbus_mmio_map(s, 4, base + MISC_SYS); 430 } 431 if (aux1_base) { 432 /* AUX 1 (Misc System Functions) */ 433 sysbus_mmio_map(s, 5, aux1_base); 434 } 435 if (aux2_base) { 436 /* AUX 2 (Software Powerdown Control) */ 437 sysbus_mmio_map(s, 6, aux2_base); 438 } 439 sysbus_connect_irq(s, 0, irq); 440 sysbus_connect_irq(s, 1, fdc_tc); 441 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 442 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 443 } 444 445 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 446 { 447 DeviceState *dev; 448 SysBusDevice *s; 449 450 dev = qdev_create(NULL, "eccmemctl"); 451 qdev_prop_set_uint32(dev, "version", version); 452 qdev_init_nofail(dev); 453 s = SYS_BUS_DEVICE(dev); 454 sysbus_connect_irq(s, 0, irq); 455 sysbus_mmio_map(s, 0, base); 456 if (version == 0) { // SS-600MP only 457 sysbus_mmio_map(s, 1, base + 0x1000); 458 } 459 } 460 461 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 462 { 463 DeviceState *dev; 464 SysBusDevice *s; 465 466 dev = qdev_create(NULL, "apc"); 467 qdev_init_nofail(dev); 468 s = SYS_BUS_DEVICE(dev); 469 /* Power management (APC) XXX: not a Slavio device */ 470 sysbus_mmio_map(s, 0, power_base); 471 sysbus_connect_irq(s, 0, cpu_halt); 472 } 473 474 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 475 int height, int depth) 476 { 477 DeviceState *dev; 478 SysBusDevice *s; 479 480 dev = qdev_create(NULL, "SUNW,tcx"); 481 qdev_prop_set_uint32(dev, "vram_size", vram_size); 482 qdev_prop_set_uint16(dev, "width", width); 483 qdev_prop_set_uint16(dev, "height", height); 484 qdev_prop_set_uint16(dev, "depth", depth); 485 qdev_init_nofail(dev); 486 s = SYS_BUS_DEVICE(dev); 487 488 /* 10/ROM : FCode ROM */ 489 sysbus_mmio_map(s, 0, addr); 490 /* 2/STIP : Stipple */ 491 sysbus_mmio_map(s, 1, addr + 0x04000000ULL); 492 /* 3/BLIT : Blitter */ 493 sysbus_mmio_map(s, 2, addr + 0x06000000ULL); 494 /* 5/RSTIP : Raw Stipple */ 495 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); 496 /* 6/RBLIT : Raw Blitter */ 497 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); 498 /* 7/TEC : Transform Engine */ 499 sysbus_mmio_map(s, 5, addr + 0x00700000ULL); 500 /* 8/CMAP : DAC */ 501 sysbus_mmio_map(s, 6, addr + 0x00200000ULL); 502 /* 9/THC : */ 503 if (depth == 8) { 504 sysbus_mmio_map(s, 7, addr + 0x00300000ULL); 505 } else { 506 sysbus_mmio_map(s, 7, addr + 0x00301000ULL); 507 } 508 /* 11/DHC : */ 509 sysbus_mmio_map(s, 8, addr + 0x00240000ULL); 510 /* 12/ALT : */ 511 sysbus_mmio_map(s, 9, addr + 0x00280000ULL); 512 /* 0/DFB8 : 8-bit plane */ 513 sysbus_mmio_map(s, 10, addr + 0x00800000ULL); 514 /* 1/DFB24 : 24bit plane */ 515 sysbus_mmio_map(s, 11, addr + 0x02000000ULL); 516 /* 4/RDFB32: Raw framebuffer. Control plane */ 517 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); 518 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 519 if (depth == 8) { 520 sysbus_mmio_map(s, 13, addr + 0x00301000ULL); 521 } 522 523 sysbus_connect_irq(s, 0, irq); 524 } 525 526 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 527 int height, int depth) 528 { 529 DeviceState *dev; 530 SysBusDevice *s; 531 532 dev = qdev_create(NULL, "cgthree"); 533 qdev_prop_set_uint32(dev, "vram-size", vram_size); 534 qdev_prop_set_uint16(dev, "width", width); 535 qdev_prop_set_uint16(dev, "height", height); 536 qdev_prop_set_uint16(dev, "depth", depth); 537 qdev_init_nofail(dev); 538 s = SYS_BUS_DEVICE(dev); 539 540 /* FCode ROM */ 541 sysbus_mmio_map(s, 0, addr); 542 /* DAC */ 543 sysbus_mmio_map(s, 1, addr + 0x400000ULL); 544 /* 8-bit plane */ 545 sysbus_mmio_map(s, 2, addr + 0x800000ULL); 546 547 sysbus_connect_irq(s, 0, irq); 548 } 549 550 /* NCR89C100/MACIO Internal ID register */ 551 552 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 553 554 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 555 556 static void idreg_init(hwaddr addr) 557 { 558 DeviceState *dev; 559 SysBusDevice *s; 560 561 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER); 562 qdev_init_nofail(dev); 563 s = SYS_BUS_DEVICE(dev); 564 565 sysbus_mmio_map(s, 0, addr); 566 cpu_physical_memory_write_rom(&address_space_memory, 567 addr, idreg_data, sizeof(idreg_data)); 568 } 569 570 #define MACIO_ID_REGISTER(obj) \ 571 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER) 572 573 typedef struct IDRegState { 574 SysBusDevice parent_obj; 575 576 MemoryRegion mem; 577 } IDRegState; 578 579 static void idreg_init1(Object *obj) 580 { 581 IDRegState *s = MACIO_ID_REGISTER(obj); 582 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 583 584 memory_region_init_ram_nomigrate(&s->mem, obj, 585 "sun4m.idreg", sizeof(idreg_data), &error_fatal); 586 vmstate_register_ram_global(&s->mem); 587 memory_region_set_readonly(&s->mem, true); 588 sysbus_init_mmio(dev, &s->mem); 589 } 590 591 static const TypeInfo idreg_info = { 592 .name = TYPE_MACIO_ID_REGISTER, 593 .parent = TYPE_SYS_BUS_DEVICE, 594 .instance_size = sizeof(IDRegState), 595 .instance_init = idreg_init1, 596 }; 597 598 #define TYPE_TCX_AFX "tcx_afx" 599 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX) 600 601 typedef struct AFXState { 602 SysBusDevice parent_obj; 603 604 MemoryRegion mem; 605 } AFXState; 606 607 /* SS-5 TCX AFX register */ 608 static void afx_init(hwaddr addr) 609 { 610 DeviceState *dev; 611 SysBusDevice *s; 612 613 dev = qdev_create(NULL, TYPE_TCX_AFX); 614 qdev_init_nofail(dev); 615 s = SYS_BUS_DEVICE(dev); 616 617 sysbus_mmio_map(s, 0, addr); 618 } 619 620 static void afx_init1(Object *obj) 621 { 622 AFXState *s = TCX_AFX(obj); 623 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 624 625 memory_region_init_ram_nomigrate(&s->mem, obj, "sun4m.afx", 4, &error_fatal); 626 vmstate_register_ram_global(&s->mem); 627 sysbus_init_mmio(dev, &s->mem); 628 } 629 630 static const TypeInfo afx_info = { 631 .name = TYPE_TCX_AFX, 632 .parent = TYPE_SYS_BUS_DEVICE, 633 .instance_size = sizeof(AFXState), 634 .instance_init = afx_init1, 635 }; 636 637 #define TYPE_OPENPROM "openprom" 638 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 639 640 typedef struct PROMState { 641 SysBusDevice parent_obj; 642 643 MemoryRegion prom; 644 } PROMState; 645 646 /* Boot PROM (OpenBIOS) */ 647 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 648 { 649 hwaddr *base_addr = (hwaddr *)opaque; 650 return addr + *base_addr - PROM_VADDR; 651 } 652 653 static void prom_init(hwaddr addr, const char *bios_name) 654 { 655 DeviceState *dev; 656 SysBusDevice *s; 657 char *filename; 658 int ret; 659 660 dev = qdev_create(NULL, TYPE_OPENPROM); 661 qdev_init_nofail(dev); 662 s = SYS_BUS_DEVICE(dev); 663 664 sysbus_mmio_map(s, 0, addr); 665 666 /* load boot prom */ 667 if (bios_name == NULL) { 668 bios_name = PROM_FILENAME; 669 } 670 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 671 if (filename) { 672 ret = load_elf(filename, translate_prom_address, &addr, NULL, 673 NULL, NULL, 1, EM_SPARC, 0, 0); 674 if (ret < 0 || ret > PROM_SIZE_MAX) { 675 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 676 } 677 g_free(filename); 678 } else { 679 ret = -1; 680 } 681 if (ret < 0 || ret > PROM_SIZE_MAX) { 682 error_report("could not load prom '%s'", bios_name); 683 exit(1); 684 } 685 } 686 687 static void prom_init1(Object *obj) 688 { 689 PROMState *s = OPENPROM(obj); 690 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 691 692 memory_region_init_ram_nomigrate(&s->prom, obj, "sun4m.prom", PROM_SIZE_MAX, 693 &error_fatal); 694 vmstate_register_ram_global(&s->prom); 695 memory_region_set_readonly(&s->prom, true); 696 sysbus_init_mmio(dev, &s->prom); 697 } 698 699 static Property prom_properties[] = { 700 {/* end of property list */}, 701 }; 702 703 static void prom_class_init(ObjectClass *klass, void *data) 704 { 705 DeviceClass *dc = DEVICE_CLASS(klass); 706 707 dc->props = prom_properties; 708 } 709 710 static const TypeInfo prom_info = { 711 .name = TYPE_OPENPROM, 712 .parent = TYPE_SYS_BUS_DEVICE, 713 .instance_size = sizeof(PROMState), 714 .class_init = prom_class_init, 715 .instance_init = prom_init1, 716 }; 717 718 #define TYPE_SUN4M_MEMORY "memory" 719 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY) 720 721 typedef struct RamDevice { 722 SysBusDevice parent_obj; 723 724 MemoryRegion ram; 725 uint64_t size; 726 } RamDevice; 727 728 /* System RAM */ 729 static void ram_realize(DeviceState *dev, Error **errp) 730 { 731 RamDevice *d = SUN4M_RAM(dev); 732 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 733 734 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram", 735 d->size); 736 sysbus_init_mmio(sbd, &d->ram); 737 } 738 739 static void ram_init(hwaddr addr, ram_addr_t RAM_size, 740 uint64_t max_mem) 741 { 742 DeviceState *dev; 743 SysBusDevice *s; 744 RamDevice *d; 745 746 /* allocate RAM */ 747 if ((uint64_t)RAM_size > max_mem) { 748 error_report("Too much memory for this machine: %d, maximum %d", 749 (unsigned int)(RAM_size / (1024 * 1024)), 750 (unsigned int)(max_mem / (1024 * 1024))); 751 exit(1); 752 } 753 dev = qdev_create(NULL, "memory"); 754 s = SYS_BUS_DEVICE(dev); 755 756 d = SUN4M_RAM(dev); 757 d->size = RAM_size; 758 qdev_init_nofail(dev); 759 760 sysbus_mmio_map(s, 0, addr); 761 } 762 763 static Property ram_properties[] = { 764 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 765 DEFINE_PROP_END_OF_LIST(), 766 }; 767 768 static void ram_class_init(ObjectClass *klass, void *data) 769 { 770 DeviceClass *dc = DEVICE_CLASS(klass); 771 772 dc->realize = ram_realize; 773 dc->props = ram_properties; 774 } 775 776 static const TypeInfo ram_info = { 777 .name = TYPE_SUN4M_MEMORY, 778 .parent = TYPE_SYS_BUS_DEVICE, 779 .instance_size = sizeof(RamDevice), 780 .class_init = ram_class_init, 781 }; 782 783 static void cpu_devinit(const char *cpu_type, unsigned int id, 784 uint64_t prom_addr, qemu_irq **cpu_irqs) 785 { 786 CPUState *cs; 787 SPARCCPU *cpu; 788 CPUSPARCState *env; 789 790 cpu = SPARC_CPU(cpu_create(cpu_type)); 791 env = &cpu->env; 792 793 cpu_sparc_set_id(env, id); 794 if (id == 0) { 795 qemu_register_reset(main_cpu_reset, cpu); 796 } else { 797 qemu_register_reset(secondary_cpu_reset, cpu); 798 cs = CPU(cpu); 799 cs->halted = 1; 800 } 801 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 802 env->prom_addr = prom_addr; 803 } 804 805 static void dummy_fdc_tc(void *opaque, int irq, int level) 806 { 807 } 808 809 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, 810 MachineState *machine) 811 { 812 DeviceState *slavio_intctl; 813 unsigned int i; 814 void *nvram; 815 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; 816 qemu_irq fdc_tc; 817 unsigned long kernel_size; 818 DriveInfo *fd[MAX_FD]; 819 FWCfgState *fw_cfg; 820 unsigned int num_vsimms; 821 DeviceState *dev; 822 SysBusDevice *s; 823 824 /* init CPUs */ 825 for(i = 0; i < smp_cpus; i++) { 826 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); 827 } 828 829 for (i = smp_cpus; i < MAX_CPUS; i++) 830 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 831 832 833 /* set up devices */ 834 ram_init(0, machine->ram_size, hwdef->max_mem); 835 /* models without ECC don't trap when missing ram is accessed */ 836 if (!hwdef->ecc_base) { 837 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size); 838 } 839 840 prom_init(hwdef->slavio_base, bios_name); 841 842 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 843 hwdef->intctl_base + 0x10000ULL, 844 cpu_irqs); 845 846 for (i = 0; i < 32; i++) { 847 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 848 } 849 for (i = 0; i < MAX_CPUS; i++) { 850 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 851 } 852 853 if (hwdef->idreg_base) { 854 idreg_init(hwdef->idreg_base); 855 } 856 857 if (hwdef->afx_base) { 858 afx_init(hwdef->afx_base); 859 } 860 861 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]); 862 863 if (hwdef->iommu_pad_base) { 864 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 865 Software shouldn't use aliased addresses, neither should it crash 866 when does. Using empty_slot instead of aliasing can help with 867 debugging such accesses */ 868 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); 869 } 870 871 sparc32_dma_init(hwdef->dma_base, 872 hwdef->esp_base, slavio_irq[18], 873 hwdef->le_base, slavio_irq[16]); 874 875 if (graphic_depth != 8 && graphic_depth != 24) { 876 error_report("Unsupported depth: %d", graphic_depth); 877 exit (1); 878 } 879 num_vsimms = 0; 880 if (num_vsimms == 0) { 881 if (vga_interface_type == VGA_CG3) { 882 if (graphic_depth != 8) { 883 error_report("Unsupported depth: %d", graphic_depth); 884 exit(1); 885 } 886 887 if (!(graphic_width == 1024 && graphic_height == 768) && 888 !(graphic_width == 1152 && graphic_height == 900)) { 889 error_report("Unsupported resolution: %d x %d", graphic_width, 890 graphic_height); 891 exit(1); 892 } 893 894 /* sbus irq 5 */ 895 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 896 graphic_width, graphic_height, graphic_depth); 897 } else { 898 /* If no display specified, default to TCX */ 899 if (graphic_depth != 8 && graphic_depth != 24) { 900 error_report("Unsupported depth: %d", graphic_depth); 901 exit(1); 902 } 903 904 if (!(graphic_width == 1024 && graphic_height == 768)) { 905 error_report("Unsupported resolution: %d x %d", 906 graphic_width, graphic_height); 907 exit(1); 908 } 909 910 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 911 graphic_width, graphic_height, graphic_depth); 912 } 913 } 914 915 for (i = num_vsimms; i < MAX_VSIMMS; i++) { 916 /* vsimm registers probed by OBP */ 917 if (hwdef->vsimm[i].reg_base) { 918 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); 919 } 920 } 921 922 if (hwdef->sx_base) { 923 empty_slot_init(hwdef->sx_base, 0x2000); 924 } 925 926 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8); 927 928 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 929 930 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 931 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 932 dev = qdev_create(NULL, TYPE_ESCC); 933 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics); 934 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 935 qdev_prop_set_uint32(dev, "it_shift", 1); 936 qdev_prop_set_chr(dev, "chrB", NULL); 937 qdev_prop_set_chr(dev, "chrA", NULL); 938 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse); 939 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd); 940 qdev_init_nofail(dev); 941 s = SYS_BUS_DEVICE(dev); 942 sysbus_connect_irq(s, 0, slavio_irq[14]); 943 sysbus_connect_irq(s, 1, slavio_irq[14]); 944 sysbus_mmio_map(s, 0, hwdef->ms_kb_base); 945 946 dev = qdev_create(NULL, TYPE_ESCC); 947 qdev_prop_set_uint32(dev, "disabled", 0); 948 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 949 qdev_prop_set_uint32(dev, "it_shift", 1); 950 qdev_prop_set_chr(dev, "chrB", serial_hds[1]); 951 qdev_prop_set_chr(dev, "chrA", serial_hds[0]); 952 qdev_prop_set_uint32(dev, "chnBtype", escc_serial); 953 qdev_prop_set_uint32(dev, "chnAtype", escc_serial); 954 qdev_init_nofail(dev); 955 956 s = SYS_BUS_DEVICE(dev); 957 sysbus_connect_irq(s, 0, slavio_irq[15]); 958 sysbus_connect_irq(s, 1, slavio_irq[15]); 959 sysbus_mmio_map(s, 0, hwdef->serial_base); 960 961 if (hwdef->apc_base) { 962 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); 963 } 964 965 if (hwdef->fd_base) { 966 /* there is zero or one floppy drive */ 967 memset(fd, 0, sizeof(fd)); 968 fd[0] = drive_get(IF_FLOPPY, 0, 0); 969 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 970 &fdc_tc); 971 } else { 972 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); 973 } 974 975 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 976 slavio_irq[30], fdc_tc); 977 978 if (hwdef->cs_base) { 979 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, 980 slavio_irq[5]); 981 } 982 983 if (hwdef->dbri_base) { 984 /* ISDN chip with attached CS4215 audio codec */ 985 /* prom space */ 986 empty_slot_init(hwdef->dbri_base+0x1000, 0x30); 987 /* reg space */ 988 empty_slot_init(hwdef->dbri_base+0x10000, 0x100); 989 } 990 991 if (hwdef->bpp_base) { 992 /* parallel port */ 993 empty_slot_init(hwdef->bpp_base, 0x20); 994 } 995 996 kernel_size = sun4m_load_kernel(machine->kernel_filename, 997 machine->initrd_filename, 998 machine->ram_size); 999 1000 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline, 1001 machine->boot_order, machine->ram_size, kernel_size, 1002 graphic_width, graphic_height, graphic_depth, 1003 hwdef->nvram_machine_id, "Sun4m"); 1004 1005 if (hwdef->ecc_base) 1006 ecc_init(hwdef->ecc_base, slavio_irq[28], 1007 hwdef->ecc_version); 1008 1009 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 1010 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 1011 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1012 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1013 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1014 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1015 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1016 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1017 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1018 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1019 if (machine->kernel_cmdline) { 1020 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1021 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1022 machine->kernel_cmdline); 1023 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 1024 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1025 strlen(machine->kernel_cmdline) + 1); 1026 } else { 1027 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1028 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1029 } 1030 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1031 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used 1032 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 1033 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1034 } 1035 1036 enum { 1037 ss5_id = 32, 1038 vger_id, 1039 lx_id, 1040 ss4_id, 1041 scls_id, 1042 sbook_id, 1043 ss10_id = 64, 1044 ss20_id, 1045 ss600mp_id, 1046 }; 1047 1048 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1049 /* SS-5 */ 1050 { 1051 .iommu_base = 0x10000000, 1052 .iommu_pad_base = 0x10004000, 1053 .iommu_pad_len = 0x0fffb000, 1054 .tcx_base = 0x50000000, 1055 .cs_base = 0x6c000000, 1056 .slavio_base = 0x70000000, 1057 .ms_kb_base = 0x71000000, 1058 .serial_base = 0x71100000, 1059 .nvram_base = 0x71200000, 1060 .fd_base = 0x71400000, 1061 .counter_base = 0x71d00000, 1062 .intctl_base = 0x71e00000, 1063 .idreg_base = 0x78000000, 1064 .dma_base = 0x78400000, 1065 .esp_base = 0x78800000, 1066 .le_base = 0x78c00000, 1067 .apc_base = 0x6a000000, 1068 .afx_base = 0x6e000000, 1069 .aux1_base = 0x71900000, 1070 .aux2_base = 0x71910000, 1071 .nvram_machine_id = 0x80, 1072 .machine_id = ss5_id, 1073 .iommu_version = 0x05000000, 1074 .max_mem = 0x10000000, 1075 }, 1076 /* SS-10 */ 1077 { 1078 .iommu_base = 0xfe0000000ULL, 1079 .tcx_base = 0xe20000000ULL, 1080 .slavio_base = 0xff0000000ULL, 1081 .ms_kb_base = 0xff1000000ULL, 1082 .serial_base = 0xff1100000ULL, 1083 .nvram_base = 0xff1200000ULL, 1084 .fd_base = 0xff1700000ULL, 1085 .counter_base = 0xff1300000ULL, 1086 .intctl_base = 0xff1400000ULL, 1087 .idreg_base = 0xef0000000ULL, 1088 .dma_base = 0xef0400000ULL, 1089 .esp_base = 0xef0800000ULL, 1090 .le_base = 0xef0c00000ULL, 1091 .apc_base = 0xefa000000ULL, // XXX should not exist 1092 .aux1_base = 0xff1800000ULL, 1093 .aux2_base = 0xff1a01000ULL, 1094 .ecc_base = 0xf00000000ULL, 1095 .ecc_version = 0x10000000, // version 0, implementation 1 1096 .nvram_machine_id = 0x72, 1097 .machine_id = ss10_id, 1098 .iommu_version = 0x03000000, 1099 .max_mem = 0xf00000000ULL, 1100 }, 1101 /* SS-600MP */ 1102 { 1103 .iommu_base = 0xfe0000000ULL, 1104 .tcx_base = 0xe20000000ULL, 1105 .slavio_base = 0xff0000000ULL, 1106 .ms_kb_base = 0xff1000000ULL, 1107 .serial_base = 0xff1100000ULL, 1108 .nvram_base = 0xff1200000ULL, 1109 .counter_base = 0xff1300000ULL, 1110 .intctl_base = 0xff1400000ULL, 1111 .dma_base = 0xef0081000ULL, 1112 .esp_base = 0xef0080000ULL, 1113 .le_base = 0xef0060000ULL, 1114 .apc_base = 0xefa000000ULL, // XXX should not exist 1115 .aux1_base = 0xff1800000ULL, 1116 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1117 .ecc_base = 0xf00000000ULL, 1118 .ecc_version = 0x00000000, // version 0, implementation 0 1119 .nvram_machine_id = 0x71, 1120 .machine_id = ss600mp_id, 1121 .iommu_version = 0x01000000, 1122 .max_mem = 0xf00000000ULL, 1123 }, 1124 /* SS-20 */ 1125 { 1126 .iommu_base = 0xfe0000000ULL, 1127 .tcx_base = 0xe20000000ULL, 1128 .slavio_base = 0xff0000000ULL, 1129 .ms_kb_base = 0xff1000000ULL, 1130 .serial_base = 0xff1100000ULL, 1131 .nvram_base = 0xff1200000ULL, 1132 .fd_base = 0xff1700000ULL, 1133 .counter_base = 0xff1300000ULL, 1134 .intctl_base = 0xff1400000ULL, 1135 .idreg_base = 0xef0000000ULL, 1136 .dma_base = 0xef0400000ULL, 1137 .esp_base = 0xef0800000ULL, 1138 .le_base = 0xef0c00000ULL, 1139 .bpp_base = 0xef4800000ULL, 1140 .apc_base = 0xefa000000ULL, // XXX should not exist 1141 .aux1_base = 0xff1800000ULL, 1142 .aux2_base = 0xff1a01000ULL, 1143 .dbri_base = 0xee0000000ULL, 1144 .sx_base = 0xf80000000ULL, 1145 .vsimm = { 1146 { 1147 .reg_base = 0x9c000000ULL, 1148 .vram_base = 0xfc000000ULL 1149 }, { 1150 .reg_base = 0x90000000ULL, 1151 .vram_base = 0xf0000000ULL 1152 }, { 1153 .reg_base = 0x94000000ULL 1154 }, { 1155 .reg_base = 0x98000000ULL 1156 } 1157 }, 1158 .ecc_base = 0xf00000000ULL, 1159 .ecc_version = 0x20000000, // version 0, implementation 2 1160 .nvram_machine_id = 0x72, 1161 .machine_id = ss20_id, 1162 .iommu_version = 0x13000000, 1163 .max_mem = 0xf00000000ULL, 1164 }, 1165 /* Voyager */ 1166 { 1167 .iommu_base = 0x10000000, 1168 .tcx_base = 0x50000000, 1169 .slavio_base = 0x70000000, 1170 .ms_kb_base = 0x71000000, 1171 .serial_base = 0x71100000, 1172 .nvram_base = 0x71200000, 1173 .fd_base = 0x71400000, 1174 .counter_base = 0x71d00000, 1175 .intctl_base = 0x71e00000, 1176 .idreg_base = 0x78000000, 1177 .dma_base = 0x78400000, 1178 .esp_base = 0x78800000, 1179 .le_base = 0x78c00000, 1180 .apc_base = 0x71300000, // pmc 1181 .aux1_base = 0x71900000, 1182 .aux2_base = 0x71910000, 1183 .nvram_machine_id = 0x80, 1184 .machine_id = vger_id, 1185 .iommu_version = 0x05000000, 1186 .max_mem = 0x10000000, 1187 }, 1188 /* LX */ 1189 { 1190 .iommu_base = 0x10000000, 1191 .iommu_pad_base = 0x10004000, 1192 .iommu_pad_len = 0x0fffb000, 1193 .tcx_base = 0x50000000, 1194 .slavio_base = 0x70000000, 1195 .ms_kb_base = 0x71000000, 1196 .serial_base = 0x71100000, 1197 .nvram_base = 0x71200000, 1198 .fd_base = 0x71400000, 1199 .counter_base = 0x71d00000, 1200 .intctl_base = 0x71e00000, 1201 .idreg_base = 0x78000000, 1202 .dma_base = 0x78400000, 1203 .esp_base = 0x78800000, 1204 .le_base = 0x78c00000, 1205 .aux1_base = 0x71900000, 1206 .aux2_base = 0x71910000, 1207 .nvram_machine_id = 0x80, 1208 .machine_id = lx_id, 1209 .iommu_version = 0x04000000, 1210 .max_mem = 0x10000000, 1211 }, 1212 /* SS-4 */ 1213 { 1214 .iommu_base = 0x10000000, 1215 .tcx_base = 0x50000000, 1216 .cs_base = 0x6c000000, 1217 .slavio_base = 0x70000000, 1218 .ms_kb_base = 0x71000000, 1219 .serial_base = 0x71100000, 1220 .nvram_base = 0x71200000, 1221 .fd_base = 0x71400000, 1222 .counter_base = 0x71d00000, 1223 .intctl_base = 0x71e00000, 1224 .idreg_base = 0x78000000, 1225 .dma_base = 0x78400000, 1226 .esp_base = 0x78800000, 1227 .le_base = 0x78c00000, 1228 .apc_base = 0x6a000000, 1229 .aux1_base = 0x71900000, 1230 .aux2_base = 0x71910000, 1231 .nvram_machine_id = 0x80, 1232 .machine_id = ss4_id, 1233 .iommu_version = 0x05000000, 1234 .max_mem = 0x10000000, 1235 }, 1236 /* SPARCClassic */ 1237 { 1238 .iommu_base = 0x10000000, 1239 .tcx_base = 0x50000000, 1240 .slavio_base = 0x70000000, 1241 .ms_kb_base = 0x71000000, 1242 .serial_base = 0x71100000, 1243 .nvram_base = 0x71200000, 1244 .fd_base = 0x71400000, 1245 .counter_base = 0x71d00000, 1246 .intctl_base = 0x71e00000, 1247 .idreg_base = 0x78000000, 1248 .dma_base = 0x78400000, 1249 .esp_base = 0x78800000, 1250 .le_base = 0x78c00000, 1251 .apc_base = 0x6a000000, 1252 .aux1_base = 0x71900000, 1253 .aux2_base = 0x71910000, 1254 .nvram_machine_id = 0x80, 1255 .machine_id = scls_id, 1256 .iommu_version = 0x05000000, 1257 .max_mem = 0x10000000, 1258 }, 1259 /* SPARCbook */ 1260 { 1261 .iommu_base = 0x10000000, 1262 .tcx_base = 0x50000000, // XXX 1263 .slavio_base = 0x70000000, 1264 .ms_kb_base = 0x71000000, 1265 .serial_base = 0x71100000, 1266 .nvram_base = 0x71200000, 1267 .fd_base = 0x71400000, 1268 .counter_base = 0x71d00000, 1269 .intctl_base = 0x71e00000, 1270 .idreg_base = 0x78000000, 1271 .dma_base = 0x78400000, 1272 .esp_base = 0x78800000, 1273 .le_base = 0x78c00000, 1274 .apc_base = 0x6a000000, 1275 .aux1_base = 0x71900000, 1276 .aux2_base = 0x71910000, 1277 .nvram_machine_id = 0x80, 1278 .machine_id = sbook_id, 1279 .iommu_version = 0x05000000, 1280 .max_mem = 0x10000000, 1281 }, 1282 }; 1283 1284 /* SPARCstation 5 hardware initialisation */ 1285 static void ss5_init(MachineState *machine) 1286 { 1287 sun4m_hw_init(&sun4m_hwdefs[0], machine); 1288 } 1289 1290 /* SPARCstation 10 hardware initialisation */ 1291 static void ss10_init(MachineState *machine) 1292 { 1293 sun4m_hw_init(&sun4m_hwdefs[1], machine); 1294 } 1295 1296 /* SPARCserver 600MP hardware initialisation */ 1297 static void ss600mp_init(MachineState *machine) 1298 { 1299 sun4m_hw_init(&sun4m_hwdefs[2], machine); 1300 } 1301 1302 /* SPARCstation 20 hardware initialisation */ 1303 static void ss20_init(MachineState *machine) 1304 { 1305 sun4m_hw_init(&sun4m_hwdefs[3], machine); 1306 } 1307 1308 /* SPARCstation Voyager hardware initialisation */ 1309 static void vger_init(MachineState *machine) 1310 { 1311 sun4m_hw_init(&sun4m_hwdefs[4], machine); 1312 } 1313 1314 /* SPARCstation LX hardware initialisation */ 1315 static void ss_lx_init(MachineState *machine) 1316 { 1317 sun4m_hw_init(&sun4m_hwdefs[5], machine); 1318 } 1319 1320 /* SPARCstation 4 hardware initialisation */ 1321 static void ss4_init(MachineState *machine) 1322 { 1323 sun4m_hw_init(&sun4m_hwdefs[6], machine); 1324 } 1325 1326 /* SPARCClassic hardware initialisation */ 1327 static void scls_init(MachineState *machine) 1328 { 1329 sun4m_hw_init(&sun4m_hwdefs[7], machine); 1330 } 1331 1332 /* SPARCbook hardware initialisation */ 1333 static void sbook_init(MachineState *machine) 1334 { 1335 sun4m_hw_init(&sun4m_hwdefs[8], machine); 1336 } 1337 1338 static void ss5_class_init(ObjectClass *oc, void *data) 1339 { 1340 MachineClass *mc = MACHINE_CLASS(oc); 1341 1342 mc->desc = "Sun4m platform, SPARCstation 5"; 1343 mc->init = ss5_init; 1344 mc->block_default_type = IF_SCSI; 1345 mc->is_default = 1; 1346 mc->default_boot_order = "c"; 1347 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1348 } 1349 1350 static const TypeInfo ss5_type = { 1351 .name = MACHINE_TYPE_NAME("SS-5"), 1352 .parent = TYPE_MACHINE, 1353 .class_init = ss5_class_init, 1354 }; 1355 1356 static void ss10_class_init(ObjectClass *oc, void *data) 1357 { 1358 MachineClass *mc = MACHINE_CLASS(oc); 1359 1360 mc->desc = "Sun4m platform, SPARCstation 10"; 1361 mc->init = ss10_init; 1362 mc->block_default_type = IF_SCSI; 1363 mc->max_cpus = 4; 1364 mc->default_boot_order = "c"; 1365 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1366 } 1367 1368 static const TypeInfo ss10_type = { 1369 .name = MACHINE_TYPE_NAME("SS-10"), 1370 .parent = TYPE_MACHINE, 1371 .class_init = ss10_class_init, 1372 }; 1373 1374 static void ss600mp_class_init(ObjectClass *oc, void *data) 1375 { 1376 MachineClass *mc = MACHINE_CLASS(oc); 1377 1378 mc->desc = "Sun4m platform, SPARCserver 600MP"; 1379 mc->init = ss600mp_init; 1380 mc->block_default_type = IF_SCSI; 1381 mc->max_cpus = 4; 1382 mc->default_boot_order = "c"; 1383 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1384 } 1385 1386 static const TypeInfo ss600mp_type = { 1387 .name = MACHINE_TYPE_NAME("SS-600MP"), 1388 .parent = TYPE_MACHINE, 1389 .class_init = ss600mp_class_init, 1390 }; 1391 1392 static void ss20_class_init(ObjectClass *oc, void *data) 1393 { 1394 MachineClass *mc = MACHINE_CLASS(oc); 1395 1396 mc->desc = "Sun4m platform, SPARCstation 20"; 1397 mc->init = ss20_init; 1398 mc->block_default_type = IF_SCSI; 1399 mc->max_cpus = 4; 1400 mc->default_boot_order = "c"; 1401 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1402 } 1403 1404 static const TypeInfo ss20_type = { 1405 .name = MACHINE_TYPE_NAME("SS-20"), 1406 .parent = TYPE_MACHINE, 1407 .class_init = ss20_class_init, 1408 }; 1409 1410 static void voyager_class_init(ObjectClass *oc, void *data) 1411 { 1412 MachineClass *mc = MACHINE_CLASS(oc); 1413 1414 mc->desc = "Sun4m platform, SPARCstation Voyager"; 1415 mc->init = vger_init; 1416 mc->block_default_type = IF_SCSI; 1417 mc->default_boot_order = "c"; 1418 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1419 } 1420 1421 static const TypeInfo voyager_type = { 1422 .name = MACHINE_TYPE_NAME("Voyager"), 1423 .parent = TYPE_MACHINE, 1424 .class_init = voyager_class_init, 1425 }; 1426 1427 static void ss_lx_class_init(ObjectClass *oc, void *data) 1428 { 1429 MachineClass *mc = MACHINE_CLASS(oc); 1430 1431 mc->desc = "Sun4m platform, SPARCstation LX"; 1432 mc->init = ss_lx_init; 1433 mc->block_default_type = IF_SCSI; 1434 mc->default_boot_order = "c"; 1435 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1436 } 1437 1438 static const TypeInfo ss_lx_type = { 1439 .name = MACHINE_TYPE_NAME("LX"), 1440 .parent = TYPE_MACHINE, 1441 .class_init = ss_lx_class_init, 1442 }; 1443 1444 static void ss4_class_init(ObjectClass *oc, void *data) 1445 { 1446 MachineClass *mc = MACHINE_CLASS(oc); 1447 1448 mc->desc = "Sun4m platform, SPARCstation 4"; 1449 mc->init = ss4_init; 1450 mc->block_default_type = IF_SCSI; 1451 mc->default_boot_order = "c"; 1452 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1453 } 1454 1455 static const TypeInfo ss4_type = { 1456 .name = MACHINE_TYPE_NAME("SS-4"), 1457 .parent = TYPE_MACHINE, 1458 .class_init = ss4_class_init, 1459 }; 1460 1461 static void scls_class_init(ObjectClass *oc, void *data) 1462 { 1463 MachineClass *mc = MACHINE_CLASS(oc); 1464 1465 mc->desc = "Sun4m platform, SPARCClassic"; 1466 mc->init = scls_init; 1467 mc->block_default_type = IF_SCSI; 1468 mc->default_boot_order = "c"; 1469 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1470 } 1471 1472 static const TypeInfo scls_type = { 1473 .name = MACHINE_TYPE_NAME("SPARCClassic"), 1474 .parent = TYPE_MACHINE, 1475 .class_init = scls_class_init, 1476 }; 1477 1478 static void sbook_class_init(ObjectClass *oc, void *data) 1479 { 1480 MachineClass *mc = MACHINE_CLASS(oc); 1481 1482 mc->desc = "Sun4m platform, SPARCbook"; 1483 mc->init = sbook_init; 1484 mc->block_default_type = IF_SCSI; 1485 mc->default_boot_order = "c"; 1486 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1487 } 1488 1489 static const TypeInfo sbook_type = { 1490 .name = MACHINE_TYPE_NAME("SPARCbook"), 1491 .parent = TYPE_MACHINE, 1492 .class_init = sbook_class_init, 1493 }; 1494 1495 static void sun4m_register_types(void) 1496 { 1497 type_register_static(&idreg_info); 1498 type_register_static(&afx_info); 1499 type_register_static(&prom_info); 1500 type_register_static(&ram_info); 1501 1502 type_register_static(&ss5_type); 1503 type_register_static(&ss10_type); 1504 type_register_static(&ss600mp_type); 1505 type_register_static(&ss20_type); 1506 type_register_static(&voyager_type); 1507 type_register_static(&ss_lx_type); 1508 type_register_static(&ss4_type); 1509 type_register_static(&scls_type); 1510 type_register_static(&sbook_type); 1511 } 1512 1513 type_init(sun4m_register_types) 1514