1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/sysbus.h" 25 #include "qemu/timer.h" 26 #include "hw/sun4m.h" 27 #include "hw/nvram.h" 28 #include "hw/sparc32_dma.h" 29 #include "hw/fdc.h" 30 #include "sysemu/sysemu.h" 31 #include "net/net.h" 32 #include "hw/boards.h" 33 #include "hw/firmware_abi.h" 34 #include "hw/esp.h" 35 #include "hw/pc.h" 36 #include "hw/isa.h" 37 #include "hw/fw_cfg.h" 38 #include "hw/escc.h" 39 #include "hw/empty_slot.h" 40 #include "hw/qdev-addr.h" 41 #include "hw/loader.h" 42 #include "elf.h" 43 #include "sysemu/blockdev.h" 44 #include "trace.h" 45 46 /* 47 * Sun4m architecture was used in the following machines: 48 * 49 * SPARCserver 6xxMP/xx 50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 51 * SPARCclassic X (4/10) 52 * SPARCstation LX/ZX (4/30) 53 * SPARCstation Voyager 54 * SPARCstation 10/xx, SPARCserver 10/xx 55 * SPARCstation 5, SPARCserver 5 56 * SPARCstation 20/xx, SPARCserver 20 57 * SPARCstation 4 58 * 59 * Sun4d architecture was used in the following machines: 60 * 61 * SPARCcenter 2000 62 * SPARCserver 1000 63 * 64 * Sun4c architecture was used in the following machines: 65 * SPARCstation 1/1+, SPARCserver 1/1+ 66 * SPARCstation SLC 67 * SPARCstation IPC 68 * SPARCstation ELC 69 * SPARCstation IPX 70 * 71 * See for example: http://www.sunhelp.org/faq/sunref1.html 72 */ 73 74 #define KERNEL_LOAD_ADDR 0x00004000 75 #define CMDLINE_ADDR 0x007ff000 76 #define INITRD_LOAD_ADDR 0x00800000 77 #define PROM_SIZE_MAX (1024 * 1024) 78 #define PROM_VADDR 0xffd00000 79 #define PROM_FILENAME "openbios-sparc32" 80 #define CFG_ADDR 0xd00000510ULL 81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 82 83 #define MAX_CPUS 16 84 #define MAX_PILS 16 85 #define MAX_VSIMMS 4 86 87 #define ESCC_CLOCK 4915200 88 89 struct sun4m_hwdef { 90 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 91 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 92 hwaddr serial_base, fd_base; 93 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 94 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 95 hwaddr bpp_base, dbri_base, sx_base; 96 struct { 97 hwaddr reg_base, vram_base; 98 } vsimm[MAX_VSIMMS]; 99 hwaddr ecc_base; 100 uint64_t max_mem; 101 const char * const default_cpu_model; 102 uint32_t ecc_version; 103 uint32_t iommu_version; 104 uint16_t machine_id; 105 uint8_t nvram_machine_id; 106 }; 107 108 #define MAX_IOUNITS 5 109 110 struct sun4d_hwdef { 111 hwaddr iounit_bases[MAX_IOUNITS], slavio_base; 112 hwaddr counter_base, nvram_base, ms_kb_base; 113 hwaddr serial_base; 114 hwaddr espdma_base, esp_base; 115 hwaddr ledma_base, le_base; 116 hwaddr tcx_base; 117 hwaddr sbi_base; 118 uint64_t max_mem; 119 const char * const default_cpu_model; 120 uint32_t iounit_version; 121 uint16_t machine_id; 122 uint8_t nvram_machine_id; 123 }; 124 125 struct sun4c_hwdef { 126 hwaddr iommu_base, slavio_base; 127 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 128 hwaddr serial_base, fd_base; 129 hwaddr idreg_base, dma_base, esp_base, le_base; 130 hwaddr tcx_base, aux1_base; 131 uint64_t max_mem; 132 const char * const default_cpu_model; 133 uint32_t iommu_version; 134 uint16_t machine_id; 135 uint8_t nvram_machine_id; 136 }; 137 138 int DMA_get_channel_mode (int nchan) 139 { 140 return 0; 141 } 142 int DMA_read_memory (int nchan, void *buf, int pos, int size) 143 { 144 return 0; 145 } 146 int DMA_write_memory (int nchan, void *buf, int pos, int size) 147 { 148 return 0; 149 } 150 void DMA_hold_DREQ (int nchan) {} 151 void DMA_release_DREQ (int nchan) {} 152 void DMA_schedule(int nchan) {} 153 154 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) 155 { 156 } 157 158 void DMA_register_channel (int nchan, 159 DMA_transfer_handler transfer_handler, 160 void *opaque) 161 { 162 } 163 164 static int fw_cfg_boot_set(void *opaque, const char *boot_device) 165 { 166 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 167 return 0; 168 } 169 170 static void nvram_init(M48t59State *nvram, uint8_t *macaddr, 171 const char *cmdline, const char *boot_devices, 172 ram_addr_t RAM_size, uint32_t kernel_size, 173 int width, int height, int depth, 174 int nvram_machine_id, const char *arch) 175 { 176 unsigned int i; 177 uint32_t start, end; 178 uint8_t image[0x1ff0]; 179 struct OpenBIOS_nvpart_v1 *part_header; 180 181 memset(image, '\0', sizeof(image)); 182 183 start = 0; 184 185 // OpenBIOS nvram variables 186 // Variable partition 187 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 188 part_header->signature = OPENBIOS_PART_SYSTEM; 189 pstrcpy(part_header->name, sizeof(part_header->name), "system"); 190 191 end = start + sizeof(struct OpenBIOS_nvpart_v1); 192 for (i = 0; i < nb_prom_envs; i++) 193 end = OpenBIOS_set_var(image, end, prom_envs[i]); 194 195 // End marker 196 image[end++] = '\0'; 197 198 end = start + ((end - start + 15) & ~15); 199 OpenBIOS_finish_partition(part_header, end - start); 200 201 // free partition 202 start = end; 203 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 204 part_header->signature = OPENBIOS_PART_FREE; 205 pstrcpy(part_header->name, sizeof(part_header->name), "free"); 206 207 end = 0x1fd0; 208 OpenBIOS_finish_partition(part_header, end - start); 209 210 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 211 nvram_machine_id); 212 213 for (i = 0; i < sizeof(image); i++) 214 m48t59_write(nvram, i, image[i]); 215 } 216 217 static DeviceState *slavio_intctl; 218 219 void sun4m_pic_info(Monitor *mon, const QDict *qdict) 220 { 221 if (slavio_intctl) 222 slavio_pic_info(mon, slavio_intctl); 223 } 224 225 void sun4m_irq_info(Monitor *mon, const QDict *qdict) 226 { 227 if (slavio_intctl) 228 slavio_irq_info(mon, slavio_intctl); 229 } 230 231 void cpu_check_irqs(CPUSPARCState *env) 232 { 233 if (env->pil_in && (env->interrupt_index == 0 || 234 (env->interrupt_index & ~15) == TT_EXTINT)) { 235 unsigned int i; 236 237 for (i = 15; i > 0; i--) { 238 if (env->pil_in & (1 << i)) { 239 int old_interrupt = env->interrupt_index; 240 241 env->interrupt_index = TT_EXTINT | i; 242 if (old_interrupt != env->interrupt_index) { 243 trace_sun4m_cpu_interrupt(i); 244 cpu_interrupt(env, CPU_INTERRUPT_HARD); 245 } 246 break; 247 } 248 } 249 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 250 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 251 env->interrupt_index = 0; 252 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); 253 } 254 } 255 256 static void cpu_kick_irq(SPARCCPU *cpu) 257 { 258 CPUSPARCState *env = &cpu->env; 259 260 env->halted = 0; 261 cpu_check_irqs(env); 262 qemu_cpu_kick(CPU(cpu)); 263 } 264 265 static void cpu_set_irq(void *opaque, int irq, int level) 266 { 267 SPARCCPU *cpu = opaque; 268 CPUSPARCState *env = &cpu->env; 269 270 if (level) { 271 trace_sun4m_cpu_set_irq_raise(irq); 272 env->pil_in |= 1 << irq; 273 cpu_kick_irq(cpu); 274 } else { 275 trace_sun4m_cpu_set_irq_lower(irq); 276 env->pil_in &= ~(1 << irq); 277 cpu_check_irqs(env); 278 } 279 } 280 281 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 282 { 283 } 284 285 static void main_cpu_reset(void *opaque) 286 { 287 SPARCCPU *cpu = opaque; 288 CPUSPARCState *env = &cpu->env; 289 290 cpu_reset(CPU(cpu)); 291 env->halted = 0; 292 } 293 294 static void secondary_cpu_reset(void *opaque) 295 { 296 SPARCCPU *cpu = opaque; 297 CPUSPARCState *env = &cpu->env; 298 299 cpu_reset(CPU(cpu)); 300 env->halted = 1; 301 } 302 303 static void cpu_halt_signal(void *opaque, int irq, int level) 304 { 305 if (level && cpu_single_env) 306 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); 307 } 308 309 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 310 { 311 return addr - 0xf0000000ULL; 312 } 313 314 static unsigned long sun4m_load_kernel(const char *kernel_filename, 315 const char *initrd_filename, 316 ram_addr_t RAM_size) 317 { 318 int linux_boot; 319 unsigned int i; 320 long initrd_size, kernel_size; 321 uint8_t *ptr; 322 323 linux_boot = (kernel_filename != NULL); 324 325 kernel_size = 0; 326 if (linux_boot) { 327 int bswap_needed; 328 329 #ifdef BSWAP_NEEDED 330 bswap_needed = 1; 331 #else 332 bswap_needed = 0; 333 #endif 334 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 335 NULL, NULL, NULL, 1, ELF_MACHINE, 0); 336 if (kernel_size < 0) 337 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 338 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 339 TARGET_PAGE_SIZE); 340 if (kernel_size < 0) 341 kernel_size = load_image_targphys(kernel_filename, 342 KERNEL_LOAD_ADDR, 343 RAM_size - KERNEL_LOAD_ADDR); 344 if (kernel_size < 0) { 345 fprintf(stderr, "qemu: could not load kernel '%s'\n", 346 kernel_filename); 347 exit(1); 348 } 349 350 /* load initrd */ 351 initrd_size = 0; 352 if (initrd_filename) { 353 initrd_size = load_image_targphys(initrd_filename, 354 INITRD_LOAD_ADDR, 355 RAM_size - INITRD_LOAD_ADDR); 356 if (initrd_size < 0) { 357 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 358 initrd_filename); 359 exit(1); 360 } 361 } 362 if (initrd_size > 0) { 363 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 364 ptr = rom_ptr(KERNEL_LOAD_ADDR + i); 365 if (ldl_p(ptr) == 0x48647253) { // HdrS 366 stl_p(ptr + 16, INITRD_LOAD_ADDR); 367 stl_p(ptr + 20, initrd_size); 368 break; 369 } 370 } 371 } 372 } 373 return kernel_size; 374 } 375 376 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 377 { 378 DeviceState *dev; 379 SysBusDevice *s; 380 381 dev = qdev_create(NULL, "iommu"); 382 qdev_prop_set_uint32(dev, "version", version); 383 qdev_init_nofail(dev); 384 s = SYS_BUS_DEVICE(dev); 385 sysbus_connect_irq(s, 0, irq); 386 sysbus_mmio_map(s, 0, addr); 387 388 return s; 389 } 390 391 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq, 392 void *iommu, qemu_irq *dev_irq, int is_ledma) 393 { 394 DeviceState *dev; 395 SysBusDevice *s; 396 397 dev = qdev_create(NULL, "sparc32_dma"); 398 qdev_prop_set_ptr(dev, "iommu_opaque", iommu); 399 qdev_prop_set_uint32(dev, "is_ledma", is_ledma); 400 qdev_init_nofail(dev); 401 s = SYS_BUS_DEVICE(dev); 402 sysbus_connect_irq(s, 0, parent_irq); 403 *dev_irq = qdev_get_gpio_in(dev, 0); 404 sysbus_mmio_map(s, 0, daddr); 405 406 return s; 407 } 408 409 static void lance_init(NICInfo *nd, hwaddr leaddr, 410 void *dma_opaque, qemu_irq irq) 411 { 412 DeviceState *dev; 413 SysBusDevice *s; 414 qemu_irq reset; 415 416 qemu_check_nic_model(&nd_table[0], "lance"); 417 418 dev = qdev_create(NULL, "lance"); 419 qdev_set_nic_properties(dev, nd); 420 qdev_prop_set_ptr(dev, "dma", dma_opaque); 421 qdev_init_nofail(dev); 422 s = SYS_BUS_DEVICE(dev); 423 sysbus_mmio_map(s, 0, leaddr); 424 sysbus_connect_irq(s, 0, irq); 425 reset = qdev_get_gpio_in(dev, 0); 426 qdev_connect_gpio_out(dma_opaque, 0, reset); 427 } 428 429 static DeviceState *slavio_intctl_init(hwaddr addr, 430 hwaddr addrg, 431 qemu_irq **parent_irq) 432 { 433 DeviceState *dev; 434 SysBusDevice *s; 435 unsigned int i, j; 436 437 dev = qdev_create(NULL, "slavio_intctl"); 438 qdev_init_nofail(dev); 439 440 s = SYS_BUS_DEVICE(dev); 441 442 for (i = 0; i < MAX_CPUS; i++) { 443 for (j = 0; j < MAX_PILS; j++) { 444 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 445 } 446 } 447 sysbus_mmio_map(s, 0, addrg); 448 for (i = 0; i < MAX_CPUS; i++) { 449 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 450 } 451 452 return dev; 453 } 454 455 #define SYS_TIMER_OFFSET 0x10000ULL 456 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 457 458 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 459 qemu_irq *cpu_irqs, unsigned int num_cpus) 460 { 461 DeviceState *dev; 462 SysBusDevice *s; 463 unsigned int i; 464 465 dev = qdev_create(NULL, "slavio_timer"); 466 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 467 qdev_init_nofail(dev); 468 s = SYS_BUS_DEVICE(dev); 469 sysbus_connect_irq(s, 0, master_irq); 470 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 471 472 for (i = 0; i < MAX_CPUS; i++) { 473 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 474 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 475 } 476 } 477 478 static qemu_irq slavio_system_powerdown; 479 480 static void slavio_powerdown_req(Notifier *n, void *opaque) 481 { 482 qemu_irq_raise(slavio_system_powerdown); 483 } 484 485 static Notifier slavio_system_powerdown_notifier = { 486 .notify = slavio_powerdown_req 487 }; 488 489 #define MISC_LEDS 0x01600000 490 #define MISC_CFG 0x01800000 491 #define MISC_DIAG 0x01a00000 492 #define MISC_MDM 0x01b00000 493 #define MISC_SYS 0x01f00000 494 495 static void slavio_misc_init(hwaddr base, 496 hwaddr aux1_base, 497 hwaddr aux2_base, qemu_irq irq, 498 qemu_irq fdc_tc) 499 { 500 DeviceState *dev; 501 SysBusDevice *s; 502 503 dev = qdev_create(NULL, "slavio_misc"); 504 qdev_init_nofail(dev); 505 s = SYS_BUS_DEVICE(dev); 506 if (base) { 507 /* 8 bit registers */ 508 /* Slavio control */ 509 sysbus_mmio_map(s, 0, base + MISC_CFG); 510 /* Diagnostics */ 511 sysbus_mmio_map(s, 1, base + MISC_DIAG); 512 /* Modem control */ 513 sysbus_mmio_map(s, 2, base + MISC_MDM); 514 /* 16 bit registers */ 515 /* ss600mp diag LEDs */ 516 sysbus_mmio_map(s, 3, base + MISC_LEDS); 517 /* 32 bit registers */ 518 /* System control */ 519 sysbus_mmio_map(s, 4, base + MISC_SYS); 520 } 521 if (aux1_base) { 522 /* AUX 1 (Misc System Functions) */ 523 sysbus_mmio_map(s, 5, aux1_base); 524 } 525 if (aux2_base) { 526 /* AUX 2 (Software Powerdown Control) */ 527 sysbus_mmio_map(s, 6, aux2_base); 528 } 529 sysbus_connect_irq(s, 0, irq); 530 sysbus_connect_irq(s, 1, fdc_tc); 531 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 532 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 533 } 534 535 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 536 { 537 DeviceState *dev; 538 SysBusDevice *s; 539 540 dev = qdev_create(NULL, "eccmemctl"); 541 qdev_prop_set_uint32(dev, "version", version); 542 qdev_init_nofail(dev); 543 s = SYS_BUS_DEVICE(dev); 544 sysbus_connect_irq(s, 0, irq); 545 sysbus_mmio_map(s, 0, base); 546 if (version == 0) { // SS-600MP only 547 sysbus_mmio_map(s, 1, base + 0x1000); 548 } 549 } 550 551 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 552 { 553 DeviceState *dev; 554 SysBusDevice *s; 555 556 dev = qdev_create(NULL, "apc"); 557 qdev_init_nofail(dev); 558 s = SYS_BUS_DEVICE(dev); 559 /* Power management (APC) XXX: not a Slavio device */ 560 sysbus_mmio_map(s, 0, power_base); 561 sysbus_connect_irq(s, 0, cpu_halt); 562 } 563 564 static void tcx_init(hwaddr addr, int vram_size, int width, 565 int height, int depth) 566 { 567 DeviceState *dev; 568 SysBusDevice *s; 569 570 dev = qdev_create(NULL, "SUNW,tcx"); 571 qdev_prop_set_taddr(dev, "addr", addr); 572 qdev_prop_set_uint32(dev, "vram_size", vram_size); 573 qdev_prop_set_uint16(dev, "width", width); 574 qdev_prop_set_uint16(dev, "height", height); 575 qdev_prop_set_uint16(dev, "depth", depth); 576 qdev_init_nofail(dev); 577 s = SYS_BUS_DEVICE(dev); 578 /* 8-bit plane */ 579 sysbus_mmio_map(s, 0, addr + 0x00800000ULL); 580 /* DAC */ 581 sysbus_mmio_map(s, 1, addr + 0x00200000ULL); 582 /* TEC (dummy) */ 583 sysbus_mmio_map(s, 2, addr + 0x00700000ULL); 584 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */ 585 sysbus_mmio_map(s, 3, addr + 0x00301000ULL); 586 if (depth == 24) { 587 /* 24-bit plane */ 588 sysbus_mmio_map(s, 4, addr + 0x02000000ULL); 589 /* Control plane */ 590 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL); 591 } else { 592 /* THC 8 bit (dummy) */ 593 sysbus_mmio_map(s, 4, addr + 0x00300000ULL); 594 } 595 } 596 597 /* NCR89C100/MACIO Internal ID register */ 598 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 599 600 static void idreg_init(hwaddr addr) 601 { 602 DeviceState *dev; 603 SysBusDevice *s; 604 605 dev = qdev_create(NULL, "macio_idreg"); 606 qdev_init_nofail(dev); 607 s = SYS_BUS_DEVICE(dev); 608 609 sysbus_mmio_map(s, 0, addr); 610 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data)); 611 } 612 613 typedef struct IDRegState { 614 SysBusDevice busdev; 615 MemoryRegion mem; 616 } IDRegState; 617 618 static int idreg_init1(SysBusDevice *dev) 619 { 620 IDRegState *s = FROM_SYSBUS(IDRegState, dev); 621 622 memory_region_init_ram(&s->mem, "sun4m.idreg", sizeof(idreg_data)); 623 vmstate_register_ram_global(&s->mem); 624 memory_region_set_readonly(&s->mem, true); 625 sysbus_init_mmio(dev, &s->mem); 626 return 0; 627 } 628 629 static void idreg_class_init(ObjectClass *klass, void *data) 630 { 631 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 632 633 k->init = idreg_init1; 634 } 635 636 static const TypeInfo idreg_info = { 637 .name = "macio_idreg", 638 .parent = TYPE_SYS_BUS_DEVICE, 639 .instance_size = sizeof(IDRegState), 640 .class_init = idreg_class_init, 641 }; 642 643 typedef struct AFXState { 644 SysBusDevice busdev; 645 MemoryRegion mem; 646 } AFXState; 647 648 /* SS-5 TCX AFX register */ 649 static void afx_init(hwaddr addr) 650 { 651 DeviceState *dev; 652 SysBusDevice *s; 653 654 dev = qdev_create(NULL, "tcx_afx"); 655 qdev_init_nofail(dev); 656 s = SYS_BUS_DEVICE(dev); 657 658 sysbus_mmio_map(s, 0, addr); 659 } 660 661 static int afx_init1(SysBusDevice *dev) 662 { 663 AFXState *s = FROM_SYSBUS(AFXState, dev); 664 665 memory_region_init_ram(&s->mem, "sun4m.afx", 4); 666 vmstate_register_ram_global(&s->mem); 667 sysbus_init_mmio(dev, &s->mem); 668 return 0; 669 } 670 671 static void afx_class_init(ObjectClass *klass, void *data) 672 { 673 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 674 675 k->init = afx_init1; 676 } 677 678 static const TypeInfo afx_info = { 679 .name = "tcx_afx", 680 .parent = TYPE_SYS_BUS_DEVICE, 681 .instance_size = sizeof(AFXState), 682 .class_init = afx_class_init, 683 }; 684 685 typedef struct PROMState { 686 SysBusDevice busdev; 687 MemoryRegion prom; 688 } PROMState; 689 690 /* Boot PROM (OpenBIOS) */ 691 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 692 { 693 hwaddr *base_addr = (hwaddr *)opaque; 694 return addr + *base_addr - PROM_VADDR; 695 } 696 697 static void prom_init(hwaddr addr, const char *bios_name) 698 { 699 DeviceState *dev; 700 SysBusDevice *s; 701 char *filename; 702 int ret; 703 704 dev = qdev_create(NULL, "openprom"); 705 qdev_init_nofail(dev); 706 s = SYS_BUS_DEVICE(dev); 707 708 sysbus_mmio_map(s, 0, addr); 709 710 /* load boot prom */ 711 if (bios_name == NULL) { 712 bios_name = PROM_FILENAME; 713 } 714 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 715 if (filename) { 716 ret = load_elf(filename, translate_prom_address, &addr, NULL, 717 NULL, NULL, 1, ELF_MACHINE, 0); 718 if (ret < 0 || ret > PROM_SIZE_MAX) { 719 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 720 } 721 g_free(filename); 722 } else { 723 ret = -1; 724 } 725 if (ret < 0 || ret > PROM_SIZE_MAX) { 726 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 727 exit(1); 728 } 729 } 730 731 static int prom_init1(SysBusDevice *dev) 732 { 733 PROMState *s = FROM_SYSBUS(PROMState, dev); 734 735 memory_region_init_ram(&s->prom, "sun4m.prom", PROM_SIZE_MAX); 736 vmstate_register_ram_global(&s->prom); 737 memory_region_set_readonly(&s->prom, true); 738 sysbus_init_mmio(dev, &s->prom); 739 return 0; 740 } 741 742 static Property prom_properties[] = { 743 {/* end of property list */}, 744 }; 745 746 static void prom_class_init(ObjectClass *klass, void *data) 747 { 748 DeviceClass *dc = DEVICE_CLASS(klass); 749 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 750 751 k->init = prom_init1; 752 dc->props = prom_properties; 753 } 754 755 static const TypeInfo prom_info = { 756 .name = "openprom", 757 .parent = TYPE_SYS_BUS_DEVICE, 758 .instance_size = sizeof(PROMState), 759 .class_init = prom_class_init, 760 }; 761 762 typedef struct RamDevice 763 { 764 SysBusDevice busdev; 765 MemoryRegion ram; 766 uint64_t size; 767 } RamDevice; 768 769 /* System RAM */ 770 static int ram_init1(SysBusDevice *dev) 771 { 772 RamDevice *d = FROM_SYSBUS(RamDevice, dev); 773 774 memory_region_init_ram(&d->ram, "sun4m.ram", d->size); 775 vmstate_register_ram_global(&d->ram); 776 sysbus_init_mmio(dev, &d->ram); 777 return 0; 778 } 779 780 static void ram_init(hwaddr addr, ram_addr_t RAM_size, 781 uint64_t max_mem) 782 { 783 DeviceState *dev; 784 SysBusDevice *s; 785 RamDevice *d; 786 787 /* allocate RAM */ 788 if ((uint64_t)RAM_size > max_mem) { 789 fprintf(stderr, 790 "qemu: Too much memory for this machine: %d, maximum %d\n", 791 (unsigned int)(RAM_size / (1024 * 1024)), 792 (unsigned int)(max_mem / (1024 * 1024))); 793 exit(1); 794 } 795 dev = qdev_create(NULL, "memory"); 796 s = SYS_BUS_DEVICE(dev); 797 798 d = FROM_SYSBUS(RamDevice, s); 799 d->size = RAM_size; 800 qdev_init_nofail(dev); 801 802 sysbus_mmio_map(s, 0, addr); 803 } 804 805 static Property ram_properties[] = { 806 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 807 DEFINE_PROP_END_OF_LIST(), 808 }; 809 810 static void ram_class_init(ObjectClass *klass, void *data) 811 { 812 DeviceClass *dc = DEVICE_CLASS(klass); 813 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 814 815 k->init = ram_init1; 816 dc->props = ram_properties; 817 } 818 819 static const TypeInfo ram_info = { 820 .name = "memory", 821 .parent = TYPE_SYS_BUS_DEVICE, 822 .instance_size = sizeof(RamDevice), 823 .class_init = ram_class_init, 824 }; 825 826 static void cpu_devinit(const char *cpu_model, unsigned int id, 827 uint64_t prom_addr, qemu_irq **cpu_irqs) 828 { 829 SPARCCPU *cpu; 830 CPUSPARCState *env; 831 832 cpu = cpu_sparc_init(cpu_model); 833 if (cpu == NULL) { 834 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); 835 exit(1); 836 } 837 env = &cpu->env; 838 839 cpu_sparc_set_id(env, id); 840 if (id == 0) { 841 qemu_register_reset(main_cpu_reset, cpu); 842 } else { 843 qemu_register_reset(secondary_cpu_reset, cpu); 844 env->halted = 1; 845 } 846 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 847 env->prom_addr = prom_addr; 848 } 849 850 static void dummy_fdc_tc(void *opaque, int irq, int level) 851 { 852 } 853 854 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, 855 const char *boot_device, 856 const char *kernel_filename, 857 const char *kernel_cmdline, 858 const char *initrd_filename, const char *cpu_model) 859 { 860 unsigned int i; 861 void *iommu, *espdma, *ledma, *nvram; 862 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS], 863 espdma_irq, ledma_irq; 864 qemu_irq esp_reset, dma_enable; 865 qemu_irq fdc_tc; 866 qemu_irq *cpu_halt; 867 unsigned long kernel_size; 868 DriveInfo *fd[MAX_FD]; 869 void *fw_cfg; 870 unsigned int num_vsimms; 871 872 /* init CPUs */ 873 if (!cpu_model) 874 cpu_model = hwdef->default_cpu_model; 875 876 for(i = 0; i < smp_cpus; i++) { 877 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); 878 } 879 880 for (i = smp_cpus; i < MAX_CPUS; i++) 881 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 882 883 884 /* set up devices */ 885 ram_init(0, RAM_size, hwdef->max_mem); 886 /* models without ECC don't trap when missing ram is accessed */ 887 if (!hwdef->ecc_base) { 888 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size); 889 } 890 891 prom_init(hwdef->slavio_base, bios_name); 892 893 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 894 hwdef->intctl_base + 0x10000ULL, 895 cpu_irqs); 896 897 for (i = 0; i < 32; i++) { 898 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 899 } 900 for (i = 0; i < MAX_CPUS; i++) { 901 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 902 } 903 904 if (hwdef->idreg_base) { 905 idreg_init(hwdef->idreg_base); 906 } 907 908 if (hwdef->afx_base) { 909 afx_init(hwdef->afx_base); 910 } 911 912 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, 913 slavio_irq[30]); 914 915 if (hwdef->iommu_pad_base) { 916 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 917 Software shouldn't use aliased addresses, neither should it crash 918 when does. Using empty_slot instead of aliasing can help with 919 debugging such accesses */ 920 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); 921 } 922 923 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18], 924 iommu, &espdma_irq, 0); 925 926 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, 927 slavio_irq[16], iommu, &ledma_irq, 1); 928 929 if (graphic_depth != 8 && graphic_depth != 24) { 930 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); 931 exit (1); 932 } 933 num_vsimms = 0; 934 if (num_vsimms == 0) { 935 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height, 936 graphic_depth); 937 } 938 939 for (i = num_vsimms; i < MAX_VSIMMS; i++) { 940 /* vsimm registers probed by OBP */ 941 if (hwdef->vsimm[i].reg_base) { 942 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); 943 } 944 } 945 946 if (hwdef->sx_base) { 947 empty_slot_init(hwdef->sx_base, 0x2000); 948 } 949 950 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq); 951 952 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8); 953 954 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 955 956 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14], 957 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1); 958 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 959 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 960 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], 961 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); 962 963 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); 964 if (hwdef->apc_base) { 965 apc_init(hwdef->apc_base, cpu_halt[0]); 966 } 967 968 if (hwdef->fd_base) { 969 /* there is zero or one floppy drive */ 970 memset(fd, 0, sizeof(fd)); 971 fd[0] = drive_get(IF_FLOPPY, 0, 0); 972 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 973 &fdc_tc); 974 } else { 975 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1); 976 } 977 978 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 979 slavio_irq[30], fdc_tc); 980 981 if (drive_get_max_bus(IF_SCSI) > 0) { 982 fprintf(stderr, "qemu: too many SCSI bus\n"); 983 exit(1); 984 } 985 986 esp_init(hwdef->esp_base, 2, 987 espdma_memory_read, espdma_memory_write, 988 espdma, espdma_irq, &esp_reset, &dma_enable); 989 990 qdev_connect_gpio_out(espdma, 0, esp_reset); 991 qdev_connect_gpio_out(espdma, 1, dma_enable); 992 993 if (hwdef->cs_base) { 994 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, 995 slavio_irq[5]); 996 } 997 998 if (hwdef->dbri_base) { 999 /* ISDN chip with attached CS4215 audio codec */ 1000 /* prom space */ 1001 empty_slot_init(hwdef->dbri_base+0x1000, 0x30); 1002 /* reg space */ 1003 empty_slot_init(hwdef->dbri_base+0x10000, 0x100); 1004 } 1005 1006 if (hwdef->bpp_base) { 1007 /* parallel port */ 1008 empty_slot_init(hwdef->bpp_base, 0x20); 1009 } 1010 1011 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, 1012 RAM_size); 1013 1014 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, 1015 boot_device, RAM_size, kernel_size, graphic_width, 1016 graphic_height, graphic_depth, hwdef->nvram_machine_id, 1017 "Sun4m"); 1018 1019 if (hwdef->ecc_base) 1020 ecc_init(hwdef->ecc_base, slavio_irq[28], 1021 hwdef->ecc_version); 1022 1023 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); 1024 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1025 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 1026 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1027 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1028 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1029 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1030 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1031 if (kernel_cmdline) { 1032 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1033 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); 1034 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1035 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1036 strlen(kernel_cmdline) + 1); 1037 } else { 1038 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1039 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1040 } 1041 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1042 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used 1043 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]); 1044 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1045 } 1046 1047 enum { 1048 ss2_id = 0, 1049 ss5_id = 32, 1050 vger_id, 1051 lx_id, 1052 ss4_id, 1053 scls_id, 1054 sbook_id, 1055 ss10_id = 64, 1056 ss20_id, 1057 ss600mp_id, 1058 ss1000_id = 96, 1059 ss2000_id, 1060 }; 1061 1062 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1063 /* SS-5 */ 1064 { 1065 .iommu_base = 0x10000000, 1066 .iommu_pad_base = 0x10004000, 1067 .iommu_pad_len = 0x0fffb000, 1068 .tcx_base = 0x50000000, 1069 .cs_base = 0x6c000000, 1070 .slavio_base = 0x70000000, 1071 .ms_kb_base = 0x71000000, 1072 .serial_base = 0x71100000, 1073 .nvram_base = 0x71200000, 1074 .fd_base = 0x71400000, 1075 .counter_base = 0x71d00000, 1076 .intctl_base = 0x71e00000, 1077 .idreg_base = 0x78000000, 1078 .dma_base = 0x78400000, 1079 .esp_base = 0x78800000, 1080 .le_base = 0x78c00000, 1081 .apc_base = 0x6a000000, 1082 .afx_base = 0x6e000000, 1083 .aux1_base = 0x71900000, 1084 .aux2_base = 0x71910000, 1085 .nvram_machine_id = 0x80, 1086 .machine_id = ss5_id, 1087 .iommu_version = 0x05000000, 1088 .max_mem = 0x10000000, 1089 .default_cpu_model = "Fujitsu MB86904", 1090 }, 1091 /* SS-10 */ 1092 { 1093 .iommu_base = 0xfe0000000ULL, 1094 .tcx_base = 0xe20000000ULL, 1095 .slavio_base = 0xff0000000ULL, 1096 .ms_kb_base = 0xff1000000ULL, 1097 .serial_base = 0xff1100000ULL, 1098 .nvram_base = 0xff1200000ULL, 1099 .fd_base = 0xff1700000ULL, 1100 .counter_base = 0xff1300000ULL, 1101 .intctl_base = 0xff1400000ULL, 1102 .idreg_base = 0xef0000000ULL, 1103 .dma_base = 0xef0400000ULL, 1104 .esp_base = 0xef0800000ULL, 1105 .le_base = 0xef0c00000ULL, 1106 .apc_base = 0xefa000000ULL, // XXX should not exist 1107 .aux1_base = 0xff1800000ULL, 1108 .aux2_base = 0xff1a01000ULL, 1109 .ecc_base = 0xf00000000ULL, 1110 .ecc_version = 0x10000000, // version 0, implementation 1 1111 .nvram_machine_id = 0x72, 1112 .machine_id = ss10_id, 1113 .iommu_version = 0x03000000, 1114 .max_mem = 0xf00000000ULL, 1115 .default_cpu_model = "TI SuperSparc II", 1116 }, 1117 /* SS-600MP */ 1118 { 1119 .iommu_base = 0xfe0000000ULL, 1120 .tcx_base = 0xe20000000ULL, 1121 .slavio_base = 0xff0000000ULL, 1122 .ms_kb_base = 0xff1000000ULL, 1123 .serial_base = 0xff1100000ULL, 1124 .nvram_base = 0xff1200000ULL, 1125 .counter_base = 0xff1300000ULL, 1126 .intctl_base = 0xff1400000ULL, 1127 .dma_base = 0xef0081000ULL, 1128 .esp_base = 0xef0080000ULL, 1129 .le_base = 0xef0060000ULL, 1130 .apc_base = 0xefa000000ULL, // XXX should not exist 1131 .aux1_base = 0xff1800000ULL, 1132 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1133 .ecc_base = 0xf00000000ULL, 1134 .ecc_version = 0x00000000, // version 0, implementation 0 1135 .nvram_machine_id = 0x71, 1136 .machine_id = ss600mp_id, 1137 .iommu_version = 0x01000000, 1138 .max_mem = 0xf00000000ULL, 1139 .default_cpu_model = "TI SuperSparc II", 1140 }, 1141 /* SS-20 */ 1142 { 1143 .iommu_base = 0xfe0000000ULL, 1144 .tcx_base = 0xe20000000ULL, 1145 .slavio_base = 0xff0000000ULL, 1146 .ms_kb_base = 0xff1000000ULL, 1147 .serial_base = 0xff1100000ULL, 1148 .nvram_base = 0xff1200000ULL, 1149 .fd_base = 0xff1700000ULL, 1150 .counter_base = 0xff1300000ULL, 1151 .intctl_base = 0xff1400000ULL, 1152 .idreg_base = 0xef0000000ULL, 1153 .dma_base = 0xef0400000ULL, 1154 .esp_base = 0xef0800000ULL, 1155 .le_base = 0xef0c00000ULL, 1156 .bpp_base = 0xef4800000ULL, 1157 .apc_base = 0xefa000000ULL, // XXX should not exist 1158 .aux1_base = 0xff1800000ULL, 1159 .aux2_base = 0xff1a01000ULL, 1160 .dbri_base = 0xee0000000ULL, 1161 .sx_base = 0xf80000000ULL, 1162 .vsimm = { 1163 { 1164 .reg_base = 0x9c000000ULL, 1165 .vram_base = 0xfc000000ULL 1166 }, { 1167 .reg_base = 0x90000000ULL, 1168 .vram_base = 0xf0000000ULL 1169 }, { 1170 .reg_base = 0x94000000ULL 1171 }, { 1172 .reg_base = 0x98000000ULL 1173 } 1174 }, 1175 .ecc_base = 0xf00000000ULL, 1176 .ecc_version = 0x20000000, // version 0, implementation 2 1177 .nvram_machine_id = 0x72, 1178 .machine_id = ss20_id, 1179 .iommu_version = 0x13000000, 1180 .max_mem = 0xf00000000ULL, 1181 .default_cpu_model = "TI SuperSparc II", 1182 }, 1183 /* Voyager */ 1184 { 1185 .iommu_base = 0x10000000, 1186 .tcx_base = 0x50000000, 1187 .slavio_base = 0x70000000, 1188 .ms_kb_base = 0x71000000, 1189 .serial_base = 0x71100000, 1190 .nvram_base = 0x71200000, 1191 .fd_base = 0x71400000, 1192 .counter_base = 0x71d00000, 1193 .intctl_base = 0x71e00000, 1194 .idreg_base = 0x78000000, 1195 .dma_base = 0x78400000, 1196 .esp_base = 0x78800000, 1197 .le_base = 0x78c00000, 1198 .apc_base = 0x71300000, // pmc 1199 .aux1_base = 0x71900000, 1200 .aux2_base = 0x71910000, 1201 .nvram_machine_id = 0x80, 1202 .machine_id = vger_id, 1203 .iommu_version = 0x05000000, 1204 .max_mem = 0x10000000, 1205 .default_cpu_model = "Fujitsu MB86904", 1206 }, 1207 /* LX */ 1208 { 1209 .iommu_base = 0x10000000, 1210 .iommu_pad_base = 0x10004000, 1211 .iommu_pad_len = 0x0fffb000, 1212 .tcx_base = 0x50000000, 1213 .slavio_base = 0x70000000, 1214 .ms_kb_base = 0x71000000, 1215 .serial_base = 0x71100000, 1216 .nvram_base = 0x71200000, 1217 .fd_base = 0x71400000, 1218 .counter_base = 0x71d00000, 1219 .intctl_base = 0x71e00000, 1220 .idreg_base = 0x78000000, 1221 .dma_base = 0x78400000, 1222 .esp_base = 0x78800000, 1223 .le_base = 0x78c00000, 1224 .aux1_base = 0x71900000, 1225 .aux2_base = 0x71910000, 1226 .nvram_machine_id = 0x80, 1227 .machine_id = lx_id, 1228 .iommu_version = 0x04000000, 1229 .max_mem = 0x10000000, 1230 .default_cpu_model = "TI MicroSparc I", 1231 }, 1232 /* SS-4 */ 1233 { 1234 .iommu_base = 0x10000000, 1235 .tcx_base = 0x50000000, 1236 .cs_base = 0x6c000000, 1237 .slavio_base = 0x70000000, 1238 .ms_kb_base = 0x71000000, 1239 .serial_base = 0x71100000, 1240 .nvram_base = 0x71200000, 1241 .fd_base = 0x71400000, 1242 .counter_base = 0x71d00000, 1243 .intctl_base = 0x71e00000, 1244 .idreg_base = 0x78000000, 1245 .dma_base = 0x78400000, 1246 .esp_base = 0x78800000, 1247 .le_base = 0x78c00000, 1248 .apc_base = 0x6a000000, 1249 .aux1_base = 0x71900000, 1250 .aux2_base = 0x71910000, 1251 .nvram_machine_id = 0x80, 1252 .machine_id = ss4_id, 1253 .iommu_version = 0x05000000, 1254 .max_mem = 0x10000000, 1255 .default_cpu_model = "Fujitsu MB86904", 1256 }, 1257 /* SPARCClassic */ 1258 { 1259 .iommu_base = 0x10000000, 1260 .tcx_base = 0x50000000, 1261 .slavio_base = 0x70000000, 1262 .ms_kb_base = 0x71000000, 1263 .serial_base = 0x71100000, 1264 .nvram_base = 0x71200000, 1265 .fd_base = 0x71400000, 1266 .counter_base = 0x71d00000, 1267 .intctl_base = 0x71e00000, 1268 .idreg_base = 0x78000000, 1269 .dma_base = 0x78400000, 1270 .esp_base = 0x78800000, 1271 .le_base = 0x78c00000, 1272 .apc_base = 0x6a000000, 1273 .aux1_base = 0x71900000, 1274 .aux2_base = 0x71910000, 1275 .nvram_machine_id = 0x80, 1276 .machine_id = scls_id, 1277 .iommu_version = 0x05000000, 1278 .max_mem = 0x10000000, 1279 .default_cpu_model = "TI MicroSparc I", 1280 }, 1281 /* SPARCbook */ 1282 { 1283 .iommu_base = 0x10000000, 1284 .tcx_base = 0x50000000, // XXX 1285 .slavio_base = 0x70000000, 1286 .ms_kb_base = 0x71000000, 1287 .serial_base = 0x71100000, 1288 .nvram_base = 0x71200000, 1289 .fd_base = 0x71400000, 1290 .counter_base = 0x71d00000, 1291 .intctl_base = 0x71e00000, 1292 .idreg_base = 0x78000000, 1293 .dma_base = 0x78400000, 1294 .esp_base = 0x78800000, 1295 .le_base = 0x78c00000, 1296 .apc_base = 0x6a000000, 1297 .aux1_base = 0x71900000, 1298 .aux2_base = 0x71910000, 1299 .nvram_machine_id = 0x80, 1300 .machine_id = sbook_id, 1301 .iommu_version = 0x05000000, 1302 .max_mem = 0x10000000, 1303 .default_cpu_model = "TI MicroSparc I", 1304 }, 1305 }; 1306 1307 /* SPARCstation 5 hardware initialisation */ 1308 static void ss5_init(QEMUMachineInitArgs *args) 1309 { 1310 ram_addr_t RAM_size = args->ram_size; 1311 const char *cpu_model = args->cpu_model; 1312 const char *kernel_filename = args->kernel_filename; 1313 const char *kernel_cmdline = args->kernel_cmdline; 1314 const char *initrd_filename = args->initrd_filename; 1315 const char *boot_device = args->boot_device; 1316 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename, 1317 kernel_cmdline, initrd_filename, cpu_model); 1318 } 1319 1320 /* SPARCstation 10 hardware initialisation */ 1321 static void ss10_init(QEMUMachineInitArgs *args) 1322 { 1323 ram_addr_t RAM_size = args->ram_size; 1324 const char *cpu_model = args->cpu_model; 1325 const char *kernel_filename = args->kernel_filename; 1326 const char *kernel_cmdline = args->kernel_cmdline; 1327 const char *initrd_filename = args->initrd_filename; 1328 const char *boot_device = args->boot_device; 1329 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename, 1330 kernel_cmdline, initrd_filename, cpu_model); 1331 } 1332 1333 /* SPARCserver 600MP hardware initialisation */ 1334 static void ss600mp_init(QEMUMachineInitArgs *args) 1335 { 1336 ram_addr_t RAM_size = args->ram_size; 1337 const char *cpu_model = args->cpu_model; 1338 const char *kernel_filename = args->kernel_filename; 1339 const char *kernel_cmdline = args->kernel_cmdline; 1340 const char *initrd_filename = args->initrd_filename; 1341 const char *boot_device = args->boot_device; 1342 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename, 1343 kernel_cmdline, initrd_filename, cpu_model); 1344 } 1345 1346 /* SPARCstation 20 hardware initialisation */ 1347 static void ss20_init(QEMUMachineInitArgs *args) 1348 { 1349 ram_addr_t RAM_size = args->ram_size; 1350 const char *cpu_model = args->cpu_model; 1351 const char *kernel_filename = args->kernel_filename; 1352 const char *kernel_cmdline = args->kernel_cmdline; 1353 const char *initrd_filename = args->initrd_filename; 1354 const char *boot_device = args->boot_device; 1355 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename, 1356 kernel_cmdline, initrd_filename, cpu_model); 1357 } 1358 1359 /* SPARCstation Voyager hardware initialisation */ 1360 static void vger_init(QEMUMachineInitArgs *args) 1361 { 1362 ram_addr_t RAM_size = args->ram_size; 1363 const char *cpu_model = args->cpu_model; 1364 const char *kernel_filename = args->kernel_filename; 1365 const char *kernel_cmdline = args->kernel_cmdline; 1366 const char *initrd_filename = args->initrd_filename; 1367 const char *boot_device = args->boot_device; 1368 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename, 1369 kernel_cmdline, initrd_filename, cpu_model); 1370 } 1371 1372 /* SPARCstation LX hardware initialisation */ 1373 static void ss_lx_init(QEMUMachineInitArgs *args) 1374 { 1375 ram_addr_t RAM_size = args->ram_size; 1376 const char *cpu_model = args->cpu_model; 1377 const char *kernel_filename = args->kernel_filename; 1378 const char *kernel_cmdline = args->kernel_cmdline; 1379 const char *initrd_filename = args->initrd_filename; 1380 const char *boot_device = args->boot_device; 1381 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename, 1382 kernel_cmdline, initrd_filename, cpu_model); 1383 } 1384 1385 /* SPARCstation 4 hardware initialisation */ 1386 static void ss4_init(QEMUMachineInitArgs *args) 1387 { 1388 ram_addr_t RAM_size = args->ram_size; 1389 const char *cpu_model = args->cpu_model; 1390 const char *kernel_filename = args->kernel_filename; 1391 const char *kernel_cmdline = args->kernel_cmdline; 1392 const char *initrd_filename = args->initrd_filename; 1393 const char *boot_device = args->boot_device; 1394 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename, 1395 kernel_cmdline, initrd_filename, cpu_model); 1396 } 1397 1398 /* SPARCClassic hardware initialisation */ 1399 static void scls_init(QEMUMachineInitArgs *args) 1400 { 1401 ram_addr_t RAM_size = args->ram_size; 1402 const char *cpu_model = args->cpu_model; 1403 const char *kernel_filename = args->kernel_filename; 1404 const char *kernel_cmdline = args->kernel_cmdline; 1405 const char *initrd_filename = args->initrd_filename; 1406 const char *boot_device = args->boot_device; 1407 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename, 1408 kernel_cmdline, initrd_filename, cpu_model); 1409 } 1410 1411 /* SPARCbook hardware initialisation */ 1412 static void sbook_init(QEMUMachineInitArgs *args) 1413 { 1414 ram_addr_t RAM_size = args->ram_size; 1415 const char *cpu_model = args->cpu_model; 1416 const char *kernel_filename = args->kernel_filename; 1417 const char *kernel_cmdline = args->kernel_cmdline; 1418 const char *initrd_filename = args->initrd_filename; 1419 const char *boot_device = args->boot_device; 1420 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename, 1421 kernel_cmdline, initrd_filename, cpu_model); 1422 } 1423 1424 static QEMUMachine ss5_machine = { 1425 .name = "SS-5", 1426 .desc = "Sun4m platform, SPARCstation 5", 1427 .init = ss5_init, 1428 .block_default_type = IF_SCSI, 1429 .is_default = 1, 1430 DEFAULT_MACHINE_OPTIONS, 1431 }; 1432 1433 static QEMUMachine ss10_machine = { 1434 .name = "SS-10", 1435 .desc = "Sun4m platform, SPARCstation 10", 1436 .init = ss10_init, 1437 .block_default_type = IF_SCSI, 1438 .max_cpus = 4, 1439 DEFAULT_MACHINE_OPTIONS, 1440 }; 1441 1442 static QEMUMachine ss600mp_machine = { 1443 .name = "SS-600MP", 1444 .desc = "Sun4m platform, SPARCserver 600MP", 1445 .init = ss600mp_init, 1446 .block_default_type = IF_SCSI, 1447 .max_cpus = 4, 1448 DEFAULT_MACHINE_OPTIONS, 1449 }; 1450 1451 static QEMUMachine ss20_machine = { 1452 .name = "SS-20", 1453 .desc = "Sun4m platform, SPARCstation 20", 1454 .init = ss20_init, 1455 .block_default_type = IF_SCSI, 1456 .max_cpus = 4, 1457 DEFAULT_MACHINE_OPTIONS, 1458 }; 1459 1460 static QEMUMachine voyager_machine = { 1461 .name = "Voyager", 1462 .desc = "Sun4m platform, SPARCstation Voyager", 1463 .init = vger_init, 1464 .block_default_type = IF_SCSI, 1465 DEFAULT_MACHINE_OPTIONS, 1466 }; 1467 1468 static QEMUMachine ss_lx_machine = { 1469 .name = "LX", 1470 .desc = "Sun4m platform, SPARCstation LX", 1471 .init = ss_lx_init, 1472 .block_default_type = IF_SCSI, 1473 DEFAULT_MACHINE_OPTIONS, 1474 }; 1475 1476 static QEMUMachine ss4_machine = { 1477 .name = "SS-4", 1478 .desc = "Sun4m platform, SPARCstation 4", 1479 .init = ss4_init, 1480 .block_default_type = IF_SCSI, 1481 DEFAULT_MACHINE_OPTIONS, 1482 }; 1483 1484 static QEMUMachine scls_machine = { 1485 .name = "SPARCClassic", 1486 .desc = "Sun4m platform, SPARCClassic", 1487 .init = scls_init, 1488 .block_default_type = IF_SCSI, 1489 DEFAULT_MACHINE_OPTIONS, 1490 }; 1491 1492 static QEMUMachine sbook_machine = { 1493 .name = "SPARCbook", 1494 .desc = "Sun4m platform, SPARCbook", 1495 .init = sbook_init, 1496 .block_default_type = IF_SCSI, 1497 DEFAULT_MACHINE_OPTIONS, 1498 }; 1499 1500 static const struct sun4d_hwdef sun4d_hwdefs[] = { 1501 /* SS-1000 */ 1502 { 1503 .iounit_bases = { 1504 0xfe0200000ULL, 1505 0xfe1200000ULL, 1506 0xfe2200000ULL, 1507 0xfe3200000ULL, 1508 -1, 1509 }, 1510 .tcx_base = 0x820000000ULL, 1511 .slavio_base = 0xf00000000ULL, 1512 .ms_kb_base = 0xf00240000ULL, 1513 .serial_base = 0xf00200000ULL, 1514 .nvram_base = 0xf00280000ULL, 1515 .counter_base = 0xf00300000ULL, 1516 .espdma_base = 0x800081000ULL, 1517 .esp_base = 0x800080000ULL, 1518 .ledma_base = 0x800040000ULL, 1519 .le_base = 0x800060000ULL, 1520 .sbi_base = 0xf02800000ULL, 1521 .nvram_machine_id = 0x80, 1522 .machine_id = ss1000_id, 1523 .iounit_version = 0x03000000, 1524 .max_mem = 0xf00000000ULL, 1525 .default_cpu_model = "TI SuperSparc II", 1526 }, 1527 /* SS-2000 */ 1528 { 1529 .iounit_bases = { 1530 0xfe0200000ULL, 1531 0xfe1200000ULL, 1532 0xfe2200000ULL, 1533 0xfe3200000ULL, 1534 0xfe4200000ULL, 1535 }, 1536 .tcx_base = 0x820000000ULL, 1537 .slavio_base = 0xf00000000ULL, 1538 .ms_kb_base = 0xf00240000ULL, 1539 .serial_base = 0xf00200000ULL, 1540 .nvram_base = 0xf00280000ULL, 1541 .counter_base = 0xf00300000ULL, 1542 .espdma_base = 0x800081000ULL, 1543 .esp_base = 0x800080000ULL, 1544 .ledma_base = 0x800040000ULL, 1545 .le_base = 0x800060000ULL, 1546 .sbi_base = 0xf02800000ULL, 1547 .nvram_machine_id = 0x80, 1548 .machine_id = ss2000_id, 1549 .iounit_version = 0x03000000, 1550 .max_mem = 0xf00000000ULL, 1551 .default_cpu_model = "TI SuperSparc II", 1552 }, 1553 }; 1554 1555 static DeviceState *sbi_init(hwaddr addr, qemu_irq **parent_irq) 1556 { 1557 DeviceState *dev; 1558 SysBusDevice *s; 1559 unsigned int i; 1560 1561 dev = qdev_create(NULL, "sbi"); 1562 qdev_init_nofail(dev); 1563 1564 s = SYS_BUS_DEVICE(dev); 1565 1566 for (i = 0; i < MAX_CPUS; i++) { 1567 sysbus_connect_irq(s, i, *parent_irq[i]); 1568 } 1569 1570 sysbus_mmio_map(s, 0, addr); 1571 1572 return dev; 1573 } 1574 1575 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, 1576 const char *boot_device, 1577 const char *kernel_filename, 1578 const char *kernel_cmdline, 1579 const char *initrd_filename, const char *cpu_model) 1580 { 1581 unsigned int i; 1582 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram; 1583 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS], 1584 espdma_irq, ledma_irq; 1585 qemu_irq esp_reset, dma_enable; 1586 unsigned long kernel_size; 1587 void *fw_cfg; 1588 DeviceState *dev; 1589 1590 /* init CPUs */ 1591 if (!cpu_model) 1592 cpu_model = hwdef->default_cpu_model; 1593 1594 for(i = 0; i < smp_cpus; i++) { 1595 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); 1596 } 1597 1598 for (i = smp_cpus; i < MAX_CPUS; i++) 1599 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 1600 1601 /* set up devices */ 1602 ram_init(0, RAM_size, hwdef->max_mem); 1603 1604 prom_init(hwdef->slavio_base, bios_name); 1605 1606 dev = sbi_init(hwdef->sbi_base, cpu_irqs); 1607 1608 for (i = 0; i < 32; i++) { 1609 sbi_irq[i] = qdev_get_gpio_in(dev, i); 1610 } 1611 for (i = 0; i < MAX_CPUS; i++) { 1612 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i); 1613 } 1614 1615 for (i = 0; i < MAX_IOUNITS; i++) 1616 if (hwdef->iounit_bases[i] != (hwaddr)-1) 1617 iounits[i] = iommu_init(hwdef->iounit_bases[i], 1618 hwdef->iounit_version, 1619 sbi_irq[0]); 1620 1621 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3], 1622 iounits[0], &espdma_irq, 0); 1623 1624 /* should be lebuffer instead */ 1625 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4], 1626 iounits[0], &ledma_irq, 0); 1627 1628 if (graphic_depth != 8 && graphic_depth != 24) { 1629 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); 1630 exit (1); 1631 } 1632 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height, 1633 graphic_depth); 1634 1635 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq); 1636 1637 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8); 1638 1639 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus); 1640 1641 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12], 1642 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1); 1643 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 1644 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 1645 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12], 1646 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); 1647 1648 if (drive_get_max_bus(IF_SCSI) > 0) { 1649 fprintf(stderr, "qemu: too many SCSI bus\n"); 1650 exit(1); 1651 } 1652 1653 esp_init(hwdef->esp_base, 2, 1654 espdma_memory_read, espdma_memory_write, 1655 espdma, espdma_irq, &esp_reset, &dma_enable); 1656 1657 qdev_connect_gpio_out(espdma, 0, esp_reset); 1658 qdev_connect_gpio_out(espdma, 1, dma_enable); 1659 1660 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, 1661 RAM_size); 1662 1663 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, 1664 boot_device, RAM_size, kernel_size, graphic_width, 1665 graphic_height, graphic_depth, hwdef->nvram_machine_id, 1666 "Sun4d"); 1667 1668 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); 1669 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1670 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 1671 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1672 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1673 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1674 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1675 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1676 if (kernel_cmdline) { 1677 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1678 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); 1679 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1680 } else { 1681 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1682 } 1683 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1684 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used 1685 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]); 1686 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1687 } 1688 1689 /* SPARCserver 1000 hardware initialisation */ 1690 static void ss1000_init(QEMUMachineInitArgs *args) 1691 { 1692 ram_addr_t RAM_size = args->ram_size; 1693 const char *cpu_model = args->cpu_model; 1694 const char *kernel_filename = args->kernel_filename; 1695 const char *kernel_cmdline = args->kernel_cmdline; 1696 const char *initrd_filename = args->initrd_filename; 1697 const char *boot_device = args->boot_device; 1698 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename, 1699 kernel_cmdline, initrd_filename, cpu_model); 1700 } 1701 1702 /* SPARCcenter 2000 hardware initialisation */ 1703 static void ss2000_init(QEMUMachineInitArgs *args) 1704 { 1705 ram_addr_t RAM_size = args->ram_size; 1706 const char *cpu_model = args->cpu_model; 1707 const char *kernel_filename = args->kernel_filename; 1708 const char *kernel_cmdline = args->kernel_cmdline; 1709 const char *initrd_filename = args->initrd_filename; 1710 const char *boot_device = args->boot_device; 1711 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename, 1712 kernel_cmdline, initrd_filename, cpu_model); 1713 } 1714 1715 static QEMUMachine ss1000_machine = { 1716 .name = "SS-1000", 1717 .desc = "Sun4d platform, SPARCserver 1000", 1718 .init = ss1000_init, 1719 .block_default_type = IF_SCSI, 1720 .max_cpus = 8, 1721 DEFAULT_MACHINE_OPTIONS, 1722 }; 1723 1724 static QEMUMachine ss2000_machine = { 1725 .name = "SS-2000", 1726 .desc = "Sun4d platform, SPARCcenter 2000", 1727 .init = ss2000_init, 1728 .block_default_type = IF_SCSI, 1729 .max_cpus = 20, 1730 DEFAULT_MACHINE_OPTIONS, 1731 }; 1732 1733 static const struct sun4c_hwdef sun4c_hwdefs[] = { 1734 /* SS-2 */ 1735 { 1736 .iommu_base = 0xf8000000, 1737 .tcx_base = 0xfe000000, 1738 .slavio_base = 0xf6000000, 1739 .intctl_base = 0xf5000000, 1740 .counter_base = 0xf3000000, 1741 .ms_kb_base = 0xf0000000, 1742 .serial_base = 0xf1000000, 1743 .nvram_base = 0xf2000000, 1744 .fd_base = 0xf7200000, 1745 .dma_base = 0xf8400000, 1746 .esp_base = 0xf8800000, 1747 .le_base = 0xf8c00000, 1748 .aux1_base = 0xf7400003, 1749 .nvram_machine_id = 0x55, 1750 .machine_id = ss2_id, 1751 .max_mem = 0x10000000, 1752 .default_cpu_model = "Cypress CY7C601", 1753 }, 1754 }; 1755 1756 static DeviceState *sun4c_intctl_init(hwaddr addr, 1757 qemu_irq *parent_irq) 1758 { 1759 DeviceState *dev; 1760 SysBusDevice *s; 1761 unsigned int i; 1762 1763 dev = qdev_create(NULL, "sun4c_intctl"); 1764 qdev_init_nofail(dev); 1765 1766 s = SYS_BUS_DEVICE(dev); 1767 1768 for (i = 0; i < MAX_PILS; i++) { 1769 sysbus_connect_irq(s, i, parent_irq[i]); 1770 } 1771 sysbus_mmio_map(s, 0, addr); 1772 1773 return dev; 1774 } 1775 1776 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, 1777 const char *boot_device, 1778 const char *kernel_filename, 1779 const char *kernel_cmdline, 1780 const char *initrd_filename, const char *cpu_model) 1781 { 1782 void *iommu, *espdma, *ledma, *nvram; 1783 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq; 1784 qemu_irq esp_reset, dma_enable; 1785 qemu_irq fdc_tc; 1786 unsigned long kernel_size; 1787 DriveInfo *fd[MAX_FD]; 1788 void *fw_cfg; 1789 DeviceState *dev; 1790 unsigned int i; 1791 1792 /* init CPU */ 1793 if (!cpu_model) 1794 cpu_model = hwdef->default_cpu_model; 1795 1796 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs); 1797 1798 /* set up devices */ 1799 ram_init(0, RAM_size, hwdef->max_mem); 1800 1801 prom_init(hwdef->slavio_base, bios_name); 1802 1803 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs); 1804 1805 for (i = 0; i < 8; i++) { 1806 slavio_irq[i] = qdev_get_gpio_in(dev, i); 1807 } 1808 1809 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, 1810 slavio_irq[1]); 1811 1812 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2], 1813 iommu, &espdma_irq, 0); 1814 1815 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, 1816 slavio_irq[3], iommu, &ledma_irq, 1); 1817 1818 if (graphic_depth != 8 && graphic_depth != 24) { 1819 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); 1820 exit (1); 1821 } 1822 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height, 1823 graphic_depth); 1824 1825 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq); 1826 1827 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2); 1828 1829 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1], 1830 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1); 1831 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 1832 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 1833 escc_init(hwdef->serial_base, slavio_irq[1], 1834 slavio_irq[1], serial_hds[0], serial_hds[1], 1835 ESCC_CLOCK, 1); 1836 1837 if (hwdef->fd_base != (hwaddr)-1) { 1838 /* there is zero or one floppy drive */ 1839 memset(fd, 0, sizeof(fd)); 1840 fd[0] = drive_get(IF_FLOPPY, 0, 0); 1841 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd, 1842 &fdc_tc); 1843 } else { 1844 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1); 1845 } 1846 1847 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc); 1848 1849 if (drive_get_max_bus(IF_SCSI) > 0) { 1850 fprintf(stderr, "qemu: too many SCSI bus\n"); 1851 exit(1); 1852 } 1853 1854 esp_init(hwdef->esp_base, 2, 1855 espdma_memory_read, espdma_memory_write, 1856 espdma, espdma_irq, &esp_reset, &dma_enable); 1857 1858 qdev_connect_gpio_out(espdma, 0, esp_reset); 1859 qdev_connect_gpio_out(espdma, 1, dma_enable); 1860 1861 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, 1862 RAM_size); 1863 1864 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, 1865 boot_device, RAM_size, kernel_size, graphic_width, 1866 graphic_height, graphic_depth, hwdef->nvram_machine_id, 1867 "Sun4c"); 1868 1869 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); 1870 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1871 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 1872 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1873 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1874 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1875 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1876 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1877 if (kernel_cmdline) { 1878 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1879 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); 1880 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1881 } else { 1882 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1883 } 1884 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1885 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used 1886 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]); 1887 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1888 } 1889 1890 /* SPARCstation 2 hardware initialisation */ 1891 static void ss2_init(QEMUMachineInitArgs *args) 1892 { 1893 ram_addr_t RAM_size = args->ram_size; 1894 const char *cpu_model = args->cpu_model; 1895 const char *kernel_filename = args->kernel_filename; 1896 const char *kernel_cmdline = args->kernel_cmdline; 1897 const char *initrd_filename = args->initrd_filename; 1898 const char *boot_device = args->boot_device; 1899 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename, 1900 kernel_cmdline, initrd_filename, cpu_model); 1901 } 1902 1903 static QEMUMachine ss2_machine = { 1904 .name = "SS-2", 1905 .desc = "Sun4c platform, SPARCstation 2", 1906 .init = ss2_init, 1907 .block_default_type = IF_SCSI, 1908 DEFAULT_MACHINE_OPTIONS, 1909 }; 1910 1911 static void sun4m_register_types(void) 1912 { 1913 type_register_static(&idreg_info); 1914 type_register_static(&afx_info); 1915 type_register_static(&prom_info); 1916 type_register_static(&ram_info); 1917 } 1918 1919 static void ss2_machine_init(void) 1920 { 1921 qemu_register_machine(&ss5_machine); 1922 qemu_register_machine(&ss10_machine); 1923 qemu_register_machine(&ss600mp_machine); 1924 qemu_register_machine(&ss20_machine); 1925 qemu_register_machine(&voyager_machine); 1926 qemu_register_machine(&ss_lx_machine); 1927 qemu_register_machine(&ss4_machine); 1928 qemu_register_machine(&scls_machine); 1929 qemu_register_machine(&sbook_machine); 1930 qemu_register_machine(&ss1000_machine); 1931 qemu_register_machine(&ss2000_machine); 1932 qemu_register_machine(&ss2_machine); 1933 } 1934 1935 type_init(sun4m_register_types) 1936 machine_init(ss2_machine_init); 1937