1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/sysbus.h" 25 #include "qemu/timer.h" 26 #include "hw/sparc/sun4m.h" 27 #include "hw/timer/m48t59.h" 28 #include "hw/sparc/sparc32_dma.h" 29 #include "hw/block/fdc.h" 30 #include "sysemu/sysemu.h" 31 #include "net/net.h" 32 #include "hw/boards.h" 33 #include "hw/nvram/openbios_firmware_abi.h" 34 #include "hw/scsi/esp.h" 35 #include "hw/i386/pc.h" 36 #include "hw/isa/isa.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/char/escc.h" 39 #include "hw/empty_slot.h" 40 #include "hw/loader.h" 41 #include "elf.h" 42 #include "sysemu/blockdev.h" 43 #include "trace.h" 44 45 /* 46 * Sun4m architecture was used in the following machines: 47 * 48 * SPARCserver 6xxMP/xx 49 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 50 * SPARCclassic X (4/10) 51 * SPARCstation LX/ZX (4/30) 52 * SPARCstation Voyager 53 * SPARCstation 10/xx, SPARCserver 10/xx 54 * SPARCstation 5, SPARCserver 5 55 * SPARCstation 20/xx, SPARCserver 20 56 * SPARCstation 4 57 * 58 * See for example: http://www.sunhelp.org/faq/sunref1.html 59 */ 60 61 #define KERNEL_LOAD_ADDR 0x00004000 62 #define CMDLINE_ADDR 0x007ff000 63 #define INITRD_LOAD_ADDR 0x00800000 64 #define PROM_SIZE_MAX (1024 * 1024) 65 #define PROM_VADDR 0xffd00000 66 #define PROM_FILENAME "openbios-sparc32" 67 #define CFG_ADDR 0xd00000510ULL 68 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 69 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 70 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 71 72 #define MAX_CPUS 16 73 #define MAX_PILS 16 74 #define MAX_VSIMMS 4 75 76 #define ESCC_CLOCK 4915200 77 78 struct sun4m_hwdef { 79 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 80 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 81 hwaddr serial_base, fd_base; 82 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 83 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 84 hwaddr bpp_base, dbri_base, sx_base; 85 struct { 86 hwaddr reg_base, vram_base; 87 } vsimm[MAX_VSIMMS]; 88 hwaddr ecc_base; 89 uint64_t max_mem; 90 const char * const default_cpu_model; 91 uint32_t ecc_version; 92 uint32_t iommu_version; 93 uint16_t machine_id; 94 uint8_t nvram_machine_id; 95 }; 96 97 int DMA_get_channel_mode (int nchan) 98 { 99 return 0; 100 } 101 int DMA_read_memory (int nchan, void *buf, int pos, int size) 102 { 103 return 0; 104 } 105 int DMA_write_memory (int nchan, void *buf, int pos, int size) 106 { 107 return 0; 108 } 109 void DMA_hold_DREQ (int nchan) {} 110 void DMA_release_DREQ (int nchan) {} 111 void DMA_schedule(int nchan) {} 112 113 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) 114 { 115 } 116 117 void DMA_register_channel (int nchan, 118 DMA_transfer_handler transfer_handler, 119 void *opaque) 120 { 121 } 122 123 static int fw_cfg_boot_set(void *opaque, const char *boot_device) 124 { 125 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 126 return 0; 127 } 128 129 static void nvram_init(M48t59State *nvram, uint8_t *macaddr, 130 const char *cmdline, const char *boot_devices, 131 ram_addr_t RAM_size, uint32_t kernel_size, 132 int width, int height, int depth, 133 int nvram_machine_id, const char *arch) 134 { 135 unsigned int i; 136 uint32_t start, end; 137 uint8_t image[0x1ff0]; 138 struct OpenBIOS_nvpart_v1 *part_header; 139 140 memset(image, '\0', sizeof(image)); 141 142 start = 0; 143 144 // OpenBIOS nvram variables 145 // Variable partition 146 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 147 part_header->signature = OPENBIOS_PART_SYSTEM; 148 pstrcpy(part_header->name, sizeof(part_header->name), "system"); 149 150 end = start + sizeof(struct OpenBIOS_nvpart_v1); 151 for (i = 0; i < nb_prom_envs; i++) 152 end = OpenBIOS_set_var(image, end, prom_envs[i]); 153 154 // End marker 155 image[end++] = '\0'; 156 157 end = start + ((end - start + 15) & ~15); 158 OpenBIOS_finish_partition(part_header, end - start); 159 160 // free partition 161 start = end; 162 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 163 part_header->signature = OPENBIOS_PART_FREE; 164 pstrcpy(part_header->name, sizeof(part_header->name), "free"); 165 166 end = 0x1fd0; 167 OpenBIOS_finish_partition(part_header, end - start); 168 169 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 170 nvram_machine_id); 171 172 for (i = 0; i < sizeof(image); i++) 173 m48t59_write(nvram, i, image[i]); 174 } 175 176 static DeviceState *slavio_intctl; 177 178 void sun4m_pic_info(Monitor *mon, const QDict *qdict) 179 { 180 if (slavio_intctl) 181 slavio_pic_info(mon, slavio_intctl); 182 } 183 184 void sun4m_irq_info(Monitor *mon, const QDict *qdict) 185 { 186 if (slavio_intctl) 187 slavio_irq_info(mon, slavio_intctl); 188 } 189 190 void cpu_check_irqs(CPUSPARCState *env) 191 { 192 CPUState *cs; 193 194 if (env->pil_in && (env->interrupt_index == 0 || 195 (env->interrupt_index & ~15) == TT_EXTINT)) { 196 unsigned int i; 197 198 for (i = 15; i > 0; i--) { 199 if (env->pil_in & (1 << i)) { 200 int old_interrupt = env->interrupt_index; 201 202 env->interrupt_index = TT_EXTINT | i; 203 if (old_interrupt != env->interrupt_index) { 204 cs = CPU(sparc_env_get_cpu(env)); 205 trace_sun4m_cpu_interrupt(i); 206 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 207 } 208 break; 209 } 210 } 211 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 212 cs = CPU(sparc_env_get_cpu(env)); 213 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 214 env->interrupt_index = 0; 215 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 216 } 217 } 218 219 static void cpu_kick_irq(SPARCCPU *cpu) 220 { 221 CPUSPARCState *env = &cpu->env; 222 CPUState *cs = CPU(cpu); 223 224 cs->halted = 0; 225 cpu_check_irqs(env); 226 qemu_cpu_kick(cs); 227 } 228 229 static void cpu_set_irq(void *opaque, int irq, int level) 230 { 231 SPARCCPU *cpu = opaque; 232 CPUSPARCState *env = &cpu->env; 233 234 if (level) { 235 trace_sun4m_cpu_set_irq_raise(irq); 236 env->pil_in |= 1 << irq; 237 cpu_kick_irq(cpu); 238 } else { 239 trace_sun4m_cpu_set_irq_lower(irq); 240 env->pil_in &= ~(1 << irq); 241 cpu_check_irqs(env); 242 } 243 } 244 245 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 246 { 247 } 248 249 static void main_cpu_reset(void *opaque) 250 { 251 SPARCCPU *cpu = opaque; 252 CPUState *cs = CPU(cpu); 253 254 cpu_reset(cs); 255 cs->halted = 0; 256 } 257 258 static void secondary_cpu_reset(void *opaque) 259 { 260 SPARCCPU *cpu = opaque; 261 CPUState *cs = CPU(cpu); 262 263 cpu_reset(cs); 264 cs->halted = 1; 265 } 266 267 static void cpu_halt_signal(void *opaque, int irq, int level) 268 { 269 if (level && current_cpu) { 270 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 271 } 272 } 273 274 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 275 { 276 return addr - 0xf0000000ULL; 277 } 278 279 static unsigned long sun4m_load_kernel(const char *kernel_filename, 280 const char *initrd_filename, 281 ram_addr_t RAM_size) 282 { 283 int linux_boot; 284 unsigned int i; 285 long initrd_size, kernel_size; 286 uint8_t *ptr; 287 288 linux_boot = (kernel_filename != NULL); 289 290 kernel_size = 0; 291 if (linux_boot) { 292 int bswap_needed; 293 294 #ifdef BSWAP_NEEDED 295 bswap_needed = 1; 296 #else 297 bswap_needed = 0; 298 #endif 299 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 300 NULL, NULL, NULL, 1, ELF_MACHINE, 0); 301 if (kernel_size < 0) 302 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 303 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 304 TARGET_PAGE_SIZE); 305 if (kernel_size < 0) 306 kernel_size = load_image_targphys(kernel_filename, 307 KERNEL_LOAD_ADDR, 308 RAM_size - KERNEL_LOAD_ADDR); 309 if (kernel_size < 0) { 310 fprintf(stderr, "qemu: could not load kernel '%s'\n", 311 kernel_filename); 312 exit(1); 313 } 314 315 /* load initrd */ 316 initrd_size = 0; 317 if (initrd_filename) { 318 initrd_size = load_image_targphys(initrd_filename, 319 INITRD_LOAD_ADDR, 320 RAM_size - INITRD_LOAD_ADDR); 321 if (initrd_size < 0) { 322 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 323 initrd_filename); 324 exit(1); 325 } 326 } 327 if (initrd_size > 0) { 328 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 329 ptr = rom_ptr(KERNEL_LOAD_ADDR + i); 330 if (ldl_p(ptr) == 0x48647253) { // HdrS 331 stl_p(ptr + 16, INITRD_LOAD_ADDR); 332 stl_p(ptr + 20, initrd_size); 333 break; 334 } 335 } 336 } 337 } 338 return kernel_size; 339 } 340 341 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 342 { 343 DeviceState *dev; 344 SysBusDevice *s; 345 346 dev = qdev_create(NULL, "iommu"); 347 qdev_prop_set_uint32(dev, "version", version); 348 qdev_init_nofail(dev); 349 s = SYS_BUS_DEVICE(dev); 350 sysbus_connect_irq(s, 0, irq); 351 sysbus_mmio_map(s, 0, addr); 352 353 return s; 354 } 355 356 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq, 357 void *iommu, qemu_irq *dev_irq, int is_ledma) 358 { 359 DeviceState *dev; 360 SysBusDevice *s; 361 362 dev = qdev_create(NULL, "sparc32_dma"); 363 qdev_prop_set_ptr(dev, "iommu_opaque", iommu); 364 qdev_prop_set_uint32(dev, "is_ledma", is_ledma); 365 qdev_init_nofail(dev); 366 s = SYS_BUS_DEVICE(dev); 367 sysbus_connect_irq(s, 0, parent_irq); 368 *dev_irq = qdev_get_gpio_in(dev, 0); 369 sysbus_mmio_map(s, 0, daddr); 370 371 return s; 372 } 373 374 static void lance_init(NICInfo *nd, hwaddr leaddr, 375 void *dma_opaque, qemu_irq irq) 376 { 377 DeviceState *dev; 378 SysBusDevice *s; 379 qemu_irq reset; 380 381 qemu_check_nic_model(&nd_table[0], "lance"); 382 383 dev = qdev_create(NULL, "lance"); 384 qdev_set_nic_properties(dev, nd); 385 qdev_prop_set_ptr(dev, "dma", dma_opaque); 386 qdev_init_nofail(dev); 387 s = SYS_BUS_DEVICE(dev); 388 sysbus_mmio_map(s, 0, leaddr); 389 sysbus_connect_irq(s, 0, irq); 390 reset = qdev_get_gpio_in(dev, 0); 391 qdev_connect_gpio_out(dma_opaque, 0, reset); 392 } 393 394 static DeviceState *slavio_intctl_init(hwaddr addr, 395 hwaddr addrg, 396 qemu_irq **parent_irq) 397 { 398 DeviceState *dev; 399 SysBusDevice *s; 400 unsigned int i, j; 401 402 dev = qdev_create(NULL, "slavio_intctl"); 403 qdev_init_nofail(dev); 404 405 s = SYS_BUS_DEVICE(dev); 406 407 for (i = 0; i < MAX_CPUS; i++) { 408 for (j = 0; j < MAX_PILS; j++) { 409 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 410 } 411 } 412 sysbus_mmio_map(s, 0, addrg); 413 for (i = 0; i < MAX_CPUS; i++) { 414 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 415 } 416 417 return dev; 418 } 419 420 #define SYS_TIMER_OFFSET 0x10000ULL 421 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 422 423 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 424 qemu_irq *cpu_irqs, unsigned int num_cpus) 425 { 426 DeviceState *dev; 427 SysBusDevice *s; 428 unsigned int i; 429 430 dev = qdev_create(NULL, "slavio_timer"); 431 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 432 qdev_init_nofail(dev); 433 s = SYS_BUS_DEVICE(dev); 434 sysbus_connect_irq(s, 0, master_irq); 435 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 436 437 for (i = 0; i < MAX_CPUS; i++) { 438 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 439 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 440 } 441 } 442 443 static qemu_irq slavio_system_powerdown; 444 445 static void slavio_powerdown_req(Notifier *n, void *opaque) 446 { 447 qemu_irq_raise(slavio_system_powerdown); 448 } 449 450 static Notifier slavio_system_powerdown_notifier = { 451 .notify = slavio_powerdown_req 452 }; 453 454 #define MISC_LEDS 0x01600000 455 #define MISC_CFG 0x01800000 456 #define MISC_DIAG 0x01a00000 457 #define MISC_MDM 0x01b00000 458 #define MISC_SYS 0x01f00000 459 460 static void slavio_misc_init(hwaddr base, 461 hwaddr aux1_base, 462 hwaddr aux2_base, qemu_irq irq, 463 qemu_irq fdc_tc) 464 { 465 DeviceState *dev; 466 SysBusDevice *s; 467 468 dev = qdev_create(NULL, "slavio_misc"); 469 qdev_init_nofail(dev); 470 s = SYS_BUS_DEVICE(dev); 471 if (base) { 472 /* 8 bit registers */ 473 /* Slavio control */ 474 sysbus_mmio_map(s, 0, base + MISC_CFG); 475 /* Diagnostics */ 476 sysbus_mmio_map(s, 1, base + MISC_DIAG); 477 /* Modem control */ 478 sysbus_mmio_map(s, 2, base + MISC_MDM); 479 /* 16 bit registers */ 480 /* ss600mp diag LEDs */ 481 sysbus_mmio_map(s, 3, base + MISC_LEDS); 482 /* 32 bit registers */ 483 /* System control */ 484 sysbus_mmio_map(s, 4, base + MISC_SYS); 485 } 486 if (aux1_base) { 487 /* AUX 1 (Misc System Functions) */ 488 sysbus_mmio_map(s, 5, aux1_base); 489 } 490 if (aux2_base) { 491 /* AUX 2 (Software Powerdown Control) */ 492 sysbus_mmio_map(s, 6, aux2_base); 493 } 494 sysbus_connect_irq(s, 0, irq); 495 sysbus_connect_irq(s, 1, fdc_tc); 496 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 497 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 498 } 499 500 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 501 { 502 DeviceState *dev; 503 SysBusDevice *s; 504 505 dev = qdev_create(NULL, "eccmemctl"); 506 qdev_prop_set_uint32(dev, "version", version); 507 qdev_init_nofail(dev); 508 s = SYS_BUS_DEVICE(dev); 509 sysbus_connect_irq(s, 0, irq); 510 sysbus_mmio_map(s, 0, base); 511 if (version == 0) { // SS-600MP only 512 sysbus_mmio_map(s, 1, base + 0x1000); 513 } 514 } 515 516 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 517 { 518 DeviceState *dev; 519 SysBusDevice *s; 520 521 dev = qdev_create(NULL, "apc"); 522 qdev_init_nofail(dev); 523 s = SYS_BUS_DEVICE(dev); 524 /* Power management (APC) XXX: not a Slavio device */ 525 sysbus_mmio_map(s, 0, power_base); 526 sysbus_connect_irq(s, 0, cpu_halt); 527 } 528 529 static void tcx_init(hwaddr addr, int vram_size, int width, 530 int height, int depth) 531 { 532 DeviceState *dev; 533 SysBusDevice *s; 534 535 dev = qdev_create(NULL, "SUNW,tcx"); 536 qdev_prop_set_uint32(dev, "vram_size", vram_size); 537 qdev_prop_set_uint16(dev, "width", width); 538 qdev_prop_set_uint16(dev, "height", height); 539 qdev_prop_set_uint16(dev, "depth", depth); 540 qdev_init_nofail(dev); 541 s = SYS_BUS_DEVICE(dev); 542 /* 8-bit plane */ 543 sysbus_mmio_map(s, 0, addr + 0x00800000ULL); 544 /* DAC */ 545 sysbus_mmio_map(s, 1, addr + 0x00200000ULL); 546 /* TEC (dummy) */ 547 sysbus_mmio_map(s, 2, addr + 0x00700000ULL); 548 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */ 549 sysbus_mmio_map(s, 3, addr + 0x00301000ULL); 550 if (depth == 24) { 551 /* 24-bit plane */ 552 sysbus_mmio_map(s, 4, addr + 0x02000000ULL); 553 /* Control plane */ 554 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL); 555 } else { 556 /* THC 8 bit (dummy) */ 557 sysbus_mmio_map(s, 4, addr + 0x00300000ULL); 558 } 559 } 560 561 /* NCR89C100/MACIO Internal ID register */ 562 563 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 564 565 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 566 567 static void idreg_init(hwaddr addr) 568 { 569 DeviceState *dev; 570 SysBusDevice *s; 571 572 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER); 573 qdev_init_nofail(dev); 574 s = SYS_BUS_DEVICE(dev); 575 576 sysbus_mmio_map(s, 0, addr); 577 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data)); 578 } 579 580 #define MACIO_ID_REGISTER(obj) \ 581 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER) 582 583 typedef struct IDRegState { 584 SysBusDevice parent_obj; 585 586 MemoryRegion mem; 587 } IDRegState; 588 589 static int idreg_init1(SysBusDevice *dev) 590 { 591 IDRegState *s = MACIO_ID_REGISTER(dev); 592 593 memory_region_init_ram(&s->mem, OBJECT(s), 594 "sun4m.idreg", sizeof(idreg_data)); 595 vmstate_register_ram_global(&s->mem); 596 memory_region_set_readonly(&s->mem, true); 597 sysbus_init_mmio(dev, &s->mem); 598 return 0; 599 } 600 601 static void idreg_class_init(ObjectClass *klass, void *data) 602 { 603 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 604 605 k->init = idreg_init1; 606 } 607 608 static const TypeInfo idreg_info = { 609 .name = TYPE_MACIO_ID_REGISTER, 610 .parent = TYPE_SYS_BUS_DEVICE, 611 .instance_size = sizeof(IDRegState), 612 .class_init = idreg_class_init, 613 }; 614 615 #define TYPE_TCX_AFX "tcx_afx" 616 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX) 617 618 typedef struct AFXState { 619 SysBusDevice parent_obj; 620 621 MemoryRegion mem; 622 } AFXState; 623 624 /* SS-5 TCX AFX register */ 625 static void afx_init(hwaddr addr) 626 { 627 DeviceState *dev; 628 SysBusDevice *s; 629 630 dev = qdev_create(NULL, TYPE_TCX_AFX); 631 qdev_init_nofail(dev); 632 s = SYS_BUS_DEVICE(dev); 633 634 sysbus_mmio_map(s, 0, addr); 635 } 636 637 static int afx_init1(SysBusDevice *dev) 638 { 639 AFXState *s = TCX_AFX(dev); 640 641 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4); 642 vmstate_register_ram_global(&s->mem); 643 sysbus_init_mmio(dev, &s->mem); 644 return 0; 645 } 646 647 static void afx_class_init(ObjectClass *klass, void *data) 648 { 649 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 650 651 k->init = afx_init1; 652 } 653 654 static const TypeInfo afx_info = { 655 .name = TYPE_TCX_AFX, 656 .parent = TYPE_SYS_BUS_DEVICE, 657 .instance_size = sizeof(AFXState), 658 .class_init = afx_class_init, 659 }; 660 661 #define TYPE_OPENPROM "openprom" 662 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 663 664 typedef struct PROMState { 665 SysBusDevice parent_obj; 666 667 MemoryRegion prom; 668 } PROMState; 669 670 /* Boot PROM (OpenBIOS) */ 671 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 672 { 673 hwaddr *base_addr = (hwaddr *)opaque; 674 return addr + *base_addr - PROM_VADDR; 675 } 676 677 static void prom_init(hwaddr addr, const char *bios_name) 678 { 679 DeviceState *dev; 680 SysBusDevice *s; 681 char *filename; 682 int ret; 683 684 dev = qdev_create(NULL, TYPE_OPENPROM); 685 qdev_init_nofail(dev); 686 s = SYS_BUS_DEVICE(dev); 687 688 sysbus_mmio_map(s, 0, addr); 689 690 /* load boot prom */ 691 if (bios_name == NULL) { 692 bios_name = PROM_FILENAME; 693 } 694 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 695 if (filename) { 696 ret = load_elf(filename, translate_prom_address, &addr, NULL, 697 NULL, NULL, 1, ELF_MACHINE, 0); 698 if (ret < 0 || ret > PROM_SIZE_MAX) { 699 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 700 } 701 g_free(filename); 702 } else { 703 ret = -1; 704 } 705 if (ret < 0 || ret > PROM_SIZE_MAX) { 706 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 707 exit(1); 708 } 709 } 710 711 static int prom_init1(SysBusDevice *dev) 712 { 713 PROMState *s = OPENPROM(dev); 714 715 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX); 716 vmstate_register_ram_global(&s->prom); 717 memory_region_set_readonly(&s->prom, true); 718 sysbus_init_mmio(dev, &s->prom); 719 return 0; 720 } 721 722 static Property prom_properties[] = { 723 {/* end of property list */}, 724 }; 725 726 static void prom_class_init(ObjectClass *klass, void *data) 727 { 728 DeviceClass *dc = DEVICE_CLASS(klass); 729 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 730 731 k->init = prom_init1; 732 dc->props = prom_properties; 733 } 734 735 static const TypeInfo prom_info = { 736 .name = TYPE_OPENPROM, 737 .parent = TYPE_SYS_BUS_DEVICE, 738 .instance_size = sizeof(PROMState), 739 .class_init = prom_class_init, 740 }; 741 742 #define TYPE_SUN4M_MEMORY "memory" 743 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY) 744 745 typedef struct RamDevice { 746 SysBusDevice parent_obj; 747 748 MemoryRegion ram; 749 uint64_t size; 750 } RamDevice; 751 752 /* System RAM */ 753 static int ram_init1(SysBusDevice *dev) 754 { 755 RamDevice *d = SUN4M_RAM(dev); 756 757 memory_region_init_ram(&d->ram, OBJECT(d), "sun4m.ram", d->size); 758 vmstate_register_ram_global(&d->ram); 759 sysbus_init_mmio(dev, &d->ram); 760 return 0; 761 } 762 763 static void ram_init(hwaddr addr, ram_addr_t RAM_size, 764 uint64_t max_mem) 765 { 766 DeviceState *dev; 767 SysBusDevice *s; 768 RamDevice *d; 769 770 /* allocate RAM */ 771 if ((uint64_t)RAM_size > max_mem) { 772 fprintf(stderr, 773 "qemu: Too much memory for this machine: %d, maximum %d\n", 774 (unsigned int)(RAM_size / (1024 * 1024)), 775 (unsigned int)(max_mem / (1024 * 1024))); 776 exit(1); 777 } 778 dev = qdev_create(NULL, "memory"); 779 s = SYS_BUS_DEVICE(dev); 780 781 d = SUN4M_RAM(dev); 782 d->size = RAM_size; 783 qdev_init_nofail(dev); 784 785 sysbus_mmio_map(s, 0, addr); 786 } 787 788 static Property ram_properties[] = { 789 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 790 DEFINE_PROP_END_OF_LIST(), 791 }; 792 793 static void ram_class_init(ObjectClass *klass, void *data) 794 { 795 DeviceClass *dc = DEVICE_CLASS(klass); 796 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 797 798 k->init = ram_init1; 799 dc->props = ram_properties; 800 } 801 802 static const TypeInfo ram_info = { 803 .name = TYPE_SUN4M_MEMORY, 804 .parent = TYPE_SYS_BUS_DEVICE, 805 .instance_size = sizeof(RamDevice), 806 .class_init = ram_class_init, 807 }; 808 809 static void cpu_devinit(const char *cpu_model, unsigned int id, 810 uint64_t prom_addr, qemu_irq **cpu_irqs) 811 { 812 CPUState *cs; 813 SPARCCPU *cpu; 814 CPUSPARCState *env; 815 816 cpu = cpu_sparc_init(cpu_model); 817 if (cpu == NULL) { 818 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); 819 exit(1); 820 } 821 env = &cpu->env; 822 823 cpu_sparc_set_id(env, id); 824 if (id == 0) { 825 qemu_register_reset(main_cpu_reset, cpu); 826 } else { 827 qemu_register_reset(secondary_cpu_reset, cpu); 828 cs = CPU(cpu); 829 cs->halted = 1; 830 } 831 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 832 env->prom_addr = prom_addr; 833 } 834 835 static void dummy_fdc_tc(void *opaque, int irq, int level) 836 { 837 } 838 839 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, 840 QEMUMachineInitArgs *args) 841 { 842 const char *cpu_model = args->cpu_model; 843 unsigned int i; 844 void *iommu, *espdma, *ledma, *nvram; 845 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS], 846 espdma_irq, ledma_irq; 847 qemu_irq esp_reset, dma_enable; 848 qemu_irq fdc_tc; 849 qemu_irq *cpu_halt; 850 unsigned long kernel_size; 851 DriveInfo *fd[MAX_FD]; 852 FWCfgState *fw_cfg; 853 unsigned int num_vsimms; 854 855 /* init CPUs */ 856 if (!cpu_model) 857 cpu_model = hwdef->default_cpu_model; 858 859 for(i = 0; i < smp_cpus; i++) { 860 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); 861 } 862 863 for (i = smp_cpus; i < MAX_CPUS; i++) 864 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 865 866 867 /* set up devices */ 868 ram_init(0, args->ram_size, hwdef->max_mem); 869 /* models without ECC don't trap when missing ram is accessed */ 870 if (!hwdef->ecc_base) { 871 empty_slot_init(args->ram_size, hwdef->max_mem - args->ram_size); 872 } 873 874 prom_init(hwdef->slavio_base, bios_name); 875 876 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 877 hwdef->intctl_base + 0x10000ULL, 878 cpu_irqs); 879 880 for (i = 0; i < 32; i++) { 881 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 882 } 883 for (i = 0; i < MAX_CPUS; i++) { 884 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 885 } 886 887 if (hwdef->idreg_base) { 888 idreg_init(hwdef->idreg_base); 889 } 890 891 if (hwdef->afx_base) { 892 afx_init(hwdef->afx_base); 893 } 894 895 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, 896 slavio_irq[30]); 897 898 if (hwdef->iommu_pad_base) { 899 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 900 Software shouldn't use aliased addresses, neither should it crash 901 when does. Using empty_slot instead of aliasing can help with 902 debugging such accesses */ 903 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); 904 } 905 906 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18], 907 iommu, &espdma_irq, 0); 908 909 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, 910 slavio_irq[16], iommu, &ledma_irq, 1); 911 912 if (graphic_depth != 8 && graphic_depth != 24) { 913 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); 914 exit (1); 915 } 916 num_vsimms = 0; 917 if (num_vsimms == 0) { 918 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height, 919 graphic_depth); 920 } 921 922 for (i = num_vsimms; i < MAX_VSIMMS; i++) { 923 /* vsimm registers probed by OBP */ 924 if (hwdef->vsimm[i].reg_base) { 925 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); 926 } 927 } 928 929 if (hwdef->sx_base) { 930 empty_slot_init(hwdef->sx_base, 0x2000); 931 } 932 933 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq); 934 935 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8); 936 937 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 938 939 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14], 940 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1); 941 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 942 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 943 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], 944 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); 945 946 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); 947 if (hwdef->apc_base) { 948 apc_init(hwdef->apc_base, cpu_halt[0]); 949 } 950 951 if (hwdef->fd_base) { 952 /* there is zero or one floppy drive */ 953 memset(fd, 0, sizeof(fd)); 954 fd[0] = drive_get(IF_FLOPPY, 0, 0); 955 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 956 &fdc_tc); 957 } else { 958 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1); 959 } 960 961 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 962 slavio_irq[30], fdc_tc); 963 964 if (drive_get_max_bus(IF_SCSI) > 0) { 965 fprintf(stderr, "qemu: too many SCSI bus\n"); 966 exit(1); 967 } 968 969 esp_init(hwdef->esp_base, 2, 970 espdma_memory_read, espdma_memory_write, 971 espdma, espdma_irq, &esp_reset, &dma_enable); 972 973 qdev_connect_gpio_out(espdma, 0, esp_reset); 974 qdev_connect_gpio_out(espdma, 1, dma_enable); 975 976 if (hwdef->cs_base) { 977 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, 978 slavio_irq[5]); 979 } 980 981 if (hwdef->dbri_base) { 982 /* ISDN chip with attached CS4215 audio codec */ 983 /* prom space */ 984 empty_slot_init(hwdef->dbri_base+0x1000, 0x30); 985 /* reg space */ 986 empty_slot_init(hwdef->dbri_base+0x10000, 0x100); 987 } 988 989 if (hwdef->bpp_base) { 990 /* parallel port */ 991 empty_slot_init(hwdef->bpp_base, 0x20); 992 } 993 994 kernel_size = sun4m_load_kernel(args->kernel_filename, 995 args->initrd_filename, 996 args->ram_size); 997 998 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, args->kernel_cmdline, 999 args->boot_order, args->ram_size, kernel_size, graphic_width, 1000 graphic_height, graphic_depth, hwdef->nvram_machine_id, 1001 "Sun4m"); 1002 1003 if (hwdef->ecc_base) 1004 ecc_init(hwdef->ecc_base, slavio_irq[28], 1005 hwdef->ecc_version); 1006 1007 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); 1008 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1009 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 1010 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1011 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1012 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1013 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1014 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1015 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1016 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1017 if (args->kernel_cmdline) { 1018 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1019 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1020 args->kernel_cmdline); 1021 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, args->kernel_cmdline); 1022 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1023 strlen(args->kernel_cmdline) + 1); 1024 } else { 1025 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1026 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1027 } 1028 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1029 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used 1030 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, args->boot_order[0]); 1031 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1032 } 1033 1034 enum { 1035 ss5_id = 32, 1036 vger_id, 1037 lx_id, 1038 ss4_id, 1039 scls_id, 1040 sbook_id, 1041 ss10_id = 64, 1042 ss20_id, 1043 ss600mp_id, 1044 }; 1045 1046 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1047 /* SS-5 */ 1048 { 1049 .iommu_base = 0x10000000, 1050 .iommu_pad_base = 0x10004000, 1051 .iommu_pad_len = 0x0fffb000, 1052 .tcx_base = 0x50000000, 1053 .cs_base = 0x6c000000, 1054 .slavio_base = 0x70000000, 1055 .ms_kb_base = 0x71000000, 1056 .serial_base = 0x71100000, 1057 .nvram_base = 0x71200000, 1058 .fd_base = 0x71400000, 1059 .counter_base = 0x71d00000, 1060 .intctl_base = 0x71e00000, 1061 .idreg_base = 0x78000000, 1062 .dma_base = 0x78400000, 1063 .esp_base = 0x78800000, 1064 .le_base = 0x78c00000, 1065 .apc_base = 0x6a000000, 1066 .afx_base = 0x6e000000, 1067 .aux1_base = 0x71900000, 1068 .aux2_base = 0x71910000, 1069 .nvram_machine_id = 0x80, 1070 .machine_id = ss5_id, 1071 .iommu_version = 0x05000000, 1072 .max_mem = 0x10000000, 1073 .default_cpu_model = "Fujitsu MB86904", 1074 }, 1075 /* SS-10 */ 1076 { 1077 .iommu_base = 0xfe0000000ULL, 1078 .tcx_base = 0xe20000000ULL, 1079 .slavio_base = 0xff0000000ULL, 1080 .ms_kb_base = 0xff1000000ULL, 1081 .serial_base = 0xff1100000ULL, 1082 .nvram_base = 0xff1200000ULL, 1083 .fd_base = 0xff1700000ULL, 1084 .counter_base = 0xff1300000ULL, 1085 .intctl_base = 0xff1400000ULL, 1086 .idreg_base = 0xef0000000ULL, 1087 .dma_base = 0xef0400000ULL, 1088 .esp_base = 0xef0800000ULL, 1089 .le_base = 0xef0c00000ULL, 1090 .apc_base = 0xefa000000ULL, // XXX should not exist 1091 .aux1_base = 0xff1800000ULL, 1092 .aux2_base = 0xff1a01000ULL, 1093 .ecc_base = 0xf00000000ULL, 1094 .ecc_version = 0x10000000, // version 0, implementation 1 1095 .nvram_machine_id = 0x72, 1096 .machine_id = ss10_id, 1097 .iommu_version = 0x03000000, 1098 .max_mem = 0xf00000000ULL, 1099 .default_cpu_model = "TI SuperSparc II", 1100 }, 1101 /* SS-600MP */ 1102 { 1103 .iommu_base = 0xfe0000000ULL, 1104 .tcx_base = 0xe20000000ULL, 1105 .slavio_base = 0xff0000000ULL, 1106 .ms_kb_base = 0xff1000000ULL, 1107 .serial_base = 0xff1100000ULL, 1108 .nvram_base = 0xff1200000ULL, 1109 .counter_base = 0xff1300000ULL, 1110 .intctl_base = 0xff1400000ULL, 1111 .dma_base = 0xef0081000ULL, 1112 .esp_base = 0xef0080000ULL, 1113 .le_base = 0xef0060000ULL, 1114 .apc_base = 0xefa000000ULL, // XXX should not exist 1115 .aux1_base = 0xff1800000ULL, 1116 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1117 .ecc_base = 0xf00000000ULL, 1118 .ecc_version = 0x00000000, // version 0, implementation 0 1119 .nvram_machine_id = 0x71, 1120 .machine_id = ss600mp_id, 1121 .iommu_version = 0x01000000, 1122 .max_mem = 0xf00000000ULL, 1123 .default_cpu_model = "TI SuperSparc II", 1124 }, 1125 /* SS-20 */ 1126 { 1127 .iommu_base = 0xfe0000000ULL, 1128 .tcx_base = 0xe20000000ULL, 1129 .slavio_base = 0xff0000000ULL, 1130 .ms_kb_base = 0xff1000000ULL, 1131 .serial_base = 0xff1100000ULL, 1132 .nvram_base = 0xff1200000ULL, 1133 .fd_base = 0xff1700000ULL, 1134 .counter_base = 0xff1300000ULL, 1135 .intctl_base = 0xff1400000ULL, 1136 .idreg_base = 0xef0000000ULL, 1137 .dma_base = 0xef0400000ULL, 1138 .esp_base = 0xef0800000ULL, 1139 .le_base = 0xef0c00000ULL, 1140 .bpp_base = 0xef4800000ULL, 1141 .apc_base = 0xefa000000ULL, // XXX should not exist 1142 .aux1_base = 0xff1800000ULL, 1143 .aux2_base = 0xff1a01000ULL, 1144 .dbri_base = 0xee0000000ULL, 1145 .sx_base = 0xf80000000ULL, 1146 .vsimm = { 1147 { 1148 .reg_base = 0x9c000000ULL, 1149 .vram_base = 0xfc000000ULL 1150 }, { 1151 .reg_base = 0x90000000ULL, 1152 .vram_base = 0xf0000000ULL 1153 }, { 1154 .reg_base = 0x94000000ULL 1155 }, { 1156 .reg_base = 0x98000000ULL 1157 } 1158 }, 1159 .ecc_base = 0xf00000000ULL, 1160 .ecc_version = 0x20000000, // version 0, implementation 2 1161 .nvram_machine_id = 0x72, 1162 .machine_id = ss20_id, 1163 .iommu_version = 0x13000000, 1164 .max_mem = 0xf00000000ULL, 1165 .default_cpu_model = "TI SuperSparc II", 1166 }, 1167 /* Voyager */ 1168 { 1169 .iommu_base = 0x10000000, 1170 .tcx_base = 0x50000000, 1171 .slavio_base = 0x70000000, 1172 .ms_kb_base = 0x71000000, 1173 .serial_base = 0x71100000, 1174 .nvram_base = 0x71200000, 1175 .fd_base = 0x71400000, 1176 .counter_base = 0x71d00000, 1177 .intctl_base = 0x71e00000, 1178 .idreg_base = 0x78000000, 1179 .dma_base = 0x78400000, 1180 .esp_base = 0x78800000, 1181 .le_base = 0x78c00000, 1182 .apc_base = 0x71300000, // pmc 1183 .aux1_base = 0x71900000, 1184 .aux2_base = 0x71910000, 1185 .nvram_machine_id = 0x80, 1186 .machine_id = vger_id, 1187 .iommu_version = 0x05000000, 1188 .max_mem = 0x10000000, 1189 .default_cpu_model = "Fujitsu MB86904", 1190 }, 1191 /* LX */ 1192 { 1193 .iommu_base = 0x10000000, 1194 .iommu_pad_base = 0x10004000, 1195 .iommu_pad_len = 0x0fffb000, 1196 .tcx_base = 0x50000000, 1197 .slavio_base = 0x70000000, 1198 .ms_kb_base = 0x71000000, 1199 .serial_base = 0x71100000, 1200 .nvram_base = 0x71200000, 1201 .fd_base = 0x71400000, 1202 .counter_base = 0x71d00000, 1203 .intctl_base = 0x71e00000, 1204 .idreg_base = 0x78000000, 1205 .dma_base = 0x78400000, 1206 .esp_base = 0x78800000, 1207 .le_base = 0x78c00000, 1208 .aux1_base = 0x71900000, 1209 .aux2_base = 0x71910000, 1210 .nvram_machine_id = 0x80, 1211 .machine_id = lx_id, 1212 .iommu_version = 0x04000000, 1213 .max_mem = 0x10000000, 1214 .default_cpu_model = "TI MicroSparc I", 1215 }, 1216 /* SS-4 */ 1217 { 1218 .iommu_base = 0x10000000, 1219 .tcx_base = 0x50000000, 1220 .cs_base = 0x6c000000, 1221 .slavio_base = 0x70000000, 1222 .ms_kb_base = 0x71000000, 1223 .serial_base = 0x71100000, 1224 .nvram_base = 0x71200000, 1225 .fd_base = 0x71400000, 1226 .counter_base = 0x71d00000, 1227 .intctl_base = 0x71e00000, 1228 .idreg_base = 0x78000000, 1229 .dma_base = 0x78400000, 1230 .esp_base = 0x78800000, 1231 .le_base = 0x78c00000, 1232 .apc_base = 0x6a000000, 1233 .aux1_base = 0x71900000, 1234 .aux2_base = 0x71910000, 1235 .nvram_machine_id = 0x80, 1236 .machine_id = ss4_id, 1237 .iommu_version = 0x05000000, 1238 .max_mem = 0x10000000, 1239 .default_cpu_model = "Fujitsu MB86904", 1240 }, 1241 /* SPARCClassic */ 1242 { 1243 .iommu_base = 0x10000000, 1244 .tcx_base = 0x50000000, 1245 .slavio_base = 0x70000000, 1246 .ms_kb_base = 0x71000000, 1247 .serial_base = 0x71100000, 1248 .nvram_base = 0x71200000, 1249 .fd_base = 0x71400000, 1250 .counter_base = 0x71d00000, 1251 .intctl_base = 0x71e00000, 1252 .idreg_base = 0x78000000, 1253 .dma_base = 0x78400000, 1254 .esp_base = 0x78800000, 1255 .le_base = 0x78c00000, 1256 .apc_base = 0x6a000000, 1257 .aux1_base = 0x71900000, 1258 .aux2_base = 0x71910000, 1259 .nvram_machine_id = 0x80, 1260 .machine_id = scls_id, 1261 .iommu_version = 0x05000000, 1262 .max_mem = 0x10000000, 1263 .default_cpu_model = "TI MicroSparc I", 1264 }, 1265 /* SPARCbook */ 1266 { 1267 .iommu_base = 0x10000000, 1268 .tcx_base = 0x50000000, // XXX 1269 .slavio_base = 0x70000000, 1270 .ms_kb_base = 0x71000000, 1271 .serial_base = 0x71100000, 1272 .nvram_base = 0x71200000, 1273 .fd_base = 0x71400000, 1274 .counter_base = 0x71d00000, 1275 .intctl_base = 0x71e00000, 1276 .idreg_base = 0x78000000, 1277 .dma_base = 0x78400000, 1278 .esp_base = 0x78800000, 1279 .le_base = 0x78c00000, 1280 .apc_base = 0x6a000000, 1281 .aux1_base = 0x71900000, 1282 .aux2_base = 0x71910000, 1283 .nvram_machine_id = 0x80, 1284 .machine_id = sbook_id, 1285 .iommu_version = 0x05000000, 1286 .max_mem = 0x10000000, 1287 .default_cpu_model = "TI MicroSparc I", 1288 }, 1289 }; 1290 1291 /* SPARCstation 5 hardware initialisation */ 1292 static void ss5_init(QEMUMachineInitArgs *args) 1293 { 1294 sun4m_hw_init(&sun4m_hwdefs[0], args); 1295 } 1296 1297 /* SPARCstation 10 hardware initialisation */ 1298 static void ss10_init(QEMUMachineInitArgs *args) 1299 { 1300 sun4m_hw_init(&sun4m_hwdefs[1], args); 1301 } 1302 1303 /* SPARCserver 600MP hardware initialisation */ 1304 static void ss600mp_init(QEMUMachineInitArgs *args) 1305 { 1306 sun4m_hw_init(&sun4m_hwdefs[2], args); 1307 } 1308 1309 /* SPARCstation 20 hardware initialisation */ 1310 static void ss20_init(QEMUMachineInitArgs *args) 1311 { 1312 sun4m_hw_init(&sun4m_hwdefs[3], args); 1313 } 1314 1315 /* SPARCstation Voyager hardware initialisation */ 1316 static void vger_init(QEMUMachineInitArgs *args) 1317 { 1318 sun4m_hw_init(&sun4m_hwdefs[4], args); 1319 } 1320 1321 /* SPARCstation LX hardware initialisation */ 1322 static void ss_lx_init(QEMUMachineInitArgs *args) 1323 { 1324 sun4m_hw_init(&sun4m_hwdefs[5], args); 1325 } 1326 1327 /* SPARCstation 4 hardware initialisation */ 1328 static void ss4_init(QEMUMachineInitArgs *args) 1329 { 1330 sun4m_hw_init(&sun4m_hwdefs[6], args); 1331 } 1332 1333 /* SPARCClassic hardware initialisation */ 1334 static void scls_init(QEMUMachineInitArgs *args) 1335 { 1336 sun4m_hw_init(&sun4m_hwdefs[7], args); 1337 } 1338 1339 /* SPARCbook hardware initialisation */ 1340 static void sbook_init(QEMUMachineInitArgs *args) 1341 { 1342 sun4m_hw_init(&sun4m_hwdefs[8], args); 1343 } 1344 1345 static QEMUMachine ss5_machine = { 1346 .name = "SS-5", 1347 .desc = "Sun4m platform, SPARCstation 5", 1348 .init = ss5_init, 1349 .block_default_type = IF_SCSI, 1350 .is_default = 1, 1351 .default_boot_order = "c", 1352 }; 1353 1354 static QEMUMachine ss10_machine = { 1355 .name = "SS-10", 1356 .desc = "Sun4m platform, SPARCstation 10", 1357 .init = ss10_init, 1358 .block_default_type = IF_SCSI, 1359 .max_cpus = 4, 1360 .default_boot_order = "c", 1361 }; 1362 1363 static QEMUMachine ss600mp_machine = { 1364 .name = "SS-600MP", 1365 .desc = "Sun4m platform, SPARCserver 600MP", 1366 .init = ss600mp_init, 1367 .block_default_type = IF_SCSI, 1368 .max_cpus = 4, 1369 .default_boot_order = "c", 1370 }; 1371 1372 static QEMUMachine ss20_machine = { 1373 .name = "SS-20", 1374 .desc = "Sun4m platform, SPARCstation 20", 1375 .init = ss20_init, 1376 .block_default_type = IF_SCSI, 1377 .max_cpus = 4, 1378 .default_boot_order = "c", 1379 }; 1380 1381 static QEMUMachine voyager_machine = { 1382 .name = "Voyager", 1383 .desc = "Sun4m platform, SPARCstation Voyager", 1384 .init = vger_init, 1385 .block_default_type = IF_SCSI, 1386 .default_boot_order = "c", 1387 }; 1388 1389 static QEMUMachine ss_lx_machine = { 1390 .name = "LX", 1391 .desc = "Sun4m platform, SPARCstation LX", 1392 .init = ss_lx_init, 1393 .block_default_type = IF_SCSI, 1394 .default_boot_order = "c", 1395 }; 1396 1397 static QEMUMachine ss4_machine = { 1398 .name = "SS-4", 1399 .desc = "Sun4m platform, SPARCstation 4", 1400 .init = ss4_init, 1401 .block_default_type = IF_SCSI, 1402 .default_boot_order = "c", 1403 }; 1404 1405 static QEMUMachine scls_machine = { 1406 .name = "SPARCClassic", 1407 .desc = "Sun4m platform, SPARCClassic", 1408 .init = scls_init, 1409 .block_default_type = IF_SCSI, 1410 .default_boot_order = "c", 1411 }; 1412 1413 static QEMUMachine sbook_machine = { 1414 .name = "SPARCbook", 1415 .desc = "Sun4m platform, SPARCbook", 1416 .init = sbook_init, 1417 .block_default_type = IF_SCSI, 1418 .default_boot_order = "c", 1419 }; 1420 1421 static void sun4m_register_types(void) 1422 { 1423 type_register_static(&idreg_info); 1424 type_register_static(&afx_info); 1425 type_register_static(&prom_info); 1426 type_register_static(&ram_info); 1427 } 1428 1429 static void sun4m_machine_init(void) 1430 { 1431 qemu_register_machine(&ss5_machine); 1432 qemu_register_machine(&ss10_machine); 1433 qemu_register_machine(&ss600mp_machine); 1434 qemu_register_machine(&ss20_machine); 1435 qemu_register_machine(&voyager_machine); 1436 qemu_register_machine(&ss_lx_machine); 1437 qemu_register_machine(&ss4_machine); 1438 qemu_register_machine(&scls_machine); 1439 qemu_register_machine(&sbook_machine); 1440 } 1441 1442 type_init(sun4m_register_types) 1443 machine_init(sun4m_machine_init); 1444