1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/sysbus.h" 29 #include "qemu/error-report.h" 30 #include "qemu/timer.h" 31 #include "hw/sparc/sun4m.h" 32 #include "hw/timer/m48t59.h" 33 #include "hw/sparc/sparc32_dma.h" 34 #include "hw/block/fdc.h" 35 #include "sysemu/sysemu.h" 36 #include "net/net.h" 37 #include "hw/boards.h" 38 #include "hw/scsi/esp.h" 39 #include "hw/i386/pc.h" 40 #include "hw/isa/isa.h" 41 #include "hw/nvram/sun_nvram.h" 42 #include "hw/nvram/chrp_nvram.h" 43 #include "hw/nvram/fw_cfg.h" 44 #include "hw/char/escc.h" 45 #include "hw/empty_slot.h" 46 #include "hw/loader.h" 47 #include "elf.h" 48 #include "sysemu/block-backend.h" 49 #include "trace.h" 50 #include "qemu/cutils.h" 51 52 /* 53 * Sun4m architecture was used in the following machines: 54 * 55 * SPARCserver 6xxMP/xx 56 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 57 * SPARCclassic X (4/10) 58 * SPARCstation LX/ZX (4/30) 59 * SPARCstation Voyager 60 * SPARCstation 10/xx, SPARCserver 10/xx 61 * SPARCstation 5, SPARCserver 5 62 * SPARCstation 20/xx, SPARCserver 20 63 * SPARCstation 4 64 * 65 * See for example: http://www.sunhelp.org/faq/sunref1.html 66 */ 67 68 #define KERNEL_LOAD_ADDR 0x00004000 69 #define CMDLINE_ADDR 0x007ff000 70 #define INITRD_LOAD_ADDR 0x00800000 71 #define PROM_SIZE_MAX (1024 * 1024) 72 #define PROM_VADDR 0xffd00000 73 #define PROM_FILENAME "openbios-sparc32" 74 #define CFG_ADDR 0xd00000510ULL 75 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 76 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 77 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 78 79 #define MAX_CPUS 16 80 #define MAX_PILS 16 81 #define MAX_VSIMMS 4 82 83 #define ESCC_CLOCK 4915200 84 85 struct sun4m_hwdef { 86 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 87 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 88 hwaddr serial_base, fd_base; 89 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 90 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 91 hwaddr bpp_base, dbri_base, sx_base; 92 struct { 93 hwaddr reg_base, vram_base; 94 } vsimm[MAX_VSIMMS]; 95 hwaddr ecc_base; 96 uint64_t max_mem; 97 uint32_t ecc_version; 98 uint32_t iommu_version; 99 uint16_t machine_id; 100 uint8_t nvram_machine_id; 101 }; 102 103 void DMA_init(ISABus *bus, int high_page_enable) 104 { 105 } 106 107 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 108 Error **errp) 109 { 110 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 111 } 112 113 static void nvram_init(Nvram *nvram, uint8_t *macaddr, 114 const char *cmdline, const char *boot_devices, 115 ram_addr_t RAM_size, uint32_t kernel_size, 116 int width, int height, int depth, 117 int nvram_machine_id, const char *arch) 118 { 119 unsigned int i; 120 int sysp_end; 121 uint8_t image[0x1ff0]; 122 NvramClass *k = NVRAM_GET_CLASS(nvram); 123 124 memset(image, '\0', sizeof(image)); 125 126 /* OpenBIOS nvram variables partition */ 127 sysp_end = chrp_nvram_create_system_partition(image, 0); 128 129 /* Free space partition */ 130 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 131 132 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 133 nvram_machine_id); 134 135 for (i = 0; i < sizeof(image); i++) { 136 (k->write)(nvram, i, image[i]); 137 } 138 } 139 140 void cpu_check_irqs(CPUSPARCState *env) 141 { 142 CPUState *cs; 143 144 /* We should be holding the BQL before we mess with IRQs */ 145 g_assert(qemu_mutex_iothread_locked()); 146 147 if (env->pil_in && (env->interrupt_index == 0 || 148 (env->interrupt_index & ~15) == TT_EXTINT)) { 149 unsigned int i; 150 151 for (i = 15; i > 0; i--) { 152 if (env->pil_in & (1 << i)) { 153 int old_interrupt = env->interrupt_index; 154 155 env->interrupt_index = TT_EXTINT | i; 156 if (old_interrupt != env->interrupt_index) { 157 cs = CPU(sparc_env_get_cpu(env)); 158 trace_sun4m_cpu_interrupt(i); 159 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 160 } 161 break; 162 } 163 } 164 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 165 cs = CPU(sparc_env_get_cpu(env)); 166 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 167 env->interrupt_index = 0; 168 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 169 } 170 } 171 172 static void cpu_kick_irq(SPARCCPU *cpu) 173 { 174 CPUSPARCState *env = &cpu->env; 175 CPUState *cs = CPU(cpu); 176 177 cs->halted = 0; 178 cpu_check_irqs(env); 179 qemu_cpu_kick(cs); 180 } 181 182 static void cpu_set_irq(void *opaque, int irq, int level) 183 { 184 SPARCCPU *cpu = opaque; 185 CPUSPARCState *env = &cpu->env; 186 187 if (level) { 188 trace_sun4m_cpu_set_irq_raise(irq); 189 env->pil_in |= 1 << irq; 190 cpu_kick_irq(cpu); 191 } else { 192 trace_sun4m_cpu_set_irq_lower(irq); 193 env->pil_in &= ~(1 << irq); 194 cpu_check_irqs(env); 195 } 196 } 197 198 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 199 { 200 } 201 202 static void main_cpu_reset(void *opaque) 203 { 204 SPARCCPU *cpu = opaque; 205 CPUState *cs = CPU(cpu); 206 207 cpu_reset(cs); 208 cs->halted = 0; 209 } 210 211 static void secondary_cpu_reset(void *opaque) 212 { 213 SPARCCPU *cpu = opaque; 214 CPUState *cs = CPU(cpu); 215 216 cpu_reset(cs); 217 cs->halted = 1; 218 } 219 220 static void cpu_halt_signal(void *opaque, int irq, int level) 221 { 222 if (level && current_cpu) { 223 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 224 } 225 } 226 227 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 228 { 229 return addr - 0xf0000000ULL; 230 } 231 232 static unsigned long sun4m_load_kernel(const char *kernel_filename, 233 const char *initrd_filename, 234 ram_addr_t RAM_size) 235 { 236 int linux_boot; 237 unsigned int i; 238 long initrd_size, kernel_size; 239 uint8_t *ptr; 240 241 linux_boot = (kernel_filename != NULL); 242 243 kernel_size = 0; 244 if (linux_boot) { 245 int bswap_needed; 246 247 #ifdef BSWAP_NEEDED 248 bswap_needed = 1; 249 #else 250 bswap_needed = 0; 251 #endif 252 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 253 NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 254 if (kernel_size < 0) 255 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 256 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 257 TARGET_PAGE_SIZE); 258 if (kernel_size < 0) 259 kernel_size = load_image_targphys(kernel_filename, 260 KERNEL_LOAD_ADDR, 261 RAM_size - KERNEL_LOAD_ADDR); 262 if (kernel_size < 0) { 263 fprintf(stderr, "qemu: could not load kernel '%s'\n", 264 kernel_filename); 265 exit(1); 266 } 267 268 /* load initrd */ 269 initrd_size = 0; 270 if (initrd_filename) { 271 initrd_size = load_image_targphys(initrd_filename, 272 INITRD_LOAD_ADDR, 273 RAM_size - INITRD_LOAD_ADDR); 274 if (initrd_size < 0) { 275 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 276 initrd_filename); 277 exit(1); 278 } 279 } 280 if (initrd_size > 0) { 281 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 282 ptr = rom_ptr(KERNEL_LOAD_ADDR + i); 283 if (ldl_p(ptr) == 0x48647253) { // HdrS 284 stl_p(ptr + 16, INITRD_LOAD_ADDR); 285 stl_p(ptr + 20, initrd_size); 286 break; 287 } 288 } 289 } 290 } 291 return kernel_size; 292 } 293 294 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 295 { 296 DeviceState *dev; 297 SysBusDevice *s; 298 299 dev = qdev_create(NULL, "iommu"); 300 qdev_prop_set_uint32(dev, "version", version); 301 qdev_init_nofail(dev); 302 s = SYS_BUS_DEVICE(dev); 303 sysbus_connect_irq(s, 0, irq); 304 sysbus_mmio_map(s, 0, addr); 305 306 return s; 307 } 308 309 static void *sparc32_dma_init(hwaddr daddr, void *iommu, int is_ledma) 310 { 311 DeviceState *dev; 312 SysBusDevice *s; 313 314 dev = qdev_create(NULL, is_ledma ? "sparc32-ledma" : "sparc32-espdma"); 315 qdev_prop_set_ptr(dev, "iommu_opaque", iommu); 316 qdev_init_nofail(dev); 317 s = SYS_BUS_DEVICE(dev); 318 sysbus_mmio_map(s, 0, daddr); 319 320 return s; 321 } 322 323 static void lance_init(NICInfo *nd, hwaddr leaddr, 324 void *dma_opaque, qemu_irq irq) 325 { 326 DeviceState *dev; 327 SysBusDevice *s; 328 qemu_irq reset; 329 330 qemu_check_nic_model(&nd_table[0], "lance"); 331 332 dev = qdev_create(NULL, "lance"); 333 qdev_set_nic_properties(dev, nd); 334 qdev_prop_set_ptr(dev, "dma", dma_opaque); 335 qdev_init_nofail(dev); 336 s = SYS_BUS_DEVICE(dev); 337 sysbus_mmio_map(s, 0, leaddr); 338 sysbus_connect_irq(s, 0, irq); 339 reset = qdev_get_gpio_in(dev, 0); 340 qdev_connect_gpio_out(dma_opaque, 0, reset); 341 } 342 343 static DeviceState *slavio_intctl_init(hwaddr addr, 344 hwaddr addrg, 345 qemu_irq **parent_irq) 346 { 347 DeviceState *dev; 348 SysBusDevice *s; 349 unsigned int i, j; 350 351 dev = qdev_create(NULL, "slavio_intctl"); 352 qdev_init_nofail(dev); 353 354 s = SYS_BUS_DEVICE(dev); 355 356 for (i = 0; i < MAX_CPUS; i++) { 357 for (j = 0; j < MAX_PILS; j++) { 358 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 359 } 360 } 361 sysbus_mmio_map(s, 0, addrg); 362 for (i = 0; i < MAX_CPUS; i++) { 363 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 364 } 365 366 return dev; 367 } 368 369 #define SYS_TIMER_OFFSET 0x10000ULL 370 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 371 372 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 373 qemu_irq *cpu_irqs, unsigned int num_cpus) 374 { 375 DeviceState *dev; 376 SysBusDevice *s; 377 unsigned int i; 378 379 dev = qdev_create(NULL, "slavio_timer"); 380 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 381 qdev_init_nofail(dev); 382 s = SYS_BUS_DEVICE(dev); 383 sysbus_connect_irq(s, 0, master_irq); 384 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 385 386 for (i = 0; i < MAX_CPUS; i++) { 387 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 388 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 389 } 390 } 391 392 static qemu_irq slavio_system_powerdown; 393 394 static void slavio_powerdown_req(Notifier *n, void *opaque) 395 { 396 qemu_irq_raise(slavio_system_powerdown); 397 } 398 399 static Notifier slavio_system_powerdown_notifier = { 400 .notify = slavio_powerdown_req 401 }; 402 403 #define MISC_LEDS 0x01600000 404 #define MISC_CFG 0x01800000 405 #define MISC_DIAG 0x01a00000 406 #define MISC_MDM 0x01b00000 407 #define MISC_SYS 0x01f00000 408 409 static void slavio_misc_init(hwaddr base, 410 hwaddr aux1_base, 411 hwaddr aux2_base, qemu_irq irq, 412 qemu_irq fdc_tc) 413 { 414 DeviceState *dev; 415 SysBusDevice *s; 416 417 dev = qdev_create(NULL, "slavio_misc"); 418 qdev_init_nofail(dev); 419 s = SYS_BUS_DEVICE(dev); 420 if (base) { 421 /* 8 bit registers */ 422 /* Slavio control */ 423 sysbus_mmio_map(s, 0, base + MISC_CFG); 424 /* Diagnostics */ 425 sysbus_mmio_map(s, 1, base + MISC_DIAG); 426 /* Modem control */ 427 sysbus_mmio_map(s, 2, base + MISC_MDM); 428 /* 16 bit registers */ 429 /* ss600mp diag LEDs */ 430 sysbus_mmio_map(s, 3, base + MISC_LEDS); 431 /* 32 bit registers */ 432 /* System control */ 433 sysbus_mmio_map(s, 4, base + MISC_SYS); 434 } 435 if (aux1_base) { 436 /* AUX 1 (Misc System Functions) */ 437 sysbus_mmio_map(s, 5, aux1_base); 438 } 439 if (aux2_base) { 440 /* AUX 2 (Software Powerdown Control) */ 441 sysbus_mmio_map(s, 6, aux2_base); 442 } 443 sysbus_connect_irq(s, 0, irq); 444 sysbus_connect_irq(s, 1, fdc_tc); 445 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 446 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 447 } 448 449 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 450 { 451 DeviceState *dev; 452 SysBusDevice *s; 453 454 dev = qdev_create(NULL, "eccmemctl"); 455 qdev_prop_set_uint32(dev, "version", version); 456 qdev_init_nofail(dev); 457 s = SYS_BUS_DEVICE(dev); 458 sysbus_connect_irq(s, 0, irq); 459 sysbus_mmio_map(s, 0, base); 460 if (version == 0) { // SS-600MP only 461 sysbus_mmio_map(s, 1, base + 0x1000); 462 } 463 } 464 465 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 466 { 467 DeviceState *dev; 468 SysBusDevice *s; 469 470 dev = qdev_create(NULL, "apc"); 471 qdev_init_nofail(dev); 472 s = SYS_BUS_DEVICE(dev); 473 /* Power management (APC) XXX: not a Slavio device */ 474 sysbus_mmio_map(s, 0, power_base); 475 sysbus_connect_irq(s, 0, cpu_halt); 476 } 477 478 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 479 int height, int depth) 480 { 481 DeviceState *dev; 482 SysBusDevice *s; 483 484 dev = qdev_create(NULL, "SUNW,tcx"); 485 qdev_prop_set_uint32(dev, "vram_size", vram_size); 486 qdev_prop_set_uint16(dev, "width", width); 487 qdev_prop_set_uint16(dev, "height", height); 488 qdev_prop_set_uint16(dev, "depth", depth); 489 qdev_init_nofail(dev); 490 s = SYS_BUS_DEVICE(dev); 491 492 /* 10/ROM : FCode ROM */ 493 sysbus_mmio_map(s, 0, addr); 494 /* 2/STIP : Stipple */ 495 sysbus_mmio_map(s, 1, addr + 0x04000000ULL); 496 /* 3/BLIT : Blitter */ 497 sysbus_mmio_map(s, 2, addr + 0x06000000ULL); 498 /* 5/RSTIP : Raw Stipple */ 499 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); 500 /* 6/RBLIT : Raw Blitter */ 501 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); 502 /* 7/TEC : Transform Engine */ 503 sysbus_mmio_map(s, 5, addr + 0x00700000ULL); 504 /* 8/CMAP : DAC */ 505 sysbus_mmio_map(s, 6, addr + 0x00200000ULL); 506 /* 9/THC : */ 507 if (depth == 8) { 508 sysbus_mmio_map(s, 7, addr + 0x00300000ULL); 509 } else { 510 sysbus_mmio_map(s, 7, addr + 0x00301000ULL); 511 } 512 /* 11/DHC : */ 513 sysbus_mmio_map(s, 8, addr + 0x00240000ULL); 514 /* 12/ALT : */ 515 sysbus_mmio_map(s, 9, addr + 0x00280000ULL); 516 /* 0/DFB8 : 8-bit plane */ 517 sysbus_mmio_map(s, 10, addr + 0x00800000ULL); 518 /* 1/DFB24 : 24bit plane */ 519 sysbus_mmio_map(s, 11, addr + 0x02000000ULL); 520 /* 4/RDFB32: Raw framebuffer. Control plane */ 521 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); 522 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 523 if (depth == 8) { 524 sysbus_mmio_map(s, 13, addr + 0x00301000ULL); 525 } 526 527 sysbus_connect_irq(s, 0, irq); 528 } 529 530 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 531 int height, int depth) 532 { 533 DeviceState *dev; 534 SysBusDevice *s; 535 536 dev = qdev_create(NULL, "cgthree"); 537 qdev_prop_set_uint32(dev, "vram-size", vram_size); 538 qdev_prop_set_uint16(dev, "width", width); 539 qdev_prop_set_uint16(dev, "height", height); 540 qdev_prop_set_uint16(dev, "depth", depth); 541 qdev_init_nofail(dev); 542 s = SYS_BUS_DEVICE(dev); 543 544 /* FCode ROM */ 545 sysbus_mmio_map(s, 0, addr); 546 /* DAC */ 547 sysbus_mmio_map(s, 1, addr + 0x400000ULL); 548 /* 8-bit plane */ 549 sysbus_mmio_map(s, 2, addr + 0x800000ULL); 550 551 sysbus_connect_irq(s, 0, irq); 552 } 553 554 /* NCR89C100/MACIO Internal ID register */ 555 556 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 557 558 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 559 560 static void idreg_init(hwaddr addr) 561 { 562 DeviceState *dev; 563 SysBusDevice *s; 564 565 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER); 566 qdev_init_nofail(dev); 567 s = SYS_BUS_DEVICE(dev); 568 569 sysbus_mmio_map(s, 0, addr); 570 cpu_physical_memory_write_rom(&address_space_memory, 571 addr, idreg_data, sizeof(idreg_data)); 572 } 573 574 #define MACIO_ID_REGISTER(obj) \ 575 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER) 576 577 typedef struct IDRegState { 578 SysBusDevice parent_obj; 579 580 MemoryRegion mem; 581 } IDRegState; 582 583 static void idreg_init1(Object *obj) 584 { 585 IDRegState *s = MACIO_ID_REGISTER(obj); 586 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 587 588 memory_region_init_ram_nomigrate(&s->mem, obj, 589 "sun4m.idreg", sizeof(idreg_data), &error_fatal); 590 vmstate_register_ram_global(&s->mem); 591 memory_region_set_readonly(&s->mem, true); 592 sysbus_init_mmio(dev, &s->mem); 593 } 594 595 static const TypeInfo idreg_info = { 596 .name = TYPE_MACIO_ID_REGISTER, 597 .parent = TYPE_SYS_BUS_DEVICE, 598 .instance_size = sizeof(IDRegState), 599 .instance_init = idreg_init1, 600 }; 601 602 #define TYPE_TCX_AFX "tcx_afx" 603 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX) 604 605 typedef struct AFXState { 606 SysBusDevice parent_obj; 607 608 MemoryRegion mem; 609 } AFXState; 610 611 /* SS-5 TCX AFX register */ 612 static void afx_init(hwaddr addr) 613 { 614 DeviceState *dev; 615 SysBusDevice *s; 616 617 dev = qdev_create(NULL, TYPE_TCX_AFX); 618 qdev_init_nofail(dev); 619 s = SYS_BUS_DEVICE(dev); 620 621 sysbus_mmio_map(s, 0, addr); 622 } 623 624 static void afx_init1(Object *obj) 625 { 626 AFXState *s = TCX_AFX(obj); 627 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 628 629 memory_region_init_ram_nomigrate(&s->mem, obj, "sun4m.afx", 4, &error_fatal); 630 vmstate_register_ram_global(&s->mem); 631 sysbus_init_mmio(dev, &s->mem); 632 } 633 634 static const TypeInfo afx_info = { 635 .name = TYPE_TCX_AFX, 636 .parent = TYPE_SYS_BUS_DEVICE, 637 .instance_size = sizeof(AFXState), 638 .instance_init = afx_init1, 639 }; 640 641 #define TYPE_OPENPROM "openprom" 642 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 643 644 typedef struct PROMState { 645 SysBusDevice parent_obj; 646 647 MemoryRegion prom; 648 } PROMState; 649 650 /* Boot PROM (OpenBIOS) */ 651 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 652 { 653 hwaddr *base_addr = (hwaddr *)opaque; 654 return addr + *base_addr - PROM_VADDR; 655 } 656 657 static void prom_init(hwaddr addr, const char *bios_name) 658 { 659 DeviceState *dev; 660 SysBusDevice *s; 661 char *filename; 662 int ret; 663 664 dev = qdev_create(NULL, TYPE_OPENPROM); 665 qdev_init_nofail(dev); 666 s = SYS_BUS_DEVICE(dev); 667 668 sysbus_mmio_map(s, 0, addr); 669 670 /* load boot prom */ 671 if (bios_name == NULL) { 672 bios_name = PROM_FILENAME; 673 } 674 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 675 if (filename) { 676 ret = load_elf(filename, translate_prom_address, &addr, NULL, 677 NULL, NULL, 1, EM_SPARC, 0, 0); 678 if (ret < 0 || ret > PROM_SIZE_MAX) { 679 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 680 } 681 g_free(filename); 682 } else { 683 ret = -1; 684 } 685 if (ret < 0 || ret > PROM_SIZE_MAX) { 686 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 687 exit(1); 688 } 689 } 690 691 static void prom_init1(Object *obj) 692 { 693 PROMState *s = OPENPROM(obj); 694 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 695 696 memory_region_init_ram_nomigrate(&s->prom, obj, "sun4m.prom", PROM_SIZE_MAX, 697 &error_fatal); 698 vmstate_register_ram_global(&s->prom); 699 memory_region_set_readonly(&s->prom, true); 700 sysbus_init_mmio(dev, &s->prom); 701 } 702 703 static Property prom_properties[] = { 704 {/* end of property list */}, 705 }; 706 707 static void prom_class_init(ObjectClass *klass, void *data) 708 { 709 DeviceClass *dc = DEVICE_CLASS(klass); 710 711 dc->props = prom_properties; 712 } 713 714 static const TypeInfo prom_info = { 715 .name = TYPE_OPENPROM, 716 .parent = TYPE_SYS_BUS_DEVICE, 717 .instance_size = sizeof(PROMState), 718 .class_init = prom_class_init, 719 .instance_init = prom_init1, 720 }; 721 722 #define TYPE_SUN4M_MEMORY "memory" 723 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY) 724 725 typedef struct RamDevice { 726 SysBusDevice parent_obj; 727 728 MemoryRegion ram; 729 uint64_t size; 730 } RamDevice; 731 732 /* System RAM */ 733 static void ram_realize(DeviceState *dev, Error **errp) 734 { 735 RamDevice *d = SUN4M_RAM(dev); 736 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 737 738 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram", 739 d->size); 740 sysbus_init_mmio(sbd, &d->ram); 741 } 742 743 static void ram_init(hwaddr addr, ram_addr_t RAM_size, 744 uint64_t max_mem) 745 { 746 DeviceState *dev; 747 SysBusDevice *s; 748 RamDevice *d; 749 750 /* allocate RAM */ 751 if ((uint64_t)RAM_size > max_mem) { 752 fprintf(stderr, 753 "qemu: Too much memory for this machine: %d, maximum %d\n", 754 (unsigned int)(RAM_size / (1024 * 1024)), 755 (unsigned int)(max_mem / (1024 * 1024))); 756 exit(1); 757 } 758 dev = qdev_create(NULL, "memory"); 759 s = SYS_BUS_DEVICE(dev); 760 761 d = SUN4M_RAM(dev); 762 d->size = RAM_size; 763 qdev_init_nofail(dev); 764 765 sysbus_mmio_map(s, 0, addr); 766 } 767 768 static Property ram_properties[] = { 769 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 770 DEFINE_PROP_END_OF_LIST(), 771 }; 772 773 static void ram_class_init(ObjectClass *klass, void *data) 774 { 775 DeviceClass *dc = DEVICE_CLASS(klass); 776 777 dc->realize = ram_realize; 778 dc->props = ram_properties; 779 } 780 781 static const TypeInfo ram_info = { 782 .name = TYPE_SUN4M_MEMORY, 783 .parent = TYPE_SYS_BUS_DEVICE, 784 .instance_size = sizeof(RamDevice), 785 .class_init = ram_class_init, 786 }; 787 788 static void cpu_devinit(const char *cpu_type, unsigned int id, 789 uint64_t prom_addr, qemu_irq **cpu_irqs) 790 { 791 CPUState *cs; 792 SPARCCPU *cpu; 793 CPUSPARCState *env; 794 795 cpu = SPARC_CPU(cpu_create(cpu_type)); 796 env = &cpu->env; 797 798 cpu_sparc_set_id(env, id); 799 if (id == 0) { 800 qemu_register_reset(main_cpu_reset, cpu); 801 } else { 802 qemu_register_reset(secondary_cpu_reset, cpu); 803 cs = CPU(cpu); 804 cs->halted = 1; 805 } 806 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 807 env->prom_addr = prom_addr; 808 } 809 810 static void dummy_fdc_tc(void *opaque, int irq, int level) 811 { 812 } 813 814 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, 815 MachineState *machine) 816 { 817 DeviceState *slavio_intctl; 818 unsigned int i; 819 void *iommu, *nvram; 820 DeviceState *espdma, *ledma; 821 SysBusDevice *sbd; 822 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; 823 qemu_irq esp_reset, dma_enable; 824 qemu_irq fdc_tc; 825 unsigned long kernel_size; 826 DriveInfo *fd[MAX_FD]; 827 FWCfgState *fw_cfg; 828 unsigned int num_vsimms; 829 830 /* init CPUs */ 831 for(i = 0; i < smp_cpus; i++) { 832 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); 833 } 834 835 for (i = smp_cpus; i < MAX_CPUS; i++) 836 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 837 838 839 /* set up devices */ 840 ram_init(0, machine->ram_size, hwdef->max_mem); 841 /* models without ECC don't trap when missing ram is accessed */ 842 if (!hwdef->ecc_base) { 843 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size); 844 } 845 846 prom_init(hwdef->slavio_base, bios_name); 847 848 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 849 hwdef->intctl_base + 0x10000ULL, 850 cpu_irqs); 851 852 for (i = 0; i < 32; i++) { 853 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 854 } 855 for (i = 0; i < MAX_CPUS; i++) { 856 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 857 } 858 859 if (hwdef->idreg_base) { 860 idreg_init(hwdef->idreg_base); 861 } 862 863 if (hwdef->afx_base) { 864 afx_init(hwdef->afx_base); 865 } 866 867 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, 868 slavio_irq[30]); 869 870 if (hwdef->iommu_pad_base) { 871 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 872 Software shouldn't use aliased addresses, neither should it crash 873 when does. Using empty_slot instead of aliasing can help with 874 debugging such accesses */ 875 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); 876 } 877 878 espdma = sparc32_dma_init(hwdef->dma_base, iommu, 0); 879 sbd = SYS_BUS_DEVICE(espdma); 880 sysbus_connect_irq(sbd, 0, slavio_irq[18]); 881 882 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, iommu, 1); 883 sbd = SYS_BUS_DEVICE(ledma); 884 sysbus_connect_irq(sbd, 0, slavio_irq[16]); 885 886 if (graphic_depth != 8 && graphic_depth != 24) { 887 error_report("Unsupported depth: %d", graphic_depth); 888 exit (1); 889 } 890 num_vsimms = 0; 891 if (num_vsimms == 0) { 892 if (vga_interface_type == VGA_CG3) { 893 if (graphic_depth != 8) { 894 error_report("Unsupported depth: %d", graphic_depth); 895 exit(1); 896 } 897 898 if (!(graphic_width == 1024 && graphic_height == 768) && 899 !(graphic_width == 1152 && graphic_height == 900)) { 900 error_report("Unsupported resolution: %d x %d", graphic_width, 901 graphic_height); 902 exit(1); 903 } 904 905 /* sbus irq 5 */ 906 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 907 graphic_width, graphic_height, graphic_depth); 908 } else { 909 /* If no display specified, default to TCX */ 910 if (graphic_depth != 8 && graphic_depth != 24) { 911 error_report("Unsupported depth: %d", graphic_depth); 912 exit(1); 913 } 914 915 if (!(graphic_width == 1024 && graphic_height == 768)) { 916 error_report("Unsupported resolution: %d x %d", 917 graphic_width, graphic_height); 918 exit(1); 919 } 920 921 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 922 graphic_width, graphic_height, graphic_depth); 923 } 924 } 925 926 for (i = num_vsimms; i < MAX_VSIMMS; i++) { 927 /* vsimm registers probed by OBP */ 928 if (hwdef->vsimm[i].reg_base) { 929 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); 930 } 931 } 932 933 if (hwdef->sx_base) { 934 empty_slot_init(hwdef->sx_base, 0x2000); 935 } 936 937 lance_init(&nd_table[0], hwdef->le_base, ledma, 938 qdev_get_gpio_in(ledma, 0)); 939 940 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8); 941 942 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 943 944 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14], 945 !machine->enable_graphics, ESCC_CLOCK, 1); 946 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 947 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 948 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], 949 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); 950 951 if (hwdef->apc_base) { 952 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); 953 } 954 955 if (hwdef->fd_base) { 956 /* there is zero or one floppy drive */ 957 memset(fd, 0, sizeof(fd)); 958 fd[0] = drive_get(IF_FLOPPY, 0, 0); 959 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 960 &fdc_tc); 961 } else { 962 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); 963 } 964 965 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 966 slavio_irq[30], fdc_tc); 967 968 esp_init(hwdef->esp_base, 2, 969 espdma_memory_read, espdma_memory_write, 970 espdma, 971 qdev_get_gpio_in(espdma, 0), 972 &esp_reset, &dma_enable); 973 974 qdev_connect_gpio_out(espdma, 0, esp_reset); 975 qdev_connect_gpio_out(espdma, 1, dma_enable); 976 977 if (hwdef->cs_base) { 978 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, 979 slavio_irq[5]); 980 } 981 982 if (hwdef->dbri_base) { 983 /* ISDN chip with attached CS4215 audio codec */ 984 /* prom space */ 985 empty_slot_init(hwdef->dbri_base+0x1000, 0x30); 986 /* reg space */ 987 empty_slot_init(hwdef->dbri_base+0x10000, 0x100); 988 } 989 990 if (hwdef->bpp_base) { 991 /* parallel port */ 992 empty_slot_init(hwdef->bpp_base, 0x20); 993 } 994 995 kernel_size = sun4m_load_kernel(machine->kernel_filename, 996 machine->initrd_filename, 997 machine->ram_size); 998 999 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline, 1000 machine->boot_order, machine->ram_size, kernel_size, 1001 graphic_width, graphic_height, graphic_depth, 1002 hwdef->nvram_machine_id, "Sun4m"); 1003 1004 if (hwdef->ecc_base) 1005 ecc_init(hwdef->ecc_base, slavio_irq[28], 1006 hwdef->ecc_version); 1007 1008 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 1009 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 1010 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1011 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1012 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1013 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1014 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1015 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1016 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1017 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1018 if (machine->kernel_cmdline) { 1019 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1020 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1021 machine->kernel_cmdline); 1022 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 1023 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1024 strlen(machine->kernel_cmdline) + 1); 1025 } else { 1026 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1027 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1028 } 1029 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1030 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used 1031 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 1032 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1033 } 1034 1035 enum { 1036 ss5_id = 32, 1037 vger_id, 1038 lx_id, 1039 ss4_id, 1040 scls_id, 1041 sbook_id, 1042 ss10_id = 64, 1043 ss20_id, 1044 ss600mp_id, 1045 }; 1046 1047 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1048 /* SS-5 */ 1049 { 1050 .iommu_base = 0x10000000, 1051 .iommu_pad_base = 0x10004000, 1052 .iommu_pad_len = 0x0fffb000, 1053 .tcx_base = 0x50000000, 1054 .cs_base = 0x6c000000, 1055 .slavio_base = 0x70000000, 1056 .ms_kb_base = 0x71000000, 1057 .serial_base = 0x71100000, 1058 .nvram_base = 0x71200000, 1059 .fd_base = 0x71400000, 1060 .counter_base = 0x71d00000, 1061 .intctl_base = 0x71e00000, 1062 .idreg_base = 0x78000000, 1063 .dma_base = 0x78400000, 1064 .esp_base = 0x78800000, 1065 .le_base = 0x78c00000, 1066 .apc_base = 0x6a000000, 1067 .afx_base = 0x6e000000, 1068 .aux1_base = 0x71900000, 1069 .aux2_base = 0x71910000, 1070 .nvram_machine_id = 0x80, 1071 .machine_id = ss5_id, 1072 .iommu_version = 0x05000000, 1073 .max_mem = 0x10000000, 1074 }, 1075 /* SS-10 */ 1076 { 1077 .iommu_base = 0xfe0000000ULL, 1078 .tcx_base = 0xe20000000ULL, 1079 .slavio_base = 0xff0000000ULL, 1080 .ms_kb_base = 0xff1000000ULL, 1081 .serial_base = 0xff1100000ULL, 1082 .nvram_base = 0xff1200000ULL, 1083 .fd_base = 0xff1700000ULL, 1084 .counter_base = 0xff1300000ULL, 1085 .intctl_base = 0xff1400000ULL, 1086 .idreg_base = 0xef0000000ULL, 1087 .dma_base = 0xef0400000ULL, 1088 .esp_base = 0xef0800000ULL, 1089 .le_base = 0xef0c00000ULL, 1090 .apc_base = 0xefa000000ULL, // XXX should not exist 1091 .aux1_base = 0xff1800000ULL, 1092 .aux2_base = 0xff1a01000ULL, 1093 .ecc_base = 0xf00000000ULL, 1094 .ecc_version = 0x10000000, // version 0, implementation 1 1095 .nvram_machine_id = 0x72, 1096 .machine_id = ss10_id, 1097 .iommu_version = 0x03000000, 1098 .max_mem = 0xf00000000ULL, 1099 }, 1100 /* SS-600MP */ 1101 { 1102 .iommu_base = 0xfe0000000ULL, 1103 .tcx_base = 0xe20000000ULL, 1104 .slavio_base = 0xff0000000ULL, 1105 .ms_kb_base = 0xff1000000ULL, 1106 .serial_base = 0xff1100000ULL, 1107 .nvram_base = 0xff1200000ULL, 1108 .counter_base = 0xff1300000ULL, 1109 .intctl_base = 0xff1400000ULL, 1110 .dma_base = 0xef0081000ULL, 1111 .esp_base = 0xef0080000ULL, 1112 .le_base = 0xef0060000ULL, 1113 .apc_base = 0xefa000000ULL, // XXX should not exist 1114 .aux1_base = 0xff1800000ULL, 1115 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1116 .ecc_base = 0xf00000000ULL, 1117 .ecc_version = 0x00000000, // version 0, implementation 0 1118 .nvram_machine_id = 0x71, 1119 .machine_id = ss600mp_id, 1120 .iommu_version = 0x01000000, 1121 .max_mem = 0xf00000000ULL, 1122 }, 1123 /* SS-20 */ 1124 { 1125 .iommu_base = 0xfe0000000ULL, 1126 .tcx_base = 0xe20000000ULL, 1127 .slavio_base = 0xff0000000ULL, 1128 .ms_kb_base = 0xff1000000ULL, 1129 .serial_base = 0xff1100000ULL, 1130 .nvram_base = 0xff1200000ULL, 1131 .fd_base = 0xff1700000ULL, 1132 .counter_base = 0xff1300000ULL, 1133 .intctl_base = 0xff1400000ULL, 1134 .idreg_base = 0xef0000000ULL, 1135 .dma_base = 0xef0400000ULL, 1136 .esp_base = 0xef0800000ULL, 1137 .le_base = 0xef0c00000ULL, 1138 .bpp_base = 0xef4800000ULL, 1139 .apc_base = 0xefa000000ULL, // XXX should not exist 1140 .aux1_base = 0xff1800000ULL, 1141 .aux2_base = 0xff1a01000ULL, 1142 .dbri_base = 0xee0000000ULL, 1143 .sx_base = 0xf80000000ULL, 1144 .vsimm = { 1145 { 1146 .reg_base = 0x9c000000ULL, 1147 .vram_base = 0xfc000000ULL 1148 }, { 1149 .reg_base = 0x90000000ULL, 1150 .vram_base = 0xf0000000ULL 1151 }, { 1152 .reg_base = 0x94000000ULL 1153 }, { 1154 .reg_base = 0x98000000ULL 1155 } 1156 }, 1157 .ecc_base = 0xf00000000ULL, 1158 .ecc_version = 0x20000000, // version 0, implementation 2 1159 .nvram_machine_id = 0x72, 1160 .machine_id = ss20_id, 1161 .iommu_version = 0x13000000, 1162 .max_mem = 0xf00000000ULL, 1163 }, 1164 /* Voyager */ 1165 { 1166 .iommu_base = 0x10000000, 1167 .tcx_base = 0x50000000, 1168 .slavio_base = 0x70000000, 1169 .ms_kb_base = 0x71000000, 1170 .serial_base = 0x71100000, 1171 .nvram_base = 0x71200000, 1172 .fd_base = 0x71400000, 1173 .counter_base = 0x71d00000, 1174 .intctl_base = 0x71e00000, 1175 .idreg_base = 0x78000000, 1176 .dma_base = 0x78400000, 1177 .esp_base = 0x78800000, 1178 .le_base = 0x78c00000, 1179 .apc_base = 0x71300000, // pmc 1180 .aux1_base = 0x71900000, 1181 .aux2_base = 0x71910000, 1182 .nvram_machine_id = 0x80, 1183 .machine_id = vger_id, 1184 .iommu_version = 0x05000000, 1185 .max_mem = 0x10000000, 1186 }, 1187 /* LX */ 1188 { 1189 .iommu_base = 0x10000000, 1190 .iommu_pad_base = 0x10004000, 1191 .iommu_pad_len = 0x0fffb000, 1192 .tcx_base = 0x50000000, 1193 .slavio_base = 0x70000000, 1194 .ms_kb_base = 0x71000000, 1195 .serial_base = 0x71100000, 1196 .nvram_base = 0x71200000, 1197 .fd_base = 0x71400000, 1198 .counter_base = 0x71d00000, 1199 .intctl_base = 0x71e00000, 1200 .idreg_base = 0x78000000, 1201 .dma_base = 0x78400000, 1202 .esp_base = 0x78800000, 1203 .le_base = 0x78c00000, 1204 .aux1_base = 0x71900000, 1205 .aux2_base = 0x71910000, 1206 .nvram_machine_id = 0x80, 1207 .machine_id = lx_id, 1208 .iommu_version = 0x04000000, 1209 .max_mem = 0x10000000, 1210 }, 1211 /* SS-4 */ 1212 { 1213 .iommu_base = 0x10000000, 1214 .tcx_base = 0x50000000, 1215 .cs_base = 0x6c000000, 1216 .slavio_base = 0x70000000, 1217 .ms_kb_base = 0x71000000, 1218 .serial_base = 0x71100000, 1219 .nvram_base = 0x71200000, 1220 .fd_base = 0x71400000, 1221 .counter_base = 0x71d00000, 1222 .intctl_base = 0x71e00000, 1223 .idreg_base = 0x78000000, 1224 .dma_base = 0x78400000, 1225 .esp_base = 0x78800000, 1226 .le_base = 0x78c00000, 1227 .apc_base = 0x6a000000, 1228 .aux1_base = 0x71900000, 1229 .aux2_base = 0x71910000, 1230 .nvram_machine_id = 0x80, 1231 .machine_id = ss4_id, 1232 .iommu_version = 0x05000000, 1233 .max_mem = 0x10000000, 1234 }, 1235 /* SPARCClassic */ 1236 { 1237 .iommu_base = 0x10000000, 1238 .tcx_base = 0x50000000, 1239 .slavio_base = 0x70000000, 1240 .ms_kb_base = 0x71000000, 1241 .serial_base = 0x71100000, 1242 .nvram_base = 0x71200000, 1243 .fd_base = 0x71400000, 1244 .counter_base = 0x71d00000, 1245 .intctl_base = 0x71e00000, 1246 .idreg_base = 0x78000000, 1247 .dma_base = 0x78400000, 1248 .esp_base = 0x78800000, 1249 .le_base = 0x78c00000, 1250 .apc_base = 0x6a000000, 1251 .aux1_base = 0x71900000, 1252 .aux2_base = 0x71910000, 1253 .nvram_machine_id = 0x80, 1254 .machine_id = scls_id, 1255 .iommu_version = 0x05000000, 1256 .max_mem = 0x10000000, 1257 }, 1258 /* SPARCbook */ 1259 { 1260 .iommu_base = 0x10000000, 1261 .tcx_base = 0x50000000, // XXX 1262 .slavio_base = 0x70000000, 1263 .ms_kb_base = 0x71000000, 1264 .serial_base = 0x71100000, 1265 .nvram_base = 0x71200000, 1266 .fd_base = 0x71400000, 1267 .counter_base = 0x71d00000, 1268 .intctl_base = 0x71e00000, 1269 .idreg_base = 0x78000000, 1270 .dma_base = 0x78400000, 1271 .esp_base = 0x78800000, 1272 .le_base = 0x78c00000, 1273 .apc_base = 0x6a000000, 1274 .aux1_base = 0x71900000, 1275 .aux2_base = 0x71910000, 1276 .nvram_machine_id = 0x80, 1277 .machine_id = sbook_id, 1278 .iommu_version = 0x05000000, 1279 .max_mem = 0x10000000, 1280 }, 1281 }; 1282 1283 /* SPARCstation 5 hardware initialisation */ 1284 static void ss5_init(MachineState *machine) 1285 { 1286 sun4m_hw_init(&sun4m_hwdefs[0], machine); 1287 } 1288 1289 /* SPARCstation 10 hardware initialisation */ 1290 static void ss10_init(MachineState *machine) 1291 { 1292 sun4m_hw_init(&sun4m_hwdefs[1], machine); 1293 } 1294 1295 /* SPARCserver 600MP hardware initialisation */ 1296 static void ss600mp_init(MachineState *machine) 1297 { 1298 sun4m_hw_init(&sun4m_hwdefs[2], machine); 1299 } 1300 1301 /* SPARCstation 20 hardware initialisation */ 1302 static void ss20_init(MachineState *machine) 1303 { 1304 sun4m_hw_init(&sun4m_hwdefs[3], machine); 1305 } 1306 1307 /* SPARCstation Voyager hardware initialisation */ 1308 static void vger_init(MachineState *machine) 1309 { 1310 sun4m_hw_init(&sun4m_hwdefs[4], machine); 1311 } 1312 1313 /* SPARCstation LX hardware initialisation */ 1314 static void ss_lx_init(MachineState *machine) 1315 { 1316 sun4m_hw_init(&sun4m_hwdefs[5], machine); 1317 } 1318 1319 /* SPARCstation 4 hardware initialisation */ 1320 static void ss4_init(MachineState *machine) 1321 { 1322 sun4m_hw_init(&sun4m_hwdefs[6], machine); 1323 } 1324 1325 /* SPARCClassic hardware initialisation */ 1326 static void scls_init(MachineState *machine) 1327 { 1328 sun4m_hw_init(&sun4m_hwdefs[7], machine); 1329 } 1330 1331 /* SPARCbook hardware initialisation */ 1332 static void sbook_init(MachineState *machine) 1333 { 1334 sun4m_hw_init(&sun4m_hwdefs[8], machine); 1335 } 1336 1337 static void ss5_class_init(ObjectClass *oc, void *data) 1338 { 1339 MachineClass *mc = MACHINE_CLASS(oc); 1340 1341 mc->desc = "Sun4m platform, SPARCstation 5"; 1342 mc->init = ss5_init; 1343 mc->block_default_type = IF_SCSI; 1344 mc->is_default = 1; 1345 mc->default_boot_order = "c"; 1346 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1347 } 1348 1349 static const TypeInfo ss5_type = { 1350 .name = MACHINE_TYPE_NAME("SS-5"), 1351 .parent = TYPE_MACHINE, 1352 .class_init = ss5_class_init, 1353 }; 1354 1355 static void ss10_class_init(ObjectClass *oc, void *data) 1356 { 1357 MachineClass *mc = MACHINE_CLASS(oc); 1358 1359 mc->desc = "Sun4m platform, SPARCstation 10"; 1360 mc->init = ss10_init; 1361 mc->block_default_type = IF_SCSI; 1362 mc->max_cpus = 4; 1363 mc->default_boot_order = "c"; 1364 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1365 } 1366 1367 static const TypeInfo ss10_type = { 1368 .name = MACHINE_TYPE_NAME("SS-10"), 1369 .parent = TYPE_MACHINE, 1370 .class_init = ss10_class_init, 1371 }; 1372 1373 static void ss600mp_class_init(ObjectClass *oc, void *data) 1374 { 1375 MachineClass *mc = MACHINE_CLASS(oc); 1376 1377 mc->desc = "Sun4m platform, SPARCserver 600MP"; 1378 mc->init = ss600mp_init; 1379 mc->block_default_type = IF_SCSI; 1380 mc->max_cpus = 4; 1381 mc->default_boot_order = "c"; 1382 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1383 } 1384 1385 static const TypeInfo ss600mp_type = { 1386 .name = MACHINE_TYPE_NAME("SS-600MP"), 1387 .parent = TYPE_MACHINE, 1388 .class_init = ss600mp_class_init, 1389 }; 1390 1391 static void ss20_class_init(ObjectClass *oc, void *data) 1392 { 1393 MachineClass *mc = MACHINE_CLASS(oc); 1394 1395 mc->desc = "Sun4m platform, SPARCstation 20"; 1396 mc->init = ss20_init; 1397 mc->block_default_type = IF_SCSI; 1398 mc->max_cpus = 4; 1399 mc->default_boot_order = "c"; 1400 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1401 } 1402 1403 static const TypeInfo ss20_type = { 1404 .name = MACHINE_TYPE_NAME("SS-20"), 1405 .parent = TYPE_MACHINE, 1406 .class_init = ss20_class_init, 1407 }; 1408 1409 static void voyager_class_init(ObjectClass *oc, void *data) 1410 { 1411 MachineClass *mc = MACHINE_CLASS(oc); 1412 1413 mc->desc = "Sun4m platform, SPARCstation Voyager"; 1414 mc->init = vger_init; 1415 mc->block_default_type = IF_SCSI; 1416 mc->default_boot_order = "c"; 1417 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1418 } 1419 1420 static const TypeInfo voyager_type = { 1421 .name = MACHINE_TYPE_NAME("Voyager"), 1422 .parent = TYPE_MACHINE, 1423 .class_init = voyager_class_init, 1424 }; 1425 1426 static void ss_lx_class_init(ObjectClass *oc, void *data) 1427 { 1428 MachineClass *mc = MACHINE_CLASS(oc); 1429 1430 mc->desc = "Sun4m platform, SPARCstation LX"; 1431 mc->init = ss_lx_init; 1432 mc->block_default_type = IF_SCSI; 1433 mc->default_boot_order = "c"; 1434 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1435 } 1436 1437 static const TypeInfo ss_lx_type = { 1438 .name = MACHINE_TYPE_NAME("LX"), 1439 .parent = TYPE_MACHINE, 1440 .class_init = ss_lx_class_init, 1441 }; 1442 1443 static void ss4_class_init(ObjectClass *oc, void *data) 1444 { 1445 MachineClass *mc = MACHINE_CLASS(oc); 1446 1447 mc->desc = "Sun4m platform, SPARCstation 4"; 1448 mc->init = ss4_init; 1449 mc->block_default_type = IF_SCSI; 1450 mc->default_boot_order = "c"; 1451 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1452 } 1453 1454 static const TypeInfo ss4_type = { 1455 .name = MACHINE_TYPE_NAME("SS-4"), 1456 .parent = TYPE_MACHINE, 1457 .class_init = ss4_class_init, 1458 }; 1459 1460 static void scls_class_init(ObjectClass *oc, void *data) 1461 { 1462 MachineClass *mc = MACHINE_CLASS(oc); 1463 1464 mc->desc = "Sun4m platform, SPARCClassic"; 1465 mc->init = scls_init; 1466 mc->block_default_type = IF_SCSI; 1467 mc->default_boot_order = "c"; 1468 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1469 } 1470 1471 static const TypeInfo scls_type = { 1472 .name = MACHINE_TYPE_NAME("SPARCClassic"), 1473 .parent = TYPE_MACHINE, 1474 .class_init = scls_class_init, 1475 }; 1476 1477 static void sbook_class_init(ObjectClass *oc, void *data) 1478 { 1479 MachineClass *mc = MACHINE_CLASS(oc); 1480 1481 mc->desc = "Sun4m platform, SPARCbook"; 1482 mc->init = sbook_init; 1483 mc->block_default_type = IF_SCSI; 1484 mc->default_boot_order = "c"; 1485 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1486 } 1487 1488 static const TypeInfo sbook_type = { 1489 .name = MACHINE_TYPE_NAME("SPARCbook"), 1490 .parent = TYPE_MACHINE, 1491 .class_init = sbook_class_init, 1492 }; 1493 1494 static void sun4m_register_types(void) 1495 { 1496 type_register_static(&idreg_info); 1497 type_register_static(&afx_info); 1498 type_register_static(&prom_info); 1499 type_register_static(&ram_info); 1500 1501 type_register_static(&ss5_type); 1502 type_register_static(&ss10_type); 1503 type_register_static(&ss600mp_type); 1504 type_register_static(&ss20_type); 1505 type_register_static(&voyager_type); 1506 type_register_static(&ss_lx_type); 1507 type_register_static(&ss4_type); 1508 type_register_static(&scls_type); 1509 type_register_static(&sbook_type); 1510 } 1511 1512 type_init(sun4m_register_types) 1513