1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/sysbus.h" 29 #include "qemu/error-report.h" 30 #include "qemu/timer.h" 31 #include "hw/sparc/sun4m.h" 32 #include "hw/timer/m48t59.h" 33 #include "hw/sparc/sparc32_dma.h" 34 #include "hw/block/fdc.h" 35 #include "sysemu/sysemu.h" 36 #include "net/net.h" 37 #include "hw/boards.h" 38 #include "hw/scsi/esp.h" 39 #include "hw/i386/pc.h" 40 #include "hw/isa/isa.h" 41 #include "hw/nvram/sun_nvram.h" 42 #include "hw/nvram/chrp_nvram.h" 43 #include "hw/nvram/fw_cfg.h" 44 #include "hw/char/escc.h" 45 #include "hw/empty_slot.h" 46 #include "hw/loader.h" 47 #include "elf.h" 48 #include "sysemu/block-backend.h" 49 #include "trace.h" 50 #include "qemu/cutils.h" 51 52 /* 53 * Sun4m architecture was used in the following machines: 54 * 55 * SPARCserver 6xxMP/xx 56 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 57 * SPARCclassic X (4/10) 58 * SPARCstation LX/ZX (4/30) 59 * SPARCstation Voyager 60 * SPARCstation 10/xx, SPARCserver 10/xx 61 * SPARCstation 5, SPARCserver 5 62 * SPARCstation 20/xx, SPARCserver 20 63 * SPARCstation 4 64 * 65 * See for example: http://www.sunhelp.org/faq/sunref1.html 66 */ 67 68 #define KERNEL_LOAD_ADDR 0x00004000 69 #define CMDLINE_ADDR 0x007ff000 70 #define INITRD_LOAD_ADDR 0x00800000 71 #define PROM_SIZE_MAX (1024 * 1024) 72 #define PROM_VADDR 0xffd00000 73 #define PROM_FILENAME "openbios-sparc32" 74 #define CFG_ADDR 0xd00000510ULL 75 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 76 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 77 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 78 79 #define MAX_CPUS 16 80 #define MAX_PILS 16 81 #define MAX_VSIMMS 4 82 83 #define ESCC_CLOCK 4915200 84 85 struct sun4m_hwdef { 86 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 87 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 88 hwaddr serial_base, fd_base; 89 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 90 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 91 hwaddr bpp_base, dbri_base, sx_base; 92 struct { 93 hwaddr reg_base, vram_base; 94 } vsimm[MAX_VSIMMS]; 95 hwaddr ecc_base; 96 uint64_t max_mem; 97 const char * const default_cpu_model; 98 uint32_t ecc_version; 99 uint32_t iommu_version; 100 uint16_t machine_id; 101 uint8_t nvram_machine_id; 102 }; 103 104 void DMA_init(ISABus *bus, int high_page_enable) 105 { 106 } 107 108 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 109 Error **errp) 110 { 111 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 112 } 113 114 static void nvram_init(Nvram *nvram, uint8_t *macaddr, 115 const char *cmdline, const char *boot_devices, 116 ram_addr_t RAM_size, uint32_t kernel_size, 117 int width, int height, int depth, 118 int nvram_machine_id, const char *arch) 119 { 120 unsigned int i; 121 int sysp_end; 122 uint8_t image[0x1ff0]; 123 NvramClass *k = NVRAM_GET_CLASS(nvram); 124 125 memset(image, '\0', sizeof(image)); 126 127 /* OpenBIOS nvram variables partition */ 128 sysp_end = chrp_nvram_create_system_partition(image, 0); 129 130 /* Free space partition */ 131 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 132 133 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 134 nvram_machine_id); 135 136 for (i = 0; i < sizeof(image); i++) { 137 (k->write)(nvram, i, image[i]); 138 } 139 } 140 141 void cpu_check_irqs(CPUSPARCState *env) 142 { 143 CPUState *cs; 144 145 /* We should be holding the BQL before we mess with IRQs */ 146 g_assert(qemu_mutex_iothread_locked()); 147 148 if (env->pil_in && (env->interrupt_index == 0 || 149 (env->interrupt_index & ~15) == TT_EXTINT)) { 150 unsigned int i; 151 152 for (i = 15; i > 0; i--) { 153 if (env->pil_in & (1 << i)) { 154 int old_interrupt = env->interrupt_index; 155 156 env->interrupt_index = TT_EXTINT | i; 157 if (old_interrupt != env->interrupt_index) { 158 cs = CPU(sparc_env_get_cpu(env)); 159 trace_sun4m_cpu_interrupt(i); 160 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 161 } 162 break; 163 } 164 } 165 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 166 cs = CPU(sparc_env_get_cpu(env)); 167 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 168 env->interrupt_index = 0; 169 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 170 } 171 } 172 173 static void cpu_kick_irq(SPARCCPU *cpu) 174 { 175 CPUSPARCState *env = &cpu->env; 176 CPUState *cs = CPU(cpu); 177 178 cs->halted = 0; 179 cpu_check_irqs(env); 180 qemu_cpu_kick(cs); 181 } 182 183 static void cpu_set_irq(void *opaque, int irq, int level) 184 { 185 SPARCCPU *cpu = opaque; 186 CPUSPARCState *env = &cpu->env; 187 188 if (level) { 189 trace_sun4m_cpu_set_irq_raise(irq); 190 env->pil_in |= 1 << irq; 191 cpu_kick_irq(cpu); 192 } else { 193 trace_sun4m_cpu_set_irq_lower(irq); 194 env->pil_in &= ~(1 << irq); 195 cpu_check_irqs(env); 196 } 197 } 198 199 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 200 { 201 } 202 203 static void main_cpu_reset(void *opaque) 204 { 205 SPARCCPU *cpu = opaque; 206 CPUState *cs = CPU(cpu); 207 208 cpu_reset(cs); 209 cs->halted = 0; 210 } 211 212 static void secondary_cpu_reset(void *opaque) 213 { 214 SPARCCPU *cpu = opaque; 215 CPUState *cs = CPU(cpu); 216 217 cpu_reset(cs); 218 cs->halted = 1; 219 } 220 221 static void cpu_halt_signal(void *opaque, int irq, int level) 222 { 223 if (level && current_cpu) { 224 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 225 } 226 } 227 228 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 229 { 230 return addr - 0xf0000000ULL; 231 } 232 233 static unsigned long sun4m_load_kernel(const char *kernel_filename, 234 const char *initrd_filename, 235 ram_addr_t RAM_size) 236 { 237 int linux_boot; 238 unsigned int i; 239 long initrd_size, kernel_size; 240 uint8_t *ptr; 241 242 linux_boot = (kernel_filename != NULL); 243 244 kernel_size = 0; 245 if (linux_boot) { 246 int bswap_needed; 247 248 #ifdef BSWAP_NEEDED 249 bswap_needed = 1; 250 #else 251 bswap_needed = 0; 252 #endif 253 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 254 NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 255 if (kernel_size < 0) 256 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 257 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 258 TARGET_PAGE_SIZE); 259 if (kernel_size < 0) 260 kernel_size = load_image_targphys(kernel_filename, 261 KERNEL_LOAD_ADDR, 262 RAM_size - KERNEL_LOAD_ADDR); 263 if (kernel_size < 0) { 264 fprintf(stderr, "qemu: could not load kernel '%s'\n", 265 kernel_filename); 266 exit(1); 267 } 268 269 /* load initrd */ 270 initrd_size = 0; 271 if (initrd_filename) { 272 initrd_size = load_image_targphys(initrd_filename, 273 INITRD_LOAD_ADDR, 274 RAM_size - INITRD_LOAD_ADDR); 275 if (initrd_size < 0) { 276 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 277 initrd_filename); 278 exit(1); 279 } 280 } 281 if (initrd_size > 0) { 282 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 283 ptr = rom_ptr(KERNEL_LOAD_ADDR + i); 284 if (ldl_p(ptr) == 0x48647253) { // HdrS 285 stl_p(ptr + 16, INITRD_LOAD_ADDR); 286 stl_p(ptr + 20, initrd_size); 287 break; 288 } 289 } 290 } 291 } 292 return kernel_size; 293 } 294 295 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 296 { 297 DeviceState *dev; 298 SysBusDevice *s; 299 300 dev = qdev_create(NULL, "iommu"); 301 qdev_prop_set_uint32(dev, "version", version); 302 qdev_init_nofail(dev); 303 s = SYS_BUS_DEVICE(dev); 304 sysbus_connect_irq(s, 0, irq); 305 sysbus_mmio_map(s, 0, addr); 306 307 return s; 308 } 309 310 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq, 311 void *iommu, qemu_irq *dev_irq, int is_ledma) 312 { 313 DeviceState *dev; 314 SysBusDevice *s; 315 316 dev = qdev_create(NULL, "sparc32_dma"); 317 qdev_prop_set_ptr(dev, "iommu_opaque", iommu); 318 qdev_prop_set_uint32(dev, "is_ledma", is_ledma); 319 qdev_init_nofail(dev); 320 s = SYS_BUS_DEVICE(dev); 321 sysbus_connect_irq(s, 0, parent_irq); 322 *dev_irq = qdev_get_gpio_in(dev, 0); 323 sysbus_mmio_map(s, 0, daddr); 324 325 return s; 326 } 327 328 static void lance_init(NICInfo *nd, hwaddr leaddr, 329 void *dma_opaque, qemu_irq irq) 330 { 331 DeviceState *dev; 332 SysBusDevice *s; 333 qemu_irq reset; 334 335 qemu_check_nic_model(&nd_table[0], "lance"); 336 337 dev = qdev_create(NULL, "lance"); 338 qdev_set_nic_properties(dev, nd); 339 qdev_prop_set_ptr(dev, "dma", dma_opaque); 340 qdev_init_nofail(dev); 341 s = SYS_BUS_DEVICE(dev); 342 sysbus_mmio_map(s, 0, leaddr); 343 sysbus_connect_irq(s, 0, irq); 344 reset = qdev_get_gpio_in(dev, 0); 345 qdev_connect_gpio_out(dma_opaque, 0, reset); 346 } 347 348 static DeviceState *slavio_intctl_init(hwaddr addr, 349 hwaddr addrg, 350 qemu_irq **parent_irq) 351 { 352 DeviceState *dev; 353 SysBusDevice *s; 354 unsigned int i, j; 355 356 dev = qdev_create(NULL, "slavio_intctl"); 357 qdev_init_nofail(dev); 358 359 s = SYS_BUS_DEVICE(dev); 360 361 for (i = 0; i < MAX_CPUS; i++) { 362 for (j = 0; j < MAX_PILS; j++) { 363 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 364 } 365 } 366 sysbus_mmio_map(s, 0, addrg); 367 for (i = 0; i < MAX_CPUS; i++) { 368 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 369 } 370 371 return dev; 372 } 373 374 #define SYS_TIMER_OFFSET 0x10000ULL 375 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 376 377 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 378 qemu_irq *cpu_irqs, unsigned int num_cpus) 379 { 380 DeviceState *dev; 381 SysBusDevice *s; 382 unsigned int i; 383 384 dev = qdev_create(NULL, "slavio_timer"); 385 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 386 qdev_init_nofail(dev); 387 s = SYS_BUS_DEVICE(dev); 388 sysbus_connect_irq(s, 0, master_irq); 389 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 390 391 for (i = 0; i < MAX_CPUS; i++) { 392 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 393 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 394 } 395 } 396 397 static qemu_irq slavio_system_powerdown; 398 399 static void slavio_powerdown_req(Notifier *n, void *opaque) 400 { 401 qemu_irq_raise(slavio_system_powerdown); 402 } 403 404 static Notifier slavio_system_powerdown_notifier = { 405 .notify = slavio_powerdown_req 406 }; 407 408 #define MISC_LEDS 0x01600000 409 #define MISC_CFG 0x01800000 410 #define MISC_DIAG 0x01a00000 411 #define MISC_MDM 0x01b00000 412 #define MISC_SYS 0x01f00000 413 414 static void slavio_misc_init(hwaddr base, 415 hwaddr aux1_base, 416 hwaddr aux2_base, qemu_irq irq, 417 qemu_irq fdc_tc) 418 { 419 DeviceState *dev; 420 SysBusDevice *s; 421 422 dev = qdev_create(NULL, "slavio_misc"); 423 qdev_init_nofail(dev); 424 s = SYS_BUS_DEVICE(dev); 425 if (base) { 426 /* 8 bit registers */ 427 /* Slavio control */ 428 sysbus_mmio_map(s, 0, base + MISC_CFG); 429 /* Diagnostics */ 430 sysbus_mmio_map(s, 1, base + MISC_DIAG); 431 /* Modem control */ 432 sysbus_mmio_map(s, 2, base + MISC_MDM); 433 /* 16 bit registers */ 434 /* ss600mp diag LEDs */ 435 sysbus_mmio_map(s, 3, base + MISC_LEDS); 436 /* 32 bit registers */ 437 /* System control */ 438 sysbus_mmio_map(s, 4, base + MISC_SYS); 439 } 440 if (aux1_base) { 441 /* AUX 1 (Misc System Functions) */ 442 sysbus_mmio_map(s, 5, aux1_base); 443 } 444 if (aux2_base) { 445 /* AUX 2 (Software Powerdown Control) */ 446 sysbus_mmio_map(s, 6, aux2_base); 447 } 448 sysbus_connect_irq(s, 0, irq); 449 sysbus_connect_irq(s, 1, fdc_tc); 450 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 451 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 452 } 453 454 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 455 { 456 DeviceState *dev; 457 SysBusDevice *s; 458 459 dev = qdev_create(NULL, "eccmemctl"); 460 qdev_prop_set_uint32(dev, "version", version); 461 qdev_init_nofail(dev); 462 s = SYS_BUS_DEVICE(dev); 463 sysbus_connect_irq(s, 0, irq); 464 sysbus_mmio_map(s, 0, base); 465 if (version == 0) { // SS-600MP only 466 sysbus_mmio_map(s, 1, base + 0x1000); 467 } 468 } 469 470 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 471 { 472 DeviceState *dev; 473 SysBusDevice *s; 474 475 dev = qdev_create(NULL, "apc"); 476 qdev_init_nofail(dev); 477 s = SYS_BUS_DEVICE(dev); 478 /* Power management (APC) XXX: not a Slavio device */ 479 sysbus_mmio_map(s, 0, power_base); 480 sysbus_connect_irq(s, 0, cpu_halt); 481 } 482 483 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 484 int height, int depth) 485 { 486 DeviceState *dev; 487 SysBusDevice *s; 488 489 dev = qdev_create(NULL, "SUNW,tcx"); 490 qdev_prop_set_uint32(dev, "vram_size", vram_size); 491 qdev_prop_set_uint16(dev, "width", width); 492 qdev_prop_set_uint16(dev, "height", height); 493 qdev_prop_set_uint16(dev, "depth", depth); 494 qdev_prop_set_uint64(dev, "prom_addr", addr); 495 qdev_init_nofail(dev); 496 s = SYS_BUS_DEVICE(dev); 497 498 /* 10/ROM : FCode ROM */ 499 sysbus_mmio_map(s, 0, addr); 500 /* 2/STIP : Stipple */ 501 sysbus_mmio_map(s, 1, addr + 0x04000000ULL); 502 /* 3/BLIT : Blitter */ 503 sysbus_mmio_map(s, 2, addr + 0x06000000ULL); 504 /* 5/RSTIP : Raw Stipple */ 505 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); 506 /* 6/RBLIT : Raw Blitter */ 507 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); 508 /* 7/TEC : Transform Engine */ 509 sysbus_mmio_map(s, 5, addr + 0x00700000ULL); 510 /* 8/CMAP : DAC */ 511 sysbus_mmio_map(s, 6, addr + 0x00200000ULL); 512 /* 9/THC : */ 513 if (depth == 8) { 514 sysbus_mmio_map(s, 7, addr + 0x00300000ULL); 515 } else { 516 sysbus_mmio_map(s, 7, addr + 0x00301000ULL); 517 } 518 /* 11/DHC : */ 519 sysbus_mmio_map(s, 8, addr + 0x00240000ULL); 520 /* 12/ALT : */ 521 sysbus_mmio_map(s, 9, addr + 0x00280000ULL); 522 /* 0/DFB8 : 8-bit plane */ 523 sysbus_mmio_map(s, 10, addr + 0x00800000ULL); 524 /* 1/DFB24 : 24bit plane */ 525 sysbus_mmio_map(s, 11, addr + 0x02000000ULL); 526 /* 4/RDFB32: Raw framebuffer. Control plane */ 527 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); 528 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 529 if (depth == 8) { 530 sysbus_mmio_map(s, 13, addr + 0x00301000ULL); 531 } 532 533 sysbus_connect_irq(s, 0, irq); 534 } 535 536 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 537 int height, int depth) 538 { 539 DeviceState *dev; 540 SysBusDevice *s; 541 542 dev = qdev_create(NULL, "cgthree"); 543 qdev_prop_set_uint32(dev, "vram-size", vram_size); 544 qdev_prop_set_uint16(dev, "width", width); 545 qdev_prop_set_uint16(dev, "height", height); 546 qdev_prop_set_uint16(dev, "depth", depth); 547 qdev_init_nofail(dev); 548 s = SYS_BUS_DEVICE(dev); 549 550 /* FCode ROM */ 551 sysbus_mmio_map(s, 0, addr); 552 /* DAC */ 553 sysbus_mmio_map(s, 1, addr + 0x400000ULL); 554 /* 8-bit plane */ 555 sysbus_mmio_map(s, 2, addr + 0x800000ULL); 556 557 sysbus_connect_irq(s, 0, irq); 558 } 559 560 /* NCR89C100/MACIO Internal ID register */ 561 562 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 563 564 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 565 566 static void idreg_init(hwaddr addr) 567 { 568 DeviceState *dev; 569 SysBusDevice *s; 570 571 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER); 572 qdev_init_nofail(dev); 573 s = SYS_BUS_DEVICE(dev); 574 575 sysbus_mmio_map(s, 0, addr); 576 cpu_physical_memory_write_rom(&address_space_memory, 577 addr, idreg_data, sizeof(idreg_data)); 578 } 579 580 #define MACIO_ID_REGISTER(obj) \ 581 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER) 582 583 typedef struct IDRegState { 584 SysBusDevice parent_obj; 585 586 MemoryRegion mem; 587 } IDRegState; 588 589 static int idreg_init1(SysBusDevice *dev) 590 { 591 IDRegState *s = MACIO_ID_REGISTER(dev); 592 593 memory_region_init_ram(&s->mem, OBJECT(s), 594 "sun4m.idreg", sizeof(idreg_data), &error_fatal); 595 vmstate_register_ram_global(&s->mem); 596 memory_region_set_readonly(&s->mem, true); 597 sysbus_init_mmio(dev, &s->mem); 598 return 0; 599 } 600 601 static void idreg_class_init(ObjectClass *klass, void *data) 602 { 603 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 604 605 k->init = idreg_init1; 606 } 607 608 static const TypeInfo idreg_info = { 609 .name = TYPE_MACIO_ID_REGISTER, 610 .parent = TYPE_SYS_BUS_DEVICE, 611 .instance_size = sizeof(IDRegState), 612 .class_init = idreg_class_init, 613 }; 614 615 #define TYPE_TCX_AFX "tcx_afx" 616 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX) 617 618 typedef struct AFXState { 619 SysBusDevice parent_obj; 620 621 MemoryRegion mem; 622 } AFXState; 623 624 /* SS-5 TCX AFX register */ 625 static void afx_init(hwaddr addr) 626 { 627 DeviceState *dev; 628 SysBusDevice *s; 629 630 dev = qdev_create(NULL, TYPE_TCX_AFX); 631 qdev_init_nofail(dev); 632 s = SYS_BUS_DEVICE(dev); 633 634 sysbus_mmio_map(s, 0, addr); 635 } 636 637 static int afx_init1(SysBusDevice *dev) 638 { 639 AFXState *s = TCX_AFX(dev); 640 641 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4, &error_fatal); 642 vmstate_register_ram_global(&s->mem); 643 sysbus_init_mmio(dev, &s->mem); 644 return 0; 645 } 646 647 static void afx_class_init(ObjectClass *klass, void *data) 648 { 649 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 650 651 k->init = afx_init1; 652 } 653 654 static const TypeInfo afx_info = { 655 .name = TYPE_TCX_AFX, 656 .parent = TYPE_SYS_BUS_DEVICE, 657 .instance_size = sizeof(AFXState), 658 .class_init = afx_class_init, 659 }; 660 661 #define TYPE_OPENPROM "openprom" 662 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 663 664 typedef struct PROMState { 665 SysBusDevice parent_obj; 666 667 MemoryRegion prom; 668 } PROMState; 669 670 /* Boot PROM (OpenBIOS) */ 671 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 672 { 673 hwaddr *base_addr = (hwaddr *)opaque; 674 return addr + *base_addr - PROM_VADDR; 675 } 676 677 static void prom_init(hwaddr addr, const char *bios_name) 678 { 679 DeviceState *dev; 680 SysBusDevice *s; 681 char *filename; 682 int ret; 683 684 dev = qdev_create(NULL, TYPE_OPENPROM); 685 qdev_init_nofail(dev); 686 s = SYS_BUS_DEVICE(dev); 687 688 sysbus_mmio_map(s, 0, addr); 689 690 /* load boot prom */ 691 if (bios_name == NULL) { 692 bios_name = PROM_FILENAME; 693 } 694 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 695 if (filename) { 696 ret = load_elf(filename, translate_prom_address, &addr, NULL, 697 NULL, NULL, 1, EM_SPARC, 0, 0); 698 if (ret < 0 || ret > PROM_SIZE_MAX) { 699 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 700 } 701 g_free(filename); 702 } else { 703 ret = -1; 704 } 705 if (ret < 0 || ret > PROM_SIZE_MAX) { 706 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 707 exit(1); 708 } 709 } 710 711 static int prom_init1(SysBusDevice *dev) 712 { 713 PROMState *s = OPENPROM(dev); 714 715 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX, 716 &error_fatal); 717 vmstate_register_ram_global(&s->prom); 718 memory_region_set_readonly(&s->prom, true); 719 sysbus_init_mmio(dev, &s->prom); 720 return 0; 721 } 722 723 static Property prom_properties[] = { 724 {/* end of property list */}, 725 }; 726 727 static void prom_class_init(ObjectClass *klass, void *data) 728 { 729 DeviceClass *dc = DEVICE_CLASS(klass); 730 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 731 732 k->init = prom_init1; 733 dc->props = prom_properties; 734 } 735 736 static const TypeInfo prom_info = { 737 .name = TYPE_OPENPROM, 738 .parent = TYPE_SYS_BUS_DEVICE, 739 .instance_size = sizeof(PROMState), 740 .class_init = prom_class_init, 741 }; 742 743 #define TYPE_SUN4M_MEMORY "memory" 744 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY) 745 746 typedef struct RamDevice { 747 SysBusDevice parent_obj; 748 749 MemoryRegion ram; 750 uint64_t size; 751 } RamDevice; 752 753 /* System RAM */ 754 static int ram_init1(SysBusDevice *dev) 755 { 756 RamDevice *d = SUN4M_RAM(dev); 757 758 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram", 759 d->size); 760 sysbus_init_mmio(dev, &d->ram); 761 return 0; 762 } 763 764 static void ram_init(hwaddr addr, ram_addr_t RAM_size, 765 uint64_t max_mem) 766 { 767 DeviceState *dev; 768 SysBusDevice *s; 769 RamDevice *d; 770 771 /* allocate RAM */ 772 if ((uint64_t)RAM_size > max_mem) { 773 fprintf(stderr, 774 "qemu: Too much memory for this machine: %d, maximum %d\n", 775 (unsigned int)(RAM_size / (1024 * 1024)), 776 (unsigned int)(max_mem / (1024 * 1024))); 777 exit(1); 778 } 779 dev = qdev_create(NULL, "memory"); 780 s = SYS_BUS_DEVICE(dev); 781 782 d = SUN4M_RAM(dev); 783 d->size = RAM_size; 784 qdev_init_nofail(dev); 785 786 sysbus_mmio_map(s, 0, addr); 787 } 788 789 static Property ram_properties[] = { 790 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 791 DEFINE_PROP_END_OF_LIST(), 792 }; 793 794 static void ram_class_init(ObjectClass *klass, void *data) 795 { 796 DeviceClass *dc = DEVICE_CLASS(klass); 797 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 798 799 k->init = ram_init1; 800 dc->props = ram_properties; 801 } 802 803 static const TypeInfo ram_info = { 804 .name = TYPE_SUN4M_MEMORY, 805 .parent = TYPE_SYS_BUS_DEVICE, 806 .instance_size = sizeof(RamDevice), 807 .class_init = ram_class_init, 808 }; 809 810 static void cpu_devinit(const char *cpu_model, unsigned int id, 811 uint64_t prom_addr, qemu_irq **cpu_irqs) 812 { 813 CPUState *cs; 814 SPARCCPU *cpu; 815 CPUSPARCState *env; 816 817 cpu = cpu_sparc_init(cpu_model); 818 if (cpu == NULL) { 819 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); 820 exit(1); 821 } 822 env = &cpu->env; 823 824 cpu_sparc_set_id(env, id); 825 if (id == 0) { 826 qemu_register_reset(main_cpu_reset, cpu); 827 } else { 828 qemu_register_reset(secondary_cpu_reset, cpu); 829 cs = CPU(cpu); 830 cs->halted = 1; 831 } 832 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 833 env->prom_addr = prom_addr; 834 } 835 836 static void dummy_fdc_tc(void *opaque, int irq, int level) 837 { 838 } 839 840 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, 841 MachineState *machine) 842 { 843 DeviceState *slavio_intctl; 844 const char *cpu_model = machine->cpu_model; 845 unsigned int i; 846 void *iommu, *espdma, *ledma, *nvram; 847 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS], 848 espdma_irq, ledma_irq; 849 qemu_irq esp_reset, dma_enable; 850 qemu_irq fdc_tc; 851 unsigned long kernel_size; 852 DriveInfo *fd[MAX_FD]; 853 FWCfgState *fw_cfg; 854 unsigned int num_vsimms; 855 856 /* init CPUs */ 857 if (!cpu_model) 858 cpu_model = hwdef->default_cpu_model; 859 860 for(i = 0; i < smp_cpus; i++) { 861 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); 862 } 863 864 for (i = smp_cpus; i < MAX_CPUS; i++) 865 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 866 867 868 /* set up devices */ 869 ram_init(0, machine->ram_size, hwdef->max_mem); 870 /* models without ECC don't trap when missing ram is accessed */ 871 if (!hwdef->ecc_base) { 872 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size); 873 } 874 875 prom_init(hwdef->slavio_base, bios_name); 876 877 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 878 hwdef->intctl_base + 0x10000ULL, 879 cpu_irqs); 880 881 for (i = 0; i < 32; i++) { 882 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 883 } 884 for (i = 0; i < MAX_CPUS; i++) { 885 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 886 } 887 888 if (hwdef->idreg_base) { 889 idreg_init(hwdef->idreg_base); 890 } 891 892 if (hwdef->afx_base) { 893 afx_init(hwdef->afx_base); 894 } 895 896 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, 897 slavio_irq[30]); 898 899 if (hwdef->iommu_pad_base) { 900 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 901 Software shouldn't use aliased addresses, neither should it crash 902 when does. Using empty_slot instead of aliasing can help with 903 debugging such accesses */ 904 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); 905 } 906 907 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18], 908 iommu, &espdma_irq, 0); 909 910 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, 911 slavio_irq[16], iommu, &ledma_irq, 1); 912 913 if (graphic_depth != 8 && graphic_depth != 24) { 914 error_report("Unsupported depth: %d", graphic_depth); 915 exit (1); 916 } 917 num_vsimms = 0; 918 if (num_vsimms == 0) { 919 if (vga_interface_type == VGA_CG3) { 920 if (graphic_depth != 8) { 921 error_report("Unsupported depth: %d", graphic_depth); 922 exit(1); 923 } 924 925 if (!(graphic_width == 1024 && graphic_height == 768) && 926 !(graphic_width == 1152 && graphic_height == 900)) { 927 error_report("Unsupported resolution: %d x %d", graphic_width, 928 graphic_height); 929 exit(1); 930 } 931 932 /* sbus irq 5 */ 933 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 934 graphic_width, graphic_height, graphic_depth); 935 } else { 936 /* If no display specified, default to TCX */ 937 if (graphic_depth != 8 && graphic_depth != 24) { 938 error_report("Unsupported depth: %d", graphic_depth); 939 exit(1); 940 } 941 942 if (!(graphic_width == 1024 && graphic_height == 768)) { 943 error_report("Unsupported resolution: %d x %d", 944 graphic_width, graphic_height); 945 exit(1); 946 } 947 948 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 949 graphic_width, graphic_height, graphic_depth); 950 } 951 } 952 953 for (i = num_vsimms; i < MAX_VSIMMS; i++) { 954 /* vsimm registers probed by OBP */ 955 if (hwdef->vsimm[i].reg_base) { 956 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); 957 } 958 } 959 960 if (hwdef->sx_base) { 961 empty_slot_init(hwdef->sx_base, 0x2000); 962 } 963 964 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq); 965 966 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8); 967 968 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 969 970 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14], 971 !machine->enable_graphics, ESCC_CLOCK, 1); 972 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 973 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 974 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], 975 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); 976 977 if (hwdef->apc_base) { 978 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); 979 } 980 981 if (hwdef->fd_base) { 982 /* there is zero or one floppy drive */ 983 memset(fd, 0, sizeof(fd)); 984 fd[0] = drive_get(IF_FLOPPY, 0, 0); 985 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 986 &fdc_tc); 987 } else { 988 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); 989 } 990 991 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 992 slavio_irq[30], fdc_tc); 993 994 esp_init(hwdef->esp_base, 2, 995 espdma_memory_read, espdma_memory_write, 996 espdma, espdma_irq, &esp_reset, &dma_enable); 997 998 qdev_connect_gpio_out(espdma, 0, esp_reset); 999 qdev_connect_gpio_out(espdma, 1, dma_enable); 1000 1001 if (hwdef->cs_base) { 1002 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, 1003 slavio_irq[5]); 1004 } 1005 1006 if (hwdef->dbri_base) { 1007 /* ISDN chip with attached CS4215 audio codec */ 1008 /* prom space */ 1009 empty_slot_init(hwdef->dbri_base+0x1000, 0x30); 1010 /* reg space */ 1011 empty_slot_init(hwdef->dbri_base+0x10000, 0x100); 1012 } 1013 1014 if (hwdef->bpp_base) { 1015 /* parallel port */ 1016 empty_slot_init(hwdef->bpp_base, 0x20); 1017 } 1018 1019 kernel_size = sun4m_load_kernel(machine->kernel_filename, 1020 machine->initrd_filename, 1021 machine->ram_size); 1022 1023 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline, 1024 machine->boot_order, machine->ram_size, kernel_size, 1025 graphic_width, graphic_height, graphic_depth, 1026 hwdef->nvram_machine_id, "Sun4m"); 1027 1028 if (hwdef->ecc_base) 1029 ecc_init(hwdef->ecc_base, slavio_irq[28], 1030 hwdef->ecc_version); 1031 1032 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 1033 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 1034 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1035 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1036 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1037 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1038 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1039 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1040 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1041 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1042 if (machine->kernel_cmdline) { 1043 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1044 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1045 machine->kernel_cmdline); 1046 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 1047 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1048 strlen(machine->kernel_cmdline) + 1); 1049 } else { 1050 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1051 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1052 } 1053 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1054 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used 1055 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 1056 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1057 } 1058 1059 enum { 1060 ss5_id = 32, 1061 vger_id, 1062 lx_id, 1063 ss4_id, 1064 scls_id, 1065 sbook_id, 1066 ss10_id = 64, 1067 ss20_id, 1068 ss600mp_id, 1069 }; 1070 1071 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1072 /* SS-5 */ 1073 { 1074 .iommu_base = 0x10000000, 1075 .iommu_pad_base = 0x10004000, 1076 .iommu_pad_len = 0x0fffb000, 1077 .tcx_base = 0x50000000, 1078 .cs_base = 0x6c000000, 1079 .slavio_base = 0x70000000, 1080 .ms_kb_base = 0x71000000, 1081 .serial_base = 0x71100000, 1082 .nvram_base = 0x71200000, 1083 .fd_base = 0x71400000, 1084 .counter_base = 0x71d00000, 1085 .intctl_base = 0x71e00000, 1086 .idreg_base = 0x78000000, 1087 .dma_base = 0x78400000, 1088 .esp_base = 0x78800000, 1089 .le_base = 0x78c00000, 1090 .apc_base = 0x6a000000, 1091 .afx_base = 0x6e000000, 1092 .aux1_base = 0x71900000, 1093 .aux2_base = 0x71910000, 1094 .nvram_machine_id = 0x80, 1095 .machine_id = ss5_id, 1096 .iommu_version = 0x05000000, 1097 .max_mem = 0x10000000, 1098 .default_cpu_model = "Fujitsu MB86904", 1099 }, 1100 /* SS-10 */ 1101 { 1102 .iommu_base = 0xfe0000000ULL, 1103 .tcx_base = 0xe20000000ULL, 1104 .slavio_base = 0xff0000000ULL, 1105 .ms_kb_base = 0xff1000000ULL, 1106 .serial_base = 0xff1100000ULL, 1107 .nvram_base = 0xff1200000ULL, 1108 .fd_base = 0xff1700000ULL, 1109 .counter_base = 0xff1300000ULL, 1110 .intctl_base = 0xff1400000ULL, 1111 .idreg_base = 0xef0000000ULL, 1112 .dma_base = 0xef0400000ULL, 1113 .esp_base = 0xef0800000ULL, 1114 .le_base = 0xef0c00000ULL, 1115 .apc_base = 0xefa000000ULL, // XXX should not exist 1116 .aux1_base = 0xff1800000ULL, 1117 .aux2_base = 0xff1a01000ULL, 1118 .ecc_base = 0xf00000000ULL, 1119 .ecc_version = 0x10000000, // version 0, implementation 1 1120 .nvram_machine_id = 0x72, 1121 .machine_id = ss10_id, 1122 .iommu_version = 0x03000000, 1123 .max_mem = 0xf00000000ULL, 1124 .default_cpu_model = "TI SuperSparc II", 1125 }, 1126 /* SS-600MP */ 1127 { 1128 .iommu_base = 0xfe0000000ULL, 1129 .tcx_base = 0xe20000000ULL, 1130 .slavio_base = 0xff0000000ULL, 1131 .ms_kb_base = 0xff1000000ULL, 1132 .serial_base = 0xff1100000ULL, 1133 .nvram_base = 0xff1200000ULL, 1134 .counter_base = 0xff1300000ULL, 1135 .intctl_base = 0xff1400000ULL, 1136 .dma_base = 0xef0081000ULL, 1137 .esp_base = 0xef0080000ULL, 1138 .le_base = 0xef0060000ULL, 1139 .apc_base = 0xefa000000ULL, // XXX should not exist 1140 .aux1_base = 0xff1800000ULL, 1141 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1142 .ecc_base = 0xf00000000ULL, 1143 .ecc_version = 0x00000000, // version 0, implementation 0 1144 .nvram_machine_id = 0x71, 1145 .machine_id = ss600mp_id, 1146 .iommu_version = 0x01000000, 1147 .max_mem = 0xf00000000ULL, 1148 .default_cpu_model = "TI SuperSparc II", 1149 }, 1150 /* SS-20 */ 1151 { 1152 .iommu_base = 0xfe0000000ULL, 1153 .tcx_base = 0xe20000000ULL, 1154 .slavio_base = 0xff0000000ULL, 1155 .ms_kb_base = 0xff1000000ULL, 1156 .serial_base = 0xff1100000ULL, 1157 .nvram_base = 0xff1200000ULL, 1158 .fd_base = 0xff1700000ULL, 1159 .counter_base = 0xff1300000ULL, 1160 .intctl_base = 0xff1400000ULL, 1161 .idreg_base = 0xef0000000ULL, 1162 .dma_base = 0xef0400000ULL, 1163 .esp_base = 0xef0800000ULL, 1164 .le_base = 0xef0c00000ULL, 1165 .bpp_base = 0xef4800000ULL, 1166 .apc_base = 0xefa000000ULL, // XXX should not exist 1167 .aux1_base = 0xff1800000ULL, 1168 .aux2_base = 0xff1a01000ULL, 1169 .dbri_base = 0xee0000000ULL, 1170 .sx_base = 0xf80000000ULL, 1171 .vsimm = { 1172 { 1173 .reg_base = 0x9c000000ULL, 1174 .vram_base = 0xfc000000ULL 1175 }, { 1176 .reg_base = 0x90000000ULL, 1177 .vram_base = 0xf0000000ULL 1178 }, { 1179 .reg_base = 0x94000000ULL 1180 }, { 1181 .reg_base = 0x98000000ULL 1182 } 1183 }, 1184 .ecc_base = 0xf00000000ULL, 1185 .ecc_version = 0x20000000, // version 0, implementation 2 1186 .nvram_machine_id = 0x72, 1187 .machine_id = ss20_id, 1188 .iommu_version = 0x13000000, 1189 .max_mem = 0xf00000000ULL, 1190 .default_cpu_model = "TI SuperSparc II", 1191 }, 1192 /* Voyager */ 1193 { 1194 .iommu_base = 0x10000000, 1195 .tcx_base = 0x50000000, 1196 .slavio_base = 0x70000000, 1197 .ms_kb_base = 0x71000000, 1198 .serial_base = 0x71100000, 1199 .nvram_base = 0x71200000, 1200 .fd_base = 0x71400000, 1201 .counter_base = 0x71d00000, 1202 .intctl_base = 0x71e00000, 1203 .idreg_base = 0x78000000, 1204 .dma_base = 0x78400000, 1205 .esp_base = 0x78800000, 1206 .le_base = 0x78c00000, 1207 .apc_base = 0x71300000, // pmc 1208 .aux1_base = 0x71900000, 1209 .aux2_base = 0x71910000, 1210 .nvram_machine_id = 0x80, 1211 .machine_id = vger_id, 1212 .iommu_version = 0x05000000, 1213 .max_mem = 0x10000000, 1214 .default_cpu_model = "Fujitsu MB86904", 1215 }, 1216 /* LX */ 1217 { 1218 .iommu_base = 0x10000000, 1219 .iommu_pad_base = 0x10004000, 1220 .iommu_pad_len = 0x0fffb000, 1221 .tcx_base = 0x50000000, 1222 .slavio_base = 0x70000000, 1223 .ms_kb_base = 0x71000000, 1224 .serial_base = 0x71100000, 1225 .nvram_base = 0x71200000, 1226 .fd_base = 0x71400000, 1227 .counter_base = 0x71d00000, 1228 .intctl_base = 0x71e00000, 1229 .idreg_base = 0x78000000, 1230 .dma_base = 0x78400000, 1231 .esp_base = 0x78800000, 1232 .le_base = 0x78c00000, 1233 .aux1_base = 0x71900000, 1234 .aux2_base = 0x71910000, 1235 .nvram_machine_id = 0x80, 1236 .machine_id = lx_id, 1237 .iommu_version = 0x04000000, 1238 .max_mem = 0x10000000, 1239 .default_cpu_model = "TI MicroSparc I", 1240 }, 1241 /* SS-4 */ 1242 { 1243 .iommu_base = 0x10000000, 1244 .tcx_base = 0x50000000, 1245 .cs_base = 0x6c000000, 1246 .slavio_base = 0x70000000, 1247 .ms_kb_base = 0x71000000, 1248 .serial_base = 0x71100000, 1249 .nvram_base = 0x71200000, 1250 .fd_base = 0x71400000, 1251 .counter_base = 0x71d00000, 1252 .intctl_base = 0x71e00000, 1253 .idreg_base = 0x78000000, 1254 .dma_base = 0x78400000, 1255 .esp_base = 0x78800000, 1256 .le_base = 0x78c00000, 1257 .apc_base = 0x6a000000, 1258 .aux1_base = 0x71900000, 1259 .aux2_base = 0x71910000, 1260 .nvram_machine_id = 0x80, 1261 .machine_id = ss4_id, 1262 .iommu_version = 0x05000000, 1263 .max_mem = 0x10000000, 1264 .default_cpu_model = "Fujitsu MB86904", 1265 }, 1266 /* SPARCClassic */ 1267 { 1268 .iommu_base = 0x10000000, 1269 .tcx_base = 0x50000000, 1270 .slavio_base = 0x70000000, 1271 .ms_kb_base = 0x71000000, 1272 .serial_base = 0x71100000, 1273 .nvram_base = 0x71200000, 1274 .fd_base = 0x71400000, 1275 .counter_base = 0x71d00000, 1276 .intctl_base = 0x71e00000, 1277 .idreg_base = 0x78000000, 1278 .dma_base = 0x78400000, 1279 .esp_base = 0x78800000, 1280 .le_base = 0x78c00000, 1281 .apc_base = 0x6a000000, 1282 .aux1_base = 0x71900000, 1283 .aux2_base = 0x71910000, 1284 .nvram_machine_id = 0x80, 1285 .machine_id = scls_id, 1286 .iommu_version = 0x05000000, 1287 .max_mem = 0x10000000, 1288 .default_cpu_model = "TI MicroSparc I", 1289 }, 1290 /* SPARCbook */ 1291 { 1292 .iommu_base = 0x10000000, 1293 .tcx_base = 0x50000000, // XXX 1294 .slavio_base = 0x70000000, 1295 .ms_kb_base = 0x71000000, 1296 .serial_base = 0x71100000, 1297 .nvram_base = 0x71200000, 1298 .fd_base = 0x71400000, 1299 .counter_base = 0x71d00000, 1300 .intctl_base = 0x71e00000, 1301 .idreg_base = 0x78000000, 1302 .dma_base = 0x78400000, 1303 .esp_base = 0x78800000, 1304 .le_base = 0x78c00000, 1305 .apc_base = 0x6a000000, 1306 .aux1_base = 0x71900000, 1307 .aux2_base = 0x71910000, 1308 .nvram_machine_id = 0x80, 1309 .machine_id = sbook_id, 1310 .iommu_version = 0x05000000, 1311 .max_mem = 0x10000000, 1312 .default_cpu_model = "TI MicroSparc I", 1313 }, 1314 }; 1315 1316 /* SPARCstation 5 hardware initialisation */ 1317 static void ss5_init(MachineState *machine) 1318 { 1319 sun4m_hw_init(&sun4m_hwdefs[0], machine); 1320 } 1321 1322 /* SPARCstation 10 hardware initialisation */ 1323 static void ss10_init(MachineState *machine) 1324 { 1325 sun4m_hw_init(&sun4m_hwdefs[1], machine); 1326 } 1327 1328 /* SPARCserver 600MP hardware initialisation */ 1329 static void ss600mp_init(MachineState *machine) 1330 { 1331 sun4m_hw_init(&sun4m_hwdefs[2], machine); 1332 } 1333 1334 /* SPARCstation 20 hardware initialisation */ 1335 static void ss20_init(MachineState *machine) 1336 { 1337 sun4m_hw_init(&sun4m_hwdefs[3], machine); 1338 } 1339 1340 /* SPARCstation Voyager hardware initialisation */ 1341 static void vger_init(MachineState *machine) 1342 { 1343 sun4m_hw_init(&sun4m_hwdefs[4], machine); 1344 } 1345 1346 /* SPARCstation LX hardware initialisation */ 1347 static void ss_lx_init(MachineState *machine) 1348 { 1349 sun4m_hw_init(&sun4m_hwdefs[5], machine); 1350 } 1351 1352 /* SPARCstation 4 hardware initialisation */ 1353 static void ss4_init(MachineState *machine) 1354 { 1355 sun4m_hw_init(&sun4m_hwdefs[6], machine); 1356 } 1357 1358 /* SPARCClassic hardware initialisation */ 1359 static void scls_init(MachineState *machine) 1360 { 1361 sun4m_hw_init(&sun4m_hwdefs[7], machine); 1362 } 1363 1364 /* SPARCbook hardware initialisation */ 1365 static void sbook_init(MachineState *machine) 1366 { 1367 sun4m_hw_init(&sun4m_hwdefs[8], machine); 1368 } 1369 1370 static void ss5_class_init(ObjectClass *oc, void *data) 1371 { 1372 MachineClass *mc = MACHINE_CLASS(oc); 1373 1374 mc->desc = "Sun4m platform, SPARCstation 5"; 1375 mc->init = ss5_init; 1376 mc->block_default_type = IF_SCSI; 1377 mc->is_default = 1; 1378 mc->default_boot_order = "c"; 1379 } 1380 1381 static const TypeInfo ss5_type = { 1382 .name = MACHINE_TYPE_NAME("SS-5"), 1383 .parent = TYPE_MACHINE, 1384 .class_init = ss5_class_init, 1385 }; 1386 1387 static void ss10_class_init(ObjectClass *oc, void *data) 1388 { 1389 MachineClass *mc = MACHINE_CLASS(oc); 1390 1391 mc->desc = "Sun4m platform, SPARCstation 10"; 1392 mc->init = ss10_init; 1393 mc->block_default_type = IF_SCSI; 1394 mc->max_cpus = 4; 1395 mc->default_boot_order = "c"; 1396 } 1397 1398 static const TypeInfo ss10_type = { 1399 .name = MACHINE_TYPE_NAME("SS-10"), 1400 .parent = TYPE_MACHINE, 1401 .class_init = ss10_class_init, 1402 }; 1403 1404 static void ss600mp_class_init(ObjectClass *oc, void *data) 1405 { 1406 MachineClass *mc = MACHINE_CLASS(oc); 1407 1408 mc->desc = "Sun4m platform, SPARCserver 600MP"; 1409 mc->init = ss600mp_init; 1410 mc->block_default_type = IF_SCSI; 1411 mc->max_cpus = 4; 1412 mc->default_boot_order = "c"; 1413 } 1414 1415 static const TypeInfo ss600mp_type = { 1416 .name = MACHINE_TYPE_NAME("SS-600MP"), 1417 .parent = TYPE_MACHINE, 1418 .class_init = ss600mp_class_init, 1419 }; 1420 1421 static void ss20_class_init(ObjectClass *oc, void *data) 1422 { 1423 MachineClass *mc = MACHINE_CLASS(oc); 1424 1425 mc->desc = "Sun4m platform, SPARCstation 20"; 1426 mc->init = ss20_init; 1427 mc->block_default_type = IF_SCSI; 1428 mc->max_cpus = 4; 1429 mc->default_boot_order = "c"; 1430 } 1431 1432 static const TypeInfo ss20_type = { 1433 .name = MACHINE_TYPE_NAME("SS-20"), 1434 .parent = TYPE_MACHINE, 1435 .class_init = ss20_class_init, 1436 }; 1437 1438 static void voyager_class_init(ObjectClass *oc, void *data) 1439 { 1440 MachineClass *mc = MACHINE_CLASS(oc); 1441 1442 mc->desc = "Sun4m platform, SPARCstation Voyager"; 1443 mc->init = vger_init; 1444 mc->block_default_type = IF_SCSI; 1445 mc->default_boot_order = "c"; 1446 } 1447 1448 static const TypeInfo voyager_type = { 1449 .name = MACHINE_TYPE_NAME("Voyager"), 1450 .parent = TYPE_MACHINE, 1451 .class_init = voyager_class_init, 1452 }; 1453 1454 static void ss_lx_class_init(ObjectClass *oc, void *data) 1455 { 1456 MachineClass *mc = MACHINE_CLASS(oc); 1457 1458 mc->desc = "Sun4m platform, SPARCstation LX"; 1459 mc->init = ss_lx_init; 1460 mc->block_default_type = IF_SCSI; 1461 mc->default_boot_order = "c"; 1462 } 1463 1464 static const TypeInfo ss_lx_type = { 1465 .name = MACHINE_TYPE_NAME("LX"), 1466 .parent = TYPE_MACHINE, 1467 .class_init = ss_lx_class_init, 1468 }; 1469 1470 static void ss4_class_init(ObjectClass *oc, void *data) 1471 { 1472 MachineClass *mc = MACHINE_CLASS(oc); 1473 1474 mc->desc = "Sun4m platform, SPARCstation 4"; 1475 mc->init = ss4_init; 1476 mc->block_default_type = IF_SCSI; 1477 mc->default_boot_order = "c"; 1478 } 1479 1480 static const TypeInfo ss4_type = { 1481 .name = MACHINE_TYPE_NAME("SS-4"), 1482 .parent = TYPE_MACHINE, 1483 .class_init = ss4_class_init, 1484 }; 1485 1486 static void scls_class_init(ObjectClass *oc, void *data) 1487 { 1488 MachineClass *mc = MACHINE_CLASS(oc); 1489 1490 mc->desc = "Sun4m platform, SPARCClassic"; 1491 mc->init = scls_init; 1492 mc->block_default_type = IF_SCSI; 1493 mc->default_boot_order = "c"; 1494 } 1495 1496 static const TypeInfo scls_type = { 1497 .name = MACHINE_TYPE_NAME("SPARCClassic"), 1498 .parent = TYPE_MACHINE, 1499 .class_init = scls_class_init, 1500 }; 1501 1502 static void sbook_class_init(ObjectClass *oc, void *data) 1503 { 1504 MachineClass *mc = MACHINE_CLASS(oc); 1505 1506 mc->desc = "Sun4m platform, SPARCbook"; 1507 mc->init = sbook_init; 1508 mc->block_default_type = IF_SCSI; 1509 mc->default_boot_order = "c"; 1510 } 1511 1512 static const TypeInfo sbook_type = { 1513 .name = MACHINE_TYPE_NAME("SPARCbook"), 1514 .parent = TYPE_MACHINE, 1515 .class_init = sbook_class_init, 1516 }; 1517 1518 static void sun4m_register_types(void) 1519 { 1520 type_register_static(&idreg_info); 1521 type_register_static(&afx_info); 1522 type_register_static(&prom_info); 1523 type_register_static(&ram_info); 1524 1525 type_register_static(&ss5_type); 1526 type_register_static(&ss10_type); 1527 type_register_static(&ss600mp_type); 1528 type_register_static(&ss20_type); 1529 type_register_static(&voyager_type); 1530 type_register_static(&ss_lx_type); 1531 type_register_static(&ss4_type); 1532 type_register_static(&scls_type); 1533 type_register_static(&sbook_type); 1534 } 1535 1536 type_init(sun4m_register_types) 1537