1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "qemu/datadir.h" 29 #include "qemu-common.h" 30 #include "cpu.h" 31 #include "hw/sysbus.h" 32 #include "qemu/error-report.h" 33 #include "qemu/timer.h" 34 #include "hw/sparc/sun4m_iommu.h" 35 #include "hw/rtc/m48t59.h" 36 #include "migration/vmstate.h" 37 #include "hw/sparc/sparc32_dma.h" 38 #include "hw/block/fdc.h" 39 #include "sysemu/reset.h" 40 #include "sysemu/runstate.h" 41 #include "sysemu/sysemu.h" 42 #include "net/net.h" 43 #include "hw/boards.h" 44 #include "hw/scsi/esp.h" 45 #include "hw/nvram/sun_nvram.h" 46 #include "hw/qdev-properties.h" 47 #include "hw/nvram/chrp_nvram.h" 48 #include "hw/nvram/fw_cfg.h" 49 #include "hw/char/escc.h" 50 #include "hw/misc/empty_slot.h" 51 #include "hw/misc/unimp.h" 52 #include "hw/irq.h" 53 #include "hw/or-irq.h" 54 #include "hw/loader.h" 55 #include "elf.h" 56 #include "trace.h" 57 #include "qom/object.h" 58 59 /* 60 * Sun4m architecture was used in the following machines: 61 * 62 * SPARCserver 6xxMP/xx 63 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 64 * SPARCclassic X (4/10) 65 * SPARCstation LX/ZX (4/30) 66 * SPARCstation Voyager 67 * SPARCstation 10/xx, SPARCserver 10/xx 68 * SPARCstation 5, SPARCserver 5 69 * SPARCstation 20/xx, SPARCserver 20 70 * SPARCstation 4 71 * 72 * See for example: http://www.sunhelp.org/faq/sunref1.html 73 */ 74 75 #define KERNEL_LOAD_ADDR 0x00004000 76 #define CMDLINE_ADDR 0x007ff000 77 #define INITRD_LOAD_ADDR 0x00800000 78 #define PROM_SIZE_MAX (1 * MiB) 79 #define PROM_VADDR 0xffd00000 80 #define PROM_FILENAME "openbios-sparc32" 81 #define CFG_ADDR 0xd00000510ULL 82 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 83 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 84 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 85 86 #define MAX_CPUS 16 87 #define MAX_PILS 16 88 #define MAX_VSIMMS 4 89 90 #define ESCC_CLOCK 4915200 91 92 struct sun4m_hwdef { 93 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 94 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 95 hwaddr serial_base, fd_base; 96 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 97 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 98 hwaddr bpp_base, dbri_base, sx_base; 99 struct { 100 hwaddr reg_base, vram_base; 101 } vsimm[MAX_VSIMMS]; 102 hwaddr ecc_base; 103 uint64_t max_mem; 104 uint32_t ecc_version; 105 uint32_t iommu_version; 106 uint16_t machine_id; 107 uint8_t nvram_machine_id; 108 }; 109 110 #define TYPE_SUN4M_MACHINE MACHINE_TYPE_NAME("sun4m-common") 111 112 const char *fw_cfg_arch_key_name(uint16_t key) 113 { 114 static const struct { 115 uint16_t key; 116 const char *name; 117 } fw_cfg_arch_wellknown_keys[] = { 118 {FW_CFG_SUN4M_DEPTH, "depth"}, 119 {FW_CFG_SUN4M_WIDTH, "width"}, 120 {FW_CFG_SUN4M_HEIGHT, "height"}, 121 }; 122 123 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { 124 if (fw_cfg_arch_wellknown_keys[i].key == key) { 125 return fw_cfg_arch_wellknown_keys[i].name; 126 } 127 } 128 return NULL; 129 } 130 131 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 132 Error **errp) 133 { 134 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 135 } 136 137 static void nvram_init(Nvram *nvram, uint8_t *macaddr, 138 const char *cmdline, const char *boot_devices, 139 ram_addr_t RAM_size, uint32_t kernel_size, 140 int width, int height, int depth, 141 int nvram_machine_id, const char *arch) 142 { 143 unsigned int i; 144 int sysp_end; 145 uint8_t image[0x1ff0]; 146 NvramClass *k = NVRAM_GET_CLASS(nvram); 147 148 memset(image, '\0', sizeof(image)); 149 150 /* OpenBIOS nvram variables partition */ 151 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0); 152 153 /* Free space partition */ 154 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 155 156 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 157 nvram_machine_id); 158 159 for (i = 0; i < sizeof(image); i++) { 160 (k->write)(nvram, i, image[i]); 161 } 162 } 163 164 void cpu_check_irqs(CPUSPARCState *env) 165 { 166 CPUState *cs; 167 168 /* We should be holding the BQL before we mess with IRQs */ 169 g_assert(qemu_mutex_iothread_locked()); 170 171 if (env->pil_in && (env->interrupt_index == 0 || 172 (env->interrupt_index & ~15) == TT_EXTINT)) { 173 unsigned int i; 174 175 for (i = 15; i > 0; i--) { 176 if (env->pil_in & (1 << i)) { 177 int old_interrupt = env->interrupt_index; 178 179 env->interrupt_index = TT_EXTINT | i; 180 if (old_interrupt != env->interrupt_index) { 181 cs = env_cpu(env); 182 trace_sun4m_cpu_interrupt(i); 183 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 184 } 185 break; 186 } 187 } 188 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 189 cs = env_cpu(env); 190 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 191 env->interrupt_index = 0; 192 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 193 } 194 } 195 196 static void cpu_kick_irq(SPARCCPU *cpu) 197 { 198 CPUSPARCState *env = &cpu->env; 199 CPUState *cs = CPU(cpu); 200 201 cs->halted = 0; 202 cpu_check_irqs(env); 203 qemu_cpu_kick(cs); 204 } 205 206 static void cpu_set_irq(void *opaque, int irq, int level) 207 { 208 SPARCCPU *cpu = opaque; 209 CPUSPARCState *env = &cpu->env; 210 211 if (level) { 212 trace_sun4m_cpu_set_irq_raise(irq); 213 env->pil_in |= 1 << irq; 214 cpu_kick_irq(cpu); 215 } else { 216 trace_sun4m_cpu_set_irq_lower(irq); 217 env->pil_in &= ~(1 << irq); 218 cpu_check_irqs(env); 219 } 220 } 221 222 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 223 { 224 } 225 226 static void sun4m_cpu_reset(void *opaque) 227 { 228 SPARCCPU *cpu = opaque; 229 CPUState *cs = CPU(cpu); 230 231 cpu_reset(cs); 232 } 233 234 static void cpu_halt_signal(void *opaque, int irq, int level) 235 { 236 if (level && current_cpu) { 237 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 238 } 239 } 240 241 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 242 { 243 return addr - 0xf0000000ULL; 244 } 245 246 static unsigned long sun4m_load_kernel(const char *kernel_filename, 247 const char *initrd_filename, 248 ram_addr_t RAM_size, 249 uint32_t *initrd_size) 250 { 251 int linux_boot; 252 unsigned int i; 253 long kernel_size; 254 uint8_t *ptr; 255 256 linux_boot = (kernel_filename != NULL); 257 258 kernel_size = 0; 259 if (linux_boot) { 260 int bswap_needed; 261 262 #ifdef BSWAP_NEEDED 263 bswap_needed = 1; 264 #else 265 bswap_needed = 0; 266 #endif 267 kernel_size = load_elf(kernel_filename, NULL, 268 translate_kernel_address, NULL, 269 NULL, NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 270 if (kernel_size < 0) 271 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 272 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 273 TARGET_PAGE_SIZE); 274 if (kernel_size < 0) 275 kernel_size = load_image_targphys(kernel_filename, 276 KERNEL_LOAD_ADDR, 277 RAM_size - KERNEL_LOAD_ADDR); 278 if (kernel_size < 0) { 279 error_report("could not load kernel '%s'", kernel_filename); 280 exit(1); 281 } 282 283 /* load initrd */ 284 *initrd_size = 0; 285 if (initrd_filename) { 286 *initrd_size = load_image_targphys(initrd_filename, 287 INITRD_LOAD_ADDR, 288 RAM_size - INITRD_LOAD_ADDR); 289 if ((int)*initrd_size < 0) { 290 error_report("could not load initial ram disk '%s'", 291 initrd_filename); 292 exit(1); 293 } 294 } 295 if (*initrd_size > 0) { 296 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 297 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24); 298 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */ 299 stl_p(ptr + 16, INITRD_LOAD_ADDR); 300 stl_p(ptr + 20, *initrd_size); 301 break; 302 } 303 } 304 } 305 } 306 return kernel_size; 307 } 308 309 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 310 { 311 DeviceState *dev; 312 SysBusDevice *s; 313 314 dev = qdev_new(TYPE_SUN4M_IOMMU); 315 qdev_prop_set_uint32(dev, "version", version); 316 s = SYS_BUS_DEVICE(dev); 317 sysbus_realize_and_unref(s, &error_fatal); 318 sysbus_connect_irq(s, 0, irq); 319 sysbus_mmio_map(s, 0, addr); 320 321 return s; 322 } 323 324 static void *sparc32_dma_init(hwaddr dma_base, 325 hwaddr esp_base, qemu_irq espdma_irq, 326 hwaddr le_base, qemu_irq ledma_irq, NICInfo *nd) 327 { 328 DeviceState *dma; 329 ESPDMADeviceState *espdma; 330 LEDMADeviceState *ledma; 331 SysBusESPState *esp; 332 SysBusPCNetState *lance; 333 334 dma = qdev_new(TYPE_SPARC32_DMA); 335 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( 336 OBJECT(dma), "espdma")); 337 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); 338 339 esp = SYSBUS_ESP(object_resolve_path_component(OBJECT(espdma), "esp")); 340 341 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( 342 OBJECT(dma), "ledma")); 343 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq); 344 345 lance = SYSBUS_PCNET(object_resolve_path_component( 346 OBJECT(ledma), "lance")); 347 qdev_set_nic_properties(DEVICE(lance), nd); 348 349 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); 350 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); 351 352 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base); 353 scsi_bus_legacy_handle_cmdline(&esp->esp.bus); 354 355 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base); 356 357 return dma; 358 } 359 360 static DeviceState *slavio_intctl_init(hwaddr addr, 361 hwaddr addrg, 362 qemu_irq **parent_irq) 363 { 364 DeviceState *dev; 365 SysBusDevice *s; 366 unsigned int i, j; 367 368 dev = qdev_new("slavio_intctl"); 369 370 s = SYS_BUS_DEVICE(dev); 371 sysbus_realize_and_unref(s, &error_fatal); 372 373 for (i = 0; i < MAX_CPUS; i++) { 374 for (j = 0; j < MAX_PILS; j++) { 375 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 376 } 377 } 378 sysbus_mmio_map(s, 0, addrg); 379 for (i = 0; i < MAX_CPUS; i++) { 380 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 381 } 382 383 return dev; 384 } 385 386 #define SYS_TIMER_OFFSET 0x10000ULL 387 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 388 389 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 390 qemu_irq *cpu_irqs, unsigned int num_cpus) 391 { 392 DeviceState *dev; 393 SysBusDevice *s; 394 unsigned int i; 395 396 dev = qdev_new("slavio_timer"); 397 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 398 s = SYS_BUS_DEVICE(dev); 399 sysbus_realize_and_unref(s, &error_fatal); 400 sysbus_connect_irq(s, 0, master_irq); 401 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 402 403 for (i = 0; i < MAX_CPUS; i++) { 404 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 405 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 406 } 407 } 408 409 static qemu_irq slavio_system_powerdown; 410 411 static void slavio_powerdown_req(Notifier *n, void *opaque) 412 { 413 qemu_irq_raise(slavio_system_powerdown); 414 } 415 416 static Notifier slavio_system_powerdown_notifier = { 417 .notify = slavio_powerdown_req 418 }; 419 420 #define MISC_LEDS 0x01600000 421 #define MISC_CFG 0x01800000 422 #define MISC_DIAG 0x01a00000 423 #define MISC_MDM 0x01b00000 424 #define MISC_SYS 0x01f00000 425 426 static void slavio_misc_init(hwaddr base, 427 hwaddr aux1_base, 428 hwaddr aux2_base, qemu_irq irq, 429 qemu_irq fdc_tc) 430 { 431 DeviceState *dev; 432 SysBusDevice *s; 433 434 dev = qdev_new("slavio_misc"); 435 s = SYS_BUS_DEVICE(dev); 436 sysbus_realize_and_unref(s, &error_fatal); 437 if (base) { 438 /* 8 bit registers */ 439 /* Slavio control */ 440 sysbus_mmio_map(s, 0, base + MISC_CFG); 441 /* Diagnostics */ 442 sysbus_mmio_map(s, 1, base + MISC_DIAG); 443 /* Modem control */ 444 sysbus_mmio_map(s, 2, base + MISC_MDM); 445 /* 16 bit registers */ 446 /* ss600mp diag LEDs */ 447 sysbus_mmio_map(s, 3, base + MISC_LEDS); 448 /* 32 bit registers */ 449 /* System control */ 450 sysbus_mmio_map(s, 4, base + MISC_SYS); 451 } 452 if (aux1_base) { 453 /* AUX 1 (Misc System Functions) */ 454 sysbus_mmio_map(s, 5, aux1_base); 455 } 456 if (aux2_base) { 457 /* AUX 2 (Software Powerdown Control) */ 458 sysbus_mmio_map(s, 6, aux2_base); 459 } 460 sysbus_connect_irq(s, 0, irq); 461 sysbus_connect_irq(s, 1, fdc_tc); 462 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 463 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 464 } 465 466 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 467 { 468 DeviceState *dev; 469 SysBusDevice *s; 470 471 dev = qdev_new("eccmemctl"); 472 qdev_prop_set_uint32(dev, "version", version); 473 s = SYS_BUS_DEVICE(dev); 474 sysbus_realize_and_unref(s, &error_fatal); 475 sysbus_connect_irq(s, 0, irq); 476 sysbus_mmio_map(s, 0, base); 477 if (version == 0) { // SS-600MP only 478 sysbus_mmio_map(s, 1, base + 0x1000); 479 } 480 } 481 482 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 483 { 484 DeviceState *dev; 485 SysBusDevice *s; 486 487 dev = qdev_new("apc"); 488 s = SYS_BUS_DEVICE(dev); 489 sysbus_realize_and_unref(s, &error_fatal); 490 /* Power management (APC) XXX: not a Slavio device */ 491 sysbus_mmio_map(s, 0, power_base); 492 sysbus_connect_irq(s, 0, cpu_halt); 493 } 494 495 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 496 int height, int depth) 497 { 498 DeviceState *dev; 499 SysBusDevice *s; 500 501 dev = qdev_new("sun-tcx"); 502 qdev_prop_set_uint32(dev, "vram_size", vram_size); 503 qdev_prop_set_uint16(dev, "width", width); 504 qdev_prop_set_uint16(dev, "height", height); 505 qdev_prop_set_uint16(dev, "depth", depth); 506 s = SYS_BUS_DEVICE(dev); 507 sysbus_realize_and_unref(s, &error_fatal); 508 509 /* 10/ROM : FCode ROM */ 510 sysbus_mmio_map(s, 0, addr); 511 /* 2/STIP : Stipple */ 512 sysbus_mmio_map(s, 1, addr + 0x04000000ULL); 513 /* 3/BLIT : Blitter */ 514 sysbus_mmio_map(s, 2, addr + 0x06000000ULL); 515 /* 5/RSTIP : Raw Stipple */ 516 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); 517 /* 6/RBLIT : Raw Blitter */ 518 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); 519 /* 7/TEC : Transform Engine */ 520 sysbus_mmio_map(s, 5, addr + 0x00700000ULL); 521 /* 8/CMAP : DAC */ 522 sysbus_mmio_map(s, 6, addr + 0x00200000ULL); 523 /* 9/THC : */ 524 if (depth == 8) { 525 sysbus_mmio_map(s, 7, addr + 0x00300000ULL); 526 } else { 527 sysbus_mmio_map(s, 7, addr + 0x00301000ULL); 528 } 529 /* 11/DHC : */ 530 sysbus_mmio_map(s, 8, addr + 0x00240000ULL); 531 /* 12/ALT : */ 532 sysbus_mmio_map(s, 9, addr + 0x00280000ULL); 533 /* 0/DFB8 : 8-bit plane */ 534 sysbus_mmio_map(s, 10, addr + 0x00800000ULL); 535 /* 1/DFB24 : 24bit plane */ 536 sysbus_mmio_map(s, 11, addr + 0x02000000ULL); 537 /* 4/RDFB32: Raw framebuffer. Control plane */ 538 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); 539 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 540 if (depth == 8) { 541 sysbus_mmio_map(s, 13, addr + 0x00301000ULL); 542 } 543 544 sysbus_connect_irq(s, 0, irq); 545 } 546 547 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 548 int height, int depth) 549 { 550 DeviceState *dev; 551 SysBusDevice *s; 552 553 dev = qdev_new("cgthree"); 554 qdev_prop_set_uint32(dev, "vram-size", vram_size); 555 qdev_prop_set_uint16(dev, "width", width); 556 qdev_prop_set_uint16(dev, "height", height); 557 qdev_prop_set_uint16(dev, "depth", depth); 558 s = SYS_BUS_DEVICE(dev); 559 sysbus_realize_and_unref(s, &error_fatal); 560 561 /* FCode ROM */ 562 sysbus_mmio_map(s, 0, addr); 563 /* DAC */ 564 sysbus_mmio_map(s, 1, addr + 0x400000ULL); 565 /* 8-bit plane */ 566 sysbus_mmio_map(s, 2, addr + 0x800000ULL); 567 568 sysbus_connect_irq(s, 0, irq); 569 } 570 571 /* NCR89C100/MACIO Internal ID register */ 572 573 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 574 575 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 576 577 static void idreg_init(hwaddr addr) 578 { 579 DeviceState *dev; 580 SysBusDevice *s; 581 582 dev = qdev_new(TYPE_MACIO_ID_REGISTER); 583 s = SYS_BUS_DEVICE(dev); 584 sysbus_realize_and_unref(s, &error_fatal); 585 586 sysbus_mmio_map(s, 0, addr); 587 address_space_write_rom(&address_space_memory, addr, 588 MEMTXATTRS_UNSPECIFIED, 589 idreg_data, sizeof(idreg_data)); 590 } 591 592 OBJECT_DECLARE_SIMPLE_TYPE(IDRegState, MACIO_ID_REGISTER) 593 594 struct IDRegState { 595 SysBusDevice parent_obj; 596 597 MemoryRegion mem; 598 }; 599 600 static void idreg_realize(DeviceState *ds, Error **errp) 601 { 602 IDRegState *s = MACIO_ID_REGISTER(ds); 603 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 604 Error *local_err = NULL; 605 606 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg", 607 sizeof(idreg_data), &local_err); 608 if (local_err) { 609 error_propagate(errp, local_err); 610 return; 611 } 612 613 vmstate_register_ram_global(&s->mem); 614 memory_region_set_readonly(&s->mem, true); 615 sysbus_init_mmio(dev, &s->mem); 616 } 617 618 static void idreg_class_init(ObjectClass *oc, void *data) 619 { 620 DeviceClass *dc = DEVICE_CLASS(oc); 621 622 dc->realize = idreg_realize; 623 } 624 625 static const TypeInfo idreg_info = { 626 .name = TYPE_MACIO_ID_REGISTER, 627 .parent = TYPE_SYS_BUS_DEVICE, 628 .instance_size = sizeof(IDRegState), 629 .class_init = idreg_class_init, 630 }; 631 632 #define TYPE_TCX_AFX "tcx_afx" 633 OBJECT_DECLARE_SIMPLE_TYPE(AFXState, TCX_AFX) 634 635 struct AFXState { 636 SysBusDevice parent_obj; 637 638 MemoryRegion mem; 639 }; 640 641 /* SS-5 TCX AFX register */ 642 static void afx_init(hwaddr addr) 643 { 644 DeviceState *dev; 645 SysBusDevice *s; 646 647 dev = qdev_new(TYPE_TCX_AFX); 648 s = SYS_BUS_DEVICE(dev); 649 sysbus_realize_and_unref(s, &error_fatal); 650 651 sysbus_mmio_map(s, 0, addr); 652 } 653 654 static void afx_realize(DeviceState *ds, Error **errp) 655 { 656 AFXState *s = TCX_AFX(ds); 657 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 658 Error *local_err = NULL; 659 660 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4, 661 &local_err); 662 if (local_err) { 663 error_propagate(errp, local_err); 664 return; 665 } 666 667 vmstate_register_ram_global(&s->mem); 668 sysbus_init_mmio(dev, &s->mem); 669 } 670 671 static void afx_class_init(ObjectClass *oc, void *data) 672 { 673 DeviceClass *dc = DEVICE_CLASS(oc); 674 675 dc->realize = afx_realize; 676 } 677 678 static const TypeInfo afx_info = { 679 .name = TYPE_TCX_AFX, 680 .parent = TYPE_SYS_BUS_DEVICE, 681 .instance_size = sizeof(AFXState), 682 .class_init = afx_class_init, 683 }; 684 685 #define TYPE_OPENPROM "openprom" 686 typedef struct PROMState PROMState; 687 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM, 688 TYPE_OPENPROM) 689 690 struct PROMState { 691 SysBusDevice parent_obj; 692 693 MemoryRegion prom; 694 }; 695 696 /* Boot PROM (OpenBIOS) */ 697 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 698 { 699 hwaddr *base_addr = (hwaddr *)opaque; 700 return addr + *base_addr - PROM_VADDR; 701 } 702 703 static void prom_init(hwaddr addr, const char *bios_name) 704 { 705 DeviceState *dev; 706 SysBusDevice *s; 707 char *filename; 708 int ret; 709 710 dev = qdev_new(TYPE_OPENPROM); 711 s = SYS_BUS_DEVICE(dev); 712 sysbus_realize_and_unref(s, &error_fatal); 713 714 sysbus_mmio_map(s, 0, addr); 715 716 /* load boot prom */ 717 if (bios_name == NULL) { 718 bios_name = PROM_FILENAME; 719 } 720 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 721 if (filename) { 722 ret = load_elf(filename, NULL, 723 translate_prom_address, &addr, NULL, 724 NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 725 if (ret < 0 || ret > PROM_SIZE_MAX) { 726 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 727 } 728 g_free(filename); 729 } else { 730 ret = -1; 731 } 732 if (ret < 0 || ret > PROM_SIZE_MAX) { 733 error_report("could not load prom '%s'", bios_name); 734 exit(1); 735 } 736 } 737 738 static void prom_realize(DeviceState *ds, Error **errp) 739 { 740 PROMState *s = OPENPROM(ds); 741 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 742 Error *local_err = NULL; 743 744 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom", 745 PROM_SIZE_MAX, &local_err); 746 if (local_err) { 747 error_propagate(errp, local_err); 748 return; 749 } 750 751 vmstate_register_ram_global(&s->prom); 752 memory_region_set_readonly(&s->prom, true); 753 sysbus_init_mmio(dev, &s->prom); 754 } 755 756 static Property prom_properties[] = { 757 {/* end of property list */}, 758 }; 759 760 static void prom_class_init(ObjectClass *klass, void *data) 761 { 762 DeviceClass *dc = DEVICE_CLASS(klass); 763 764 device_class_set_props(dc, prom_properties); 765 dc->realize = prom_realize; 766 } 767 768 static const TypeInfo prom_info = { 769 .name = TYPE_OPENPROM, 770 .parent = TYPE_SYS_BUS_DEVICE, 771 .instance_size = sizeof(PROMState), 772 .class_init = prom_class_init, 773 }; 774 775 #define TYPE_SUN4M_MEMORY "memory" 776 typedef struct RamDevice RamDevice; 777 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4M_RAM, 778 TYPE_SUN4M_MEMORY) 779 780 struct RamDevice { 781 SysBusDevice parent_obj; 782 HostMemoryBackend *memdev; 783 }; 784 785 /* System RAM */ 786 static void ram_realize(DeviceState *dev, Error **errp) 787 { 788 RamDevice *d = SUN4M_RAM(dev); 789 MemoryRegion *ram = host_memory_backend_get_memory(d->memdev); 790 791 sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram); 792 } 793 794 static void ram_initfn(Object *obj) 795 { 796 RamDevice *d = SUN4M_RAM(obj); 797 object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND, 798 (Object **)&d->memdev, 799 object_property_allow_set_link, 800 OBJ_PROP_LINK_STRONG); 801 object_property_set_description(obj, "memdev", "Set RAM backend" 802 "Valid value is ID of a hostmem backend"); 803 } 804 805 static void ram_class_init(ObjectClass *klass, void *data) 806 { 807 DeviceClass *dc = DEVICE_CLASS(klass); 808 809 dc->realize = ram_realize; 810 } 811 812 static const TypeInfo ram_info = { 813 .name = TYPE_SUN4M_MEMORY, 814 .parent = TYPE_SYS_BUS_DEVICE, 815 .instance_size = sizeof(RamDevice), 816 .instance_init = ram_initfn, 817 .class_init = ram_class_init, 818 }; 819 820 static void cpu_devinit(const char *cpu_type, unsigned int id, 821 uint64_t prom_addr, qemu_irq **cpu_irqs) 822 { 823 SPARCCPU *cpu; 824 CPUSPARCState *env; 825 826 cpu = SPARC_CPU(object_new(cpu_type)); 827 env = &cpu->env; 828 829 cpu_sparc_set_id(env, id); 830 qemu_register_reset(sun4m_cpu_reset, cpu); 831 object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0, 832 &error_fatal); 833 qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); 834 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 835 env->prom_addr = prom_addr; 836 } 837 838 static void dummy_fdc_tc(void *opaque, int irq, int level) 839 { 840 } 841 842 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, 843 MachineState *machine) 844 { 845 DeviceState *slavio_intctl; 846 unsigned int i; 847 Nvram *nvram; 848 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; 849 qemu_irq fdc_tc; 850 unsigned long kernel_size; 851 uint32_t initrd_size; 852 DriveInfo *fd[MAX_FD]; 853 FWCfgState *fw_cfg; 854 DeviceState *dev, *ms_kb_orgate, *serial_orgate; 855 SysBusDevice *s; 856 unsigned int smp_cpus = machine->smp.cpus; 857 unsigned int max_cpus = machine->smp.max_cpus; 858 Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id, 859 TYPE_MEMORY_BACKEND, NULL); 860 NICInfo *nd = &nd_table[0]; 861 862 if (machine->ram_size > hwdef->max_mem) { 863 error_report("Too much memory for this machine: %" PRId64 "," 864 " maximum %" PRId64, 865 machine->ram_size / MiB, hwdef->max_mem / MiB); 866 exit(1); 867 } 868 869 /* init CPUs */ 870 for(i = 0; i < smp_cpus; i++) { 871 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); 872 } 873 874 for (i = smp_cpus; i < MAX_CPUS; i++) 875 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 876 877 /* Create and map RAM frontend */ 878 dev = qdev_new("memory"); 879 object_property_set_link(OBJECT(dev), "memdev", ram_memdev, &error_fatal); 880 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 881 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0); 882 883 /* models without ECC don't trap when missing ram is accessed */ 884 if (!hwdef->ecc_base) { 885 empty_slot_init("ecc", machine->ram_size, 886 hwdef->max_mem - machine->ram_size); 887 } 888 889 prom_init(hwdef->slavio_base, machine->firmware); 890 891 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 892 hwdef->intctl_base + 0x10000ULL, 893 cpu_irqs); 894 895 for (i = 0; i < 32; i++) { 896 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 897 } 898 for (i = 0; i < MAX_CPUS; i++) { 899 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 900 } 901 902 if (hwdef->idreg_base) { 903 idreg_init(hwdef->idreg_base); 904 } 905 906 if (hwdef->afx_base) { 907 afx_init(hwdef->afx_base); 908 } 909 910 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]); 911 912 if (hwdef->iommu_pad_base) { 913 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 914 Software shouldn't use aliased addresses, neither should it crash 915 when does. Using empty_slot instead of aliasing can help with 916 debugging such accesses */ 917 empty_slot_init("iommu.alias", 918 hwdef->iommu_pad_base, hwdef->iommu_pad_len); 919 } 920 921 qemu_check_nic_model(nd, TYPE_LANCE); 922 sparc32_dma_init(hwdef->dma_base, 923 hwdef->esp_base, slavio_irq[18], 924 hwdef->le_base, slavio_irq[16], nd); 925 926 if (graphic_depth != 8 && graphic_depth != 24) { 927 error_report("Unsupported depth: %d", graphic_depth); 928 exit (1); 929 } 930 if (vga_interface_type != VGA_NONE) { 931 if (vga_interface_type == VGA_CG3) { 932 if (graphic_depth != 8) { 933 error_report("Unsupported depth: %d", graphic_depth); 934 exit(1); 935 } 936 937 if (!(graphic_width == 1024 && graphic_height == 768) && 938 !(graphic_width == 1152 && graphic_height == 900)) { 939 error_report("Unsupported resolution: %d x %d", graphic_width, 940 graphic_height); 941 exit(1); 942 } 943 944 /* sbus irq 5 */ 945 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 946 graphic_width, graphic_height, graphic_depth); 947 } else { 948 /* If no display specified, default to TCX */ 949 if (graphic_depth != 8 && graphic_depth != 24) { 950 error_report("Unsupported depth: %d", graphic_depth); 951 exit(1); 952 } 953 954 if (!(graphic_width == 1024 && graphic_height == 768)) { 955 error_report("Unsupported resolution: %d x %d", 956 graphic_width, graphic_height); 957 exit(1); 958 } 959 960 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 961 graphic_width, graphic_height, graphic_depth); 962 } 963 } 964 965 for (i = 0; i < MAX_VSIMMS; i++) { 966 /* vsimm registers probed by OBP */ 967 if (hwdef->vsimm[i].reg_base) { 968 char *name = g_strdup_printf("vsimm[%d]", i); 969 empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000); 970 g_free(name); 971 } 972 } 973 974 if (hwdef->sx_base) { 975 create_unimplemented_device("sun-sx", hwdef->sx_base, 0x2000); 976 } 977 978 dev = qdev_new("sysbus-m48t08"); 979 qdev_prop_set_int32(dev, "base-year", 1968); 980 s = SYS_BUS_DEVICE(dev); 981 sysbus_realize_and_unref(s, &error_fatal); 982 sysbus_connect_irq(s, 0, slavio_irq[0]); 983 sysbus_mmio_map(s, 0, hwdef->nvram_base); 984 nvram = NVRAM(dev); 985 986 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 987 988 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 989 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 990 dev = qdev_new(TYPE_ESCC); 991 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics); 992 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 993 qdev_prop_set_uint32(dev, "it_shift", 1); 994 qdev_prop_set_chr(dev, "chrB", NULL); 995 qdev_prop_set_chr(dev, "chrA", NULL); 996 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse); 997 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd); 998 s = SYS_BUS_DEVICE(dev); 999 sysbus_realize_and_unref(s, &error_fatal); 1000 sysbus_mmio_map(s, 0, hwdef->ms_kb_base); 1001 1002 /* Logically OR both its IRQs together */ 1003 ms_kb_orgate = DEVICE(object_new(TYPE_OR_IRQ)); 1004 object_property_set_int(OBJECT(ms_kb_orgate), "num-lines", 2, &error_fatal); 1005 qdev_realize_and_unref(ms_kb_orgate, NULL, &error_fatal); 1006 sysbus_connect_irq(s, 0, qdev_get_gpio_in(ms_kb_orgate, 0)); 1007 sysbus_connect_irq(s, 1, qdev_get_gpio_in(ms_kb_orgate, 1)); 1008 qdev_connect_gpio_out(DEVICE(ms_kb_orgate), 0, slavio_irq[14]); 1009 1010 dev = qdev_new(TYPE_ESCC); 1011 qdev_prop_set_uint32(dev, "disabled", 0); 1012 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 1013 qdev_prop_set_uint32(dev, "it_shift", 1); 1014 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 1015 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 1016 qdev_prop_set_uint32(dev, "chnBtype", escc_serial); 1017 qdev_prop_set_uint32(dev, "chnAtype", escc_serial); 1018 1019 s = SYS_BUS_DEVICE(dev); 1020 sysbus_realize_and_unref(s, &error_fatal); 1021 sysbus_mmio_map(s, 0, hwdef->serial_base); 1022 1023 /* Logically OR both its IRQs together */ 1024 serial_orgate = DEVICE(object_new(TYPE_OR_IRQ)); 1025 object_property_set_int(OBJECT(serial_orgate), "num-lines", 2, 1026 &error_fatal); 1027 qdev_realize_and_unref(serial_orgate, NULL, &error_fatal); 1028 sysbus_connect_irq(s, 0, qdev_get_gpio_in(serial_orgate, 0)); 1029 sysbus_connect_irq(s, 1, qdev_get_gpio_in(serial_orgate, 1)); 1030 qdev_connect_gpio_out(DEVICE(serial_orgate), 0, slavio_irq[15]); 1031 1032 if (hwdef->apc_base) { 1033 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); 1034 } 1035 1036 if (hwdef->fd_base) { 1037 /* there is zero or one floppy drive */ 1038 memset(fd, 0, sizeof(fd)); 1039 fd[0] = drive_get(IF_FLOPPY, 0, 0); 1040 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 1041 &fdc_tc); 1042 } else { 1043 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); 1044 } 1045 1046 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 1047 slavio_irq[30], fdc_tc); 1048 1049 if (hwdef->cs_base) { 1050 sysbus_create_simple("sun-CS4231", hwdef->cs_base, 1051 slavio_irq[5]); 1052 } 1053 1054 if (hwdef->dbri_base) { 1055 /* ISDN chip with attached CS4215 audio codec */ 1056 /* prom space */ 1057 create_unimplemented_device("sun-DBRI.prom", 1058 hwdef->dbri_base + 0x1000, 0x30); 1059 /* reg space */ 1060 create_unimplemented_device("sun-DBRI", 1061 hwdef->dbri_base + 0x10000, 0x100); 1062 } 1063 1064 if (hwdef->bpp_base) { 1065 /* parallel port */ 1066 create_unimplemented_device("sun-bpp", hwdef->bpp_base, 0x20); 1067 } 1068 1069 initrd_size = 0; 1070 kernel_size = sun4m_load_kernel(machine->kernel_filename, 1071 machine->initrd_filename, 1072 machine->ram_size, &initrd_size); 1073 1074 nvram_init(nvram, (uint8_t *)&nd->macaddr, machine->kernel_cmdline, 1075 machine->boot_order, machine->ram_size, kernel_size, 1076 graphic_width, graphic_height, graphic_depth, 1077 hwdef->nvram_machine_id, "Sun4m"); 1078 1079 if (hwdef->ecc_base) 1080 ecc_init(hwdef->ecc_base, slavio_irq[28], 1081 hwdef->ecc_version); 1082 1083 dev = qdev_new(TYPE_FW_CFG_MEM); 1084 fw_cfg = FW_CFG(dev); 1085 qdev_prop_set_uint32(dev, "data_width", 1); 1086 qdev_prop_set_bit(dev, "dma_enabled", false); 1087 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1088 OBJECT(fw_cfg)); 1089 s = SYS_BUS_DEVICE(dev); 1090 sysbus_realize_and_unref(s, &error_fatal); 1091 sysbus_mmio_map(s, 0, CFG_ADDR); 1092 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 1093 1094 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 1095 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1096 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 1097 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1098 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1099 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1100 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1101 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1102 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1103 if (machine->kernel_cmdline) { 1104 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1105 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1106 machine->kernel_cmdline); 1107 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 1108 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1109 strlen(machine->kernel_cmdline) + 1); 1110 } else { 1111 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1112 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1113 } 1114 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1115 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1116 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 1117 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1118 } 1119 1120 enum { 1121 ss5_id = 32, 1122 vger_id, 1123 lx_id, 1124 ss4_id, 1125 scls_id, 1126 sbook_id, 1127 ss10_id = 64, 1128 ss20_id, 1129 ss600mp_id, 1130 }; 1131 1132 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1133 /* SS-5 */ 1134 { 1135 .iommu_base = 0x10000000, 1136 .iommu_pad_base = 0x10004000, 1137 .iommu_pad_len = 0x0fffb000, 1138 .tcx_base = 0x50000000, 1139 .cs_base = 0x6c000000, 1140 .slavio_base = 0x70000000, 1141 .ms_kb_base = 0x71000000, 1142 .serial_base = 0x71100000, 1143 .nvram_base = 0x71200000, 1144 .fd_base = 0x71400000, 1145 .counter_base = 0x71d00000, 1146 .intctl_base = 0x71e00000, 1147 .idreg_base = 0x78000000, 1148 .dma_base = 0x78400000, 1149 .esp_base = 0x78800000, 1150 .le_base = 0x78c00000, 1151 .apc_base = 0x6a000000, 1152 .afx_base = 0x6e000000, 1153 .aux1_base = 0x71900000, 1154 .aux2_base = 0x71910000, 1155 .nvram_machine_id = 0x80, 1156 .machine_id = ss5_id, 1157 .iommu_version = 0x05000000, 1158 .max_mem = 0x10000000, 1159 }, 1160 /* SS-10 */ 1161 { 1162 .iommu_base = 0xfe0000000ULL, 1163 .tcx_base = 0xe20000000ULL, 1164 .slavio_base = 0xff0000000ULL, 1165 .ms_kb_base = 0xff1000000ULL, 1166 .serial_base = 0xff1100000ULL, 1167 .nvram_base = 0xff1200000ULL, 1168 .fd_base = 0xff1700000ULL, 1169 .counter_base = 0xff1300000ULL, 1170 .intctl_base = 0xff1400000ULL, 1171 .idreg_base = 0xef0000000ULL, 1172 .dma_base = 0xef0400000ULL, 1173 .esp_base = 0xef0800000ULL, 1174 .le_base = 0xef0c00000ULL, 1175 .apc_base = 0xefa000000ULL, // XXX should not exist 1176 .aux1_base = 0xff1800000ULL, 1177 .aux2_base = 0xff1a01000ULL, 1178 .ecc_base = 0xf00000000ULL, 1179 .ecc_version = 0x10000000, // version 0, implementation 1 1180 .nvram_machine_id = 0x72, 1181 .machine_id = ss10_id, 1182 .iommu_version = 0x03000000, 1183 .max_mem = 0xf00000000ULL, 1184 }, 1185 /* SS-600MP */ 1186 { 1187 .iommu_base = 0xfe0000000ULL, 1188 .tcx_base = 0xe20000000ULL, 1189 .slavio_base = 0xff0000000ULL, 1190 .ms_kb_base = 0xff1000000ULL, 1191 .serial_base = 0xff1100000ULL, 1192 .nvram_base = 0xff1200000ULL, 1193 .counter_base = 0xff1300000ULL, 1194 .intctl_base = 0xff1400000ULL, 1195 .dma_base = 0xef0081000ULL, 1196 .esp_base = 0xef0080000ULL, 1197 .le_base = 0xef0060000ULL, 1198 .apc_base = 0xefa000000ULL, // XXX should not exist 1199 .aux1_base = 0xff1800000ULL, 1200 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1201 .ecc_base = 0xf00000000ULL, 1202 .ecc_version = 0x00000000, // version 0, implementation 0 1203 .nvram_machine_id = 0x71, 1204 .machine_id = ss600mp_id, 1205 .iommu_version = 0x01000000, 1206 .max_mem = 0xf00000000ULL, 1207 }, 1208 /* SS-20 */ 1209 { 1210 .iommu_base = 0xfe0000000ULL, 1211 .tcx_base = 0xe20000000ULL, 1212 .slavio_base = 0xff0000000ULL, 1213 .ms_kb_base = 0xff1000000ULL, 1214 .serial_base = 0xff1100000ULL, 1215 .nvram_base = 0xff1200000ULL, 1216 .fd_base = 0xff1700000ULL, 1217 .counter_base = 0xff1300000ULL, 1218 .intctl_base = 0xff1400000ULL, 1219 .idreg_base = 0xef0000000ULL, 1220 .dma_base = 0xef0400000ULL, 1221 .esp_base = 0xef0800000ULL, 1222 .le_base = 0xef0c00000ULL, 1223 .bpp_base = 0xef4800000ULL, 1224 .apc_base = 0xefa000000ULL, // XXX should not exist 1225 .aux1_base = 0xff1800000ULL, 1226 .aux2_base = 0xff1a01000ULL, 1227 .dbri_base = 0xee0000000ULL, 1228 .sx_base = 0xf80000000ULL, 1229 .vsimm = { 1230 { 1231 .reg_base = 0x9c000000ULL, 1232 .vram_base = 0xfc000000ULL 1233 }, { 1234 .reg_base = 0x90000000ULL, 1235 .vram_base = 0xf0000000ULL 1236 }, { 1237 .reg_base = 0x94000000ULL 1238 }, { 1239 .reg_base = 0x98000000ULL 1240 } 1241 }, 1242 .ecc_base = 0xf00000000ULL, 1243 .ecc_version = 0x20000000, // version 0, implementation 2 1244 .nvram_machine_id = 0x72, 1245 .machine_id = ss20_id, 1246 .iommu_version = 0x13000000, 1247 .max_mem = 0xf00000000ULL, 1248 }, 1249 /* Voyager */ 1250 { 1251 .iommu_base = 0x10000000, 1252 .tcx_base = 0x50000000, 1253 .slavio_base = 0x70000000, 1254 .ms_kb_base = 0x71000000, 1255 .serial_base = 0x71100000, 1256 .nvram_base = 0x71200000, 1257 .fd_base = 0x71400000, 1258 .counter_base = 0x71d00000, 1259 .intctl_base = 0x71e00000, 1260 .idreg_base = 0x78000000, 1261 .dma_base = 0x78400000, 1262 .esp_base = 0x78800000, 1263 .le_base = 0x78c00000, 1264 .apc_base = 0x71300000, // pmc 1265 .aux1_base = 0x71900000, 1266 .aux2_base = 0x71910000, 1267 .nvram_machine_id = 0x80, 1268 .machine_id = vger_id, 1269 .iommu_version = 0x05000000, 1270 .max_mem = 0x10000000, 1271 }, 1272 /* LX */ 1273 { 1274 .iommu_base = 0x10000000, 1275 .iommu_pad_base = 0x10004000, 1276 .iommu_pad_len = 0x0fffb000, 1277 .tcx_base = 0x50000000, 1278 .slavio_base = 0x70000000, 1279 .ms_kb_base = 0x71000000, 1280 .serial_base = 0x71100000, 1281 .nvram_base = 0x71200000, 1282 .fd_base = 0x71400000, 1283 .counter_base = 0x71d00000, 1284 .intctl_base = 0x71e00000, 1285 .idreg_base = 0x78000000, 1286 .dma_base = 0x78400000, 1287 .esp_base = 0x78800000, 1288 .le_base = 0x78c00000, 1289 .aux1_base = 0x71900000, 1290 .aux2_base = 0x71910000, 1291 .nvram_machine_id = 0x80, 1292 .machine_id = lx_id, 1293 .iommu_version = 0x04000000, 1294 .max_mem = 0x10000000, 1295 }, 1296 /* SS-4 */ 1297 { 1298 .iommu_base = 0x10000000, 1299 .tcx_base = 0x50000000, 1300 .cs_base = 0x6c000000, 1301 .slavio_base = 0x70000000, 1302 .ms_kb_base = 0x71000000, 1303 .serial_base = 0x71100000, 1304 .nvram_base = 0x71200000, 1305 .fd_base = 0x71400000, 1306 .counter_base = 0x71d00000, 1307 .intctl_base = 0x71e00000, 1308 .idreg_base = 0x78000000, 1309 .dma_base = 0x78400000, 1310 .esp_base = 0x78800000, 1311 .le_base = 0x78c00000, 1312 .apc_base = 0x6a000000, 1313 .aux1_base = 0x71900000, 1314 .aux2_base = 0x71910000, 1315 .nvram_machine_id = 0x80, 1316 .machine_id = ss4_id, 1317 .iommu_version = 0x05000000, 1318 .max_mem = 0x10000000, 1319 }, 1320 /* SPARCClassic */ 1321 { 1322 .iommu_base = 0x10000000, 1323 .tcx_base = 0x50000000, 1324 .slavio_base = 0x70000000, 1325 .ms_kb_base = 0x71000000, 1326 .serial_base = 0x71100000, 1327 .nvram_base = 0x71200000, 1328 .fd_base = 0x71400000, 1329 .counter_base = 0x71d00000, 1330 .intctl_base = 0x71e00000, 1331 .idreg_base = 0x78000000, 1332 .dma_base = 0x78400000, 1333 .esp_base = 0x78800000, 1334 .le_base = 0x78c00000, 1335 .apc_base = 0x6a000000, 1336 .aux1_base = 0x71900000, 1337 .aux2_base = 0x71910000, 1338 .nvram_machine_id = 0x80, 1339 .machine_id = scls_id, 1340 .iommu_version = 0x05000000, 1341 .max_mem = 0x10000000, 1342 }, 1343 /* SPARCbook */ 1344 { 1345 .iommu_base = 0x10000000, 1346 .tcx_base = 0x50000000, // XXX 1347 .slavio_base = 0x70000000, 1348 .ms_kb_base = 0x71000000, 1349 .serial_base = 0x71100000, 1350 .nvram_base = 0x71200000, 1351 .fd_base = 0x71400000, 1352 .counter_base = 0x71d00000, 1353 .intctl_base = 0x71e00000, 1354 .idreg_base = 0x78000000, 1355 .dma_base = 0x78400000, 1356 .esp_base = 0x78800000, 1357 .le_base = 0x78c00000, 1358 .apc_base = 0x6a000000, 1359 .aux1_base = 0x71900000, 1360 .aux2_base = 0x71910000, 1361 .nvram_machine_id = 0x80, 1362 .machine_id = sbook_id, 1363 .iommu_version = 0x05000000, 1364 .max_mem = 0x10000000, 1365 }, 1366 }; 1367 1368 /* SPARCstation 5 hardware initialisation */ 1369 static void ss5_init(MachineState *machine) 1370 { 1371 sun4m_hw_init(&sun4m_hwdefs[0], machine); 1372 } 1373 1374 /* SPARCstation 10 hardware initialisation */ 1375 static void ss10_init(MachineState *machine) 1376 { 1377 sun4m_hw_init(&sun4m_hwdefs[1], machine); 1378 } 1379 1380 /* SPARCserver 600MP hardware initialisation */ 1381 static void ss600mp_init(MachineState *machine) 1382 { 1383 sun4m_hw_init(&sun4m_hwdefs[2], machine); 1384 } 1385 1386 /* SPARCstation 20 hardware initialisation */ 1387 static void ss20_init(MachineState *machine) 1388 { 1389 sun4m_hw_init(&sun4m_hwdefs[3], machine); 1390 } 1391 1392 /* SPARCstation Voyager hardware initialisation */ 1393 static void vger_init(MachineState *machine) 1394 { 1395 sun4m_hw_init(&sun4m_hwdefs[4], machine); 1396 } 1397 1398 /* SPARCstation LX hardware initialisation */ 1399 static void ss_lx_init(MachineState *machine) 1400 { 1401 sun4m_hw_init(&sun4m_hwdefs[5], machine); 1402 } 1403 1404 /* SPARCstation 4 hardware initialisation */ 1405 static void ss4_init(MachineState *machine) 1406 { 1407 sun4m_hw_init(&sun4m_hwdefs[6], machine); 1408 } 1409 1410 /* SPARCClassic hardware initialisation */ 1411 static void scls_init(MachineState *machine) 1412 { 1413 sun4m_hw_init(&sun4m_hwdefs[7], machine); 1414 } 1415 1416 /* SPARCbook hardware initialisation */ 1417 static void sbook_init(MachineState *machine) 1418 { 1419 sun4m_hw_init(&sun4m_hwdefs[8], machine); 1420 } 1421 1422 static void ss5_class_init(ObjectClass *oc, void *data) 1423 { 1424 MachineClass *mc = MACHINE_CLASS(oc); 1425 1426 mc->desc = "Sun4m platform, SPARCstation 5"; 1427 mc->init = ss5_init; 1428 mc->block_default_type = IF_SCSI; 1429 mc->is_default = true; 1430 mc->default_boot_order = "c"; 1431 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1432 mc->default_display = "tcx"; 1433 mc->default_ram_id = "sun4m.ram"; 1434 } 1435 1436 static const TypeInfo ss5_type = { 1437 .name = MACHINE_TYPE_NAME("SS-5"), 1438 .parent = TYPE_SUN4M_MACHINE, 1439 .class_init = ss5_class_init, 1440 }; 1441 1442 static void ss10_class_init(ObjectClass *oc, void *data) 1443 { 1444 MachineClass *mc = MACHINE_CLASS(oc); 1445 1446 mc->desc = "Sun4m platform, SPARCstation 10"; 1447 mc->init = ss10_init; 1448 mc->block_default_type = IF_SCSI; 1449 mc->max_cpus = 4; 1450 mc->default_boot_order = "c"; 1451 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1452 mc->default_display = "tcx"; 1453 mc->default_ram_id = "sun4m.ram"; 1454 } 1455 1456 static const TypeInfo ss10_type = { 1457 .name = MACHINE_TYPE_NAME("SS-10"), 1458 .parent = TYPE_SUN4M_MACHINE, 1459 .class_init = ss10_class_init, 1460 }; 1461 1462 static void ss600mp_class_init(ObjectClass *oc, void *data) 1463 { 1464 MachineClass *mc = MACHINE_CLASS(oc); 1465 1466 mc->desc = "Sun4m platform, SPARCserver 600MP"; 1467 mc->init = ss600mp_init; 1468 mc->block_default_type = IF_SCSI; 1469 mc->max_cpus = 4; 1470 mc->default_boot_order = "c"; 1471 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1472 mc->default_display = "tcx"; 1473 mc->default_ram_id = "sun4m.ram"; 1474 } 1475 1476 static const TypeInfo ss600mp_type = { 1477 .name = MACHINE_TYPE_NAME("SS-600MP"), 1478 .parent = TYPE_SUN4M_MACHINE, 1479 .class_init = ss600mp_class_init, 1480 }; 1481 1482 static void ss20_class_init(ObjectClass *oc, void *data) 1483 { 1484 MachineClass *mc = MACHINE_CLASS(oc); 1485 1486 mc->desc = "Sun4m platform, SPARCstation 20"; 1487 mc->init = ss20_init; 1488 mc->block_default_type = IF_SCSI; 1489 mc->max_cpus = 4; 1490 mc->default_boot_order = "c"; 1491 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1492 mc->default_display = "tcx"; 1493 mc->default_ram_id = "sun4m.ram"; 1494 } 1495 1496 static const TypeInfo ss20_type = { 1497 .name = MACHINE_TYPE_NAME("SS-20"), 1498 .parent = TYPE_SUN4M_MACHINE, 1499 .class_init = ss20_class_init, 1500 }; 1501 1502 static void voyager_class_init(ObjectClass *oc, void *data) 1503 { 1504 MachineClass *mc = MACHINE_CLASS(oc); 1505 1506 mc->desc = "Sun4m platform, SPARCstation Voyager"; 1507 mc->init = vger_init; 1508 mc->block_default_type = IF_SCSI; 1509 mc->default_boot_order = "c"; 1510 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1511 mc->default_display = "tcx"; 1512 mc->default_ram_id = "sun4m.ram"; 1513 } 1514 1515 static const TypeInfo voyager_type = { 1516 .name = MACHINE_TYPE_NAME("Voyager"), 1517 .parent = TYPE_SUN4M_MACHINE, 1518 .class_init = voyager_class_init, 1519 }; 1520 1521 static void ss_lx_class_init(ObjectClass *oc, void *data) 1522 { 1523 MachineClass *mc = MACHINE_CLASS(oc); 1524 1525 mc->desc = "Sun4m platform, SPARCstation LX"; 1526 mc->init = ss_lx_init; 1527 mc->block_default_type = IF_SCSI; 1528 mc->default_boot_order = "c"; 1529 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1530 mc->default_display = "tcx"; 1531 mc->default_ram_id = "sun4m.ram"; 1532 } 1533 1534 static const TypeInfo ss_lx_type = { 1535 .name = MACHINE_TYPE_NAME("LX"), 1536 .parent = TYPE_SUN4M_MACHINE, 1537 .class_init = ss_lx_class_init, 1538 }; 1539 1540 static void ss4_class_init(ObjectClass *oc, void *data) 1541 { 1542 MachineClass *mc = MACHINE_CLASS(oc); 1543 1544 mc->desc = "Sun4m platform, SPARCstation 4"; 1545 mc->init = ss4_init; 1546 mc->block_default_type = IF_SCSI; 1547 mc->default_boot_order = "c"; 1548 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1549 mc->default_display = "tcx"; 1550 mc->default_ram_id = "sun4m.ram"; 1551 } 1552 1553 static const TypeInfo ss4_type = { 1554 .name = MACHINE_TYPE_NAME("SS-4"), 1555 .parent = TYPE_SUN4M_MACHINE, 1556 .class_init = ss4_class_init, 1557 }; 1558 1559 static void scls_class_init(ObjectClass *oc, void *data) 1560 { 1561 MachineClass *mc = MACHINE_CLASS(oc); 1562 1563 mc->desc = "Sun4m platform, SPARCClassic"; 1564 mc->init = scls_init; 1565 mc->block_default_type = IF_SCSI; 1566 mc->default_boot_order = "c"; 1567 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1568 mc->default_display = "tcx"; 1569 mc->default_ram_id = "sun4m.ram"; 1570 } 1571 1572 static const TypeInfo scls_type = { 1573 .name = MACHINE_TYPE_NAME("SPARCClassic"), 1574 .parent = TYPE_SUN4M_MACHINE, 1575 .class_init = scls_class_init, 1576 }; 1577 1578 static void sbook_class_init(ObjectClass *oc, void *data) 1579 { 1580 MachineClass *mc = MACHINE_CLASS(oc); 1581 1582 mc->desc = "Sun4m platform, SPARCbook"; 1583 mc->init = sbook_init; 1584 mc->block_default_type = IF_SCSI; 1585 mc->default_boot_order = "c"; 1586 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1587 mc->default_display = "tcx"; 1588 mc->default_ram_id = "sun4m.ram"; 1589 } 1590 1591 static const TypeInfo sbook_type = { 1592 .name = MACHINE_TYPE_NAME("SPARCbook"), 1593 .parent = TYPE_SUN4M_MACHINE, 1594 .class_init = sbook_class_init, 1595 }; 1596 1597 static const TypeInfo sun4m_machine_types[] = { 1598 { 1599 .name = TYPE_SUN4M_MACHINE, 1600 .parent = TYPE_MACHINE, 1601 .abstract = true, 1602 } 1603 }; 1604 1605 DEFINE_TYPES(sun4m_machine_types) 1606 1607 static void sun4m_register_types(void) 1608 { 1609 type_register_static(&idreg_info); 1610 type_register_static(&afx_info); 1611 type_register_static(&prom_info); 1612 type_register_static(&ram_info); 1613 1614 type_register_static(&ss5_type); 1615 type_register_static(&ss10_type); 1616 type_register_static(&ss600mp_type); 1617 type_register_static(&ss20_type); 1618 type_register_static(&voyager_type); 1619 type_register_static(&ss_lx_type); 1620 type_register_static(&ss4_type); 1621 type_register_static(&scls_type); 1622 type_register_static(&sbook_type); 1623 } 1624 1625 type_init(sun4m_register_types) 1626