1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/sysbus.h" 29 #include "qemu/error-report.h" 30 #include "qemu/timer.h" 31 #include "hw/sparc/sun4m.h" 32 #include "hw/timer/m48t59.h" 33 #include "hw/sparc/sparc32_dma.h" 34 #include "hw/block/fdc.h" 35 #include "sysemu/sysemu.h" 36 #include "net/net.h" 37 #include "hw/boards.h" 38 #include "hw/scsi/esp.h" 39 #include "hw/i386/pc.h" 40 #include "hw/isa/isa.h" 41 #include "hw/nvram/sun_nvram.h" 42 #include "hw/nvram/chrp_nvram.h" 43 #include "hw/nvram/fw_cfg.h" 44 #include "hw/char/escc.h" 45 #include "hw/empty_slot.h" 46 #include "hw/loader.h" 47 #include "elf.h" 48 #include "sysemu/block-backend.h" 49 #include "trace.h" 50 #include "qemu/cutils.h" 51 52 /* 53 * Sun4m architecture was used in the following machines: 54 * 55 * SPARCserver 6xxMP/xx 56 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 57 * SPARCclassic X (4/10) 58 * SPARCstation LX/ZX (4/30) 59 * SPARCstation Voyager 60 * SPARCstation 10/xx, SPARCserver 10/xx 61 * SPARCstation 5, SPARCserver 5 62 * SPARCstation 20/xx, SPARCserver 20 63 * SPARCstation 4 64 * 65 * See for example: http://www.sunhelp.org/faq/sunref1.html 66 */ 67 68 #define KERNEL_LOAD_ADDR 0x00004000 69 #define CMDLINE_ADDR 0x007ff000 70 #define INITRD_LOAD_ADDR 0x00800000 71 #define PROM_SIZE_MAX (1024 * 1024) 72 #define PROM_VADDR 0xffd00000 73 #define PROM_FILENAME "openbios-sparc32" 74 #define CFG_ADDR 0xd00000510ULL 75 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 76 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 77 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 78 79 #define MAX_CPUS 16 80 #define MAX_PILS 16 81 #define MAX_VSIMMS 4 82 83 #define ESCC_CLOCK 4915200 84 85 struct sun4m_hwdef { 86 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 87 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 88 hwaddr serial_base, fd_base; 89 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 90 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 91 hwaddr bpp_base, dbri_base, sx_base; 92 struct { 93 hwaddr reg_base, vram_base; 94 } vsimm[MAX_VSIMMS]; 95 hwaddr ecc_base; 96 uint64_t max_mem; 97 uint32_t ecc_version; 98 uint32_t iommu_version; 99 uint16_t machine_id; 100 uint8_t nvram_machine_id; 101 }; 102 103 void DMA_init(ISABus *bus, int high_page_enable) 104 { 105 } 106 107 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 108 Error **errp) 109 { 110 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 111 } 112 113 static void nvram_init(Nvram *nvram, uint8_t *macaddr, 114 const char *cmdline, const char *boot_devices, 115 ram_addr_t RAM_size, uint32_t kernel_size, 116 int width, int height, int depth, 117 int nvram_machine_id, const char *arch) 118 { 119 unsigned int i; 120 int sysp_end; 121 uint8_t image[0x1ff0]; 122 NvramClass *k = NVRAM_GET_CLASS(nvram); 123 124 memset(image, '\0', sizeof(image)); 125 126 /* OpenBIOS nvram variables partition */ 127 sysp_end = chrp_nvram_create_system_partition(image, 0); 128 129 /* Free space partition */ 130 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 131 132 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 133 nvram_machine_id); 134 135 for (i = 0; i < sizeof(image); i++) { 136 (k->write)(nvram, i, image[i]); 137 } 138 } 139 140 void cpu_check_irqs(CPUSPARCState *env) 141 { 142 CPUState *cs; 143 144 /* We should be holding the BQL before we mess with IRQs */ 145 g_assert(qemu_mutex_iothread_locked()); 146 147 if (env->pil_in && (env->interrupt_index == 0 || 148 (env->interrupt_index & ~15) == TT_EXTINT)) { 149 unsigned int i; 150 151 for (i = 15; i > 0; i--) { 152 if (env->pil_in & (1 << i)) { 153 int old_interrupt = env->interrupt_index; 154 155 env->interrupt_index = TT_EXTINT | i; 156 if (old_interrupt != env->interrupt_index) { 157 cs = CPU(sparc_env_get_cpu(env)); 158 trace_sun4m_cpu_interrupt(i); 159 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 160 } 161 break; 162 } 163 } 164 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 165 cs = CPU(sparc_env_get_cpu(env)); 166 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 167 env->interrupt_index = 0; 168 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 169 } 170 } 171 172 static void cpu_kick_irq(SPARCCPU *cpu) 173 { 174 CPUSPARCState *env = &cpu->env; 175 CPUState *cs = CPU(cpu); 176 177 cs->halted = 0; 178 cpu_check_irqs(env); 179 qemu_cpu_kick(cs); 180 } 181 182 static void cpu_set_irq(void *opaque, int irq, int level) 183 { 184 SPARCCPU *cpu = opaque; 185 CPUSPARCState *env = &cpu->env; 186 187 if (level) { 188 trace_sun4m_cpu_set_irq_raise(irq); 189 env->pil_in |= 1 << irq; 190 cpu_kick_irq(cpu); 191 } else { 192 trace_sun4m_cpu_set_irq_lower(irq); 193 env->pil_in &= ~(1 << irq); 194 cpu_check_irqs(env); 195 } 196 } 197 198 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 199 { 200 } 201 202 static void main_cpu_reset(void *opaque) 203 { 204 SPARCCPU *cpu = opaque; 205 CPUState *cs = CPU(cpu); 206 207 cpu_reset(cs); 208 cs->halted = 0; 209 } 210 211 static void secondary_cpu_reset(void *opaque) 212 { 213 SPARCCPU *cpu = opaque; 214 CPUState *cs = CPU(cpu); 215 216 cpu_reset(cs); 217 cs->halted = 1; 218 } 219 220 static void cpu_halt_signal(void *opaque, int irq, int level) 221 { 222 if (level && current_cpu) { 223 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 224 } 225 } 226 227 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 228 { 229 return addr - 0xf0000000ULL; 230 } 231 232 static unsigned long sun4m_load_kernel(const char *kernel_filename, 233 const char *initrd_filename, 234 ram_addr_t RAM_size) 235 { 236 int linux_boot; 237 unsigned int i; 238 long initrd_size, kernel_size; 239 uint8_t *ptr; 240 241 linux_boot = (kernel_filename != NULL); 242 243 kernel_size = 0; 244 if (linux_boot) { 245 int bswap_needed; 246 247 #ifdef BSWAP_NEEDED 248 bswap_needed = 1; 249 #else 250 bswap_needed = 0; 251 #endif 252 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 253 NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 254 if (kernel_size < 0) 255 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 256 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 257 TARGET_PAGE_SIZE); 258 if (kernel_size < 0) 259 kernel_size = load_image_targphys(kernel_filename, 260 KERNEL_LOAD_ADDR, 261 RAM_size - KERNEL_LOAD_ADDR); 262 if (kernel_size < 0) { 263 fprintf(stderr, "qemu: could not load kernel '%s'\n", 264 kernel_filename); 265 exit(1); 266 } 267 268 /* load initrd */ 269 initrd_size = 0; 270 if (initrd_filename) { 271 initrd_size = load_image_targphys(initrd_filename, 272 INITRD_LOAD_ADDR, 273 RAM_size - INITRD_LOAD_ADDR); 274 if (initrd_size < 0) { 275 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 276 initrd_filename); 277 exit(1); 278 } 279 } 280 if (initrd_size > 0) { 281 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 282 ptr = rom_ptr(KERNEL_LOAD_ADDR + i); 283 if (ldl_p(ptr) == 0x48647253) { // HdrS 284 stl_p(ptr + 16, INITRD_LOAD_ADDR); 285 stl_p(ptr + 20, initrd_size); 286 break; 287 } 288 } 289 } 290 } 291 return kernel_size; 292 } 293 294 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 295 { 296 DeviceState *dev; 297 SysBusDevice *s; 298 299 dev = qdev_create(NULL, TYPE_SUN4M_IOMMU); 300 qdev_prop_set_uint32(dev, "version", version); 301 qdev_init_nofail(dev); 302 s = SYS_BUS_DEVICE(dev); 303 sysbus_connect_irq(s, 0, irq); 304 sysbus_mmio_map(s, 0, addr); 305 306 return s; 307 } 308 309 static void *sparc32_dma_init(hwaddr dma_base, 310 hwaddr esp_base, qemu_irq espdma_irq, 311 hwaddr le_base, qemu_irq ledma_irq) 312 { 313 DeviceState *dma; 314 ESPDMADeviceState *espdma; 315 LEDMADeviceState *ledma; 316 SysBusESPState *esp; 317 SysBusPCNetState *lance; 318 319 dma = qdev_create(NULL, TYPE_SPARC32_DMA); 320 qdev_init_nofail(dma); 321 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); 322 323 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( 324 OBJECT(dma), "espdma")); 325 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); 326 327 esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp")); 328 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base); 329 330 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( 331 OBJECT(dma), "ledma")); 332 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq); 333 334 lance = SYSBUS_PCNET(object_resolve_path_component( 335 OBJECT(ledma), "lance")); 336 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base); 337 338 return dma; 339 } 340 341 static DeviceState *slavio_intctl_init(hwaddr addr, 342 hwaddr addrg, 343 qemu_irq **parent_irq) 344 { 345 DeviceState *dev; 346 SysBusDevice *s; 347 unsigned int i, j; 348 349 dev = qdev_create(NULL, "slavio_intctl"); 350 qdev_init_nofail(dev); 351 352 s = SYS_BUS_DEVICE(dev); 353 354 for (i = 0; i < MAX_CPUS; i++) { 355 for (j = 0; j < MAX_PILS; j++) { 356 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 357 } 358 } 359 sysbus_mmio_map(s, 0, addrg); 360 for (i = 0; i < MAX_CPUS; i++) { 361 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 362 } 363 364 return dev; 365 } 366 367 #define SYS_TIMER_OFFSET 0x10000ULL 368 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 369 370 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 371 qemu_irq *cpu_irqs, unsigned int num_cpus) 372 { 373 DeviceState *dev; 374 SysBusDevice *s; 375 unsigned int i; 376 377 dev = qdev_create(NULL, "slavio_timer"); 378 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 379 qdev_init_nofail(dev); 380 s = SYS_BUS_DEVICE(dev); 381 sysbus_connect_irq(s, 0, master_irq); 382 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 383 384 for (i = 0; i < MAX_CPUS; i++) { 385 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 386 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 387 } 388 } 389 390 static qemu_irq slavio_system_powerdown; 391 392 static void slavio_powerdown_req(Notifier *n, void *opaque) 393 { 394 qemu_irq_raise(slavio_system_powerdown); 395 } 396 397 static Notifier slavio_system_powerdown_notifier = { 398 .notify = slavio_powerdown_req 399 }; 400 401 #define MISC_LEDS 0x01600000 402 #define MISC_CFG 0x01800000 403 #define MISC_DIAG 0x01a00000 404 #define MISC_MDM 0x01b00000 405 #define MISC_SYS 0x01f00000 406 407 static void slavio_misc_init(hwaddr base, 408 hwaddr aux1_base, 409 hwaddr aux2_base, qemu_irq irq, 410 qemu_irq fdc_tc) 411 { 412 DeviceState *dev; 413 SysBusDevice *s; 414 415 dev = qdev_create(NULL, "slavio_misc"); 416 qdev_init_nofail(dev); 417 s = SYS_BUS_DEVICE(dev); 418 if (base) { 419 /* 8 bit registers */ 420 /* Slavio control */ 421 sysbus_mmio_map(s, 0, base + MISC_CFG); 422 /* Diagnostics */ 423 sysbus_mmio_map(s, 1, base + MISC_DIAG); 424 /* Modem control */ 425 sysbus_mmio_map(s, 2, base + MISC_MDM); 426 /* 16 bit registers */ 427 /* ss600mp diag LEDs */ 428 sysbus_mmio_map(s, 3, base + MISC_LEDS); 429 /* 32 bit registers */ 430 /* System control */ 431 sysbus_mmio_map(s, 4, base + MISC_SYS); 432 } 433 if (aux1_base) { 434 /* AUX 1 (Misc System Functions) */ 435 sysbus_mmio_map(s, 5, aux1_base); 436 } 437 if (aux2_base) { 438 /* AUX 2 (Software Powerdown Control) */ 439 sysbus_mmio_map(s, 6, aux2_base); 440 } 441 sysbus_connect_irq(s, 0, irq); 442 sysbus_connect_irq(s, 1, fdc_tc); 443 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 444 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 445 } 446 447 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 448 { 449 DeviceState *dev; 450 SysBusDevice *s; 451 452 dev = qdev_create(NULL, "eccmemctl"); 453 qdev_prop_set_uint32(dev, "version", version); 454 qdev_init_nofail(dev); 455 s = SYS_BUS_DEVICE(dev); 456 sysbus_connect_irq(s, 0, irq); 457 sysbus_mmio_map(s, 0, base); 458 if (version == 0) { // SS-600MP only 459 sysbus_mmio_map(s, 1, base + 0x1000); 460 } 461 } 462 463 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 464 { 465 DeviceState *dev; 466 SysBusDevice *s; 467 468 dev = qdev_create(NULL, "apc"); 469 qdev_init_nofail(dev); 470 s = SYS_BUS_DEVICE(dev); 471 /* Power management (APC) XXX: not a Slavio device */ 472 sysbus_mmio_map(s, 0, power_base); 473 sysbus_connect_irq(s, 0, cpu_halt); 474 } 475 476 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 477 int height, int depth) 478 { 479 DeviceState *dev; 480 SysBusDevice *s; 481 482 dev = qdev_create(NULL, "SUNW,tcx"); 483 qdev_prop_set_uint32(dev, "vram_size", vram_size); 484 qdev_prop_set_uint16(dev, "width", width); 485 qdev_prop_set_uint16(dev, "height", height); 486 qdev_prop_set_uint16(dev, "depth", depth); 487 qdev_init_nofail(dev); 488 s = SYS_BUS_DEVICE(dev); 489 490 /* 10/ROM : FCode ROM */ 491 sysbus_mmio_map(s, 0, addr); 492 /* 2/STIP : Stipple */ 493 sysbus_mmio_map(s, 1, addr + 0x04000000ULL); 494 /* 3/BLIT : Blitter */ 495 sysbus_mmio_map(s, 2, addr + 0x06000000ULL); 496 /* 5/RSTIP : Raw Stipple */ 497 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); 498 /* 6/RBLIT : Raw Blitter */ 499 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); 500 /* 7/TEC : Transform Engine */ 501 sysbus_mmio_map(s, 5, addr + 0x00700000ULL); 502 /* 8/CMAP : DAC */ 503 sysbus_mmio_map(s, 6, addr + 0x00200000ULL); 504 /* 9/THC : */ 505 if (depth == 8) { 506 sysbus_mmio_map(s, 7, addr + 0x00300000ULL); 507 } else { 508 sysbus_mmio_map(s, 7, addr + 0x00301000ULL); 509 } 510 /* 11/DHC : */ 511 sysbus_mmio_map(s, 8, addr + 0x00240000ULL); 512 /* 12/ALT : */ 513 sysbus_mmio_map(s, 9, addr + 0x00280000ULL); 514 /* 0/DFB8 : 8-bit plane */ 515 sysbus_mmio_map(s, 10, addr + 0x00800000ULL); 516 /* 1/DFB24 : 24bit plane */ 517 sysbus_mmio_map(s, 11, addr + 0x02000000ULL); 518 /* 4/RDFB32: Raw framebuffer. Control plane */ 519 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); 520 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 521 if (depth == 8) { 522 sysbus_mmio_map(s, 13, addr + 0x00301000ULL); 523 } 524 525 sysbus_connect_irq(s, 0, irq); 526 } 527 528 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 529 int height, int depth) 530 { 531 DeviceState *dev; 532 SysBusDevice *s; 533 534 dev = qdev_create(NULL, "cgthree"); 535 qdev_prop_set_uint32(dev, "vram-size", vram_size); 536 qdev_prop_set_uint16(dev, "width", width); 537 qdev_prop_set_uint16(dev, "height", height); 538 qdev_prop_set_uint16(dev, "depth", depth); 539 qdev_init_nofail(dev); 540 s = SYS_BUS_DEVICE(dev); 541 542 /* FCode ROM */ 543 sysbus_mmio_map(s, 0, addr); 544 /* DAC */ 545 sysbus_mmio_map(s, 1, addr + 0x400000ULL); 546 /* 8-bit plane */ 547 sysbus_mmio_map(s, 2, addr + 0x800000ULL); 548 549 sysbus_connect_irq(s, 0, irq); 550 } 551 552 /* NCR89C100/MACIO Internal ID register */ 553 554 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 555 556 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 557 558 static void idreg_init(hwaddr addr) 559 { 560 DeviceState *dev; 561 SysBusDevice *s; 562 563 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER); 564 qdev_init_nofail(dev); 565 s = SYS_BUS_DEVICE(dev); 566 567 sysbus_mmio_map(s, 0, addr); 568 cpu_physical_memory_write_rom(&address_space_memory, 569 addr, idreg_data, sizeof(idreg_data)); 570 } 571 572 #define MACIO_ID_REGISTER(obj) \ 573 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER) 574 575 typedef struct IDRegState { 576 SysBusDevice parent_obj; 577 578 MemoryRegion mem; 579 } IDRegState; 580 581 static void idreg_init1(Object *obj) 582 { 583 IDRegState *s = MACIO_ID_REGISTER(obj); 584 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 585 586 memory_region_init_ram_nomigrate(&s->mem, obj, 587 "sun4m.idreg", sizeof(idreg_data), &error_fatal); 588 vmstate_register_ram_global(&s->mem); 589 memory_region_set_readonly(&s->mem, true); 590 sysbus_init_mmio(dev, &s->mem); 591 } 592 593 static const TypeInfo idreg_info = { 594 .name = TYPE_MACIO_ID_REGISTER, 595 .parent = TYPE_SYS_BUS_DEVICE, 596 .instance_size = sizeof(IDRegState), 597 .instance_init = idreg_init1, 598 }; 599 600 #define TYPE_TCX_AFX "tcx_afx" 601 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX) 602 603 typedef struct AFXState { 604 SysBusDevice parent_obj; 605 606 MemoryRegion mem; 607 } AFXState; 608 609 /* SS-5 TCX AFX register */ 610 static void afx_init(hwaddr addr) 611 { 612 DeviceState *dev; 613 SysBusDevice *s; 614 615 dev = qdev_create(NULL, TYPE_TCX_AFX); 616 qdev_init_nofail(dev); 617 s = SYS_BUS_DEVICE(dev); 618 619 sysbus_mmio_map(s, 0, addr); 620 } 621 622 static void afx_init1(Object *obj) 623 { 624 AFXState *s = TCX_AFX(obj); 625 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 626 627 memory_region_init_ram_nomigrate(&s->mem, obj, "sun4m.afx", 4, &error_fatal); 628 vmstate_register_ram_global(&s->mem); 629 sysbus_init_mmio(dev, &s->mem); 630 } 631 632 static const TypeInfo afx_info = { 633 .name = TYPE_TCX_AFX, 634 .parent = TYPE_SYS_BUS_DEVICE, 635 .instance_size = sizeof(AFXState), 636 .instance_init = afx_init1, 637 }; 638 639 #define TYPE_OPENPROM "openprom" 640 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 641 642 typedef struct PROMState { 643 SysBusDevice parent_obj; 644 645 MemoryRegion prom; 646 } PROMState; 647 648 /* Boot PROM (OpenBIOS) */ 649 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 650 { 651 hwaddr *base_addr = (hwaddr *)opaque; 652 return addr + *base_addr - PROM_VADDR; 653 } 654 655 static void prom_init(hwaddr addr, const char *bios_name) 656 { 657 DeviceState *dev; 658 SysBusDevice *s; 659 char *filename; 660 int ret; 661 662 dev = qdev_create(NULL, TYPE_OPENPROM); 663 qdev_init_nofail(dev); 664 s = SYS_BUS_DEVICE(dev); 665 666 sysbus_mmio_map(s, 0, addr); 667 668 /* load boot prom */ 669 if (bios_name == NULL) { 670 bios_name = PROM_FILENAME; 671 } 672 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 673 if (filename) { 674 ret = load_elf(filename, translate_prom_address, &addr, NULL, 675 NULL, NULL, 1, EM_SPARC, 0, 0); 676 if (ret < 0 || ret > PROM_SIZE_MAX) { 677 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 678 } 679 g_free(filename); 680 } else { 681 ret = -1; 682 } 683 if (ret < 0 || ret > PROM_SIZE_MAX) { 684 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 685 exit(1); 686 } 687 } 688 689 static void prom_init1(Object *obj) 690 { 691 PROMState *s = OPENPROM(obj); 692 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 693 694 memory_region_init_ram_nomigrate(&s->prom, obj, "sun4m.prom", PROM_SIZE_MAX, 695 &error_fatal); 696 vmstate_register_ram_global(&s->prom); 697 memory_region_set_readonly(&s->prom, true); 698 sysbus_init_mmio(dev, &s->prom); 699 } 700 701 static Property prom_properties[] = { 702 {/* end of property list */}, 703 }; 704 705 static void prom_class_init(ObjectClass *klass, void *data) 706 { 707 DeviceClass *dc = DEVICE_CLASS(klass); 708 709 dc->props = prom_properties; 710 } 711 712 static const TypeInfo prom_info = { 713 .name = TYPE_OPENPROM, 714 .parent = TYPE_SYS_BUS_DEVICE, 715 .instance_size = sizeof(PROMState), 716 .class_init = prom_class_init, 717 .instance_init = prom_init1, 718 }; 719 720 #define TYPE_SUN4M_MEMORY "memory" 721 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY) 722 723 typedef struct RamDevice { 724 SysBusDevice parent_obj; 725 726 MemoryRegion ram; 727 uint64_t size; 728 } RamDevice; 729 730 /* System RAM */ 731 static void ram_realize(DeviceState *dev, Error **errp) 732 { 733 RamDevice *d = SUN4M_RAM(dev); 734 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 735 736 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram", 737 d->size); 738 sysbus_init_mmio(sbd, &d->ram); 739 } 740 741 static void ram_init(hwaddr addr, ram_addr_t RAM_size, 742 uint64_t max_mem) 743 { 744 DeviceState *dev; 745 SysBusDevice *s; 746 RamDevice *d; 747 748 /* allocate RAM */ 749 if ((uint64_t)RAM_size > max_mem) { 750 fprintf(stderr, 751 "qemu: Too much memory for this machine: %d, maximum %d\n", 752 (unsigned int)(RAM_size / (1024 * 1024)), 753 (unsigned int)(max_mem / (1024 * 1024))); 754 exit(1); 755 } 756 dev = qdev_create(NULL, "memory"); 757 s = SYS_BUS_DEVICE(dev); 758 759 d = SUN4M_RAM(dev); 760 d->size = RAM_size; 761 qdev_init_nofail(dev); 762 763 sysbus_mmio_map(s, 0, addr); 764 } 765 766 static Property ram_properties[] = { 767 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 768 DEFINE_PROP_END_OF_LIST(), 769 }; 770 771 static void ram_class_init(ObjectClass *klass, void *data) 772 { 773 DeviceClass *dc = DEVICE_CLASS(klass); 774 775 dc->realize = ram_realize; 776 dc->props = ram_properties; 777 } 778 779 static const TypeInfo ram_info = { 780 .name = TYPE_SUN4M_MEMORY, 781 .parent = TYPE_SYS_BUS_DEVICE, 782 .instance_size = sizeof(RamDevice), 783 .class_init = ram_class_init, 784 }; 785 786 static void cpu_devinit(const char *cpu_type, unsigned int id, 787 uint64_t prom_addr, qemu_irq **cpu_irqs) 788 { 789 CPUState *cs; 790 SPARCCPU *cpu; 791 CPUSPARCState *env; 792 793 cpu = SPARC_CPU(cpu_create(cpu_type)); 794 env = &cpu->env; 795 796 cpu_sparc_set_id(env, id); 797 if (id == 0) { 798 qemu_register_reset(main_cpu_reset, cpu); 799 } else { 800 qemu_register_reset(secondary_cpu_reset, cpu); 801 cs = CPU(cpu); 802 cs->halted = 1; 803 } 804 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 805 env->prom_addr = prom_addr; 806 } 807 808 static void dummy_fdc_tc(void *opaque, int irq, int level) 809 { 810 } 811 812 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, 813 MachineState *machine) 814 { 815 DeviceState *slavio_intctl; 816 unsigned int i; 817 void *nvram; 818 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; 819 qemu_irq fdc_tc; 820 unsigned long kernel_size; 821 DriveInfo *fd[MAX_FD]; 822 FWCfgState *fw_cfg; 823 unsigned int num_vsimms; 824 825 /* init CPUs */ 826 for(i = 0; i < smp_cpus; i++) { 827 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); 828 } 829 830 for (i = smp_cpus; i < MAX_CPUS; i++) 831 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 832 833 834 /* set up devices */ 835 ram_init(0, machine->ram_size, hwdef->max_mem); 836 /* models without ECC don't trap when missing ram is accessed */ 837 if (!hwdef->ecc_base) { 838 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size); 839 } 840 841 prom_init(hwdef->slavio_base, bios_name); 842 843 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 844 hwdef->intctl_base + 0x10000ULL, 845 cpu_irqs); 846 847 for (i = 0; i < 32; i++) { 848 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 849 } 850 for (i = 0; i < MAX_CPUS; i++) { 851 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 852 } 853 854 if (hwdef->idreg_base) { 855 idreg_init(hwdef->idreg_base); 856 } 857 858 if (hwdef->afx_base) { 859 afx_init(hwdef->afx_base); 860 } 861 862 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]); 863 864 if (hwdef->iommu_pad_base) { 865 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 866 Software shouldn't use aliased addresses, neither should it crash 867 when does. Using empty_slot instead of aliasing can help with 868 debugging such accesses */ 869 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); 870 } 871 872 sparc32_dma_init(hwdef->dma_base, 873 hwdef->esp_base, slavio_irq[18], 874 hwdef->le_base, slavio_irq[16]); 875 876 if (graphic_depth != 8 && graphic_depth != 24) { 877 error_report("Unsupported depth: %d", graphic_depth); 878 exit (1); 879 } 880 num_vsimms = 0; 881 if (num_vsimms == 0) { 882 if (vga_interface_type == VGA_CG3) { 883 if (graphic_depth != 8) { 884 error_report("Unsupported depth: %d", graphic_depth); 885 exit(1); 886 } 887 888 if (!(graphic_width == 1024 && graphic_height == 768) && 889 !(graphic_width == 1152 && graphic_height == 900)) { 890 error_report("Unsupported resolution: %d x %d", graphic_width, 891 graphic_height); 892 exit(1); 893 } 894 895 /* sbus irq 5 */ 896 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 897 graphic_width, graphic_height, graphic_depth); 898 } else { 899 /* If no display specified, default to TCX */ 900 if (graphic_depth != 8 && graphic_depth != 24) { 901 error_report("Unsupported depth: %d", graphic_depth); 902 exit(1); 903 } 904 905 if (!(graphic_width == 1024 && graphic_height == 768)) { 906 error_report("Unsupported resolution: %d x %d", 907 graphic_width, graphic_height); 908 exit(1); 909 } 910 911 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 912 graphic_width, graphic_height, graphic_depth); 913 } 914 } 915 916 for (i = num_vsimms; i < MAX_VSIMMS; i++) { 917 /* vsimm registers probed by OBP */ 918 if (hwdef->vsimm[i].reg_base) { 919 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); 920 } 921 } 922 923 if (hwdef->sx_base) { 924 empty_slot_init(hwdef->sx_base, 0x2000); 925 } 926 927 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8); 928 929 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 930 931 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14], 932 !machine->enable_graphics, ESCC_CLOCK, 1); 933 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 934 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 935 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], 936 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); 937 938 if (hwdef->apc_base) { 939 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); 940 } 941 942 if (hwdef->fd_base) { 943 /* there is zero or one floppy drive */ 944 memset(fd, 0, sizeof(fd)); 945 fd[0] = drive_get(IF_FLOPPY, 0, 0); 946 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 947 &fdc_tc); 948 } else { 949 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); 950 } 951 952 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 953 slavio_irq[30], fdc_tc); 954 955 if (hwdef->cs_base) { 956 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, 957 slavio_irq[5]); 958 } 959 960 if (hwdef->dbri_base) { 961 /* ISDN chip with attached CS4215 audio codec */ 962 /* prom space */ 963 empty_slot_init(hwdef->dbri_base+0x1000, 0x30); 964 /* reg space */ 965 empty_slot_init(hwdef->dbri_base+0x10000, 0x100); 966 } 967 968 if (hwdef->bpp_base) { 969 /* parallel port */ 970 empty_slot_init(hwdef->bpp_base, 0x20); 971 } 972 973 kernel_size = sun4m_load_kernel(machine->kernel_filename, 974 machine->initrd_filename, 975 machine->ram_size); 976 977 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline, 978 machine->boot_order, machine->ram_size, kernel_size, 979 graphic_width, graphic_height, graphic_depth, 980 hwdef->nvram_machine_id, "Sun4m"); 981 982 if (hwdef->ecc_base) 983 ecc_init(hwdef->ecc_base, slavio_irq[28], 984 hwdef->ecc_version); 985 986 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 987 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 988 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 989 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 990 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 991 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 992 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 993 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 994 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 995 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 996 if (machine->kernel_cmdline) { 997 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 998 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 999 machine->kernel_cmdline); 1000 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 1001 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1002 strlen(machine->kernel_cmdline) + 1); 1003 } else { 1004 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1005 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1006 } 1007 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1008 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used 1009 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 1010 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1011 } 1012 1013 enum { 1014 ss5_id = 32, 1015 vger_id, 1016 lx_id, 1017 ss4_id, 1018 scls_id, 1019 sbook_id, 1020 ss10_id = 64, 1021 ss20_id, 1022 ss600mp_id, 1023 }; 1024 1025 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1026 /* SS-5 */ 1027 { 1028 .iommu_base = 0x10000000, 1029 .iommu_pad_base = 0x10004000, 1030 .iommu_pad_len = 0x0fffb000, 1031 .tcx_base = 0x50000000, 1032 .cs_base = 0x6c000000, 1033 .slavio_base = 0x70000000, 1034 .ms_kb_base = 0x71000000, 1035 .serial_base = 0x71100000, 1036 .nvram_base = 0x71200000, 1037 .fd_base = 0x71400000, 1038 .counter_base = 0x71d00000, 1039 .intctl_base = 0x71e00000, 1040 .idreg_base = 0x78000000, 1041 .dma_base = 0x78400000, 1042 .esp_base = 0x78800000, 1043 .le_base = 0x78c00000, 1044 .apc_base = 0x6a000000, 1045 .afx_base = 0x6e000000, 1046 .aux1_base = 0x71900000, 1047 .aux2_base = 0x71910000, 1048 .nvram_machine_id = 0x80, 1049 .machine_id = ss5_id, 1050 .iommu_version = 0x05000000, 1051 .max_mem = 0x10000000, 1052 }, 1053 /* SS-10 */ 1054 { 1055 .iommu_base = 0xfe0000000ULL, 1056 .tcx_base = 0xe20000000ULL, 1057 .slavio_base = 0xff0000000ULL, 1058 .ms_kb_base = 0xff1000000ULL, 1059 .serial_base = 0xff1100000ULL, 1060 .nvram_base = 0xff1200000ULL, 1061 .fd_base = 0xff1700000ULL, 1062 .counter_base = 0xff1300000ULL, 1063 .intctl_base = 0xff1400000ULL, 1064 .idreg_base = 0xef0000000ULL, 1065 .dma_base = 0xef0400000ULL, 1066 .esp_base = 0xef0800000ULL, 1067 .le_base = 0xef0c00000ULL, 1068 .apc_base = 0xefa000000ULL, // XXX should not exist 1069 .aux1_base = 0xff1800000ULL, 1070 .aux2_base = 0xff1a01000ULL, 1071 .ecc_base = 0xf00000000ULL, 1072 .ecc_version = 0x10000000, // version 0, implementation 1 1073 .nvram_machine_id = 0x72, 1074 .machine_id = ss10_id, 1075 .iommu_version = 0x03000000, 1076 .max_mem = 0xf00000000ULL, 1077 }, 1078 /* SS-600MP */ 1079 { 1080 .iommu_base = 0xfe0000000ULL, 1081 .tcx_base = 0xe20000000ULL, 1082 .slavio_base = 0xff0000000ULL, 1083 .ms_kb_base = 0xff1000000ULL, 1084 .serial_base = 0xff1100000ULL, 1085 .nvram_base = 0xff1200000ULL, 1086 .counter_base = 0xff1300000ULL, 1087 .intctl_base = 0xff1400000ULL, 1088 .dma_base = 0xef0081000ULL, 1089 .esp_base = 0xef0080000ULL, 1090 .le_base = 0xef0060000ULL, 1091 .apc_base = 0xefa000000ULL, // XXX should not exist 1092 .aux1_base = 0xff1800000ULL, 1093 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1094 .ecc_base = 0xf00000000ULL, 1095 .ecc_version = 0x00000000, // version 0, implementation 0 1096 .nvram_machine_id = 0x71, 1097 .machine_id = ss600mp_id, 1098 .iommu_version = 0x01000000, 1099 .max_mem = 0xf00000000ULL, 1100 }, 1101 /* SS-20 */ 1102 { 1103 .iommu_base = 0xfe0000000ULL, 1104 .tcx_base = 0xe20000000ULL, 1105 .slavio_base = 0xff0000000ULL, 1106 .ms_kb_base = 0xff1000000ULL, 1107 .serial_base = 0xff1100000ULL, 1108 .nvram_base = 0xff1200000ULL, 1109 .fd_base = 0xff1700000ULL, 1110 .counter_base = 0xff1300000ULL, 1111 .intctl_base = 0xff1400000ULL, 1112 .idreg_base = 0xef0000000ULL, 1113 .dma_base = 0xef0400000ULL, 1114 .esp_base = 0xef0800000ULL, 1115 .le_base = 0xef0c00000ULL, 1116 .bpp_base = 0xef4800000ULL, 1117 .apc_base = 0xefa000000ULL, // XXX should not exist 1118 .aux1_base = 0xff1800000ULL, 1119 .aux2_base = 0xff1a01000ULL, 1120 .dbri_base = 0xee0000000ULL, 1121 .sx_base = 0xf80000000ULL, 1122 .vsimm = { 1123 { 1124 .reg_base = 0x9c000000ULL, 1125 .vram_base = 0xfc000000ULL 1126 }, { 1127 .reg_base = 0x90000000ULL, 1128 .vram_base = 0xf0000000ULL 1129 }, { 1130 .reg_base = 0x94000000ULL 1131 }, { 1132 .reg_base = 0x98000000ULL 1133 } 1134 }, 1135 .ecc_base = 0xf00000000ULL, 1136 .ecc_version = 0x20000000, // version 0, implementation 2 1137 .nvram_machine_id = 0x72, 1138 .machine_id = ss20_id, 1139 .iommu_version = 0x13000000, 1140 .max_mem = 0xf00000000ULL, 1141 }, 1142 /* Voyager */ 1143 { 1144 .iommu_base = 0x10000000, 1145 .tcx_base = 0x50000000, 1146 .slavio_base = 0x70000000, 1147 .ms_kb_base = 0x71000000, 1148 .serial_base = 0x71100000, 1149 .nvram_base = 0x71200000, 1150 .fd_base = 0x71400000, 1151 .counter_base = 0x71d00000, 1152 .intctl_base = 0x71e00000, 1153 .idreg_base = 0x78000000, 1154 .dma_base = 0x78400000, 1155 .esp_base = 0x78800000, 1156 .le_base = 0x78c00000, 1157 .apc_base = 0x71300000, // pmc 1158 .aux1_base = 0x71900000, 1159 .aux2_base = 0x71910000, 1160 .nvram_machine_id = 0x80, 1161 .machine_id = vger_id, 1162 .iommu_version = 0x05000000, 1163 .max_mem = 0x10000000, 1164 }, 1165 /* LX */ 1166 { 1167 .iommu_base = 0x10000000, 1168 .iommu_pad_base = 0x10004000, 1169 .iommu_pad_len = 0x0fffb000, 1170 .tcx_base = 0x50000000, 1171 .slavio_base = 0x70000000, 1172 .ms_kb_base = 0x71000000, 1173 .serial_base = 0x71100000, 1174 .nvram_base = 0x71200000, 1175 .fd_base = 0x71400000, 1176 .counter_base = 0x71d00000, 1177 .intctl_base = 0x71e00000, 1178 .idreg_base = 0x78000000, 1179 .dma_base = 0x78400000, 1180 .esp_base = 0x78800000, 1181 .le_base = 0x78c00000, 1182 .aux1_base = 0x71900000, 1183 .aux2_base = 0x71910000, 1184 .nvram_machine_id = 0x80, 1185 .machine_id = lx_id, 1186 .iommu_version = 0x04000000, 1187 .max_mem = 0x10000000, 1188 }, 1189 /* SS-4 */ 1190 { 1191 .iommu_base = 0x10000000, 1192 .tcx_base = 0x50000000, 1193 .cs_base = 0x6c000000, 1194 .slavio_base = 0x70000000, 1195 .ms_kb_base = 0x71000000, 1196 .serial_base = 0x71100000, 1197 .nvram_base = 0x71200000, 1198 .fd_base = 0x71400000, 1199 .counter_base = 0x71d00000, 1200 .intctl_base = 0x71e00000, 1201 .idreg_base = 0x78000000, 1202 .dma_base = 0x78400000, 1203 .esp_base = 0x78800000, 1204 .le_base = 0x78c00000, 1205 .apc_base = 0x6a000000, 1206 .aux1_base = 0x71900000, 1207 .aux2_base = 0x71910000, 1208 .nvram_machine_id = 0x80, 1209 .machine_id = ss4_id, 1210 .iommu_version = 0x05000000, 1211 .max_mem = 0x10000000, 1212 }, 1213 /* SPARCClassic */ 1214 { 1215 .iommu_base = 0x10000000, 1216 .tcx_base = 0x50000000, 1217 .slavio_base = 0x70000000, 1218 .ms_kb_base = 0x71000000, 1219 .serial_base = 0x71100000, 1220 .nvram_base = 0x71200000, 1221 .fd_base = 0x71400000, 1222 .counter_base = 0x71d00000, 1223 .intctl_base = 0x71e00000, 1224 .idreg_base = 0x78000000, 1225 .dma_base = 0x78400000, 1226 .esp_base = 0x78800000, 1227 .le_base = 0x78c00000, 1228 .apc_base = 0x6a000000, 1229 .aux1_base = 0x71900000, 1230 .aux2_base = 0x71910000, 1231 .nvram_machine_id = 0x80, 1232 .machine_id = scls_id, 1233 .iommu_version = 0x05000000, 1234 .max_mem = 0x10000000, 1235 }, 1236 /* SPARCbook */ 1237 { 1238 .iommu_base = 0x10000000, 1239 .tcx_base = 0x50000000, // XXX 1240 .slavio_base = 0x70000000, 1241 .ms_kb_base = 0x71000000, 1242 .serial_base = 0x71100000, 1243 .nvram_base = 0x71200000, 1244 .fd_base = 0x71400000, 1245 .counter_base = 0x71d00000, 1246 .intctl_base = 0x71e00000, 1247 .idreg_base = 0x78000000, 1248 .dma_base = 0x78400000, 1249 .esp_base = 0x78800000, 1250 .le_base = 0x78c00000, 1251 .apc_base = 0x6a000000, 1252 .aux1_base = 0x71900000, 1253 .aux2_base = 0x71910000, 1254 .nvram_machine_id = 0x80, 1255 .machine_id = sbook_id, 1256 .iommu_version = 0x05000000, 1257 .max_mem = 0x10000000, 1258 }, 1259 }; 1260 1261 /* SPARCstation 5 hardware initialisation */ 1262 static void ss5_init(MachineState *machine) 1263 { 1264 sun4m_hw_init(&sun4m_hwdefs[0], machine); 1265 } 1266 1267 /* SPARCstation 10 hardware initialisation */ 1268 static void ss10_init(MachineState *machine) 1269 { 1270 sun4m_hw_init(&sun4m_hwdefs[1], machine); 1271 } 1272 1273 /* SPARCserver 600MP hardware initialisation */ 1274 static void ss600mp_init(MachineState *machine) 1275 { 1276 sun4m_hw_init(&sun4m_hwdefs[2], machine); 1277 } 1278 1279 /* SPARCstation 20 hardware initialisation */ 1280 static void ss20_init(MachineState *machine) 1281 { 1282 sun4m_hw_init(&sun4m_hwdefs[3], machine); 1283 } 1284 1285 /* SPARCstation Voyager hardware initialisation */ 1286 static void vger_init(MachineState *machine) 1287 { 1288 sun4m_hw_init(&sun4m_hwdefs[4], machine); 1289 } 1290 1291 /* SPARCstation LX hardware initialisation */ 1292 static void ss_lx_init(MachineState *machine) 1293 { 1294 sun4m_hw_init(&sun4m_hwdefs[5], machine); 1295 } 1296 1297 /* SPARCstation 4 hardware initialisation */ 1298 static void ss4_init(MachineState *machine) 1299 { 1300 sun4m_hw_init(&sun4m_hwdefs[6], machine); 1301 } 1302 1303 /* SPARCClassic hardware initialisation */ 1304 static void scls_init(MachineState *machine) 1305 { 1306 sun4m_hw_init(&sun4m_hwdefs[7], machine); 1307 } 1308 1309 /* SPARCbook hardware initialisation */ 1310 static void sbook_init(MachineState *machine) 1311 { 1312 sun4m_hw_init(&sun4m_hwdefs[8], machine); 1313 } 1314 1315 static void ss5_class_init(ObjectClass *oc, void *data) 1316 { 1317 MachineClass *mc = MACHINE_CLASS(oc); 1318 1319 mc->desc = "Sun4m platform, SPARCstation 5"; 1320 mc->init = ss5_init; 1321 mc->block_default_type = IF_SCSI; 1322 mc->is_default = 1; 1323 mc->default_boot_order = "c"; 1324 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1325 } 1326 1327 static const TypeInfo ss5_type = { 1328 .name = MACHINE_TYPE_NAME("SS-5"), 1329 .parent = TYPE_MACHINE, 1330 .class_init = ss5_class_init, 1331 }; 1332 1333 static void ss10_class_init(ObjectClass *oc, void *data) 1334 { 1335 MachineClass *mc = MACHINE_CLASS(oc); 1336 1337 mc->desc = "Sun4m platform, SPARCstation 10"; 1338 mc->init = ss10_init; 1339 mc->block_default_type = IF_SCSI; 1340 mc->max_cpus = 4; 1341 mc->default_boot_order = "c"; 1342 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1343 } 1344 1345 static const TypeInfo ss10_type = { 1346 .name = MACHINE_TYPE_NAME("SS-10"), 1347 .parent = TYPE_MACHINE, 1348 .class_init = ss10_class_init, 1349 }; 1350 1351 static void ss600mp_class_init(ObjectClass *oc, void *data) 1352 { 1353 MachineClass *mc = MACHINE_CLASS(oc); 1354 1355 mc->desc = "Sun4m platform, SPARCserver 600MP"; 1356 mc->init = ss600mp_init; 1357 mc->block_default_type = IF_SCSI; 1358 mc->max_cpus = 4; 1359 mc->default_boot_order = "c"; 1360 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1361 } 1362 1363 static const TypeInfo ss600mp_type = { 1364 .name = MACHINE_TYPE_NAME("SS-600MP"), 1365 .parent = TYPE_MACHINE, 1366 .class_init = ss600mp_class_init, 1367 }; 1368 1369 static void ss20_class_init(ObjectClass *oc, void *data) 1370 { 1371 MachineClass *mc = MACHINE_CLASS(oc); 1372 1373 mc->desc = "Sun4m platform, SPARCstation 20"; 1374 mc->init = ss20_init; 1375 mc->block_default_type = IF_SCSI; 1376 mc->max_cpus = 4; 1377 mc->default_boot_order = "c"; 1378 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1379 } 1380 1381 static const TypeInfo ss20_type = { 1382 .name = MACHINE_TYPE_NAME("SS-20"), 1383 .parent = TYPE_MACHINE, 1384 .class_init = ss20_class_init, 1385 }; 1386 1387 static void voyager_class_init(ObjectClass *oc, void *data) 1388 { 1389 MachineClass *mc = MACHINE_CLASS(oc); 1390 1391 mc->desc = "Sun4m platform, SPARCstation Voyager"; 1392 mc->init = vger_init; 1393 mc->block_default_type = IF_SCSI; 1394 mc->default_boot_order = "c"; 1395 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1396 } 1397 1398 static const TypeInfo voyager_type = { 1399 .name = MACHINE_TYPE_NAME("Voyager"), 1400 .parent = TYPE_MACHINE, 1401 .class_init = voyager_class_init, 1402 }; 1403 1404 static void ss_lx_class_init(ObjectClass *oc, void *data) 1405 { 1406 MachineClass *mc = MACHINE_CLASS(oc); 1407 1408 mc->desc = "Sun4m platform, SPARCstation LX"; 1409 mc->init = ss_lx_init; 1410 mc->block_default_type = IF_SCSI; 1411 mc->default_boot_order = "c"; 1412 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1413 } 1414 1415 static const TypeInfo ss_lx_type = { 1416 .name = MACHINE_TYPE_NAME("LX"), 1417 .parent = TYPE_MACHINE, 1418 .class_init = ss_lx_class_init, 1419 }; 1420 1421 static void ss4_class_init(ObjectClass *oc, void *data) 1422 { 1423 MachineClass *mc = MACHINE_CLASS(oc); 1424 1425 mc->desc = "Sun4m platform, SPARCstation 4"; 1426 mc->init = ss4_init; 1427 mc->block_default_type = IF_SCSI; 1428 mc->default_boot_order = "c"; 1429 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1430 } 1431 1432 static const TypeInfo ss4_type = { 1433 .name = MACHINE_TYPE_NAME("SS-4"), 1434 .parent = TYPE_MACHINE, 1435 .class_init = ss4_class_init, 1436 }; 1437 1438 static void scls_class_init(ObjectClass *oc, void *data) 1439 { 1440 MachineClass *mc = MACHINE_CLASS(oc); 1441 1442 mc->desc = "Sun4m platform, SPARCClassic"; 1443 mc->init = scls_init; 1444 mc->block_default_type = IF_SCSI; 1445 mc->default_boot_order = "c"; 1446 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1447 } 1448 1449 static const TypeInfo scls_type = { 1450 .name = MACHINE_TYPE_NAME("SPARCClassic"), 1451 .parent = TYPE_MACHINE, 1452 .class_init = scls_class_init, 1453 }; 1454 1455 static void sbook_class_init(ObjectClass *oc, void *data) 1456 { 1457 MachineClass *mc = MACHINE_CLASS(oc); 1458 1459 mc->desc = "Sun4m platform, SPARCbook"; 1460 mc->init = sbook_init; 1461 mc->block_default_type = IF_SCSI; 1462 mc->default_boot_order = "c"; 1463 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1464 } 1465 1466 static const TypeInfo sbook_type = { 1467 .name = MACHINE_TYPE_NAME("SPARCbook"), 1468 .parent = TYPE_MACHINE, 1469 .class_init = sbook_class_init, 1470 }; 1471 1472 static void sun4m_register_types(void) 1473 { 1474 type_register_static(&idreg_info); 1475 type_register_static(&afx_info); 1476 type_register_static(&prom_info); 1477 type_register_static(&ram_info); 1478 1479 type_register_static(&ss5_type); 1480 type_register_static(&ss10_type); 1481 type_register_static(&ss600mp_type); 1482 type_register_static(&ss20_type); 1483 type_register_static(&voyager_type); 1484 type_register_static(&ss_lx_type); 1485 type_register_static(&ss4_type); 1486 type_register_static(&scls_type); 1487 type_register_static(&sbook_type); 1488 } 1489 1490 type_init(sun4m_register_types) 1491