1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/sysbus.h" 29 #include "qemu/error-report.h" 30 #include "qemu/timer.h" 31 #include "hw/sparc/sun4m.h" 32 #include "hw/timer/m48t59.h" 33 #include "hw/sparc/sparc32_dma.h" 34 #include "hw/block/fdc.h" 35 #include "sysemu/sysemu.h" 36 #include "net/net.h" 37 #include "hw/boards.h" 38 #include "hw/scsi/esp.h" 39 #include "hw/i386/pc.h" 40 #include "hw/isa/isa.h" 41 #include "hw/nvram/sun_nvram.h" 42 #include "hw/nvram/chrp_nvram.h" 43 #include "hw/nvram/fw_cfg.h" 44 #include "hw/char/escc.h" 45 #include "hw/empty_slot.h" 46 #include "hw/loader.h" 47 #include "elf.h" 48 #include "sysemu/block-backend.h" 49 #include "trace.h" 50 #include "qemu/cutils.h" 51 52 /* 53 * Sun4m architecture was used in the following machines: 54 * 55 * SPARCserver 6xxMP/xx 56 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 57 * SPARCclassic X (4/10) 58 * SPARCstation LX/ZX (4/30) 59 * SPARCstation Voyager 60 * SPARCstation 10/xx, SPARCserver 10/xx 61 * SPARCstation 5, SPARCserver 5 62 * SPARCstation 20/xx, SPARCserver 20 63 * SPARCstation 4 64 * 65 * See for example: http://www.sunhelp.org/faq/sunref1.html 66 */ 67 68 #define KERNEL_LOAD_ADDR 0x00004000 69 #define CMDLINE_ADDR 0x007ff000 70 #define INITRD_LOAD_ADDR 0x00800000 71 #define PROM_SIZE_MAX (1024 * 1024) 72 #define PROM_VADDR 0xffd00000 73 #define PROM_FILENAME "openbios-sparc32" 74 #define CFG_ADDR 0xd00000510ULL 75 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 76 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 77 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 78 79 #define MAX_CPUS 16 80 #define MAX_PILS 16 81 #define MAX_VSIMMS 4 82 83 #define ESCC_CLOCK 4915200 84 85 struct sun4m_hwdef { 86 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 87 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 88 hwaddr serial_base, fd_base; 89 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 90 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 91 hwaddr bpp_base, dbri_base, sx_base; 92 struct { 93 hwaddr reg_base, vram_base; 94 } vsimm[MAX_VSIMMS]; 95 hwaddr ecc_base; 96 uint64_t max_mem; 97 const char * const default_cpu_model; 98 uint32_t ecc_version; 99 uint32_t iommu_version; 100 uint16_t machine_id; 101 uint8_t nvram_machine_id; 102 }; 103 104 void DMA_init(ISABus *bus, int high_page_enable) 105 { 106 } 107 108 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 109 Error **errp) 110 { 111 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 112 } 113 114 static void nvram_init(Nvram *nvram, uint8_t *macaddr, 115 const char *cmdline, const char *boot_devices, 116 ram_addr_t RAM_size, uint32_t kernel_size, 117 int width, int height, int depth, 118 int nvram_machine_id, const char *arch) 119 { 120 unsigned int i; 121 int sysp_end; 122 uint8_t image[0x1ff0]; 123 NvramClass *k = NVRAM_GET_CLASS(nvram); 124 125 memset(image, '\0', sizeof(image)); 126 127 /* OpenBIOS nvram variables partition */ 128 sysp_end = chrp_nvram_create_system_partition(image, 0); 129 130 /* Free space partition */ 131 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 132 133 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 134 nvram_machine_id); 135 136 for (i = 0; i < sizeof(image); i++) { 137 (k->write)(nvram, i, image[i]); 138 } 139 } 140 141 void cpu_check_irqs(CPUSPARCState *env) 142 { 143 CPUState *cs; 144 145 if (env->pil_in && (env->interrupt_index == 0 || 146 (env->interrupt_index & ~15) == TT_EXTINT)) { 147 unsigned int i; 148 149 for (i = 15; i > 0; i--) { 150 if (env->pil_in & (1 << i)) { 151 int old_interrupt = env->interrupt_index; 152 153 env->interrupt_index = TT_EXTINT | i; 154 if (old_interrupt != env->interrupt_index) { 155 cs = CPU(sparc_env_get_cpu(env)); 156 trace_sun4m_cpu_interrupt(i); 157 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 158 } 159 break; 160 } 161 } 162 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 163 cs = CPU(sparc_env_get_cpu(env)); 164 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 165 env->interrupt_index = 0; 166 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 167 } 168 } 169 170 static void cpu_kick_irq(SPARCCPU *cpu) 171 { 172 CPUSPARCState *env = &cpu->env; 173 CPUState *cs = CPU(cpu); 174 175 cs->halted = 0; 176 cpu_check_irqs(env); 177 qemu_cpu_kick(cs); 178 } 179 180 static void cpu_set_irq(void *opaque, int irq, int level) 181 { 182 SPARCCPU *cpu = opaque; 183 CPUSPARCState *env = &cpu->env; 184 185 if (level) { 186 trace_sun4m_cpu_set_irq_raise(irq); 187 env->pil_in |= 1 << irq; 188 cpu_kick_irq(cpu); 189 } else { 190 trace_sun4m_cpu_set_irq_lower(irq); 191 env->pil_in &= ~(1 << irq); 192 cpu_check_irqs(env); 193 } 194 } 195 196 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 197 { 198 } 199 200 static void main_cpu_reset(void *opaque) 201 { 202 SPARCCPU *cpu = opaque; 203 CPUState *cs = CPU(cpu); 204 205 cpu_reset(cs); 206 cs->halted = 0; 207 } 208 209 static void secondary_cpu_reset(void *opaque) 210 { 211 SPARCCPU *cpu = opaque; 212 CPUState *cs = CPU(cpu); 213 214 cpu_reset(cs); 215 cs->halted = 1; 216 } 217 218 static void cpu_halt_signal(void *opaque, int irq, int level) 219 { 220 if (level && current_cpu) { 221 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 222 } 223 } 224 225 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 226 { 227 return addr - 0xf0000000ULL; 228 } 229 230 static unsigned long sun4m_load_kernel(const char *kernel_filename, 231 const char *initrd_filename, 232 ram_addr_t RAM_size) 233 { 234 int linux_boot; 235 unsigned int i; 236 long initrd_size, kernel_size; 237 uint8_t *ptr; 238 239 linux_boot = (kernel_filename != NULL); 240 241 kernel_size = 0; 242 if (linux_boot) { 243 int bswap_needed; 244 245 #ifdef BSWAP_NEEDED 246 bswap_needed = 1; 247 #else 248 bswap_needed = 0; 249 #endif 250 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 251 NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 252 if (kernel_size < 0) 253 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 254 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 255 TARGET_PAGE_SIZE); 256 if (kernel_size < 0) 257 kernel_size = load_image_targphys(kernel_filename, 258 KERNEL_LOAD_ADDR, 259 RAM_size - KERNEL_LOAD_ADDR); 260 if (kernel_size < 0) { 261 fprintf(stderr, "qemu: could not load kernel '%s'\n", 262 kernel_filename); 263 exit(1); 264 } 265 266 /* load initrd */ 267 initrd_size = 0; 268 if (initrd_filename) { 269 initrd_size = load_image_targphys(initrd_filename, 270 INITRD_LOAD_ADDR, 271 RAM_size - INITRD_LOAD_ADDR); 272 if (initrd_size < 0) { 273 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 274 initrd_filename); 275 exit(1); 276 } 277 } 278 if (initrd_size > 0) { 279 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 280 ptr = rom_ptr(KERNEL_LOAD_ADDR + i); 281 if (ldl_p(ptr) == 0x48647253) { // HdrS 282 stl_p(ptr + 16, INITRD_LOAD_ADDR); 283 stl_p(ptr + 20, initrd_size); 284 break; 285 } 286 } 287 } 288 } 289 return kernel_size; 290 } 291 292 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 293 { 294 DeviceState *dev; 295 SysBusDevice *s; 296 297 dev = qdev_create(NULL, "iommu"); 298 qdev_prop_set_uint32(dev, "version", version); 299 qdev_init_nofail(dev); 300 s = SYS_BUS_DEVICE(dev); 301 sysbus_connect_irq(s, 0, irq); 302 sysbus_mmio_map(s, 0, addr); 303 304 return s; 305 } 306 307 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq, 308 void *iommu, qemu_irq *dev_irq, int is_ledma) 309 { 310 DeviceState *dev; 311 SysBusDevice *s; 312 313 dev = qdev_create(NULL, "sparc32_dma"); 314 qdev_prop_set_ptr(dev, "iommu_opaque", iommu); 315 qdev_prop_set_uint32(dev, "is_ledma", is_ledma); 316 qdev_init_nofail(dev); 317 s = SYS_BUS_DEVICE(dev); 318 sysbus_connect_irq(s, 0, parent_irq); 319 *dev_irq = qdev_get_gpio_in(dev, 0); 320 sysbus_mmio_map(s, 0, daddr); 321 322 return s; 323 } 324 325 static void lance_init(NICInfo *nd, hwaddr leaddr, 326 void *dma_opaque, qemu_irq irq) 327 { 328 DeviceState *dev; 329 SysBusDevice *s; 330 qemu_irq reset; 331 332 qemu_check_nic_model(&nd_table[0], "lance"); 333 334 dev = qdev_create(NULL, "lance"); 335 qdev_set_nic_properties(dev, nd); 336 qdev_prop_set_ptr(dev, "dma", dma_opaque); 337 qdev_init_nofail(dev); 338 s = SYS_BUS_DEVICE(dev); 339 sysbus_mmio_map(s, 0, leaddr); 340 sysbus_connect_irq(s, 0, irq); 341 reset = qdev_get_gpio_in(dev, 0); 342 qdev_connect_gpio_out(dma_opaque, 0, reset); 343 } 344 345 static DeviceState *slavio_intctl_init(hwaddr addr, 346 hwaddr addrg, 347 qemu_irq **parent_irq) 348 { 349 DeviceState *dev; 350 SysBusDevice *s; 351 unsigned int i, j; 352 353 dev = qdev_create(NULL, "slavio_intctl"); 354 qdev_init_nofail(dev); 355 356 s = SYS_BUS_DEVICE(dev); 357 358 for (i = 0; i < MAX_CPUS; i++) { 359 for (j = 0; j < MAX_PILS; j++) { 360 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 361 } 362 } 363 sysbus_mmio_map(s, 0, addrg); 364 for (i = 0; i < MAX_CPUS; i++) { 365 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 366 } 367 368 return dev; 369 } 370 371 #define SYS_TIMER_OFFSET 0x10000ULL 372 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 373 374 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 375 qemu_irq *cpu_irqs, unsigned int num_cpus) 376 { 377 DeviceState *dev; 378 SysBusDevice *s; 379 unsigned int i; 380 381 dev = qdev_create(NULL, "slavio_timer"); 382 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 383 qdev_init_nofail(dev); 384 s = SYS_BUS_DEVICE(dev); 385 sysbus_connect_irq(s, 0, master_irq); 386 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 387 388 for (i = 0; i < MAX_CPUS; i++) { 389 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 390 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 391 } 392 } 393 394 static qemu_irq slavio_system_powerdown; 395 396 static void slavio_powerdown_req(Notifier *n, void *opaque) 397 { 398 qemu_irq_raise(slavio_system_powerdown); 399 } 400 401 static Notifier slavio_system_powerdown_notifier = { 402 .notify = slavio_powerdown_req 403 }; 404 405 #define MISC_LEDS 0x01600000 406 #define MISC_CFG 0x01800000 407 #define MISC_DIAG 0x01a00000 408 #define MISC_MDM 0x01b00000 409 #define MISC_SYS 0x01f00000 410 411 static void slavio_misc_init(hwaddr base, 412 hwaddr aux1_base, 413 hwaddr aux2_base, qemu_irq irq, 414 qemu_irq fdc_tc) 415 { 416 DeviceState *dev; 417 SysBusDevice *s; 418 419 dev = qdev_create(NULL, "slavio_misc"); 420 qdev_init_nofail(dev); 421 s = SYS_BUS_DEVICE(dev); 422 if (base) { 423 /* 8 bit registers */ 424 /* Slavio control */ 425 sysbus_mmio_map(s, 0, base + MISC_CFG); 426 /* Diagnostics */ 427 sysbus_mmio_map(s, 1, base + MISC_DIAG); 428 /* Modem control */ 429 sysbus_mmio_map(s, 2, base + MISC_MDM); 430 /* 16 bit registers */ 431 /* ss600mp diag LEDs */ 432 sysbus_mmio_map(s, 3, base + MISC_LEDS); 433 /* 32 bit registers */ 434 /* System control */ 435 sysbus_mmio_map(s, 4, base + MISC_SYS); 436 } 437 if (aux1_base) { 438 /* AUX 1 (Misc System Functions) */ 439 sysbus_mmio_map(s, 5, aux1_base); 440 } 441 if (aux2_base) { 442 /* AUX 2 (Software Powerdown Control) */ 443 sysbus_mmio_map(s, 6, aux2_base); 444 } 445 sysbus_connect_irq(s, 0, irq); 446 sysbus_connect_irq(s, 1, fdc_tc); 447 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 448 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 449 } 450 451 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 452 { 453 DeviceState *dev; 454 SysBusDevice *s; 455 456 dev = qdev_create(NULL, "eccmemctl"); 457 qdev_prop_set_uint32(dev, "version", version); 458 qdev_init_nofail(dev); 459 s = SYS_BUS_DEVICE(dev); 460 sysbus_connect_irq(s, 0, irq); 461 sysbus_mmio_map(s, 0, base); 462 if (version == 0) { // SS-600MP only 463 sysbus_mmio_map(s, 1, base + 0x1000); 464 } 465 } 466 467 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 468 { 469 DeviceState *dev; 470 SysBusDevice *s; 471 472 dev = qdev_create(NULL, "apc"); 473 qdev_init_nofail(dev); 474 s = SYS_BUS_DEVICE(dev); 475 /* Power management (APC) XXX: not a Slavio device */ 476 sysbus_mmio_map(s, 0, power_base); 477 sysbus_connect_irq(s, 0, cpu_halt); 478 } 479 480 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 481 int height, int depth) 482 { 483 DeviceState *dev; 484 SysBusDevice *s; 485 486 dev = qdev_create(NULL, "SUNW,tcx"); 487 qdev_prop_set_uint32(dev, "vram_size", vram_size); 488 qdev_prop_set_uint16(dev, "width", width); 489 qdev_prop_set_uint16(dev, "height", height); 490 qdev_prop_set_uint16(dev, "depth", depth); 491 qdev_prop_set_uint64(dev, "prom_addr", addr); 492 qdev_init_nofail(dev); 493 s = SYS_BUS_DEVICE(dev); 494 495 /* 10/ROM : FCode ROM */ 496 sysbus_mmio_map(s, 0, addr); 497 /* 2/STIP : Stipple */ 498 sysbus_mmio_map(s, 1, addr + 0x04000000ULL); 499 /* 3/BLIT : Blitter */ 500 sysbus_mmio_map(s, 2, addr + 0x06000000ULL); 501 /* 5/RSTIP : Raw Stipple */ 502 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); 503 /* 6/RBLIT : Raw Blitter */ 504 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); 505 /* 7/TEC : Transform Engine */ 506 sysbus_mmio_map(s, 5, addr + 0x00700000ULL); 507 /* 8/CMAP : DAC */ 508 sysbus_mmio_map(s, 6, addr + 0x00200000ULL); 509 /* 9/THC : */ 510 if (depth == 8) { 511 sysbus_mmio_map(s, 7, addr + 0x00300000ULL); 512 } else { 513 sysbus_mmio_map(s, 7, addr + 0x00301000ULL); 514 } 515 /* 11/DHC : */ 516 sysbus_mmio_map(s, 8, addr + 0x00240000ULL); 517 /* 12/ALT : */ 518 sysbus_mmio_map(s, 9, addr + 0x00280000ULL); 519 /* 0/DFB8 : 8-bit plane */ 520 sysbus_mmio_map(s, 10, addr + 0x00800000ULL); 521 /* 1/DFB24 : 24bit plane */ 522 sysbus_mmio_map(s, 11, addr + 0x02000000ULL); 523 /* 4/RDFB32: Raw framebuffer. Control plane */ 524 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); 525 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 526 if (depth == 8) { 527 sysbus_mmio_map(s, 13, addr + 0x00301000ULL); 528 } 529 530 sysbus_connect_irq(s, 0, irq); 531 } 532 533 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 534 int height, int depth) 535 { 536 DeviceState *dev; 537 SysBusDevice *s; 538 539 dev = qdev_create(NULL, "cgthree"); 540 qdev_prop_set_uint32(dev, "vram-size", vram_size); 541 qdev_prop_set_uint16(dev, "width", width); 542 qdev_prop_set_uint16(dev, "height", height); 543 qdev_prop_set_uint16(dev, "depth", depth); 544 qdev_prop_set_uint64(dev, "prom-addr", addr); 545 qdev_init_nofail(dev); 546 s = SYS_BUS_DEVICE(dev); 547 548 /* FCode ROM */ 549 sysbus_mmio_map(s, 0, addr); 550 /* DAC */ 551 sysbus_mmio_map(s, 1, addr + 0x400000ULL); 552 /* 8-bit plane */ 553 sysbus_mmio_map(s, 2, addr + 0x800000ULL); 554 555 sysbus_connect_irq(s, 0, irq); 556 } 557 558 /* NCR89C100/MACIO Internal ID register */ 559 560 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 561 562 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 563 564 static void idreg_init(hwaddr addr) 565 { 566 DeviceState *dev; 567 SysBusDevice *s; 568 569 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER); 570 qdev_init_nofail(dev); 571 s = SYS_BUS_DEVICE(dev); 572 573 sysbus_mmio_map(s, 0, addr); 574 cpu_physical_memory_write_rom(&address_space_memory, 575 addr, idreg_data, sizeof(idreg_data)); 576 } 577 578 #define MACIO_ID_REGISTER(obj) \ 579 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER) 580 581 typedef struct IDRegState { 582 SysBusDevice parent_obj; 583 584 MemoryRegion mem; 585 } IDRegState; 586 587 static int idreg_init1(SysBusDevice *dev) 588 { 589 IDRegState *s = MACIO_ID_REGISTER(dev); 590 591 memory_region_init_ram(&s->mem, OBJECT(s), 592 "sun4m.idreg", sizeof(idreg_data), &error_fatal); 593 vmstate_register_ram_global(&s->mem); 594 memory_region_set_readonly(&s->mem, true); 595 sysbus_init_mmio(dev, &s->mem); 596 return 0; 597 } 598 599 static void idreg_class_init(ObjectClass *klass, void *data) 600 { 601 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 602 603 k->init = idreg_init1; 604 } 605 606 static const TypeInfo idreg_info = { 607 .name = TYPE_MACIO_ID_REGISTER, 608 .parent = TYPE_SYS_BUS_DEVICE, 609 .instance_size = sizeof(IDRegState), 610 .class_init = idreg_class_init, 611 }; 612 613 #define TYPE_TCX_AFX "tcx_afx" 614 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX) 615 616 typedef struct AFXState { 617 SysBusDevice parent_obj; 618 619 MemoryRegion mem; 620 } AFXState; 621 622 /* SS-5 TCX AFX register */ 623 static void afx_init(hwaddr addr) 624 { 625 DeviceState *dev; 626 SysBusDevice *s; 627 628 dev = qdev_create(NULL, TYPE_TCX_AFX); 629 qdev_init_nofail(dev); 630 s = SYS_BUS_DEVICE(dev); 631 632 sysbus_mmio_map(s, 0, addr); 633 } 634 635 static int afx_init1(SysBusDevice *dev) 636 { 637 AFXState *s = TCX_AFX(dev); 638 639 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4, &error_fatal); 640 vmstate_register_ram_global(&s->mem); 641 sysbus_init_mmio(dev, &s->mem); 642 return 0; 643 } 644 645 static void afx_class_init(ObjectClass *klass, void *data) 646 { 647 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 648 649 k->init = afx_init1; 650 } 651 652 static const TypeInfo afx_info = { 653 .name = TYPE_TCX_AFX, 654 .parent = TYPE_SYS_BUS_DEVICE, 655 .instance_size = sizeof(AFXState), 656 .class_init = afx_class_init, 657 }; 658 659 #define TYPE_OPENPROM "openprom" 660 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 661 662 typedef struct PROMState { 663 SysBusDevice parent_obj; 664 665 MemoryRegion prom; 666 } PROMState; 667 668 /* Boot PROM (OpenBIOS) */ 669 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 670 { 671 hwaddr *base_addr = (hwaddr *)opaque; 672 return addr + *base_addr - PROM_VADDR; 673 } 674 675 static void prom_init(hwaddr addr, const char *bios_name) 676 { 677 DeviceState *dev; 678 SysBusDevice *s; 679 char *filename; 680 int ret; 681 682 dev = qdev_create(NULL, TYPE_OPENPROM); 683 qdev_init_nofail(dev); 684 s = SYS_BUS_DEVICE(dev); 685 686 sysbus_mmio_map(s, 0, addr); 687 688 /* load boot prom */ 689 if (bios_name == NULL) { 690 bios_name = PROM_FILENAME; 691 } 692 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 693 if (filename) { 694 ret = load_elf(filename, translate_prom_address, &addr, NULL, 695 NULL, NULL, 1, EM_SPARC, 0, 0); 696 if (ret < 0 || ret > PROM_SIZE_MAX) { 697 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 698 } 699 g_free(filename); 700 } else { 701 ret = -1; 702 } 703 if (ret < 0 || ret > PROM_SIZE_MAX) { 704 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 705 exit(1); 706 } 707 } 708 709 static int prom_init1(SysBusDevice *dev) 710 { 711 PROMState *s = OPENPROM(dev); 712 713 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX, 714 &error_fatal); 715 vmstate_register_ram_global(&s->prom); 716 memory_region_set_readonly(&s->prom, true); 717 sysbus_init_mmio(dev, &s->prom); 718 return 0; 719 } 720 721 static Property prom_properties[] = { 722 {/* end of property list */}, 723 }; 724 725 static void prom_class_init(ObjectClass *klass, void *data) 726 { 727 DeviceClass *dc = DEVICE_CLASS(klass); 728 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 729 730 k->init = prom_init1; 731 dc->props = prom_properties; 732 } 733 734 static const TypeInfo prom_info = { 735 .name = TYPE_OPENPROM, 736 .parent = TYPE_SYS_BUS_DEVICE, 737 .instance_size = sizeof(PROMState), 738 .class_init = prom_class_init, 739 }; 740 741 #define TYPE_SUN4M_MEMORY "memory" 742 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY) 743 744 typedef struct RamDevice { 745 SysBusDevice parent_obj; 746 747 MemoryRegion ram; 748 uint64_t size; 749 } RamDevice; 750 751 /* System RAM */ 752 static int ram_init1(SysBusDevice *dev) 753 { 754 RamDevice *d = SUN4M_RAM(dev); 755 756 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram", 757 d->size); 758 sysbus_init_mmio(dev, &d->ram); 759 return 0; 760 } 761 762 static void ram_init(hwaddr addr, ram_addr_t RAM_size, 763 uint64_t max_mem) 764 { 765 DeviceState *dev; 766 SysBusDevice *s; 767 RamDevice *d; 768 769 /* allocate RAM */ 770 if ((uint64_t)RAM_size > max_mem) { 771 fprintf(stderr, 772 "qemu: Too much memory for this machine: %d, maximum %d\n", 773 (unsigned int)(RAM_size / (1024 * 1024)), 774 (unsigned int)(max_mem / (1024 * 1024))); 775 exit(1); 776 } 777 dev = qdev_create(NULL, "memory"); 778 s = SYS_BUS_DEVICE(dev); 779 780 d = SUN4M_RAM(dev); 781 d->size = RAM_size; 782 qdev_init_nofail(dev); 783 784 sysbus_mmio_map(s, 0, addr); 785 } 786 787 static Property ram_properties[] = { 788 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 789 DEFINE_PROP_END_OF_LIST(), 790 }; 791 792 static void ram_class_init(ObjectClass *klass, void *data) 793 { 794 DeviceClass *dc = DEVICE_CLASS(klass); 795 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 796 797 k->init = ram_init1; 798 dc->props = ram_properties; 799 } 800 801 static const TypeInfo ram_info = { 802 .name = TYPE_SUN4M_MEMORY, 803 .parent = TYPE_SYS_BUS_DEVICE, 804 .instance_size = sizeof(RamDevice), 805 .class_init = ram_class_init, 806 }; 807 808 static void cpu_devinit(const char *cpu_model, unsigned int id, 809 uint64_t prom_addr, qemu_irq **cpu_irqs) 810 { 811 CPUState *cs; 812 SPARCCPU *cpu; 813 CPUSPARCState *env; 814 815 cpu = cpu_sparc_init(cpu_model); 816 if (cpu == NULL) { 817 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); 818 exit(1); 819 } 820 env = &cpu->env; 821 822 cpu_sparc_set_id(env, id); 823 if (id == 0) { 824 qemu_register_reset(main_cpu_reset, cpu); 825 } else { 826 qemu_register_reset(secondary_cpu_reset, cpu); 827 cs = CPU(cpu); 828 cs->halted = 1; 829 } 830 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 831 env->prom_addr = prom_addr; 832 } 833 834 static void dummy_fdc_tc(void *opaque, int irq, int level) 835 { 836 } 837 838 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, 839 MachineState *machine) 840 { 841 DeviceState *slavio_intctl; 842 const char *cpu_model = machine->cpu_model; 843 unsigned int i; 844 void *iommu, *espdma, *ledma, *nvram; 845 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS], 846 espdma_irq, ledma_irq; 847 qemu_irq esp_reset, dma_enable; 848 qemu_irq fdc_tc; 849 unsigned long kernel_size; 850 DriveInfo *fd[MAX_FD]; 851 FWCfgState *fw_cfg; 852 unsigned int num_vsimms; 853 854 /* init CPUs */ 855 if (!cpu_model) 856 cpu_model = hwdef->default_cpu_model; 857 858 for(i = 0; i < smp_cpus; i++) { 859 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); 860 } 861 862 for (i = smp_cpus; i < MAX_CPUS; i++) 863 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 864 865 866 /* set up devices */ 867 ram_init(0, machine->ram_size, hwdef->max_mem); 868 /* models without ECC don't trap when missing ram is accessed */ 869 if (!hwdef->ecc_base) { 870 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size); 871 } 872 873 prom_init(hwdef->slavio_base, bios_name); 874 875 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 876 hwdef->intctl_base + 0x10000ULL, 877 cpu_irqs); 878 879 for (i = 0; i < 32; i++) { 880 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 881 } 882 for (i = 0; i < MAX_CPUS; i++) { 883 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 884 } 885 886 if (hwdef->idreg_base) { 887 idreg_init(hwdef->idreg_base); 888 } 889 890 if (hwdef->afx_base) { 891 afx_init(hwdef->afx_base); 892 } 893 894 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, 895 slavio_irq[30]); 896 897 if (hwdef->iommu_pad_base) { 898 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 899 Software shouldn't use aliased addresses, neither should it crash 900 when does. Using empty_slot instead of aliasing can help with 901 debugging such accesses */ 902 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); 903 } 904 905 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18], 906 iommu, &espdma_irq, 0); 907 908 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, 909 slavio_irq[16], iommu, &ledma_irq, 1); 910 911 if (graphic_depth != 8 && graphic_depth != 24) { 912 error_report("Unsupported depth: %d", graphic_depth); 913 exit (1); 914 } 915 num_vsimms = 0; 916 if (num_vsimms == 0) { 917 if (vga_interface_type == VGA_CG3) { 918 if (graphic_depth != 8) { 919 error_report("Unsupported depth: %d", graphic_depth); 920 exit(1); 921 } 922 923 if (!(graphic_width == 1024 && graphic_height == 768) && 924 !(graphic_width == 1152 && graphic_height == 900)) { 925 error_report("Unsupported resolution: %d x %d", graphic_width, 926 graphic_height); 927 exit(1); 928 } 929 930 /* sbus irq 5 */ 931 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 932 graphic_width, graphic_height, graphic_depth); 933 } else { 934 /* If no display specified, default to TCX */ 935 if (graphic_depth != 8 && graphic_depth != 24) { 936 error_report("Unsupported depth: %d", graphic_depth); 937 exit(1); 938 } 939 940 if (!(graphic_width == 1024 && graphic_height == 768)) { 941 error_report("Unsupported resolution: %d x %d", 942 graphic_width, graphic_height); 943 exit(1); 944 } 945 946 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 947 graphic_width, graphic_height, graphic_depth); 948 } 949 } 950 951 for (i = num_vsimms; i < MAX_VSIMMS; i++) { 952 /* vsimm registers probed by OBP */ 953 if (hwdef->vsimm[i].reg_base) { 954 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); 955 } 956 } 957 958 if (hwdef->sx_base) { 959 empty_slot_init(hwdef->sx_base, 0x2000); 960 } 961 962 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq); 963 964 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8); 965 966 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 967 968 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14], 969 !machine->enable_graphics, ESCC_CLOCK, 1); 970 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 971 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 972 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], 973 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); 974 975 if (hwdef->apc_base) { 976 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); 977 } 978 979 if (hwdef->fd_base) { 980 /* there is zero or one floppy drive */ 981 memset(fd, 0, sizeof(fd)); 982 fd[0] = drive_get(IF_FLOPPY, 0, 0); 983 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 984 &fdc_tc); 985 } else { 986 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); 987 } 988 989 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 990 slavio_irq[30], fdc_tc); 991 992 esp_init(hwdef->esp_base, 2, 993 espdma_memory_read, espdma_memory_write, 994 espdma, espdma_irq, &esp_reset, &dma_enable); 995 996 qdev_connect_gpio_out(espdma, 0, esp_reset); 997 qdev_connect_gpio_out(espdma, 1, dma_enable); 998 999 if (hwdef->cs_base) { 1000 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, 1001 slavio_irq[5]); 1002 } 1003 1004 if (hwdef->dbri_base) { 1005 /* ISDN chip with attached CS4215 audio codec */ 1006 /* prom space */ 1007 empty_slot_init(hwdef->dbri_base+0x1000, 0x30); 1008 /* reg space */ 1009 empty_slot_init(hwdef->dbri_base+0x10000, 0x100); 1010 } 1011 1012 if (hwdef->bpp_base) { 1013 /* parallel port */ 1014 empty_slot_init(hwdef->bpp_base, 0x20); 1015 } 1016 1017 kernel_size = sun4m_load_kernel(machine->kernel_filename, 1018 machine->initrd_filename, 1019 machine->ram_size); 1020 1021 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline, 1022 machine->boot_order, machine->ram_size, kernel_size, 1023 graphic_width, graphic_height, graphic_depth, 1024 hwdef->nvram_machine_id, "Sun4m"); 1025 1026 if (hwdef->ecc_base) 1027 ecc_init(hwdef->ecc_base, slavio_irq[28], 1028 hwdef->ecc_version); 1029 1030 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 1031 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 1032 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1033 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1034 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1035 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1036 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1037 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1038 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1039 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1040 if (machine->kernel_cmdline) { 1041 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1042 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1043 machine->kernel_cmdline); 1044 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 1045 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1046 strlen(machine->kernel_cmdline) + 1); 1047 } else { 1048 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1049 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1050 } 1051 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1052 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used 1053 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 1054 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1055 } 1056 1057 enum { 1058 ss5_id = 32, 1059 vger_id, 1060 lx_id, 1061 ss4_id, 1062 scls_id, 1063 sbook_id, 1064 ss10_id = 64, 1065 ss20_id, 1066 ss600mp_id, 1067 }; 1068 1069 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1070 /* SS-5 */ 1071 { 1072 .iommu_base = 0x10000000, 1073 .iommu_pad_base = 0x10004000, 1074 .iommu_pad_len = 0x0fffb000, 1075 .tcx_base = 0x50000000, 1076 .cs_base = 0x6c000000, 1077 .slavio_base = 0x70000000, 1078 .ms_kb_base = 0x71000000, 1079 .serial_base = 0x71100000, 1080 .nvram_base = 0x71200000, 1081 .fd_base = 0x71400000, 1082 .counter_base = 0x71d00000, 1083 .intctl_base = 0x71e00000, 1084 .idreg_base = 0x78000000, 1085 .dma_base = 0x78400000, 1086 .esp_base = 0x78800000, 1087 .le_base = 0x78c00000, 1088 .apc_base = 0x6a000000, 1089 .afx_base = 0x6e000000, 1090 .aux1_base = 0x71900000, 1091 .aux2_base = 0x71910000, 1092 .nvram_machine_id = 0x80, 1093 .machine_id = ss5_id, 1094 .iommu_version = 0x05000000, 1095 .max_mem = 0x10000000, 1096 .default_cpu_model = "Fujitsu MB86904", 1097 }, 1098 /* SS-10 */ 1099 { 1100 .iommu_base = 0xfe0000000ULL, 1101 .tcx_base = 0xe20000000ULL, 1102 .slavio_base = 0xff0000000ULL, 1103 .ms_kb_base = 0xff1000000ULL, 1104 .serial_base = 0xff1100000ULL, 1105 .nvram_base = 0xff1200000ULL, 1106 .fd_base = 0xff1700000ULL, 1107 .counter_base = 0xff1300000ULL, 1108 .intctl_base = 0xff1400000ULL, 1109 .idreg_base = 0xef0000000ULL, 1110 .dma_base = 0xef0400000ULL, 1111 .esp_base = 0xef0800000ULL, 1112 .le_base = 0xef0c00000ULL, 1113 .apc_base = 0xefa000000ULL, // XXX should not exist 1114 .aux1_base = 0xff1800000ULL, 1115 .aux2_base = 0xff1a01000ULL, 1116 .ecc_base = 0xf00000000ULL, 1117 .ecc_version = 0x10000000, // version 0, implementation 1 1118 .nvram_machine_id = 0x72, 1119 .machine_id = ss10_id, 1120 .iommu_version = 0x03000000, 1121 .max_mem = 0xf00000000ULL, 1122 .default_cpu_model = "TI SuperSparc II", 1123 }, 1124 /* SS-600MP */ 1125 { 1126 .iommu_base = 0xfe0000000ULL, 1127 .tcx_base = 0xe20000000ULL, 1128 .slavio_base = 0xff0000000ULL, 1129 .ms_kb_base = 0xff1000000ULL, 1130 .serial_base = 0xff1100000ULL, 1131 .nvram_base = 0xff1200000ULL, 1132 .counter_base = 0xff1300000ULL, 1133 .intctl_base = 0xff1400000ULL, 1134 .dma_base = 0xef0081000ULL, 1135 .esp_base = 0xef0080000ULL, 1136 .le_base = 0xef0060000ULL, 1137 .apc_base = 0xefa000000ULL, // XXX should not exist 1138 .aux1_base = 0xff1800000ULL, 1139 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1140 .ecc_base = 0xf00000000ULL, 1141 .ecc_version = 0x00000000, // version 0, implementation 0 1142 .nvram_machine_id = 0x71, 1143 .machine_id = ss600mp_id, 1144 .iommu_version = 0x01000000, 1145 .max_mem = 0xf00000000ULL, 1146 .default_cpu_model = "TI SuperSparc II", 1147 }, 1148 /* SS-20 */ 1149 { 1150 .iommu_base = 0xfe0000000ULL, 1151 .tcx_base = 0xe20000000ULL, 1152 .slavio_base = 0xff0000000ULL, 1153 .ms_kb_base = 0xff1000000ULL, 1154 .serial_base = 0xff1100000ULL, 1155 .nvram_base = 0xff1200000ULL, 1156 .fd_base = 0xff1700000ULL, 1157 .counter_base = 0xff1300000ULL, 1158 .intctl_base = 0xff1400000ULL, 1159 .idreg_base = 0xef0000000ULL, 1160 .dma_base = 0xef0400000ULL, 1161 .esp_base = 0xef0800000ULL, 1162 .le_base = 0xef0c00000ULL, 1163 .bpp_base = 0xef4800000ULL, 1164 .apc_base = 0xefa000000ULL, // XXX should not exist 1165 .aux1_base = 0xff1800000ULL, 1166 .aux2_base = 0xff1a01000ULL, 1167 .dbri_base = 0xee0000000ULL, 1168 .sx_base = 0xf80000000ULL, 1169 .vsimm = { 1170 { 1171 .reg_base = 0x9c000000ULL, 1172 .vram_base = 0xfc000000ULL 1173 }, { 1174 .reg_base = 0x90000000ULL, 1175 .vram_base = 0xf0000000ULL 1176 }, { 1177 .reg_base = 0x94000000ULL 1178 }, { 1179 .reg_base = 0x98000000ULL 1180 } 1181 }, 1182 .ecc_base = 0xf00000000ULL, 1183 .ecc_version = 0x20000000, // version 0, implementation 2 1184 .nvram_machine_id = 0x72, 1185 .machine_id = ss20_id, 1186 .iommu_version = 0x13000000, 1187 .max_mem = 0xf00000000ULL, 1188 .default_cpu_model = "TI SuperSparc II", 1189 }, 1190 /* Voyager */ 1191 { 1192 .iommu_base = 0x10000000, 1193 .tcx_base = 0x50000000, 1194 .slavio_base = 0x70000000, 1195 .ms_kb_base = 0x71000000, 1196 .serial_base = 0x71100000, 1197 .nvram_base = 0x71200000, 1198 .fd_base = 0x71400000, 1199 .counter_base = 0x71d00000, 1200 .intctl_base = 0x71e00000, 1201 .idreg_base = 0x78000000, 1202 .dma_base = 0x78400000, 1203 .esp_base = 0x78800000, 1204 .le_base = 0x78c00000, 1205 .apc_base = 0x71300000, // pmc 1206 .aux1_base = 0x71900000, 1207 .aux2_base = 0x71910000, 1208 .nvram_machine_id = 0x80, 1209 .machine_id = vger_id, 1210 .iommu_version = 0x05000000, 1211 .max_mem = 0x10000000, 1212 .default_cpu_model = "Fujitsu MB86904", 1213 }, 1214 /* LX */ 1215 { 1216 .iommu_base = 0x10000000, 1217 .iommu_pad_base = 0x10004000, 1218 .iommu_pad_len = 0x0fffb000, 1219 .tcx_base = 0x50000000, 1220 .slavio_base = 0x70000000, 1221 .ms_kb_base = 0x71000000, 1222 .serial_base = 0x71100000, 1223 .nvram_base = 0x71200000, 1224 .fd_base = 0x71400000, 1225 .counter_base = 0x71d00000, 1226 .intctl_base = 0x71e00000, 1227 .idreg_base = 0x78000000, 1228 .dma_base = 0x78400000, 1229 .esp_base = 0x78800000, 1230 .le_base = 0x78c00000, 1231 .aux1_base = 0x71900000, 1232 .aux2_base = 0x71910000, 1233 .nvram_machine_id = 0x80, 1234 .machine_id = lx_id, 1235 .iommu_version = 0x04000000, 1236 .max_mem = 0x10000000, 1237 .default_cpu_model = "TI MicroSparc I", 1238 }, 1239 /* SS-4 */ 1240 { 1241 .iommu_base = 0x10000000, 1242 .tcx_base = 0x50000000, 1243 .cs_base = 0x6c000000, 1244 .slavio_base = 0x70000000, 1245 .ms_kb_base = 0x71000000, 1246 .serial_base = 0x71100000, 1247 .nvram_base = 0x71200000, 1248 .fd_base = 0x71400000, 1249 .counter_base = 0x71d00000, 1250 .intctl_base = 0x71e00000, 1251 .idreg_base = 0x78000000, 1252 .dma_base = 0x78400000, 1253 .esp_base = 0x78800000, 1254 .le_base = 0x78c00000, 1255 .apc_base = 0x6a000000, 1256 .aux1_base = 0x71900000, 1257 .aux2_base = 0x71910000, 1258 .nvram_machine_id = 0x80, 1259 .machine_id = ss4_id, 1260 .iommu_version = 0x05000000, 1261 .max_mem = 0x10000000, 1262 .default_cpu_model = "Fujitsu MB86904", 1263 }, 1264 /* SPARCClassic */ 1265 { 1266 .iommu_base = 0x10000000, 1267 .tcx_base = 0x50000000, 1268 .slavio_base = 0x70000000, 1269 .ms_kb_base = 0x71000000, 1270 .serial_base = 0x71100000, 1271 .nvram_base = 0x71200000, 1272 .fd_base = 0x71400000, 1273 .counter_base = 0x71d00000, 1274 .intctl_base = 0x71e00000, 1275 .idreg_base = 0x78000000, 1276 .dma_base = 0x78400000, 1277 .esp_base = 0x78800000, 1278 .le_base = 0x78c00000, 1279 .apc_base = 0x6a000000, 1280 .aux1_base = 0x71900000, 1281 .aux2_base = 0x71910000, 1282 .nvram_machine_id = 0x80, 1283 .machine_id = scls_id, 1284 .iommu_version = 0x05000000, 1285 .max_mem = 0x10000000, 1286 .default_cpu_model = "TI MicroSparc I", 1287 }, 1288 /* SPARCbook */ 1289 { 1290 .iommu_base = 0x10000000, 1291 .tcx_base = 0x50000000, // XXX 1292 .slavio_base = 0x70000000, 1293 .ms_kb_base = 0x71000000, 1294 .serial_base = 0x71100000, 1295 .nvram_base = 0x71200000, 1296 .fd_base = 0x71400000, 1297 .counter_base = 0x71d00000, 1298 .intctl_base = 0x71e00000, 1299 .idreg_base = 0x78000000, 1300 .dma_base = 0x78400000, 1301 .esp_base = 0x78800000, 1302 .le_base = 0x78c00000, 1303 .apc_base = 0x6a000000, 1304 .aux1_base = 0x71900000, 1305 .aux2_base = 0x71910000, 1306 .nvram_machine_id = 0x80, 1307 .machine_id = sbook_id, 1308 .iommu_version = 0x05000000, 1309 .max_mem = 0x10000000, 1310 .default_cpu_model = "TI MicroSparc I", 1311 }, 1312 }; 1313 1314 /* SPARCstation 5 hardware initialisation */ 1315 static void ss5_init(MachineState *machine) 1316 { 1317 sun4m_hw_init(&sun4m_hwdefs[0], machine); 1318 } 1319 1320 /* SPARCstation 10 hardware initialisation */ 1321 static void ss10_init(MachineState *machine) 1322 { 1323 sun4m_hw_init(&sun4m_hwdefs[1], machine); 1324 } 1325 1326 /* SPARCserver 600MP hardware initialisation */ 1327 static void ss600mp_init(MachineState *machine) 1328 { 1329 sun4m_hw_init(&sun4m_hwdefs[2], machine); 1330 } 1331 1332 /* SPARCstation 20 hardware initialisation */ 1333 static void ss20_init(MachineState *machine) 1334 { 1335 sun4m_hw_init(&sun4m_hwdefs[3], machine); 1336 } 1337 1338 /* SPARCstation Voyager hardware initialisation */ 1339 static void vger_init(MachineState *machine) 1340 { 1341 sun4m_hw_init(&sun4m_hwdefs[4], machine); 1342 } 1343 1344 /* SPARCstation LX hardware initialisation */ 1345 static void ss_lx_init(MachineState *machine) 1346 { 1347 sun4m_hw_init(&sun4m_hwdefs[5], machine); 1348 } 1349 1350 /* SPARCstation 4 hardware initialisation */ 1351 static void ss4_init(MachineState *machine) 1352 { 1353 sun4m_hw_init(&sun4m_hwdefs[6], machine); 1354 } 1355 1356 /* SPARCClassic hardware initialisation */ 1357 static void scls_init(MachineState *machine) 1358 { 1359 sun4m_hw_init(&sun4m_hwdefs[7], machine); 1360 } 1361 1362 /* SPARCbook hardware initialisation */ 1363 static void sbook_init(MachineState *machine) 1364 { 1365 sun4m_hw_init(&sun4m_hwdefs[8], machine); 1366 } 1367 1368 static void ss5_class_init(ObjectClass *oc, void *data) 1369 { 1370 MachineClass *mc = MACHINE_CLASS(oc); 1371 1372 mc->desc = "Sun4m platform, SPARCstation 5"; 1373 mc->init = ss5_init; 1374 mc->block_default_type = IF_SCSI; 1375 mc->is_default = 1; 1376 mc->default_boot_order = "c"; 1377 } 1378 1379 static const TypeInfo ss5_type = { 1380 .name = MACHINE_TYPE_NAME("SS-5"), 1381 .parent = TYPE_MACHINE, 1382 .class_init = ss5_class_init, 1383 }; 1384 1385 static void ss10_class_init(ObjectClass *oc, void *data) 1386 { 1387 MachineClass *mc = MACHINE_CLASS(oc); 1388 1389 mc->desc = "Sun4m platform, SPARCstation 10"; 1390 mc->init = ss10_init; 1391 mc->block_default_type = IF_SCSI; 1392 mc->max_cpus = 4; 1393 mc->default_boot_order = "c"; 1394 } 1395 1396 static const TypeInfo ss10_type = { 1397 .name = MACHINE_TYPE_NAME("SS-10"), 1398 .parent = TYPE_MACHINE, 1399 .class_init = ss10_class_init, 1400 }; 1401 1402 static void ss600mp_class_init(ObjectClass *oc, void *data) 1403 { 1404 MachineClass *mc = MACHINE_CLASS(oc); 1405 1406 mc->desc = "Sun4m platform, SPARCserver 600MP"; 1407 mc->init = ss600mp_init; 1408 mc->block_default_type = IF_SCSI; 1409 mc->max_cpus = 4; 1410 mc->default_boot_order = "c"; 1411 } 1412 1413 static const TypeInfo ss600mp_type = { 1414 .name = MACHINE_TYPE_NAME("SS-600MP"), 1415 .parent = TYPE_MACHINE, 1416 .class_init = ss600mp_class_init, 1417 }; 1418 1419 static void ss20_class_init(ObjectClass *oc, void *data) 1420 { 1421 MachineClass *mc = MACHINE_CLASS(oc); 1422 1423 mc->desc = "Sun4m platform, SPARCstation 20"; 1424 mc->init = ss20_init; 1425 mc->block_default_type = IF_SCSI; 1426 mc->max_cpus = 4; 1427 mc->default_boot_order = "c"; 1428 } 1429 1430 static const TypeInfo ss20_type = { 1431 .name = MACHINE_TYPE_NAME("SS-20"), 1432 .parent = TYPE_MACHINE, 1433 .class_init = ss20_class_init, 1434 }; 1435 1436 static void voyager_class_init(ObjectClass *oc, void *data) 1437 { 1438 MachineClass *mc = MACHINE_CLASS(oc); 1439 1440 mc->desc = "Sun4m platform, SPARCstation Voyager"; 1441 mc->init = vger_init; 1442 mc->block_default_type = IF_SCSI; 1443 mc->default_boot_order = "c"; 1444 } 1445 1446 static const TypeInfo voyager_type = { 1447 .name = MACHINE_TYPE_NAME("Voyager"), 1448 .parent = TYPE_MACHINE, 1449 .class_init = voyager_class_init, 1450 }; 1451 1452 static void ss_lx_class_init(ObjectClass *oc, void *data) 1453 { 1454 MachineClass *mc = MACHINE_CLASS(oc); 1455 1456 mc->desc = "Sun4m platform, SPARCstation LX"; 1457 mc->init = ss_lx_init; 1458 mc->block_default_type = IF_SCSI; 1459 mc->default_boot_order = "c"; 1460 } 1461 1462 static const TypeInfo ss_lx_type = { 1463 .name = MACHINE_TYPE_NAME("LX"), 1464 .parent = TYPE_MACHINE, 1465 .class_init = ss_lx_class_init, 1466 }; 1467 1468 static void ss4_class_init(ObjectClass *oc, void *data) 1469 { 1470 MachineClass *mc = MACHINE_CLASS(oc); 1471 1472 mc->desc = "Sun4m platform, SPARCstation 4"; 1473 mc->init = ss4_init; 1474 mc->block_default_type = IF_SCSI; 1475 mc->default_boot_order = "c"; 1476 } 1477 1478 static const TypeInfo ss4_type = { 1479 .name = MACHINE_TYPE_NAME("SS-4"), 1480 .parent = TYPE_MACHINE, 1481 .class_init = ss4_class_init, 1482 }; 1483 1484 static void scls_class_init(ObjectClass *oc, void *data) 1485 { 1486 MachineClass *mc = MACHINE_CLASS(oc); 1487 1488 mc->desc = "Sun4m platform, SPARCClassic"; 1489 mc->init = scls_init; 1490 mc->block_default_type = IF_SCSI; 1491 mc->default_boot_order = "c"; 1492 } 1493 1494 static const TypeInfo scls_type = { 1495 .name = MACHINE_TYPE_NAME("SPARCClassic"), 1496 .parent = TYPE_MACHINE, 1497 .class_init = scls_class_init, 1498 }; 1499 1500 static void sbook_class_init(ObjectClass *oc, void *data) 1501 { 1502 MachineClass *mc = MACHINE_CLASS(oc); 1503 1504 mc->desc = "Sun4m platform, SPARCbook"; 1505 mc->init = sbook_init; 1506 mc->block_default_type = IF_SCSI; 1507 mc->default_boot_order = "c"; 1508 } 1509 1510 static const TypeInfo sbook_type = { 1511 .name = MACHINE_TYPE_NAME("SPARCbook"), 1512 .parent = TYPE_MACHINE, 1513 .class_init = sbook_class_init, 1514 }; 1515 1516 static void sun4m_register_types(void) 1517 { 1518 type_register_static(&idreg_info); 1519 type_register_static(&afx_info); 1520 type_register_static(&prom_info); 1521 type_register_static(&ram_info); 1522 1523 type_register_static(&ss5_type); 1524 type_register_static(&ss10_type); 1525 type_register_static(&ss600mp_type); 1526 type_register_static(&ss20_type); 1527 type_register_static(&voyager_type); 1528 type_register_static(&ss_lx_type); 1529 type_register_static(&ss4_type); 1530 type_register_static(&scls_type); 1531 type_register_static(&sbook_type); 1532 } 1533 1534 type_init(sun4m_register_types) 1535