1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "qemu/datadir.h" 29 #include "cpu.h" 30 #include "hw/sysbus.h" 31 #include "qemu/error-report.h" 32 #include "qemu/timer.h" 33 #include "hw/sparc/sun4m_iommu.h" 34 #include "hw/rtc/m48t59.h" 35 #include "migration/vmstate.h" 36 #include "hw/sparc/sparc32_dma.h" 37 #include "hw/block/fdc.h" 38 #include "sysemu/reset.h" 39 #include "sysemu/runstate.h" 40 #include "sysemu/sysemu.h" 41 #include "net/net.h" 42 #include "hw/boards.h" 43 #include "hw/scsi/esp.h" 44 #include "hw/nvram/sun_nvram.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/nvram/chrp_nvram.h" 47 #include "hw/nvram/fw_cfg.h" 48 #include "hw/char/escc.h" 49 #include "hw/misc/empty_slot.h" 50 #include "hw/misc/unimp.h" 51 #include "hw/irq.h" 52 #include "hw/or-irq.h" 53 #include "hw/loader.h" 54 #include "elf.h" 55 #include "trace.h" 56 #include "qom/object.h" 57 58 /* 59 * Sun4m architecture was used in the following machines: 60 * 61 * SPARCserver 6xxMP/xx 62 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 63 * SPARCclassic X (4/10) 64 * SPARCstation LX/ZX (4/30) 65 * SPARCstation Voyager 66 * SPARCstation 10/xx, SPARCserver 10/xx 67 * SPARCstation 5, SPARCserver 5 68 * SPARCstation 20/xx, SPARCserver 20 69 * SPARCstation 4 70 * 71 * See for example: http://www.sunhelp.org/faq/sunref1.html 72 */ 73 74 #define KERNEL_LOAD_ADDR 0x00004000 75 #define CMDLINE_ADDR 0x007ff000 76 #define INITRD_LOAD_ADDR 0x00800000 77 #define PROM_SIZE_MAX (1 * MiB) 78 #define PROM_VADDR 0xffd00000 79 #define PROM_FILENAME "openbios-sparc32" 80 #define CFG_ADDR 0xd00000510ULL 81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 82 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 83 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 84 85 #define MAX_CPUS 16 86 #define MAX_PILS 16 87 #define MAX_VSIMMS 4 88 89 #define ESCC_CLOCK 4915200 90 91 struct sun4m_hwdef { 92 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 93 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 94 hwaddr serial_base, fd_base; 95 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 96 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 97 hwaddr bpp_base, dbri_base, sx_base; 98 struct { 99 hwaddr reg_base, vram_base; 100 } vsimm[MAX_VSIMMS]; 101 hwaddr ecc_base; 102 uint64_t max_mem; 103 uint32_t ecc_version; 104 uint32_t iommu_version; 105 uint16_t machine_id; 106 uint8_t nvram_machine_id; 107 }; 108 109 struct Sun4mMachineClass { 110 /*< private >*/ 111 MachineClass parent_obj; 112 /*< public >*/ 113 const struct sun4m_hwdef *hwdef; 114 }; 115 typedef struct Sun4mMachineClass Sun4mMachineClass; 116 117 #define TYPE_SUN4M_MACHINE MACHINE_TYPE_NAME("sun4m-common") 118 DECLARE_CLASS_CHECKERS(Sun4mMachineClass, SUN4M_MACHINE, TYPE_SUN4M_MACHINE) 119 120 const char *fw_cfg_arch_key_name(uint16_t key) 121 { 122 static const struct { 123 uint16_t key; 124 const char *name; 125 } fw_cfg_arch_wellknown_keys[] = { 126 {FW_CFG_SUN4M_DEPTH, "depth"}, 127 {FW_CFG_SUN4M_WIDTH, "width"}, 128 {FW_CFG_SUN4M_HEIGHT, "height"}, 129 }; 130 131 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { 132 if (fw_cfg_arch_wellknown_keys[i].key == key) { 133 return fw_cfg_arch_wellknown_keys[i].name; 134 } 135 } 136 return NULL; 137 } 138 139 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 140 Error **errp) 141 { 142 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 143 } 144 145 static void nvram_init(Nvram *nvram, uint8_t *macaddr, 146 const char *cmdline, const char *boot_devices, 147 ram_addr_t RAM_size, uint32_t kernel_size, 148 int width, int height, int depth, 149 int nvram_machine_id, const char *arch) 150 { 151 unsigned int i; 152 int sysp_end; 153 uint8_t image[0x1ff0]; 154 NvramClass *k = NVRAM_GET_CLASS(nvram); 155 156 memset(image, '\0', sizeof(image)); 157 158 /* OpenBIOS nvram variables partition */ 159 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0); 160 161 /* Free space partition */ 162 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 163 164 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 165 nvram_machine_id); 166 167 for (i = 0; i < sizeof(image); i++) { 168 (k->write)(nvram, i, image[i]); 169 } 170 } 171 172 static void cpu_kick_irq(SPARCCPU *cpu) 173 { 174 CPUSPARCState *env = &cpu->env; 175 CPUState *cs = CPU(cpu); 176 177 cs->halted = 0; 178 cpu_check_irqs(env); 179 qemu_cpu_kick(cs); 180 } 181 182 static void cpu_set_irq(void *opaque, int irq, int level) 183 { 184 SPARCCPU *cpu = opaque; 185 CPUSPARCState *env = &cpu->env; 186 187 if (level) { 188 trace_sun4m_cpu_set_irq_raise(irq); 189 env->pil_in |= 1 << irq; 190 cpu_kick_irq(cpu); 191 } else { 192 trace_sun4m_cpu_set_irq_lower(irq); 193 env->pil_in &= ~(1 << irq); 194 cpu_check_irqs(env); 195 } 196 } 197 198 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 199 { 200 } 201 202 static void sun4m_cpu_reset(void *opaque) 203 { 204 SPARCCPU *cpu = opaque; 205 CPUState *cs = CPU(cpu); 206 207 cpu_reset(cs); 208 } 209 210 static void cpu_halt_signal(void *opaque, int irq, int level) 211 { 212 if (level && current_cpu) { 213 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 214 } 215 } 216 217 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 218 { 219 return addr - 0xf0000000ULL; 220 } 221 222 static unsigned long sun4m_load_kernel(const char *kernel_filename, 223 const char *initrd_filename, 224 ram_addr_t RAM_size, 225 uint32_t *initrd_size) 226 { 227 int linux_boot; 228 unsigned int i; 229 long kernel_size; 230 uint8_t *ptr; 231 232 linux_boot = (kernel_filename != NULL); 233 234 kernel_size = 0; 235 if (linux_boot) { 236 int bswap_needed; 237 238 #ifdef BSWAP_NEEDED 239 bswap_needed = 1; 240 #else 241 bswap_needed = 0; 242 #endif 243 kernel_size = load_elf(kernel_filename, NULL, 244 translate_kernel_address, NULL, 245 NULL, NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 246 if (kernel_size < 0) 247 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 248 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 249 TARGET_PAGE_SIZE); 250 if (kernel_size < 0) 251 kernel_size = load_image_targphys(kernel_filename, 252 KERNEL_LOAD_ADDR, 253 RAM_size - KERNEL_LOAD_ADDR); 254 if (kernel_size < 0) { 255 error_report("could not load kernel '%s'", kernel_filename); 256 exit(1); 257 } 258 259 /* load initrd */ 260 *initrd_size = 0; 261 if (initrd_filename) { 262 *initrd_size = load_image_targphys(initrd_filename, 263 INITRD_LOAD_ADDR, 264 RAM_size - INITRD_LOAD_ADDR); 265 if ((int)*initrd_size < 0) { 266 error_report("could not load initial ram disk '%s'", 267 initrd_filename); 268 exit(1); 269 } 270 } 271 if (*initrd_size > 0) { 272 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 273 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24); 274 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */ 275 stl_p(ptr + 16, INITRD_LOAD_ADDR); 276 stl_p(ptr + 20, *initrd_size); 277 break; 278 } 279 } 280 } 281 } 282 return kernel_size; 283 } 284 285 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 286 { 287 DeviceState *dev; 288 SysBusDevice *s; 289 290 dev = qdev_new(TYPE_SUN4M_IOMMU); 291 qdev_prop_set_uint32(dev, "version", version); 292 s = SYS_BUS_DEVICE(dev); 293 sysbus_realize_and_unref(s, &error_fatal); 294 sysbus_connect_irq(s, 0, irq); 295 sysbus_mmio_map(s, 0, addr); 296 297 return s; 298 } 299 300 static void *sparc32_dma_init(hwaddr dma_base, 301 hwaddr esp_base, qemu_irq espdma_irq, 302 hwaddr le_base, qemu_irq ledma_irq, NICInfo *nd) 303 { 304 DeviceState *dma; 305 ESPDMADeviceState *espdma; 306 LEDMADeviceState *ledma; 307 SysBusESPState *esp; 308 SysBusPCNetState *lance; 309 310 dma = qdev_new(TYPE_SPARC32_DMA); 311 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( 312 OBJECT(dma), "espdma")); 313 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); 314 315 esp = SYSBUS_ESP(object_resolve_path_component(OBJECT(espdma), "esp")); 316 317 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( 318 OBJECT(dma), "ledma")); 319 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq); 320 321 lance = SYSBUS_PCNET(object_resolve_path_component( 322 OBJECT(ledma), "lance")); 323 qdev_set_nic_properties(DEVICE(lance), nd); 324 325 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); 326 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); 327 328 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base); 329 scsi_bus_legacy_handle_cmdline(&esp->esp.bus); 330 331 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base); 332 333 return dma; 334 } 335 336 static DeviceState *slavio_intctl_init(hwaddr addr, 337 hwaddr addrg, 338 qemu_irq **parent_irq) 339 { 340 DeviceState *dev; 341 SysBusDevice *s; 342 unsigned int i, j; 343 344 dev = qdev_new("slavio_intctl"); 345 346 s = SYS_BUS_DEVICE(dev); 347 sysbus_realize_and_unref(s, &error_fatal); 348 349 for (i = 0; i < MAX_CPUS; i++) { 350 for (j = 0; j < MAX_PILS; j++) { 351 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 352 } 353 } 354 sysbus_mmio_map(s, 0, addrg); 355 for (i = 0; i < MAX_CPUS; i++) { 356 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 357 } 358 359 return dev; 360 } 361 362 #define SYS_TIMER_OFFSET 0x10000ULL 363 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 364 365 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 366 qemu_irq *cpu_irqs, unsigned int num_cpus) 367 { 368 DeviceState *dev; 369 SysBusDevice *s; 370 unsigned int i; 371 372 dev = qdev_new("slavio_timer"); 373 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 374 s = SYS_BUS_DEVICE(dev); 375 sysbus_realize_and_unref(s, &error_fatal); 376 sysbus_connect_irq(s, 0, master_irq); 377 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 378 379 for (i = 0; i < MAX_CPUS; i++) { 380 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 381 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 382 } 383 } 384 385 static qemu_irq slavio_system_powerdown; 386 387 static void slavio_powerdown_req(Notifier *n, void *opaque) 388 { 389 qemu_irq_raise(slavio_system_powerdown); 390 } 391 392 static Notifier slavio_system_powerdown_notifier = { 393 .notify = slavio_powerdown_req 394 }; 395 396 #define MISC_LEDS 0x01600000 397 #define MISC_CFG 0x01800000 398 #define MISC_DIAG 0x01a00000 399 #define MISC_MDM 0x01b00000 400 #define MISC_SYS 0x01f00000 401 402 static void slavio_misc_init(hwaddr base, 403 hwaddr aux1_base, 404 hwaddr aux2_base, qemu_irq irq, 405 qemu_irq fdc_tc) 406 { 407 DeviceState *dev; 408 SysBusDevice *s; 409 410 dev = qdev_new("slavio_misc"); 411 s = SYS_BUS_DEVICE(dev); 412 sysbus_realize_and_unref(s, &error_fatal); 413 if (base) { 414 /* 8 bit registers */ 415 /* Slavio control */ 416 sysbus_mmio_map(s, 0, base + MISC_CFG); 417 /* Diagnostics */ 418 sysbus_mmio_map(s, 1, base + MISC_DIAG); 419 /* Modem control */ 420 sysbus_mmio_map(s, 2, base + MISC_MDM); 421 /* 16 bit registers */ 422 /* ss600mp diag LEDs */ 423 sysbus_mmio_map(s, 3, base + MISC_LEDS); 424 /* 32 bit registers */ 425 /* System control */ 426 sysbus_mmio_map(s, 4, base + MISC_SYS); 427 } 428 if (aux1_base) { 429 /* AUX 1 (Misc System Functions) */ 430 sysbus_mmio_map(s, 5, aux1_base); 431 } 432 if (aux2_base) { 433 /* AUX 2 (Software Powerdown Control) */ 434 sysbus_mmio_map(s, 6, aux2_base); 435 } 436 sysbus_connect_irq(s, 0, irq); 437 sysbus_connect_irq(s, 1, fdc_tc); 438 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 439 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 440 } 441 442 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 443 { 444 DeviceState *dev; 445 SysBusDevice *s; 446 447 dev = qdev_new("eccmemctl"); 448 qdev_prop_set_uint32(dev, "version", version); 449 s = SYS_BUS_DEVICE(dev); 450 sysbus_realize_and_unref(s, &error_fatal); 451 sysbus_connect_irq(s, 0, irq); 452 sysbus_mmio_map(s, 0, base); 453 if (version == 0) { // SS-600MP only 454 sysbus_mmio_map(s, 1, base + 0x1000); 455 } 456 } 457 458 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 459 { 460 DeviceState *dev; 461 SysBusDevice *s; 462 463 dev = qdev_new("apc"); 464 s = SYS_BUS_DEVICE(dev); 465 sysbus_realize_and_unref(s, &error_fatal); 466 /* Power management (APC) XXX: not a Slavio device */ 467 sysbus_mmio_map(s, 0, power_base); 468 sysbus_connect_irq(s, 0, cpu_halt); 469 } 470 471 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 472 int height, int depth) 473 { 474 DeviceState *dev; 475 SysBusDevice *s; 476 477 dev = qdev_new("sun-tcx"); 478 qdev_prop_set_uint32(dev, "vram_size", vram_size); 479 qdev_prop_set_uint16(dev, "width", width); 480 qdev_prop_set_uint16(dev, "height", height); 481 qdev_prop_set_uint16(dev, "depth", depth); 482 s = SYS_BUS_DEVICE(dev); 483 sysbus_realize_and_unref(s, &error_fatal); 484 485 /* 10/ROM : FCode ROM */ 486 sysbus_mmio_map(s, 0, addr); 487 /* 2/STIP : Stipple */ 488 sysbus_mmio_map(s, 1, addr + 0x04000000ULL); 489 /* 3/BLIT : Blitter */ 490 sysbus_mmio_map(s, 2, addr + 0x06000000ULL); 491 /* 5/RSTIP : Raw Stipple */ 492 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); 493 /* 6/RBLIT : Raw Blitter */ 494 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); 495 /* 7/TEC : Transform Engine */ 496 sysbus_mmio_map(s, 5, addr + 0x00700000ULL); 497 /* 8/CMAP : DAC */ 498 sysbus_mmio_map(s, 6, addr + 0x00200000ULL); 499 /* 9/THC : */ 500 if (depth == 8) { 501 sysbus_mmio_map(s, 7, addr + 0x00300000ULL); 502 } else { 503 sysbus_mmio_map(s, 7, addr + 0x00301000ULL); 504 } 505 /* 11/DHC : */ 506 sysbus_mmio_map(s, 8, addr + 0x00240000ULL); 507 /* 12/ALT : */ 508 sysbus_mmio_map(s, 9, addr + 0x00280000ULL); 509 /* 0/DFB8 : 8-bit plane */ 510 sysbus_mmio_map(s, 10, addr + 0x00800000ULL); 511 /* 1/DFB24 : 24bit plane */ 512 sysbus_mmio_map(s, 11, addr + 0x02000000ULL); 513 /* 4/RDFB32: Raw framebuffer. Control plane */ 514 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); 515 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 516 if (depth == 8) { 517 sysbus_mmio_map(s, 13, addr + 0x00301000ULL); 518 } 519 520 sysbus_connect_irq(s, 0, irq); 521 } 522 523 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 524 int height, int depth) 525 { 526 DeviceState *dev; 527 SysBusDevice *s; 528 529 dev = qdev_new("cgthree"); 530 qdev_prop_set_uint32(dev, "vram-size", vram_size); 531 qdev_prop_set_uint16(dev, "width", width); 532 qdev_prop_set_uint16(dev, "height", height); 533 qdev_prop_set_uint16(dev, "depth", depth); 534 s = SYS_BUS_DEVICE(dev); 535 sysbus_realize_and_unref(s, &error_fatal); 536 537 /* FCode ROM */ 538 sysbus_mmio_map(s, 0, addr); 539 /* DAC */ 540 sysbus_mmio_map(s, 1, addr + 0x400000ULL); 541 /* 8-bit plane */ 542 sysbus_mmio_map(s, 2, addr + 0x800000ULL); 543 544 sysbus_connect_irq(s, 0, irq); 545 } 546 547 /* NCR89C100/MACIO Internal ID register */ 548 549 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 550 551 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 552 553 static void idreg_init(hwaddr addr) 554 { 555 DeviceState *dev; 556 SysBusDevice *s; 557 558 dev = qdev_new(TYPE_MACIO_ID_REGISTER); 559 s = SYS_BUS_DEVICE(dev); 560 sysbus_realize_and_unref(s, &error_fatal); 561 562 sysbus_mmio_map(s, 0, addr); 563 address_space_write_rom(&address_space_memory, addr, 564 MEMTXATTRS_UNSPECIFIED, 565 idreg_data, sizeof(idreg_data)); 566 } 567 568 OBJECT_DECLARE_SIMPLE_TYPE(IDRegState, MACIO_ID_REGISTER) 569 570 struct IDRegState { 571 SysBusDevice parent_obj; 572 573 MemoryRegion mem; 574 }; 575 576 static void idreg_realize(DeviceState *ds, Error **errp) 577 { 578 IDRegState *s = MACIO_ID_REGISTER(ds); 579 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 580 Error *local_err = NULL; 581 582 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg", 583 sizeof(idreg_data), &local_err); 584 if (local_err) { 585 error_propagate(errp, local_err); 586 return; 587 } 588 589 vmstate_register_ram_global(&s->mem); 590 memory_region_set_readonly(&s->mem, true); 591 sysbus_init_mmio(dev, &s->mem); 592 } 593 594 static void idreg_class_init(ObjectClass *oc, void *data) 595 { 596 DeviceClass *dc = DEVICE_CLASS(oc); 597 598 dc->realize = idreg_realize; 599 } 600 601 static const TypeInfo idreg_info = { 602 .name = TYPE_MACIO_ID_REGISTER, 603 .parent = TYPE_SYS_BUS_DEVICE, 604 .instance_size = sizeof(IDRegState), 605 .class_init = idreg_class_init, 606 }; 607 608 #define TYPE_TCX_AFX "tcx_afx" 609 OBJECT_DECLARE_SIMPLE_TYPE(AFXState, TCX_AFX) 610 611 struct AFXState { 612 SysBusDevice parent_obj; 613 614 MemoryRegion mem; 615 }; 616 617 /* SS-5 TCX AFX register */ 618 static void afx_init(hwaddr addr) 619 { 620 DeviceState *dev; 621 SysBusDevice *s; 622 623 dev = qdev_new(TYPE_TCX_AFX); 624 s = SYS_BUS_DEVICE(dev); 625 sysbus_realize_and_unref(s, &error_fatal); 626 627 sysbus_mmio_map(s, 0, addr); 628 } 629 630 static void afx_realize(DeviceState *ds, Error **errp) 631 { 632 AFXState *s = TCX_AFX(ds); 633 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 634 Error *local_err = NULL; 635 636 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4, 637 &local_err); 638 if (local_err) { 639 error_propagate(errp, local_err); 640 return; 641 } 642 643 vmstate_register_ram_global(&s->mem); 644 sysbus_init_mmio(dev, &s->mem); 645 } 646 647 static void afx_class_init(ObjectClass *oc, void *data) 648 { 649 DeviceClass *dc = DEVICE_CLASS(oc); 650 651 dc->realize = afx_realize; 652 } 653 654 static const TypeInfo afx_info = { 655 .name = TYPE_TCX_AFX, 656 .parent = TYPE_SYS_BUS_DEVICE, 657 .instance_size = sizeof(AFXState), 658 .class_init = afx_class_init, 659 }; 660 661 #define TYPE_OPENPROM "openprom" 662 typedef struct PROMState PROMState; 663 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM, 664 TYPE_OPENPROM) 665 666 struct PROMState { 667 SysBusDevice parent_obj; 668 669 MemoryRegion prom; 670 }; 671 672 /* Boot PROM (OpenBIOS) */ 673 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 674 { 675 hwaddr *base_addr = (hwaddr *)opaque; 676 return addr + *base_addr - PROM_VADDR; 677 } 678 679 static void prom_init(hwaddr addr, const char *bios_name) 680 { 681 DeviceState *dev; 682 SysBusDevice *s; 683 char *filename; 684 int ret; 685 686 dev = qdev_new(TYPE_OPENPROM); 687 s = SYS_BUS_DEVICE(dev); 688 sysbus_realize_and_unref(s, &error_fatal); 689 690 sysbus_mmio_map(s, 0, addr); 691 692 /* load boot prom */ 693 if (bios_name == NULL) { 694 bios_name = PROM_FILENAME; 695 } 696 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 697 if (filename) { 698 ret = load_elf(filename, NULL, 699 translate_prom_address, &addr, NULL, 700 NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 701 if (ret < 0 || ret > PROM_SIZE_MAX) { 702 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 703 } 704 g_free(filename); 705 } else { 706 ret = -1; 707 } 708 if (ret < 0 || ret > PROM_SIZE_MAX) { 709 error_report("could not load prom '%s'", bios_name); 710 exit(1); 711 } 712 } 713 714 static void prom_realize(DeviceState *ds, Error **errp) 715 { 716 PROMState *s = OPENPROM(ds); 717 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 718 Error *local_err = NULL; 719 720 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom", 721 PROM_SIZE_MAX, &local_err); 722 if (local_err) { 723 error_propagate(errp, local_err); 724 return; 725 } 726 727 vmstate_register_ram_global(&s->prom); 728 memory_region_set_readonly(&s->prom, true); 729 sysbus_init_mmio(dev, &s->prom); 730 } 731 732 static Property prom_properties[] = { 733 {/* end of property list */}, 734 }; 735 736 static void prom_class_init(ObjectClass *klass, void *data) 737 { 738 DeviceClass *dc = DEVICE_CLASS(klass); 739 740 device_class_set_props(dc, prom_properties); 741 dc->realize = prom_realize; 742 } 743 744 static const TypeInfo prom_info = { 745 .name = TYPE_OPENPROM, 746 .parent = TYPE_SYS_BUS_DEVICE, 747 .instance_size = sizeof(PROMState), 748 .class_init = prom_class_init, 749 }; 750 751 #define TYPE_SUN4M_MEMORY "memory" 752 typedef struct RamDevice RamDevice; 753 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4M_RAM, 754 TYPE_SUN4M_MEMORY) 755 756 struct RamDevice { 757 SysBusDevice parent_obj; 758 HostMemoryBackend *memdev; 759 }; 760 761 /* System RAM */ 762 static void ram_realize(DeviceState *dev, Error **errp) 763 { 764 RamDevice *d = SUN4M_RAM(dev); 765 MemoryRegion *ram = host_memory_backend_get_memory(d->memdev); 766 767 sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram); 768 } 769 770 static void ram_initfn(Object *obj) 771 { 772 RamDevice *d = SUN4M_RAM(obj); 773 object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND, 774 (Object **)&d->memdev, 775 object_property_allow_set_link, 776 OBJ_PROP_LINK_STRONG); 777 object_property_set_description(obj, "memdev", "Set RAM backend" 778 "Valid value is ID of a hostmem backend"); 779 } 780 781 static void ram_class_init(ObjectClass *klass, void *data) 782 { 783 DeviceClass *dc = DEVICE_CLASS(klass); 784 785 dc->realize = ram_realize; 786 } 787 788 static const TypeInfo ram_info = { 789 .name = TYPE_SUN4M_MEMORY, 790 .parent = TYPE_SYS_BUS_DEVICE, 791 .instance_size = sizeof(RamDevice), 792 .instance_init = ram_initfn, 793 .class_init = ram_class_init, 794 }; 795 796 static void cpu_devinit(const char *cpu_type, unsigned int id, 797 uint64_t prom_addr, qemu_irq **cpu_irqs) 798 { 799 SPARCCPU *cpu; 800 CPUSPARCState *env; 801 802 cpu = SPARC_CPU(object_new(cpu_type)); 803 env = &cpu->env; 804 805 qemu_register_reset(sun4m_cpu_reset, cpu); 806 object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0, 807 &error_fatal); 808 qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); 809 cpu_sparc_set_id(env, id); 810 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 811 env->prom_addr = prom_addr; 812 } 813 814 static void dummy_fdc_tc(void *opaque, int irq, int level) 815 { 816 } 817 818 static void sun4m_hw_init(MachineState *machine) 819 { 820 const struct sun4m_hwdef *hwdef = SUN4M_MACHINE_GET_CLASS(machine)->hwdef; 821 DeviceState *slavio_intctl; 822 unsigned int i; 823 Nvram *nvram; 824 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; 825 qemu_irq fdc_tc; 826 unsigned long kernel_size; 827 uint32_t initrd_size; 828 DriveInfo *fd[MAX_FD]; 829 FWCfgState *fw_cfg; 830 DeviceState *dev, *ms_kb_orgate, *serial_orgate; 831 SysBusDevice *s; 832 unsigned int smp_cpus = machine->smp.cpus; 833 unsigned int max_cpus = machine->smp.max_cpus; 834 HostMemoryBackend *ram_memdev = machine->memdev; 835 NICInfo *nd = &nd_table[0]; 836 837 if (machine->ram_size > hwdef->max_mem) { 838 error_report("Too much memory for this machine: %" PRId64 "," 839 " maximum %" PRId64, 840 machine->ram_size / MiB, hwdef->max_mem / MiB); 841 exit(1); 842 } 843 844 /* init CPUs */ 845 for(i = 0; i < smp_cpus; i++) { 846 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); 847 } 848 849 for (i = smp_cpus; i < MAX_CPUS; i++) 850 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 851 852 /* Create and map RAM frontend */ 853 dev = qdev_new("memory"); 854 object_property_set_link(OBJECT(dev), "memdev", OBJECT(ram_memdev), &error_fatal); 855 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 856 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0); 857 858 /* models without ECC don't trap when missing ram is accessed */ 859 if (!hwdef->ecc_base) { 860 empty_slot_init("ecc", machine->ram_size, 861 hwdef->max_mem - machine->ram_size); 862 } 863 864 prom_init(hwdef->slavio_base, machine->firmware); 865 866 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 867 hwdef->intctl_base + 0x10000ULL, 868 cpu_irqs); 869 870 for (i = 0; i < 32; i++) { 871 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 872 } 873 for (i = 0; i < MAX_CPUS; i++) { 874 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 875 } 876 877 if (hwdef->idreg_base) { 878 idreg_init(hwdef->idreg_base); 879 } 880 881 if (hwdef->afx_base) { 882 afx_init(hwdef->afx_base); 883 } 884 885 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]); 886 887 if (hwdef->iommu_pad_base) { 888 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 889 Software shouldn't use aliased addresses, neither should it crash 890 when does. Using empty_slot instead of aliasing can help with 891 debugging such accesses */ 892 empty_slot_init("iommu.alias", 893 hwdef->iommu_pad_base, hwdef->iommu_pad_len); 894 } 895 896 qemu_check_nic_model(nd, TYPE_LANCE); 897 sparc32_dma_init(hwdef->dma_base, 898 hwdef->esp_base, slavio_irq[18], 899 hwdef->le_base, slavio_irq[16], nd); 900 901 if (graphic_depth != 8 && graphic_depth != 24) { 902 error_report("Unsupported depth: %d", graphic_depth); 903 exit (1); 904 } 905 if (vga_interface_type != VGA_NONE) { 906 if (vga_interface_type == VGA_CG3) { 907 if (graphic_depth != 8) { 908 error_report("Unsupported depth: %d", graphic_depth); 909 exit(1); 910 } 911 912 if (!(graphic_width == 1024 && graphic_height == 768) && 913 !(graphic_width == 1152 && graphic_height == 900)) { 914 error_report("Unsupported resolution: %d x %d", graphic_width, 915 graphic_height); 916 exit(1); 917 } 918 919 /* sbus irq 5 */ 920 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 921 graphic_width, graphic_height, graphic_depth); 922 vga_interface_created = true; 923 } else { 924 /* If no display specified, default to TCX */ 925 if (graphic_depth != 8 && graphic_depth != 24) { 926 error_report("Unsupported depth: %d", graphic_depth); 927 exit(1); 928 } 929 930 if (!(graphic_width == 1024 && graphic_height == 768)) { 931 error_report("Unsupported resolution: %d x %d", 932 graphic_width, graphic_height); 933 exit(1); 934 } 935 936 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 937 graphic_width, graphic_height, graphic_depth); 938 vga_interface_created = true; 939 } 940 } 941 942 for (i = 0; i < MAX_VSIMMS; i++) { 943 /* vsimm registers probed by OBP */ 944 if (hwdef->vsimm[i].reg_base) { 945 char *name = g_strdup_printf("vsimm[%d]", i); 946 empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000); 947 g_free(name); 948 } 949 } 950 951 if (hwdef->sx_base) { 952 create_unimplemented_device("sun-sx", hwdef->sx_base, 0x2000); 953 } 954 955 dev = qdev_new("sysbus-m48t08"); 956 qdev_prop_set_int32(dev, "base-year", 1968); 957 s = SYS_BUS_DEVICE(dev); 958 sysbus_realize_and_unref(s, &error_fatal); 959 sysbus_connect_irq(s, 0, slavio_irq[0]); 960 sysbus_mmio_map(s, 0, hwdef->nvram_base); 961 nvram = NVRAM(dev); 962 963 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 964 965 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 966 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 967 dev = qdev_new(TYPE_ESCC); 968 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics); 969 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 970 qdev_prop_set_uint32(dev, "it_shift", 1); 971 qdev_prop_set_chr(dev, "chrB", NULL); 972 qdev_prop_set_chr(dev, "chrA", NULL); 973 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse); 974 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd); 975 s = SYS_BUS_DEVICE(dev); 976 sysbus_realize_and_unref(s, &error_fatal); 977 sysbus_mmio_map(s, 0, hwdef->ms_kb_base); 978 979 /* Logically OR both its IRQs together */ 980 ms_kb_orgate = DEVICE(object_new(TYPE_OR_IRQ)); 981 object_property_set_int(OBJECT(ms_kb_orgate), "num-lines", 2, &error_fatal); 982 qdev_realize_and_unref(ms_kb_orgate, NULL, &error_fatal); 983 sysbus_connect_irq(s, 0, qdev_get_gpio_in(ms_kb_orgate, 0)); 984 sysbus_connect_irq(s, 1, qdev_get_gpio_in(ms_kb_orgate, 1)); 985 qdev_connect_gpio_out(DEVICE(ms_kb_orgate), 0, slavio_irq[14]); 986 987 dev = qdev_new(TYPE_ESCC); 988 qdev_prop_set_uint32(dev, "disabled", 0); 989 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 990 qdev_prop_set_uint32(dev, "it_shift", 1); 991 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 992 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 993 qdev_prop_set_uint32(dev, "chnBtype", escc_serial); 994 qdev_prop_set_uint32(dev, "chnAtype", escc_serial); 995 996 s = SYS_BUS_DEVICE(dev); 997 sysbus_realize_and_unref(s, &error_fatal); 998 sysbus_mmio_map(s, 0, hwdef->serial_base); 999 1000 /* Logically OR both its IRQs together */ 1001 serial_orgate = DEVICE(object_new(TYPE_OR_IRQ)); 1002 object_property_set_int(OBJECT(serial_orgate), "num-lines", 2, 1003 &error_fatal); 1004 qdev_realize_and_unref(serial_orgate, NULL, &error_fatal); 1005 sysbus_connect_irq(s, 0, qdev_get_gpio_in(serial_orgate, 0)); 1006 sysbus_connect_irq(s, 1, qdev_get_gpio_in(serial_orgate, 1)); 1007 qdev_connect_gpio_out(DEVICE(serial_orgate), 0, slavio_irq[15]); 1008 1009 if (hwdef->apc_base) { 1010 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); 1011 } 1012 1013 if (hwdef->fd_base) { 1014 /* there is zero or one floppy drive */ 1015 memset(fd, 0, sizeof(fd)); 1016 fd[0] = drive_get(IF_FLOPPY, 0, 0); 1017 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 1018 &fdc_tc); 1019 } else { 1020 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); 1021 } 1022 1023 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 1024 slavio_irq[30], fdc_tc); 1025 1026 if (hwdef->cs_base) { 1027 sysbus_create_simple("sun-CS4231", hwdef->cs_base, 1028 slavio_irq[5]); 1029 } 1030 1031 if (hwdef->dbri_base) { 1032 /* ISDN chip with attached CS4215 audio codec */ 1033 /* prom space */ 1034 create_unimplemented_device("sun-DBRI.prom", 1035 hwdef->dbri_base + 0x1000, 0x30); 1036 /* reg space */ 1037 create_unimplemented_device("sun-DBRI", 1038 hwdef->dbri_base + 0x10000, 0x100); 1039 } 1040 1041 if (hwdef->bpp_base) { 1042 /* parallel port */ 1043 create_unimplemented_device("sun-bpp", hwdef->bpp_base, 0x20); 1044 } 1045 1046 initrd_size = 0; 1047 kernel_size = sun4m_load_kernel(machine->kernel_filename, 1048 machine->initrd_filename, 1049 machine->ram_size, &initrd_size); 1050 1051 nvram_init(nvram, (uint8_t *)&nd->macaddr, machine->kernel_cmdline, 1052 machine->boot_config.order, machine->ram_size, kernel_size, 1053 graphic_width, graphic_height, graphic_depth, 1054 hwdef->nvram_machine_id, "Sun4m"); 1055 1056 if (hwdef->ecc_base) 1057 ecc_init(hwdef->ecc_base, slavio_irq[28], 1058 hwdef->ecc_version); 1059 1060 dev = qdev_new(TYPE_FW_CFG_MEM); 1061 fw_cfg = FW_CFG(dev); 1062 qdev_prop_set_uint32(dev, "data_width", 1); 1063 qdev_prop_set_bit(dev, "dma_enabled", false); 1064 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1065 OBJECT(fw_cfg)); 1066 s = SYS_BUS_DEVICE(dev); 1067 sysbus_realize_and_unref(s, &error_fatal); 1068 sysbus_mmio_map(s, 0, CFG_ADDR); 1069 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 1070 1071 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 1072 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1073 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 1074 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1075 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1076 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1077 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1078 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1079 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1080 if (machine->kernel_cmdline) { 1081 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1082 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1083 machine->kernel_cmdline); 1084 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 1085 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1086 strlen(machine->kernel_cmdline) + 1); 1087 } else { 1088 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1089 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1090 } 1091 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1092 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1093 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_config.order[0]); 1094 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1095 } 1096 1097 enum { 1098 ss5_id = 32, 1099 vger_id, 1100 lx_id, 1101 ss4_id, 1102 scls_id, 1103 sbook_id, 1104 ss10_id = 64, 1105 ss20_id, 1106 ss600mp_id, 1107 }; 1108 1109 static void sun4m_machine_class_init(ObjectClass *oc, void *data) 1110 { 1111 MachineClass *mc = MACHINE_CLASS(oc); 1112 1113 mc->init = sun4m_hw_init; 1114 mc->block_default_type = IF_SCSI; 1115 mc->default_boot_order = "c"; 1116 mc->default_display = "tcx"; 1117 mc->default_ram_id = "sun4m.ram"; 1118 } 1119 1120 static void ss5_class_init(ObjectClass *oc, void *data) 1121 { 1122 MachineClass *mc = MACHINE_CLASS(oc); 1123 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1124 static const struct sun4m_hwdef ss5_hwdef = { 1125 .iommu_base = 0x10000000, 1126 .iommu_pad_base = 0x10004000, 1127 .iommu_pad_len = 0x0fffb000, 1128 .tcx_base = 0x50000000, 1129 .cs_base = 0x6c000000, 1130 .slavio_base = 0x70000000, 1131 .ms_kb_base = 0x71000000, 1132 .serial_base = 0x71100000, 1133 .nvram_base = 0x71200000, 1134 .fd_base = 0x71400000, 1135 .counter_base = 0x71d00000, 1136 .intctl_base = 0x71e00000, 1137 .idreg_base = 0x78000000, 1138 .dma_base = 0x78400000, 1139 .esp_base = 0x78800000, 1140 .le_base = 0x78c00000, 1141 .apc_base = 0x6a000000, 1142 .afx_base = 0x6e000000, 1143 .aux1_base = 0x71900000, 1144 .aux2_base = 0x71910000, 1145 .nvram_machine_id = 0x80, 1146 .machine_id = ss5_id, 1147 .iommu_version = 0x05000000, 1148 .max_mem = 0x10000000, 1149 }; 1150 1151 mc->desc = "Sun4m platform, SPARCstation 5"; 1152 mc->is_default = true; 1153 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1154 smc->hwdef = &ss5_hwdef; 1155 } 1156 1157 static void ss10_class_init(ObjectClass *oc, void *data) 1158 { 1159 MachineClass *mc = MACHINE_CLASS(oc); 1160 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1161 static const struct sun4m_hwdef ss10_hwdef = { 1162 .iommu_base = 0xfe0000000ULL, 1163 .tcx_base = 0xe20000000ULL, 1164 .slavio_base = 0xff0000000ULL, 1165 .ms_kb_base = 0xff1000000ULL, 1166 .serial_base = 0xff1100000ULL, 1167 .nvram_base = 0xff1200000ULL, 1168 .fd_base = 0xff1700000ULL, 1169 .counter_base = 0xff1300000ULL, 1170 .intctl_base = 0xff1400000ULL, 1171 .idreg_base = 0xef0000000ULL, 1172 .dma_base = 0xef0400000ULL, 1173 .esp_base = 0xef0800000ULL, 1174 .le_base = 0xef0c00000ULL, 1175 .apc_base = 0xefa000000ULL, /* XXX should not exist */ 1176 .aux1_base = 0xff1800000ULL, 1177 .aux2_base = 0xff1a01000ULL, 1178 .ecc_base = 0xf00000000ULL, 1179 .ecc_version = 0x10000000, /* version 0, implementation 1 */ 1180 .nvram_machine_id = 0x72, 1181 .machine_id = ss10_id, 1182 .iommu_version = 0x03000000, 1183 .max_mem = 0xf00000000ULL, 1184 }; 1185 1186 mc->desc = "Sun4m platform, SPARCstation 10"; 1187 mc->max_cpus = 4; 1188 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1189 smc->hwdef = &ss10_hwdef; 1190 } 1191 1192 static void ss600mp_class_init(ObjectClass *oc, void *data) 1193 { 1194 MachineClass *mc = MACHINE_CLASS(oc); 1195 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1196 static const struct sun4m_hwdef ss600mp_hwdef = { 1197 .iommu_base = 0xfe0000000ULL, 1198 .tcx_base = 0xe20000000ULL, 1199 .slavio_base = 0xff0000000ULL, 1200 .ms_kb_base = 0xff1000000ULL, 1201 .serial_base = 0xff1100000ULL, 1202 .nvram_base = 0xff1200000ULL, 1203 .counter_base = 0xff1300000ULL, 1204 .intctl_base = 0xff1400000ULL, 1205 .dma_base = 0xef0081000ULL, 1206 .esp_base = 0xef0080000ULL, 1207 .le_base = 0xef0060000ULL, 1208 .apc_base = 0xefa000000ULL, /* XXX should not exist */ 1209 .aux1_base = 0xff1800000ULL, 1210 .aux2_base = 0xff1a01000ULL, /* XXX should not exist */ 1211 .ecc_base = 0xf00000000ULL, 1212 .ecc_version = 0x00000000, /* version 0, implementation 0 */ 1213 .nvram_machine_id = 0x71, 1214 .machine_id = ss600mp_id, 1215 .iommu_version = 0x01000000, 1216 .max_mem = 0xf00000000ULL, 1217 }; 1218 1219 mc->desc = "Sun4m platform, SPARCserver 600MP"; 1220 mc->max_cpus = 4; 1221 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1222 smc->hwdef = &ss600mp_hwdef; 1223 } 1224 1225 static void ss20_class_init(ObjectClass *oc, void *data) 1226 { 1227 MachineClass *mc = MACHINE_CLASS(oc); 1228 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1229 static const struct sun4m_hwdef ss20_hwdef = { 1230 .iommu_base = 0xfe0000000ULL, 1231 .tcx_base = 0xe20000000ULL, 1232 .slavio_base = 0xff0000000ULL, 1233 .ms_kb_base = 0xff1000000ULL, 1234 .serial_base = 0xff1100000ULL, 1235 .nvram_base = 0xff1200000ULL, 1236 .fd_base = 0xff1700000ULL, 1237 .counter_base = 0xff1300000ULL, 1238 .intctl_base = 0xff1400000ULL, 1239 .idreg_base = 0xef0000000ULL, 1240 .dma_base = 0xef0400000ULL, 1241 .esp_base = 0xef0800000ULL, 1242 .le_base = 0xef0c00000ULL, 1243 .bpp_base = 0xef4800000ULL, 1244 .apc_base = 0xefa000000ULL, /* XXX should not exist */ 1245 .aux1_base = 0xff1800000ULL, 1246 .aux2_base = 0xff1a01000ULL, 1247 .dbri_base = 0xee0000000ULL, 1248 .sx_base = 0xf80000000ULL, 1249 .vsimm = { 1250 { 1251 .reg_base = 0x9c000000ULL, 1252 .vram_base = 0xfc000000ULL 1253 }, { 1254 .reg_base = 0x90000000ULL, 1255 .vram_base = 0xf0000000ULL 1256 }, { 1257 .reg_base = 0x94000000ULL 1258 }, { 1259 .reg_base = 0x98000000ULL 1260 } 1261 }, 1262 .ecc_base = 0xf00000000ULL, 1263 .ecc_version = 0x20000000, /* version 0, implementation 2 */ 1264 .nvram_machine_id = 0x72, 1265 .machine_id = ss20_id, 1266 .iommu_version = 0x13000000, 1267 .max_mem = 0xf00000000ULL, 1268 }; 1269 1270 mc->desc = "Sun4m platform, SPARCstation 20"; 1271 mc->max_cpus = 4; 1272 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1273 smc->hwdef = &ss20_hwdef; 1274 } 1275 1276 static void voyager_class_init(ObjectClass *oc, void *data) 1277 { 1278 MachineClass *mc = MACHINE_CLASS(oc); 1279 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1280 static const struct sun4m_hwdef voyager_hwdef = { 1281 .iommu_base = 0x10000000, 1282 .tcx_base = 0x50000000, 1283 .slavio_base = 0x70000000, 1284 .ms_kb_base = 0x71000000, 1285 .serial_base = 0x71100000, 1286 .nvram_base = 0x71200000, 1287 .fd_base = 0x71400000, 1288 .counter_base = 0x71d00000, 1289 .intctl_base = 0x71e00000, 1290 .idreg_base = 0x78000000, 1291 .dma_base = 0x78400000, 1292 .esp_base = 0x78800000, 1293 .le_base = 0x78c00000, 1294 .apc_base = 0x71300000, /* pmc */ 1295 .aux1_base = 0x71900000, 1296 .aux2_base = 0x71910000, 1297 .nvram_machine_id = 0x80, 1298 .machine_id = vger_id, 1299 .iommu_version = 0x05000000, 1300 .max_mem = 0x10000000, 1301 }; 1302 1303 mc->desc = "Sun4m platform, SPARCstation Voyager"; 1304 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1305 smc->hwdef = &voyager_hwdef; 1306 } 1307 1308 static void ss_lx_class_init(ObjectClass *oc, void *data) 1309 { 1310 MachineClass *mc = MACHINE_CLASS(oc); 1311 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1312 static const struct sun4m_hwdef ss_lx_hwdef = { 1313 .iommu_base = 0x10000000, 1314 .iommu_pad_base = 0x10004000, 1315 .iommu_pad_len = 0x0fffb000, 1316 .tcx_base = 0x50000000, 1317 .slavio_base = 0x70000000, 1318 .ms_kb_base = 0x71000000, 1319 .serial_base = 0x71100000, 1320 .nvram_base = 0x71200000, 1321 .fd_base = 0x71400000, 1322 .counter_base = 0x71d00000, 1323 .intctl_base = 0x71e00000, 1324 .idreg_base = 0x78000000, 1325 .dma_base = 0x78400000, 1326 .esp_base = 0x78800000, 1327 .le_base = 0x78c00000, 1328 .aux1_base = 0x71900000, 1329 .aux2_base = 0x71910000, 1330 .nvram_machine_id = 0x80, 1331 .machine_id = lx_id, 1332 .iommu_version = 0x04000000, 1333 .max_mem = 0x10000000, 1334 }; 1335 1336 mc->desc = "Sun4m platform, SPARCstation LX"; 1337 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1338 smc->hwdef = &ss_lx_hwdef; 1339 } 1340 1341 static void ss4_class_init(ObjectClass *oc, void *data) 1342 { 1343 MachineClass *mc = MACHINE_CLASS(oc); 1344 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1345 static const struct sun4m_hwdef ss4_hwdef = { 1346 .iommu_base = 0x10000000, 1347 .tcx_base = 0x50000000, 1348 .cs_base = 0x6c000000, 1349 .slavio_base = 0x70000000, 1350 .ms_kb_base = 0x71000000, 1351 .serial_base = 0x71100000, 1352 .nvram_base = 0x71200000, 1353 .fd_base = 0x71400000, 1354 .counter_base = 0x71d00000, 1355 .intctl_base = 0x71e00000, 1356 .idreg_base = 0x78000000, 1357 .dma_base = 0x78400000, 1358 .esp_base = 0x78800000, 1359 .le_base = 0x78c00000, 1360 .apc_base = 0x6a000000, 1361 .aux1_base = 0x71900000, 1362 .aux2_base = 0x71910000, 1363 .nvram_machine_id = 0x80, 1364 .machine_id = ss4_id, 1365 .iommu_version = 0x05000000, 1366 .max_mem = 0x10000000, 1367 }; 1368 1369 mc->desc = "Sun4m platform, SPARCstation 4"; 1370 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1371 smc->hwdef = &ss4_hwdef; 1372 } 1373 1374 static void scls_class_init(ObjectClass *oc, void *data) 1375 { 1376 MachineClass *mc = MACHINE_CLASS(oc); 1377 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1378 static const struct sun4m_hwdef scls_hwdef = { 1379 .iommu_base = 0x10000000, 1380 .tcx_base = 0x50000000, 1381 .slavio_base = 0x70000000, 1382 .ms_kb_base = 0x71000000, 1383 .serial_base = 0x71100000, 1384 .nvram_base = 0x71200000, 1385 .fd_base = 0x71400000, 1386 .counter_base = 0x71d00000, 1387 .intctl_base = 0x71e00000, 1388 .idreg_base = 0x78000000, 1389 .dma_base = 0x78400000, 1390 .esp_base = 0x78800000, 1391 .le_base = 0x78c00000, 1392 .apc_base = 0x6a000000, 1393 .aux1_base = 0x71900000, 1394 .aux2_base = 0x71910000, 1395 .nvram_machine_id = 0x80, 1396 .machine_id = scls_id, 1397 .iommu_version = 0x05000000, 1398 .max_mem = 0x10000000, 1399 }; 1400 1401 mc->desc = "Sun4m platform, SPARCClassic"; 1402 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1403 smc->hwdef = &scls_hwdef; 1404 } 1405 1406 static void sbook_class_init(ObjectClass *oc, void *data) 1407 { 1408 MachineClass *mc = MACHINE_CLASS(oc); 1409 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1410 static const struct sun4m_hwdef sbook_hwdef = { 1411 .iommu_base = 0x10000000, 1412 .tcx_base = 0x50000000, /* XXX */ 1413 .slavio_base = 0x70000000, 1414 .ms_kb_base = 0x71000000, 1415 .serial_base = 0x71100000, 1416 .nvram_base = 0x71200000, 1417 .fd_base = 0x71400000, 1418 .counter_base = 0x71d00000, 1419 .intctl_base = 0x71e00000, 1420 .idreg_base = 0x78000000, 1421 .dma_base = 0x78400000, 1422 .esp_base = 0x78800000, 1423 .le_base = 0x78c00000, 1424 .apc_base = 0x6a000000, 1425 .aux1_base = 0x71900000, 1426 .aux2_base = 0x71910000, 1427 .nvram_machine_id = 0x80, 1428 .machine_id = sbook_id, 1429 .iommu_version = 0x05000000, 1430 .max_mem = 0x10000000, 1431 }; 1432 1433 mc->desc = "Sun4m platform, SPARCbook"; 1434 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1435 smc->hwdef = &sbook_hwdef; 1436 } 1437 1438 static const TypeInfo sun4m_machine_types[] = { 1439 { 1440 .name = MACHINE_TYPE_NAME("SS-5"), 1441 .parent = TYPE_SUN4M_MACHINE, 1442 .class_init = ss5_class_init, 1443 }, { 1444 .name = MACHINE_TYPE_NAME("SS-10"), 1445 .parent = TYPE_SUN4M_MACHINE, 1446 .class_init = ss10_class_init, 1447 }, { 1448 .name = MACHINE_TYPE_NAME("SS-600MP"), 1449 .parent = TYPE_SUN4M_MACHINE, 1450 .class_init = ss600mp_class_init, 1451 }, { 1452 .name = MACHINE_TYPE_NAME("SS-20"), 1453 .parent = TYPE_SUN4M_MACHINE, 1454 .class_init = ss20_class_init, 1455 }, { 1456 .name = MACHINE_TYPE_NAME("Voyager"), 1457 .parent = TYPE_SUN4M_MACHINE, 1458 .class_init = voyager_class_init, 1459 }, { 1460 .name = MACHINE_TYPE_NAME("LX"), 1461 .parent = TYPE_SUN4M_MACHINE, 1462 .class_init = ss_lx_class_init, 1463 }, { 1464 .name = MACHINE_TYPE_NAME("SS-4"), 1465 .parent = TYPE_SUN4M_MACHINE, 1466 .class_init = ss4_class_init, 1467 }, { 1468 .name = MACHINE_TYPE_NAME("SPARCClassic"), 1469 .parent = TYPE_SUN4M_MACHINE, 1470 .class_init = scls_class_init, 1471 }, { 1472 .name = MACHINE_TYPE_NAME("SPARCbook"), 1473 .parent = TYPE_SUN4M_MACHINE, 1474 .class_init = sbook_class_init, 1475 }, { 1476 .name = TYPE_SUN4M_MACHINE, 1477 .parent = TYPE_MACHINE, 1478 .class_size = sizeof(Sun4mMachineClass), 1479 .class_init = sun4m_machine_class_init, 1480 .abstract = true, 1481 } 1482 }; 1483 1484 DEFINE_TYPES(sun4m_machine_types) 1485 1486 static void sun4m_register_types(void) 1487 { 1488 type_register_static(&idreg_info); 1489 type_register_static(&afx_info); 1490 type_register_static(&prom_info); 1491 type_register_static(&ram_info); 1492 } 1493 1494 type_init(sun4m_register_types) 1495