xref: /openbmc/qemu/hw/sparc/sun4m.c (revision 64552b6b)
1 /*
2  * QEMU Sun4m & Sun4d & Sun4c System Emulator
3  *
4  * Copyright (c) 2003-2005 Fabrice Bellard
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
28 #include "qemu-common.h"
29 #include "cpu.h"
30 #include "hw/sysbus.h"
31 #include "qemu/error-report.h"
32 #include "qemu/timer.h"
33 #include "hw/sparc/sun4m_iommu.h"
34 #include "hw/timer/m48t59.h"
35 #include "hw/sparc/sparc32_dma.h"
36 #include "hw/block/fdc.h"
37 #include "sysemu/reset.h"
38 #include "sysemu/sysemu.h"
39 #include "net/net.h"
40 #include "hw/boards.h"
41 #include "hw/scsi/esp.h"
42 #include "hw/nvram/sun_nvram.h"
43 #include "hw/nvram/chrp_nvram.h"
44 #include "hw/nvram/fw_cfg.h"
45 #include "hw/char/escc.h"
46 #include "hw/empty_slot.h"
47 #include "hw/irq.h"
48 #include "hw/loader.h"
49 #include "elf.h"
50 #include "trace.h"
51 
52 /*
53  * Sun4m architecture was used in the following machines:
54  *
55  * SPARCserver 6xxMP/xx
56  * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
57  * SPARCclassic X (4/10)
58  * SPARCstation LX/ZX (4/30)
59  * SPARCstation Voyager
60  * SPARCstation 10/xx, SPARCserver 10/xx
61  * SPARCstation 5, SPARCserver 5
62  * SPARCstation 20/xx, SPARCserver 20
63  * SPARCstation 4
64  *
65  * See for example: http://www.sunhelp.org/faq/sunref1.html
66  */
67 
68 #define KERNEL_LOAD_ADDR     0x00004000
69 #define CMDLINE_ADDR         0x007ff000
70 #define INITRD_LOAD_ADDR     0x00800000
71 #define PROM_SIZE_MAX        (1 * MiB)
72 #define PROM_VADDR           0xffd00000
73 #define PROM_FILENAME        "openbios-sparc32"
74 #define CFG_ADDR             0xd00000510ULL
75 #define FW_CFG_SUN4M_DEPTH   (FW_CFG_ARCH_LOCAL + 0x00)
76 #define FW_CFG_SUN4M_WIDTH   (FW_CFG_ARCH_LOCAL + 0x01)
77 #define FW_CFG_SUN4M_HEIGHT  (FW_CFG_ARCH_LOCAL + 0x02)
78 
79 #define MAX_CPUS 16
80 #define MAX_PILS 16
81 #define MAX_VSIMMS 4
82 
83 #define ESCC_CLOCK 4915200
84 
85 struct sun4m_hwdef {
86     hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
87     hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
88     hwaddr serial_base, fd_base;
89     hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
90     hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
91     hwaddr bpp_base, dbri_base, sx_base;
92     struct {
93         hwaddr reg_base, vram_base;
94     } vsimm[MAX_VSIMMS];
95     hwaddr ecc_base;
96     uint64_t max_mem;
97     uint32_t ecc_version;
98     uint32_t iommu_version;
99     uint16_t machine_id;
100     uint8_t nvram_machine_id;
101 };
102 
103 const char *fw_cfg_arch_key_name(uint16_t key)
104 {
105     static const struct {
106         uint16_t key;
107         const char *name;
108     } fw_cfg_arch_wellknown_keys[] = {
109         {FW_CFG_SUN4M_DEPTH, "depth"},
110         {FW_CFG_SUN4M_WIDTH, "width"},
111         {FW_CFG_SUN4M_HEIGHT, "height"},
112     };
113 
114     for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
115         if (fw_cfg_arch_wellknown_keys[i].key == key) {
116             return fw_cfg_arch_wellknown_keys[i].name;
117         }
118     }
119     return NULL;
120 }
121 
122 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
123                             Error **errp)
124 {
125     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
126 }
127 
128 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
129                        const char *cmdline, const char *boot_devices,
130                        ram_addr_t RAM_size, uint32_t kernel_size,
131                        int width, int height, int depth,
132                        int nvram_machine_id, const char *arch)
133 {
134     unsigned int i;
135     int sysp_end;
136     uint8_t image[0x1ff0];
137     NvramClass *k = NVRAM_GET_CLASS(nvram);
138 
139     memset(image, '\0', sizeof(image));
140 
141     /* OpenBIOS nvram variables partition */
142     sysp_end = chrp_nvram_create_system_partition(image, 0);
143 
144     /* Free space partition */
145     chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
146 
147     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
148                     nvram_machine_id);
149 
150     for (i = 0; i < sizeof(image); i++) {
151         (k->write)(nvram, i, image[i]);
152     }
153 }
154 
155 void cpu_check_irqs(CPUSPARCState *env)
156 {
157     CPUState *cs;
158 
159     /* We should be holding the BQL before we mess with IRQs */
160     g_assert(qemu_mutex_iothread_locked());
161 
162     if (env->pil_in && (env->interrupt_index == 0 ||
163                         (env->interrupt_index & ~15) == TT_EXTINT)) {
164         unsigned int i;
165 
166         for (i = 15; i > 0; i--) {
167             if (env->pil_in & (1 << i)) {
168                 int old_interrupt = env->interrupt_index;
169 
170                 env->interrupt_index = TT_EXTINT | i;
171                 if (old_interrupt != env->interrupt_index) {
172                     cs = env_cpu(env);
173                     trace_sun4m_cpu_interrupt(i);
174                     cpu_interrupt(cs, CPU_INTERRUPT_HARD);
175                 }
176                 break;
177             }
178         }
179     } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
180         cs = env_cpu(env);
181         trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
182         env->interrupt_index = 0;
183         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
184     }
185 }
186 
187 static void cpu_kick_irq(SPARCCPU *cpu)
188 {
189     CPUSPARCState *env = &cpu->env;
190     CPUState *cs = CPU(cpu);
191 
192     cs->halted = 0;
193     cpu_check_irqs(env);
194     qemu_cpu_kick(cs);
195 }
196 
197 static void cpu_set_irq(void *opaque, int irq, int level)
198 {
199     SPARCCPU *cpu = opaque;
200     CPUSPARCState *env = &cpu->env;
201 
202     if (level) {
203         trace_sun4m_cpu_set_irq_raise(irq);
204         env->pil_in |= 1 << irq;
205         cpu_kick_irq(cpu);
206     } else {
207         trace_sun4m_cpu_set_irq_lower(irq);
208         env->pil_in &= ~(1 << irq);
209         cpu_check_irqs(env);
210     }
211 }
212 
213 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
214 {
215 }
216 
217 static void main_cpu_reset(void *opaque)
218 {
219     SPARCCPU *cpu = opaque;
220     CPUState *cs = CPU(cpu);
221 
222     cpu_reset(cs);
223     cs->halted = 0;
224 }
225 
226 static void secondary_cpu_reset(void *opaque)
227 {
228     SPARCCPU *cpu = opaque;
229     CPUState *cs = CPU(cpu);
230 
231     cpu_reset(cs);
232     cs->halted = 1;
233 }
234 
235 static void cpu_halt_signal(void *opaque, int irq, int level)
236 {
237     if (level && current_cpu) {
238         cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
239     }
240 }
241 
242 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
243 {
244     return addr - 0xf0000000ULL;
245 }
246 
247 static unsigned long sun4m_load_kernel(const char *kernel_filename,
248                                        const char *initrd_filename,
249                                        ram_addr_t RAM_size,
250                                        uint32_t *initrd_size)
251 {
252     int linux_boot;
253     unsigned int i;
254     long kernel_size;
255     uint8_t *ptr;
256 
257     linux_boot = (kernel_filename != NULL);
258 
259     kernel_size = 0;
260     if (linux_boot) {
261         int bswap_needed;
262 
263 #ifdef BSWAP_NEEDED
264         bswap_needed = 1;
265 #else
266         bswap_needed = 0;
267 #endif
268         kernel_size = load_elf(kernel_filename, NULL,
269                                translate_kernel_address, NULL,
270                                NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
271         if (kernel_size < 0)
272             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
273                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
274                                     TARGET_PAGE_SIZE);
275         if (kernel_size < 0)
276             kernel_size = load_image_targphys(kernel_filename,
277                                               KERNEL_LOAD_ADDR,
278                                               RAM_size - KERNEL_LOAD_ADDR);
279         if (kernel_size < 0) {
280             error_report("could not load kernel '%s'", kernel_filename);
281             exit(1);
282         }
283 
284         /* load initrd */
285         *initrd_size = 0;
286         if (initrd_filename) {
287             *initrd_size = load_image_targphys(initrd_filename,
288                                                INITRD_LOAD_ADDR,
289                                                RAM_size - INITRD_LOAD_ADDR);
290             if ((int)*initrd_size < 0) {
291                 error_report("could not load initial ram disk '%s'",
292                              initrd_filename);
293                 exit(1);
294             }
295         }
296         if (*initrd_size > 0) {
297             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
298                 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24);
299                 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */
300                     stl_p(ptr + 16, INITRD_LOAD_ADDR);
301                     stl_p(ptr + 20, *initrd_size);
302                     break;
303                 }
304             }
305         }
306     }
307     return kernel_size;
308 }
309 
310 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
311 {
312     DeviceState *dev;
313     SysBusDevice *s;
314 
315     dev = qdev_create(NULL, TYPE_SUN4M_IOMMU);
316     qdev_prop_set_uint32(dev, "version", version);
317     qdev_init_nofail(dev);
318     s = SYS_BUS_DEVICE(dev);
319     sysbus_connect_irq(s, 0, irq);
320     sysbus_mmio_map(s, 0, addr);
321 
322     return s;
323 }
324 
325 static void *sparc32_dma_init(hwaddr dma_base,
326                               hwaddr esp_base, qemu_irq espdma_irq,
327                               hwaddr le_base, qemu_irq ledma_irq)
328 {
329     DeviceState *dma;
330     ESPDMADeviceState *espdma;
331     LEDMADeviceState *ledma;
332     SysBusESPState *esp;
333     SysBusPCNetState *lance;
334 
335     dma = qdev_create(NULL, TYPE_SPARC32_DMA);
336     qdev_init_nofail(dma);
337     sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
338 
339     espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
340                                    OBJECT(dma), "espdma"));
341     sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
342 
343     esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp"));
344     sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
345     scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
346 
347     ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
348                                  OBJECT(dma), "ledma"));
349     sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
350 
351     lance = SYSBUS_PCNET(object_resolve_path_component(
352                          OBJECT(ledma), "lance"));
353     sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
354 
355     return dma;
356 }
357 
358 static DeviceState *slavio_intctl_init(hwaddr addr,
359                                        hwaddr addrg,
360                                        qemu_irq **parent_irq)
361 {
362     DeviceState *dev;
363     SysBusDevice *s;
364     unsigned int i, j;
365 
366     dev = qdev_create(NULL, "slavio_intctl");
367     qdev_init_nofail(dev);
368 
369     s = SYS_BUS_DEVICE(dev);
370 
371     for (i = 0; i < MAX_CPUS; i++) {
372         for (j = 0; j < MAX_PILS; j++) {
373             sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
374         }
375     }
376     sysbus_mmio_map(s, 0, addrg);
377     for (i = 0; i < MAX_CPUS; i++) {
378         sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
379     }
380 
381     return dev;
382 }
383 
384 #define SYS_TIMER_OFFSET      0x10000ULL
385 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
386 
387 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
388                                   qemu_irq *cpu_irqs, unsigned int num_cpus)
389 {
390     DeviceState *dev;
391     SysBusDevice *s;
392     unsigned int i;
393 
394     dev = qdev_create(NULL, "slavio_timer");
395     qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
396     qdev_init_nofail(dev);
397     s = SYS_BUS_DEVICE(dev);
398     sysbus_connect_irq(s, 0, master_irq);
399     sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
400 
401     for (i = 0; i < MAX_CPUS; i++) {
402         sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
403         sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
404     }
405 }
406 
407 static qemu_irq  slavio_system_powerdown;
408 
409 static void slavio_powerdown_req(Notifier *n, void *opaque)
410 {
411     qemu_irq_raise(slavio_system_powerdown);
412 }
413 
414 static Notifier slavio_system_powerdown_notifier = {
415     .notify = slavio_powerdown_req
416 };
417 
418 #define MISC_LEDS 0x01600000
419 #define MISC_CFG  0x01800000
420 #define MISC_DIAG 0x01a00000
421 #define MISC_MDM  0x01b00000
422 #define MISC_SYS  0x01f00000
423 
424 static void slavio_misc_init(hwaddr base,
425                              hwaddr aux1_base,
426                              hwaddr aux2_base, qemu_irq irq,
427                              qemu_irq fdc_tc)
428 {
429     DeviceState *dev;
430     SysBusDevice *s;
431 
432     dev = qdev_create(NULL, "slavio_misc");
433     qdev_init_nofail(dev);
434     s = SYS_BUS_DEVICE(dev);
435     if (base) {
436         /* 8 bit registers */
437         /* Slavio control */
438         sysbus_mmio_map(s, 0, base + MISC_CFG);
439         /* Diagnostics */
440         sysbus_mmio_map(s, 1, base + MISC_DIAG);
441         /* Modem control */
442         sysbus_mmio_map(s, 2, base + MISC_MDM);
443         /* 16 bit registers */
444         /* ss600mp diag LEDs */
445         sysbus_mmio_map(s, 3, base + MISC_LEDS);
446         /* 32 bit registers */
447         /* System control */
448         sysbus_mmio_map(s, 4, base + MISC_SYS);
449     }
450     if (aux1_base) {
451         /* AUX 1 (Misc System Functions) */
452         sysbus_mmio_map(s, 5, aux1_base);
453     }
454     if (aux2_base) {
455         /* AUX 2 (Software Powerdown Control) */
456         sysbus_mmio_map(s, 6, aux2_base);
457     }
458     sysbus_connect_irq(s, 0, irq);
459     sysbus_connect_irq(s, 1, fdc_tc);
460     slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
461     qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
462 }
463 
464 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
465 {
466     DeviceState *dev;
467     SysBusDevice *s;
468 
469     dev = qdev_create(NULL, "eccmemctl");
470     qdev_prop_set_uint32(dev, "version", version);
471     qdev_init_nofail(dev);
472     s = SYS_BUS_DEVICE(dev);
473     sysbus_connect_irq(s, 0, irq);
474     sysbus_mmio_map(s, 0, base);
475     if (version == 0) { // SS-600MP only
476         sysbus_mmio_map(s, 1, base + 0x1000);
477     }
478 }
479 
480 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
481 {
482     DeviceState *dev;
483     SysBusDevice *s;
484 
485     dev = qdev_create(NULL, "apc");
486     qdev_init_nofail(dev);
487     s = SYS_BUS_DEVICE(dev);
488     /* Power management (APC) XXX: not a Slavio device */
489     sysbus_mmio_map(s, 0, power_base);
490     sysbus_connect_irq(s, 0, cpu_halt);
491 }
492 
493 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
494                      int height, int depth)
495 {
496     DeviceState *dev;
497     SysBusDevice *s;
498 
499     dev = qdev_create(NULL, "SUNW,tcx");
500     qdev_prop_set_uint32(dev, "vram_size", vram_size);
501     qdev_prop_set_uint16(dev, "width", width);
502     qdev_prop_set_uint16(dev, "height", height);
503     qdev_prop_set_uint16(dev, "depth", depth);
504     qdev_init_nofail(dev);
505     s = SYS_BUS_DEVICE(dev);
506 
507     /* 10/ROM : FCode ROM */
508     sysbus_mmio_map(s, 0, addr);
509     /* 2/STIP : Stipple */
510     sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
511     /* 3/BLIT : Blitter */
512     sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
513     /* 5/RSTIP : Raw Stipple */
514     sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
515     /* 6/RBLIT : Raw Blitter */
516     sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
517     /* 7/TEC : Transform Engine */
518     sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
519     /* 8/CMAP  : DAC */
520     sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
521     /* 9/THC : */
522     if (depth == 8) {
523         sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
524     } else {
525         sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
526     }
527     /* 11/DHC : */
528     sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
529     /* 12/ALT : */
530     sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
531     /* 0/DFB8 : 8-bit plane */
532     sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
533     /* 1/DFB24 : 24bit plane */
534     sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
535     /* 4/RDFB32: Raw framebuffer. Control plane */
536     sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
537     /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
538     if (depth == 8) {
539         sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
540     }
541 
542     sysbus_connect_irq(s, 0, irq);
543 }
544 
545 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
546                      int height, int depth)
547 {
548     DeviceState *dev;
549     SysBusDevice *s;
550 
551     dev = qdev_create(NULL, "cgthree");
552     qdev_prop_set_uint32(dev, "vram-size", vram_size);
553     qdev_prop_set_uint16(dev, "width", width);
554     qdev_prop_set_uint16(dev, "height", height);
555     qdev_prop_set_uint16(dev, "depth", depth);
556     qdev_init_nofail(dev);
557     s = SYS_BUS_DEVICE(dev);
558 
559     /* FCode ROM */
560     sysbus_mmio_map(s, 0, addr);
561     /* DAC */
562     sysbus_mmio_map(s, 1, addr + 0x400000ULL);
563     /* 8-bit plane */
564     sysbus_mmio_map(s, 2, addr + 0x800000ULL);
565 
566     sysbus_connect_irq(s, 0, irq);
567 }
568 
569 /* NCR89C100/MACIO Internal ID register */
570 
571 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
572 
573 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
574 
575 static void idreg_init(hwaddr addr)
576 {
577     DeviceState *dev;
578     SysBusDevice *s;
579 
580     dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
581     qdev_init_nofail(dev);
582     s = SYS_BUS_DEVICE(dev);
583 
584     sysbus_mmio_map(s, 0, addr);
585     address_space_write_rom(&address_space_memory, addr,
586                             MEMTXATTRS_UNSPECIFIED,
587                             idreg_data, sizeof(idreg_data));
588 }
589 
590 #define MACIO_ID_REGISTER(obj) \
591     OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
592 
593 typedef struct IDRegState {
594     SysBusDevice parent_obj;
595 
596     MemoryRegion mem;
597 } IDRegState;
598 
599 static void idreg_realize(DeviceState *ds, Error **errp)
600 {
601     IDRegState *s = MACIO_ID_REGISTER(ds);
602     SysBusDevice *dev = SYS_BUS_DEVICE(ds);
603     Error *local_err = NULL;
604 
605     memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
606                                      sizeof(idreg_data), &local_err);
607     if (local_err) {
608         error_propagate(errp, local_err);
609         return;
610     }
611 
612     vmstate_register_ram_global(&s->mem);
613     memory_region_set_readonly(&s->mem, true);
614     sysbus_init_mmio(dev, &s->mem);
615 }
616 
617 static void idreg_class_init(ObjectClass *oc, void *data)
618 {
619     DeviceClass *dc = DEVICE_CLASS(oc);
620 
621     dc->realize = idreg_realize;
622 }
623 
624 static const TypeInfo idreg_info = {
625     .name          = TYPE_MACIO_ID_REGISTER,
626     .parent        = TYPE_SYS_BUS_DEVICE,
627     .instance_size = sizeof(IDRegState),
628     .class_init    = idreg_class_init,
629 };
630 
631 #define TYPE_TCX_AFX "tcx_afx"
632 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
633 
634 typedef struct AFXState {
635     SysBusDevice parent_obj;
636 
637     MemoryRegion mem;
638 } AFXState;
639 
640 /* SS-5 TCX AFX register */
641 static void afx_init(hwaddr addr)
642 {
643     DeviceState *dev;
644     SysBusDevice *s;
645 
646     dev = qdev_create(NULL, TYPE_TCX_AFX);
647     qdev_init_nofail(dev);
648     s = SYS_BUS_DEVICE(dev);
649 
650     sysbus_mmio_map(s, 0, addr);
651 }
652 
653 static void afx_realize(DeviceState *ds, Error **errp)
654 {
655     AFXState *s = TCX_AFX(ds);
656     SysBusDevice *dev = SYS_BUS_DEVICE(ds);
657     Error *local_err = NULL;
658 
659     memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4,
660                                      &local_err);
661     if (local_err) {
662         error_propagate(errp, local_err);
663         return;
664     }
665 
666     vmstate_register_ram_global(&s->mem);
667     sysbus_init_mmio(dev, &s->mem);
668 }
669 
670 static void afx_class_init(ObjectClass *oc, void *data)
671 {
672     DeviceClass *dc = DEVICE_CLASS(oc);
673 
674     dc->realize = afx_realize;
675 }
676 
677 static const TypeInfo afx_info = {
678     .name          = TYPE_TCX_AFX,
679     .parent        = TYPE_SYS_BUS_DEVICE,
680     .instance_size = sizeof(AFXState),
681     .class_init    = afx_class_init,
682 };
683 
684 #define TYPE_OPENPROM "openprom"
685 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
686 
687 typedef struct PROMState {
688     SysBusDevice parent_obj;
689 
690     MemoryRegion prom;
691 } PROMState;
692 
693 /* Boot PROM (OpenBIOS) */
694 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
695 {
696     hwaddr *base_addr = (hwaddr *)opaque;
697     return addr + *base_addr - PROM_VADDR;
698 }
699 
700 static void prom_init(hwaddr addr, const char *bios_name)
701 {
702     DeviceState *dev;
703     SysBusDevice *s;
704     char *filename;
705     int ret;
706 
707     dev = qdev_create(NULL, TYPE_OPENPROM);
708     qdev_init_nofail(dev);
709     s = SYS_BUS_DEVICE(dev);
710 
711     sysbus_mmio_map(s, 0, addr);
712 
713     /* load boot prom */
714     if (bios_name == NULL) {
715         bios_name = PROM_FILENAME;
716     }
717     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
718     if (filename) {
719         ret = load_elf(filename, NULL,
720                        translate_prom_address, &addr, NULL,
721                        NULL, NULL, 1, EM_SPARC, 0, 0);
722         if (ret < 0 || ret > PROM_SIZE_MAX) {
723             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
724         }
725         g_free(filename);
726     } else {
727         ret = -1;
728     }
729     if (ret < 0 || ret > PROM_SIZE_MAX) {
730         error_report("could not load prom '%s'", bios_name);
731         exit(1);
732     }
733 }
734 
735 static void prom_realize(DeviceState *ds, Error **errp)
736 {
737     PROMState *s = OPENPROM(ds);
738     SysBusDevice *dev = SYS_BUS_DEVICE(ds);
739     Error *local_err = NULL;
740 
741     memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
742                                      PROM_SIZE_MAX, &local_err);
743     if (local_err) {
744         error_propagate(errp, local_err);
745         return;
746     }
747 
748     vmstate_register_ram_global(&s->prom);
749     memory_region_set_readonly(&s->prom, true);
750     sysbus_init_mmio(dev, &s->prom);
751 }
752 
753 static Property prom_properties[] = {
754     {/* end of property list */},
755 };
756 
757 static void prom_class_init(ObjectClass *klass, void *data)
758 {
759     DeviceClass *dc = DEVICE_CLASS(klass);
760 
761     dc->props = prom_properties;
762     dc->realize = prom_realize;
763 }
764 
765 static const TypeInfo prom_info = {
766     .name          = TYPE_OPENPROM,
767     .parent        = TYPE_SYS_BUS_DEVICE,
768     .instance_size = sizeof(PROMState),
769     .class_init    = prom_class_init,
770 };
771 
772 #define TYPE_SUN4M_MEMORY "memory"
773 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
774 
775 typedef struct RamDevice {
776     SysBusDevice parent_obj;
777 
778     MemoryRegion ram;
779     uint64_t size;
780 } RamDevice;
781 
782 /* System RAM */
783 static void ram_realize(DeviceState *dev, Error **errp)
784 {
785     RamDevice *d = SUN4M_RAM(dev);
786     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
787 
788     memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
789                                          d->size);
790     sysbus_init_mmio(sbd, &d->ram);
791 }
792 
793 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
794                      uint64_t max_mem)
795 {
796     DeviceState *dev;
797     SysBusDevice *s;
798     RamDevice *d;
799 
800     /* allocate RAM */
801     if ((uint64_t)RAM_size > max_mem) {
802         error_report("Too much memory for this machine: %" PRId64 ","
803                      " maximum %" PRId64,
804                      RAM_size / MiB, max_mem / MiB);
805         exit(1);
806     }
807     dev = qdev_create(NULL, "memory");
808     s = SYS_BUS_DEVICE(dev);
809 
810     d = SUN4M_RAM(dev);
811     d->size = RAM_size;
812     qdev_init_nofail(dev);
813 
814     sysbus_mmio_map(s, 0, addr);
815 }
816 
817 static Property ram_properties[] = {
818     DEFINE_PROP_UINT64("size", RamDevice, size, 0),
819     DEFINE_PROP_END_OF_LIST(),
820 };
821 
822 static void ram_class_init(ObjectClass *klass, void *data)
823 {
824     DeviceClass *dc = DEVICE_CLASS(klass);
825 
826     dc->realize = ram_realize;
827     dc->props = ram_properties;
828 }
829 
830 static const TypeInfo ram_info = {
831     .name          = TYPE_SUN4M_MEMORY,
832     .parent        = TYPE_SYS_BUS_DEVICE,
833     .instance_size = sizeof(RamDevice),
834     .class_init    = ram_class_init,
835 };
836 
837 static void cpu_devinit(const char *cpu_type, unsigned int id,
838                         uint64_t prom_addr, qemu_irq **cpu_irqs)
839 {
840     CPUState *cs;
841     SPARCCPU *cpu;
842     CPUSPARCState *env;
843 
844     cpu = SPARC_CPU(cpu_create(cpu_type));
845     env = &cpu->env;
846 
847     cpu_sparc_set_id(env, id);
848     if (id == 0) {
849         qemu_register_reset(main_cpu_reset, cpu);
850     } else {
851         qemu_register_reset(secondary_cpu_reset, cpu);
852         cs = CPU(cpu);
853         cs->halted = 1;
854     }
855     *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
856     env->prom_addr = prom_addr;
857 }
858 
859 static void dummy_fdc_tc(void *opaque, int irq, int level)
860 {
861 }
862 
863 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
864                           MachineState *machine)
865 {
866     DeviceState *slavio_intctl;
867     unsigned int i;
868     void *nvram;
869     qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
870     qemu_irq fdc_tc;
871     unsigned long kernel_size;
872     uint32_t initrd_size;
873     DriveInfo *fd[MAX_FD];
874     FWCfgState *fw_cfg;
875     DeviceState *dev;
876     SysBusDevice *s;
877     unsigned int smp_cpus = machine->smp.cpus;
878     unsigned int max_cpus = machine->smp.max_cpus;
879 
880     /* init CPUs */
881     for(i = 0; i < smp_cpus; i++) {
882         cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
883     }
884 
885     for (i = smp_cpus; i < MAX_CPUS; i++)
886         cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
887 
888 
889     /* set up devices */
890     ram_init(0, machine->ram_size, hwdef->max_mem);
891     /* models without ECC don't trap when missing ram is accessed */
892     if (!hwdef->ecc_base) {
893         empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
894     }
895 
896     prom_init(hwdef->slavio_base, bios_name);
897 
898     slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
899                                        hwdef->intctl_base + 0x10000ULL,
900                                        cpu_irqs);
901 
902     for (i = 0; i < 32; i++) {
903         slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
904     }
905     for (i = 0; i < MAX_CPUS; i++) {
906         slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
907     }
908 
909     if (hwdef->idreg_base) {
910         idreg_init(hwdef->idreg_base);
911     }
912 
913     if (hwdef->afx_base) {
914         afx_init(hwdef->afx_base);
915     }
916 
917     iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
918 
919     if (hwdef->iommu_pad_base) {
920         /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
921            Software shouldn't use aliased addresses, neither should it crash
922            when does. Using empty_slot instead of aliasing can help with
923            debugging such accesses */
924         empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
925     }
926 
927     sparc32_dma_init(hwdef->dma_base,
928                      hwdef->esp_base, slavio_irq[18],
929                      hwdef->le_base, slavio_irq[16]);
930 
931     if (graphic_depth != 8 && graphic_depth != 24) {
932         error_report("Unsupported depth: %d", graphic_depth);
933         exit (1);
934     }
935     if (vga_interface_type != VGA_NONE) {
936         if (vga_interface_type == VGA_CG3) {
937             if (graphic_depth != 8) {
938                 error_report("Unsupported depth: %d", graphic_depth);
939                 exit(1);
940             }
941 
942             if (!(graphic_width == 1024 && graphic_height == 768) &&
943                 !(graphic_width == 1152 && graphic_height == 900)) {
944                 error_report("Unsupported resolution: %d x %d", graphic_width,
945                              graphic_height);
946                 exit(1);
947             }
948 
949             /* sbus irq 5 */
950             cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
951                      graphic_width, graphic_height, graphic_depth);
952         } else {
953             /* If no display specified, default to TCX */
954             if (graphic_depth != 8 && graphic_depth != 24) {
955                 error_report("Unsupported depth: %d", graphic_depth);
956                 exit(1);
957             }
958 
959             if (!(graphic_width == 1024 && graphic_height == 768)) {
960                 error_report("Unsupported resolution: %d x %d",
961                              graphic_width, graphic_height);
962                 exit(1);
963             }
964 
965             tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
966                      graphic_width, graphic_height, graphic_depth);
967         }
968     }
969 
970     for (i = 0; i < MAX_VSIMMS; i++) {
971         /* vsimm registers probed by OBP */
972         if (hwdef->vsimm[i].reg_base) {
973             empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
974         }
975     }
976 
977     if (hwdef->sx_base) {
978         empty_slot_init(hwdef->sx_base, 0x2000);
979     }
980 
981     nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
982 
983     slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
984 
985     /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
986        Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
987     dev = qdev_create(NULL, TYPE_ESCC);
988     qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
989     qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
990     qdev_prop_set_uint32(dev, "it_shift", 1);
991     qdev_prop_set_chr(dev, "chrB", NULL);
992     qdev_prop_set_chr(dev, "chrA", NULL);
993     qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
994     qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
995     qdev_init_nofail(dev);
996     s = SYS_BUS_DEVICE(dev);
997     sysbus_connect_irq(s, 0, slavio_irq[14]);
998     sysbus_connect_irq(s, 1, slavio_irq[14]);
999     sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
1000 
1001     dev = qdev_create(NULL, TYPE_ESCC);
1002     qdev_prop_set_uint32(dev, "disabled", 0);
1003     qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
1004     qdev_prop_set_uint32(dev, "it_shift", 1);
1005     qdev_prop_set_chr(dev, "chrB", serial_hd(1));
1006     qdev_prop_set_chr(dev, "chrA", serial_hd(0));
1007     qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
1008     qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
1009     qdev_init_nofail(dev);
1010 
1011     s = SYS_BUS_DEVICE(dev);
1012     sysbus_connect_irq(s, 0, slavio_irq[15]);
1013     sysbus_connect_irq(s, 1,  slavio_irq[15]);
1014     sysbus_mmio_map(s, 0, hwdef->serial_base);
1015 
1016     if (hwdef->apc_base) {
1017         apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
1018     }
1019 
1020     if (hwdef->fd_base) {
1021         /* there is zero or one floppy drive */
1022         memset(fd, 0, sizeof(fd));
1023         fd[0] = drive_get(IF_FLOPPY, 0, 0);
1024         sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1025                           &fdc_tc);
1026     } else {
1027         fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1028     }
1029 
1030     slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1031                      slavio_irq[30], fdc_tc);
1032 
1033     if (hwdef->cs_base) {
1034         sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1035                              slavio_irq[5]);
1036     }
1037 
1038     if (hwdef->dbri_base) {
1039         /* ISDN chip with attached CS4215 audio codec */
1040         /* prom space */
1041         empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1042         /* reg space */
1043         empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1044     }
1045 
1046     if (hwdef->bpp_base) {
1047         /* parallel port */
1048         empty_slot_init(hwdef->bpp_base, 0x20);
1049     }
1050 
1051     initrd_size = 0;
1052     kernel_size = sun4m_load_kernel(machine->kernel_filename,
1053                                     machine->initrd_filename,
1054                                     machine->ram_size, &initrd_size);
1055 
1056     nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1057                machine->boot_order, machine->ram_size, kernel_size,
1058                graphic_width, graphic_height, graphic_depth,
1059                hwdef->nvram_machine_id, "Sun4m");
1060 
1061     if (hwdef->ecc_base)
1062         ecc_init(hwdef->ecc_base, slavio_irq[28],
1063                  hwdef->ecc_version);
1064 
1065     dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
1066     fw_cfg = FW_CFG(dev);
1067     qdev_prop_set_uint32(dev, "data_width", 1);
1068     qdev_prop_set_bit(dev, "dma_enabled", false);
1069     object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1070                               OBJECT(fw_cfg), NULL);
1071     qdev_init_nofail(dev);
1072     s = SYS_BUS_DEVICE(dev);
1073     sysbus_mmio_map(s, 0, CFG_ADDR);
1074     sysbus_mmio_map(s, 1, CFG_ADDR + 2);
1075 
1076     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1077     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1078     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1079     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1080     fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1081     fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1082     fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1083     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1084     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1085     if (machine->kernel_cmdline) {
1086         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1087         pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1088                          machine->kernel_cmdline);
1089         fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1090         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1091                        strlen(machine->kernel_cmdline) + 1);
1092     } else {
1093         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1094         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1095     }
1096     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1097     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1098     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1099     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1100 }
1101 
1102 enum {
1103     ss5_id = 32,
1104     vger_id,
1105     lx_id,
1106     ss4_id,
1107     scls_id,
1108     sbook_id,
1109     ss10_id = 64,
1110     ss20_id,
1111     ss600mp_id,
1112 };
1113 
1114 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1115     /* SS-5 */
1116     {
1117         .iommu_base   = 0x10000000,
1118         .iommu_pad_base = 0x10004000,
1119         .iommu_pad_len  = 0x0fffb000,
1120         .tcx_base     = 0x50000000,
1121         .cs_base      = 0x6c000000,
1122         .slavio_base  = 0x70000000,
1123         .ms_kb_base   = 0x71000000,
1124         .serial_base  = 0x71100000,
1125         .nvram_base   = 0x71200000,
1126         .fd_base      = 0x71400000,
1127         .counter_base = 0x71d00000,
1128         .intctl_base  = 0x71e00000,
1129         .idreg_base   = 0x78000000,
1130         .dma_base     = 0x78400000,
1131         .esp_base     = 0x78800000,
1132         .le_base      = 0x78c00000,
1133         .apc_base     = 0x6a000000,
1134         .afx_base     = 0x6e000000,
1135         .aux1_base    = 0x71900000,
1136         .aux2_base    = 0x71910000,
1137         .nvram_machine_id = 0x80,
1138         .machine_id = ss5_id,
1139         .iommu_version = 0x05000000,
1140         .max_mem = 0x10000000,
1141     },
1142     /* SS-10 */
1143     {
1144         .iommu_base   = 0xfe0000000ULL,
1145         .tcx_base     = 0xe20000000ULL,
1146         .slavio_base  = 0xff0000000ULL,
1147         .ms_kb_base   = 0xff1000000ULL,
1148         .serial_base  = 0xff1100000ULL,
1149         .nvram_base   = 0xff1200000ULL,
1150         .fd_base      = 0xff1700000ULL,
1151         .counter_base = 0xff1300000ULL,
1152         .intctl_base  = 0xff1400000ULL,
1153         .idreg_base   = 0xef0000000ULL,
1154         .dma_base     = 0xef0400000ULL,
1155         .esp_base     = 0xef0800000ULL,
1156         .le_base      = 0xef0c00000ULL,
1157         .apc_base     = 0xefa000000ULL, // XXX should not exist
1158         .aux1_base    = 0xff1800000ULL,
1159         .aux2_base    = 0xff1a01000ULL,
1160         .ecc_base     = 0xf00000000ULL,
1161         .ecc_version  = 0x10000000, // version 0, implementation 1
1162         .nvram_machine_id = 0x72,
1163         .machine_id = ss10_id,
1164         .iommu_version = 0x03000000,
1165         .max_mem = 0xf00000000ULL,
1166     },
1167     /* SS-600MP */
1168     {
1169         .iommu_base   = 0xfe0000000ULL,
1170         .tcx_base     = 0xe20000000ULL,
1171         .slavio_base  = 0xff0000000ULL,
1172         .ms_kb_base   = 0xff1000000ULL,
1173         .serial_base  = 0xff1100000ULL,
1174         .nvram_base   = 0xff1200000ULL,
1175         .counter_base = 0xff1300000ULL,
1176         .intctl_base  = 0xff1400000ULL,
1177         .dma_base     = 0xef0081000ULL,
1178         .esp_base     = 0xef0080000ULL,
1179         .le_base      = 0xef0060000ULL,
1180         .apc_base     = 0xefa000000ULL, // XXX should not exist
1181         .aux1_base    = 0xff1800000ULL,
1182         .aux2_base    = 0xff1a01000ULL, // XXX should not exist
1183         .ecc_base     = 0xf00000000ULL,
1184         .ecc_version  = 0x00000000, // version 0, implementation 0
1185         .nvram_machine_id = 0x71,
1186         .machine_id = ss600mp_id,
1187         .iommu_version = 0x01000000,
1188         .max_mem = 0xf00000000ULL,
1189     },
1190     /* SS-20 */
1191     {
1192         .iommu_base   = 0xfe0000000ULL,
1193         .tcx_base     = 0xe20000000ULL,
1194         .slavio_base  = 0xff0000000ULL,
1195         .ms_kb_base   = 0xff1000000ULL,
1196         .serial_base  = 0xff1100000ULL,
1197         .nvram_base   = 0xff1200000ULL,
1198         .fd_base      = 0xff1700000ULL,
1199         .counter_base = 0xff1300000ULL,
1200         .intctl_base  = 0xff1400000ULL,
1201         .idreg_base   = 0xef0000000ULL,
1202         .dma_base     = 0xef0400000ULL,
1203         .esp_base     = 0xef0800000ULL,
1204         .le_base      = 0xef0c00000ULL,
1205         .bpp_base     = 0xef4800000ULL,
1206         .apc_base     = 0xefa000000ULL, // XXX should not exist
1207         .aux1_base    = 0xff1800000ULL,
1208         .aux2_base    = 0xff1a01000ULL,
1209         .dbri_base    = 0xee0000000ULL,
1210         .sx_base      = 0xf80000000ULL,
1211         .vsimm        = {
1212             {
1213                 .reg_base  = 0x9c000000ULL,
1214                 .vram_base = 0xfc000000ULL
1215             }, {
1216                 .reg_base  = 0x90000000ULL,
1217                 .vram_base = 0xf0000000ULL
1218             }, {
1219                 .reg_base  = 0x94000000ULL
1220             }, {
1221                 .reg_base  = 0x98000000ULL
1222             }
1223         },
1224         .ecc_base     = 0xf00000000ULL,
1225         .ecc_version  = 0x20000000, // version 0, implementation 2
1226         .nvram_machine_id = 0x72,
1227         .machine_id = ss20_id,
1228         .iommu_version = 0x13000000,
1229         .max_mem = 0xf00000000ULL,
1230     },
1231     /* Voyager */
1232     {
1233         .iommu_base   = 0x10000000,
1234         .tcx_base     = 0x50000000,
1235         .slavio_base  = 0x70000000,
1236         .ms_kb_base   = 0x71000000,
1237         .serial_base  = 0x71100000,
1238         .nvram_base   = 0x71200000,
1239         .fd_base      = 0x71400000,
1240         .counter_base = 0x71d00000,
1241         .intctl_base  = 0x71e00000,
1242         .idreg_base   = 0x78000000,
1243         .dma_base     = 0x78400000,
1244         .esp_base     = 0x78800000,
1245         .le_base      = 0x78c00000,
1246         .apc_base     = 0x71300000, // pmc
1247         .aux1_base    = 0x71900000,
1248         .aux2_base    = 0x71910000,
1249         .nvram_machine_id = 0x80,
1250         .machine_id = vger_id,
1251         .iommu_version = 0x05000000,
1252         .max_mem = 0x10000000,
1253     },
1254     /* LX */
1255     {
1256         .iommu_base   = 0x10000000,
1257         .iommu_pad_base = 0x10004000,
1258         .iommu_pad_len  = 0x0fffb000,
1259         .tcx_base     = 0x50000000,
1260         .slavio_base  = 0x70000000,
1261         .ms_kb_base   = 0x71000000,
1262         .serial_base  = 0x71100000,
1263         .nvram_base   = 0x71200000,
1264         .fd_base      = 0x71400000,
1265         .counter_base = 0x71d00000,
1266         .intctl_base  = 0x71e00000,
1267         .idreg_base   = 0x78000000,
1268         .dma_base     = 0x78400000,
1269         .esp_base     = 0x78800000,
1270         .le_base      = 0x78c00000,
1271         .aux1_base    = 0x71900000,
1272         .aux2_base    = 0x71910000,
1273         .nvram_machine_id = 0x80,
1274         .machine_id = lx_id,
1275         .iommu_version = 0x04000000,
1276         .max_mem = 0x10000000,
1277     },
1278     /* SS-4 */
1279     {
1280         .iommu_base   = 0x10000000,
1281         .tcx_base     = 0x50000000,
1282         .cs_base      = 0x6c000000,
1283         .slavio_base  = 0x70000000,
1284         .ms_kb_base   = 0x71000000,
1285         .serial_base  = 0x71100000,
1286         .nvram_base   = 0x71200000,
1287         .fd_base      = 0x71400000,
1288         .counter_base = 0x71d00000,
1289         .intctl_base  = 0x71e00000,
1290         .idreg_base   = 0x78000000,
1291         .dma_base     = 0x78400000,
1292         .esp_base     = 0x78800000,
1293         .le_base      = 0x78c00000,
1294         .apc_base     = 0x6a000000,
1295         .aux1_base    = 0x71900000,
1296         .aux2_base    = 0x71910000,
1297         .nvram_machine_id = 0x80,
1298         .machine_id = ss4_id,
1299         .iommu_version = 0x05000000,
1300         .max_mem = 0x10000000,
1301     },
1302     /* SPARCClassic */
1303     {
1304         .iommu_base   = 0x10000000,
1305         .tcx_base     = 0x50000000,
1306         .slavio_base  = 0x70000000,
1307         .ms_kb_base   = 0x71000000,
1308         .serial_base  = 0x71100000,
1309         .nvram_base   = 0x71200000,
1310         .fd_base      = 0x71400000,
1311         .counter_base = 0x71d00000,
1312         .intctl_base  = 0x71e00000,
1313         .idreg_base   = 0x78000000,
1314         .dma_base     = 0x78400000,
1315         .esp_base     = 0x78800000,
1316         .le_base      = 0x78c00000,
1317         .apc_base     = 0x6a000000,
1318         .aux1_base    = 0x71900000,
1319         .aux2_base    = 0x71910000,
1320         .nvram_machine_id = 0x80,
1321         .machine_id = scls_id,
1322         .iommu_version = 0x05000000,
1323         .max_mem = 0x10000000,
1324     },
1325     /* SPARCbook */
1326     {
1327         .iommu_base   = 0x10000000,
1328         .tcx_base     = 0x50000000, // XXX
1329         .slavio_base  = 0x70000000,
1330         .ms_kb_base   = 0x71000000,
1331         .serial_base  = 0x71100000,
1332         .nvram_base   = 0x71200000,
1333         .fd_base      = 0x71400000,
1334         .counter_base = 0x71d00000,
1335         .intctl_base  = 0x71e00000,
1336         .idreg_base   = 0x78000000,
1337         .dma_base     = 0x78400000,
1338         .esp_base     = 0x78800000,
1339         .le_base      = 0x78c00000,
1340         .apc_base     = 0x6a000000,
1341         .aux1_base    = 0x71900000,
1342         .aux2_base    = 0x71910000,
1343         .nvram_machine_id = 0x80,
1344         .machine_id = sbook_id,
1345         .iommu_version = 0x05000000,
1346         .max_mem = 0x10000000,
1347     },
1348 };
1349 
1350 /* SPARCstation 5 hardware initialisation */
1351 static void ss5_init(MachineState *machine)
1352 {
1353     sun4m_hw_init(&sun4m_hwdefs[0], machine);
1354 }
1355 
1356 /* SPARCstation 10 hardware initialisation */
1357 static void ss10_init(MachineState *machine)
1358 {
1359     sun4m_hw_init(&sun4m_hwdefs[1], machine);
1360 }
1361 
1362 /* SPARCserver 600MP hardware initialisation */
1363 static void ss600mp_init(MachineState *machine)
1364 {
1365     sun4m_hw_init(&sun4m_hwdefs[2], machine);
1366 }
1367 
1368 /* SPARCstation 20 hardware initialisation */
1369 static void ss20_init(MachineState *machine)
1370 {
1371     sun4m_hw_init(&sun4m_hwdefs[3], machine);
1372 }
1373 
1374 /* SPARCstation Voyager hardware initialisation */
1375 static void vger_init(MachineState *machine)
1376 {
1377     sun4m_hw_init(&sun4m_hwdefs[4], machine);
1378 }
1379 
1380 /* SPARCstation LX hardware initialisation */
1381 static void ss_lx_init(MachineState *machine)
1382 {
1383     sun4m_hw_init(&sun4m_hwdefs[5], machine);
1384 }
1385 
1386 /* SPARCstation 4 hardware initialisation */
1387 static void ss4_init(MachineState *machine)
1388 {
1389     sun4m_hw_init(&sun4m_hwdefs[6], machine);
1390 }
1391 
1392 /* SPARCClassic hardware initialisation */
1393 static void scls_init(MachineState *machine)
1394 {
1395     sun4m_hw_init(&sun4m_hwdefs[7], machine);
1396 }
1397 
1398 /* SPARCbook hardware initialisation */
1399 static void sbook_init(MachineState *machine)
1400 {
1401     sun4m_hw_init(&sun4m_hwdefs[8], machine);
1402 }
1403 
1404 static void ss5_class_init(ObjectClass *oc, void *data)
1405 {
1406     MachineClass *mc = MACHINE_CLASS(oc);
1407 
1408     mc->desc = "Sun4m platform, SPARCstation 5";
1409     mc->init = ss5_init;
1410     mc->block_default_type = IF_SCSI;
1411     mc->is_default = 1;
1412     mc->default_boot_order = "c";
1413     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1414     mc->default_display = "tcx";
1415 }
1416 
1417 static const TypeInfo ss5_type = {
1418     .name = MACHINE_TYPE_NAME("SS-5"),
1419     .parent = TYPE_MACHINE,
1420     .class_init = ss5_class_init,
1421 };
1422 
1423 static void ss10_class_init(ObjectClass *oc, void *data)
1424 {
1425     MachineClass *mc = MACHINE_CLASS(oc);
1426 
1427     mc->desc = "Sun4m platform, SPARCstation 10";
1428     mc->init = ss10_init;
1429     mc->block_default_type = IF_SCSI;
1430     mc->max_cpus = 4;
1431     mc->default_boot_order = "c";
1432     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1433     mc->default_display = "tcx";
1434 }
1435 
1436 static const TypeInfo ss10_type = {
1437     .name = MACHINE_TYPE_NAME("SS-10"),
1438     .parent = TYPE_MACHINE,
1439     .class_init = ss10_class_init,
1440 };
1441 
1442 static void ss600mp_class_init(ObjectClass *oc, void *data)
1443 {
1444     MachineClass *mc = MACHINE_CLASS(oc);
1445 
1446     mc->desc = "Sun4m platform, SPARCserver 600MP";
1447     mc->init = ss600mp_init;
1448     mc->block_default_type = IF_SCSI;
1449     mc->max_cpus = 4;
1450     mc->default_boot_order = "c";
1451     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1452     mc->default_display = "tcx";
1453 }
1454 
1455 static const TypeInfo ss600mp_type = {
1456     .name = MACHINE_TYPE_NAME("SS-600MP"),
1457     .parent = TYPE_MACHINE,
1458     .class_init = ss600mp_class_init,
1459 };
1460 
1461 static void ss20_class_init(ObjectClass *oc, void *data)
1462 {
1463     MachineClass *mc = MACHINE_CLASS(oc);
1464 
1465     mc->desc = "Sun4m platform, SPARCstation 20";
1466     mc->init = ss20_init;
1467     mc->block_default_type = IF_SCSI;
1468     mc->max_cpus = 4;
1469     mc->default_boot_order = "c";
1470     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1471     mc->default_display = "tcx";
1472 }
1473 
1474 static const TypeInfo ss20_type = {
1475     .name = MACHINE_TYPE_NAME("SS-20"),
1476     .parent = TYPE_MACHINE,
1477     .class_init = ss20_class_init,
1478 };
1479 
1480 static void voyager_class_init(ObjectClass *oc, void *data)
1481 {
1482     MachineClass *mc = MACHINE_CLASS(oc);
1483 
1484     mc->desc = "Sun4m platform, SPARCstation Voyager";
1485     mc->init = vger_init;
1486     mc->block_default_type = IF_SCSI;
1487     mc->default_boot_order = "c";
1488     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1489     mc->default_display = "tcx";
1490 }
1491 
1492 static const TypeInfo voyager_type = {
1493     .name = MACHINE_TYPE_NAME("Voyager"),
1494     .parent = TYPE_MACHINE,
1495     .class_init = voyager_class_init,
1496 };
1497 
1498 static void ss_lx_class_init(ObjectClass *oc, void *data)
1499 {
1500     MachineClass *mc = MACHINE_CLASS(oc);
1501 
1502     mc->desc = "Sun4m platform, SPARCstation LX";
1503     mc->init = ss_lx_init;
1504     mc->block_default_type = IF_SCSI;
1505     mc->default_boot_order = "c";
1506     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1507     mc->default_display = "tcx";
1508 }
1509 
1510 static const TypeInfo ss_lx_type = {
1511     .name = MACHINE_TYPE_NAME("LX"),
1512     .parent = TYPE_MACHINE,
1513     .class_init = ss_lx_class_init,
1514 };
1515 
1516 static void ss4_class_init(ObjectClass *oc, void *data)
1517 {
1518     MachineClass *mc = MACHINE_CLASS(oc);
1519 
1520     mc->desc = "Sun4m platform, SPARCstation 4";
1521     mc->init = ss4_init;
1522     mc->block_default_type = IF_SCSI;
1523     mc->default_boot_order = "c";
1524     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1525     mc->default_display = "tcx";
1526 }
1527 
1528 static const TypeInfo ss4_type = {
1529     .name = MACHINE_TYPE_NAME("SS-4"),
1530     .parent = TYPE_MACHINE,
1531     .class_init = ss4_class_init,
1532 };
1533 
1534 static void scls_class_init(ObjectClass *oc, void *data)
1535 {
1536     MachineClass *mc = MACHINE_CLASS(oc);
1537 
1538     mc->desc = "Sun4m platform, SPARCClassic";
1539     mc->init = scls_init;
1540     mc->block_default_type = IF_SCSI;
1541     mc->default_boot_order = "c";
1542     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1543     mc->default_display = "tcx";
1544 }
1545 
1546 static const TypeInfo scls_type = {
1547     .name = MACHINE_TYPE_NAME("SPARCClassic"),
1548     .parent = TYPE_MACHINE,
1549     .class_init = scls_class_init,
1550 };
1551 
1552 static void sbook_class_init(ObjectClass *oc, void *data)
1553 {
1554     MachineClass *mc = MACHINE_CLASS(oc);
1555 
1556     mc->desc = "Sun4m platform, SPARCbook";
1557     mc->init = sbook_init;
1558     mc->block_default_type = IF_SCSI;
1559     mc->default_boot_order = "c";
1560     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1561     mc->default_display = "tcx";
1562 }
1563 
1564 static const TypeInfo sbook_type = {
1565     .name = MACHINE_TYPE_NAME("SPARCbook"),
1566     .parent = TYPE_MACHINE,
1567     .class_init = sbook_class_init,
1568 };
1569 
1570 static void sun4m_register_types(void)
1571 {
1572     type_register_static(&idreg_info);
1573     type_register_static(&afx_info);
1574     type_register_static(&prom_info);
1575     type_register_static(&ram_info);
1576 
1577     type_register_static(&ss5_type);
1578     type_register_static(&ss10_type);
1579     type_register_static(&ss600mp_type);
1580     type_register_static(&ss20_type);
1581     type_register_static(&voyager_type);
1582     type_register_static(&ss_lx_type);
1583     type_register_static(&ss4_type);
1584     type_register_static(&scls_type);
1585     type_register_static(&sbook_type);
1586 }
1587 
1588 type_init(sun4m_register_types)
1589