1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "qemu/datadir.h" 29 #include "cpu.h" 30 #include "hw/sysbus.h" 31 #include "qemu/error-report.h" 32 #include "qemu/timer.h" 33 #include "hw/sparc/sun4m_iommu.h" 34 #include "hw/rtc/m48t59.h" 35 #include "migration/vmstate.h" 36 #include "hw/sparc/sparc32_dma.h" 37 #include "hw/block/fdc.h" 38 #include "sysemu/reset.h" 39 #include "sysemu/runstate.h" 40 #include "sysemu/sysemu.h" 41 #include "net/net.h" 42 #include "hw/boards.h" 43 #include "hw/scsi/esp.h" 44 #include "hw/nvram/sun_nvram.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/nvram/chrp_nvram.h" 47 #include "hw/nvram/fw_cfg.h" 48 #include "hw/char/escc.h" 49 #include "hw/misc/empty_slot.h" 50 #include "hw/misc/unimp.h" 51 #include "hw/irq.h" 52 #include "hw/or-irq.h" 53 #include "hw/loader.h" 54 #include "elf.h" 55 #include "trace.h" 56 #include "qom/object.h" 57 58 /* 59 * Sun4m architecture was used in the following machines: 60 * 61 * SPARCserver 6xxMP/xx 62 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 63 * SPARCclassic X (4/10) 64 * SPARCstation LX/ZX (4/30) 65 * SPARCstation Voyager 66 * SPARCstation 10/xx, SPARCserver 10/xx 67 * SPARCstation 5, SPARCserver 5 68 * SPARCstation 20/xx, SPARCserver 20 69 * SPARCstation 4 70 * 71 * See for example: http://www.sunhelp.org/faq/sunref1.html 72 */ 73 74 #define KERNEL_LOAD_ADDR 0x00004000 75 #define CMDLINE_ADDR 0x007ff000 76 #define INITRD_LOAD_ADDR 0x00800000 77 #define PROM_SIZE_MAX (1 * MiB) 78 #define PROM_VADDR 0xffd00000 79 #define PROM_FILENAME "openbios-sparc32" 80 #define CFG_ADDR 0xd00000510ULL 81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 82 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 83 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 84 85 #define MAX_CPUS 16 86 #define MAX_PILS 16 87 #define MAX_VSIMMS 4 88 89 #define ESCC_CLOCK 4915200 90 91 struct sun4m_hwdef { 92 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 93 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 94 hwaddr serial_base, fd_base; 95 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 96 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 97 hwaddr bpp_base, dbri_base, sx_base; 98 struct { 99 hwaddr reg_base, vram_base; 100 } vsimm[MAX_VSIMMS]; 101 hwaddr ecc_base; 102 uint64_t max_mem; 103 uint32_t ecc_version; 104 uint32_t iommu_version; 105 uint16_t machine_id; 106 uint8_t nvram_machine_id; 107 }; 108 109 struct Sun4mMachineClass { 110 /*< private >*/ 111 MachineClass parent_obj; 112 /*< public >*/ 113 const struct sun4m_hwdef *hwdef; 114 }; 115 typedef struct Sun4mMachineClass Sun4mMachineClass; 116 117 #define TYPE_SUN4M_MACHINE MACHINE_TYPE_NAME("sun4m-common") 118 DECLARE_CLASS_CHECKERS(Sun4mMachineClass, SUN4M_MACHINE, TYPE_SUN4M_MACHINE) 119 120 const char *fw_cfg_arch_key_name(uint16_t key) 121 { 122 static const struct { 123 uint16_t key; 124 const char *name; 125 } fw_cfg_arch_wellknown_keys[] = { 126 {FW_CFG_SUN4M_DEPTH, "depth"}, 127 {FW_CFG_SUN4M_WIDTH, "width"}, 128 {FW_CFG_SUN4M_HEIGHT, "height"}, 129 }; 130 131 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { 132 if (fw_cfg_arch_wellknown_keys[i].key == key) { 133 return fw_cfg_arch_wellknown_keys[i].name; 134 } 135 } 136 return NULL; 137 } 138 139 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 140 Error **errp) 141 { 142 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 143 } 144 145 static void nvram_init(Nvram *nvram, uint8_t *macaddr, 146 const char *cmdline, const char *boot_devices, 147 ram_addr_t RAM_size, uint32_t kernel_size, 148 int width, int height, int depth, 149 int nvram_machine_id, const char *arch) 150 { 151 unsigned int i; 152 int sysp_end; 153 uint8_t image[0x1ff0]; 154 NvramClass *k = NVRAM_GET_CLASS(nvram); 155 156 memset(image, '\0', sizeof(image)); 157 158 /* OpenBIOS nvram variables partition */ 159 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0); 160 161 /* Free space partition */ 162 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 163 164 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 165 nvram_machine_id); 166 167 for (i = 0; i < sizeof(image); i++) { 168 (k->write)(nvram, i, image[i]); 169 } 170 } 171 172 static void cpu_kick_irq(SPARCCPU *cpu) 173 { 174 CPUSPARCState *env = &cpu->env; 175 CPUState *cs = CPU(cpu); 176 177 cs->halted = 0; 178 cpu_check_irqs(env); 179 qemu_cpu_kick(cs); 180 } 181 182 static void cpu_set_irq(void *opaque, int irq, int level) 183 { 184 SPARCCPU *cpu = opaque; 185 CPUSPARCState *env = &cpu->env; 186 187 if (level) { 188 trace_sun4m_cpu_set_irq_raise(irq); 189 env->pil_in |= 1 << irq; 190 cpu_kick_irq(cpu); 191 } else { 192 trace_sun4m_cpu_set_irq_lower(irq); 193 env->pil_in &= ~(1 << irq); 194 cpu_check_irqs(env); 195 } 196 } 197 198 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 199 { 200 } 201 202 static void sun4m_cpu_reset(void *opaque) 203 { 204 SPARCCPU *cpu = opaque; 205 CPUState *cs = CPU(cpu); 206 207 cpu_reset(cs); 208 } 209 210 static void cpu_halt_signal(void *opaque, int irq, int level) 211 { 212 if (level && current_cpu) { 213 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 214 } 215 } 216 217 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 218 { 219 return addr - 0xf0000000ULL; 220 } 221 222 static unsigned long sun4m_load_kernel(const char *kernel_filename, 223 const char *initrd_filename, 224 ram_addr_t RAM_size, 225 uint32_t *initrd_size) 226 { 227 int linux_boot; 228 unsigned int i; 229 long kernel_size; 230 uint8_t *ptr; 231 232 linux_boot = (kernel_filename != NULL); 233 234 kernel_size = 0; 235 if (linux_boot) { 236 int bswap_needed; 237 238 #ifdef BSWAP_NEEDED 239 bswap_needed = 1; 240 #else 241 bswap_needed = 0; 242 #endif 243 kernel_size = load_elf(kernel_filename, NULL, 244 translate_kernel_address, NULL, 245 NULL, NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 246 if (kernel_size < 0) 247 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 248 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 249 TARGET_PAGE_SIZE); 250 if (kernel_size < 0) 251 kernel_size = load_image_targphys(kernel_filename, 252 KERNEL_LOAD_ADDR, 253 RAM_size - KERNEL_LOAD_ADDR); 254 if (kernel_size < 0) { 255 error_report("could not load kernel '%s'", kernel_filename); 256 exit(1); 257 } 258 259 /* load initrd */ 260 *initrd_size = 0; 261 if (initrd_filename) { 262 *initrd_size = load_image_targphys(initrd_filename, 263 INITRD_LOAD_ADDR, 264 RAM_size - INITRD_LOAD_ADDR); 265 if ((int)*initrd_size < 0) { 266 error_report("could not load initial ram disk '%s'", 267 initrd_filename); 268 exit(1); 269 } 270 } 271 if (*initrd_size > 0) { 272 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 273 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24); 274 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */ 275 stl_p(ptr + 16, INITRD_LOAD_ADDR); 276 stl_p(ptr + 20, *initrd_size); 277 break; 278 } 279 } 280 } 281 } 282 return kernel_size; 283 } 284 285 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 286 { 287 DeviceState *dev; 288 SysBusDevice *s; 289 290 dev = qdev_new(TYPE_SUN4M_IOMMU); 291 qdev_prop_set_uint32(dev, "version", version); 292 s = SYS_BUS_DEVICE(dev); 293 sysbus_realize_and_unref(s, &error_fatal); 294 sysbus_connect_irq(s, 0, irq); 295 sysbus_mmio_map(s, 0, addr); 296 297 return s; 298 } 299 300 static void *sparc32_dma_init(hwaddr dma_base, 301 hwaddr esp_base, qemu_irq espdma_irq, 302 hwaddr le_base, qemu_irq ledma_irq, NICInfo *nd) 303 { 304 DeviceState *dma; 305 ESPDMADeviceState *espdma; 306 LEDMADeviceState *ledma; 307 SysBusESPState *esp; 308 SysBusPCNetState *lance; 309 310 dma = qdev_new(TYPE_SPARC32_DMA); 311 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( 312 OBJECT(dma), "espdma")); 313 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); 314 315 esp = SYSBUS_ESP(object_resolve_path_component(OBJECT(espdma), "esp")); 316 317 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( 318 OBJECT(dma), "ledma")); 319 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq); 320 321 lance = SYSBUS_PCNET(object_resolve_path_component( 322 OBJECT(ledma), "lance")); 323 qdev_set_nic_properties(DEVICE(lance), nd); 324 325 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); 326 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); 327 328 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base); 329 scsi_bus_legacy_handle_cmdline(&esp->esp.bus); 330 331 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base); 332 333 return dma; 334 } 335 336 static DeviceState *slavio_intctl_init(hwaddr addr, 337 hwaddr addrg, 338 qemu_irq **parent_irq) 339 { 340 DeviceState *dev; 341 SysBusDevice *s; 342 unsigned int i, j; 343 344 dev = qdev_new("slavio_intctl"); 345 346 s = SYS_BUS_DEVICE(dev); 347 sysbus_realize_and_unref(s, &error_fatal); 348 349 for (i = 0; i < MAX_CPUS; i++) { 350 for (j = 0; j < MAX_PILS; j++) { 351 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 352 } 353 } 354 sysbus_mmio_map(s, 0, addrg); 355 for (i = 0; i < MAX_CPUS; i++) { 356 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 357 } 358 359 return dev; 360 } 361 362 #define SYS_TIMER_OFFSET 0x10000ULL 363 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 364 365 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 366 qemu_irq *cpu_irqs, unsigned int num_cpus) 367 { 368 DeviceState *dev; 369 SysBusDevice *s; 370 unsigned int i; 371 372 dev = qdev_new("slavio_timer"); 373 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 374 s = SYS_BUS_DEVICE(dev); 375 sysbus_realize_and_unref(s, &error_fatal); 376 sysbus_connect_irq(s, 0, master_irq); 377 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 378 379 for (i = 0; i < MAX_CPUS; i++) { 380 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 381 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 382 } 383 } 384 385 static qemu_irq slavio_system_powerdown; 386 387 static void slavio_powerdown_req(Notifier *n, void *opaque) 388 { 389 qemu_irq_raise(slavio_system_powerdown); 390 } 391 392 static Notifier slavio_system_powerdown_notifier = { 393 .notify = slavio_powerdown_req 394 }; 395 396 #define MISC_LEDS 0x01600000 397 #define MISC_CFG 0x01800000 398 #define MISC_DIAG 0x01a00000 399 #define MISC_MDM 0x01b00000 400 #define MISC_SYS 0x01f00000 401 402 static void slavio_misc_init(hwaddr base, 403 hwaddr aux1_base, 404 hwaddr aux2_base, qemu_irq irq, 405 qemu_irq fdc_tc) 406 { 407 DeviceState *dev; 408 SysBusDevice *s; 409 410 dev = qdev_new("slavio_misc"); 411 s = SYS_BUS_DEVICE(dev); 412 sysbus_realize_and_unref(s, &error_fatal); 413 if (base) { 414 /* 8 bit registers */ 415 /* Slavio control */ 416 sysbus_mmio_map(s, 0, base + MISC_CFG); 417 /* Diagnostics */ 418 sysbus_mmio_map(s, 1, base + MISC_DIAG); 419 /* Modem control */ 420 sysbus_mmio_map(s, 2, base + MISC_MDM); 421 /* 16 bit registers */ 422 /* ss600mp diag LEDs */ 423 sysbus_mmio_map(s, 3, base + MISC_LEDS); 424 /* 32 bit registers */ 425 /* System control */ 426 sysbus_mmio_map(s, 4, base + MISC_SYS); 427 } 428 if (aux1_base) { 429 /* AUX 1 (Misc System Functions) */ 430 sysbus_mmio_map(s, 5, aux1_base); 431 } 432 if (aux2_base) { 433 /* AUX 2 (Software Powerdown Control) */ 434 sysbus_mmio_map(s, 6, aux2_base); 435 } 436 sysbus_connect_irq(s, 0, irq); 437 sysbus_connect_irq(s, 1, fdc_tc); 438 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 439 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 440 } 441 442 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 443 { 444 DeviceState *dev; 445 SysBusDevice *s; 446 447 dev = qdev_new("eccmemctl"); 448 qdev_prop_set_uint32(dev, "version", version); 449 s = SYS_BUS_DEVICE(dev); 450 sysbus_realize_and_unref(s, &error_fatal); 451 sysbus_connect_irq(s, 0, irq); 452 sysbus_mmio_map(s, 0, base); 453 if (version == 0) { // SS-600MP only 454 sysbus_mmio_map(s, 1, base + 0x1000); 455 } 456 } 457 458 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 459 { 460 DeviceState *dev; 461 SysBusDevice *s; 462 463 dev = qdev_new("apc"); 464 s = SYS_BUS_DEVICE(dev); 465 sysbus_realize_and_unref(s, &error_fatal); 466 /* Power management (APC) XXX: not a Slavio device */ 467 sysbus_mmio_map(s, 0, power_base); 468 sysbus_connect_irq(s, 0, cpu_halt); 469 } 470 471 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 472 int height, int depth) 473 { 474 DeviceState *dev; 475 SysBusDevice *s; 476 477 dev = qdev_new("sun-tcx"); 478 qdev_prop_set_uint32(dev, "vram_size", vram_size); 479 qdev_prop_set_uint16(dev, "width", width); 480 qdev_prop_set_uint16(dev, "height", height); 481 qdev_prop_set_uint16(dev, "depth", depth); 482 s = SYS_BUS_DEVICE(dev); 483 sysbus_realize_and_unref(s, &error_fatal); 484 485 /* 10/ROM : FCode ROM */ 486 sysbus_mmio_map(s, 0, addr); 487 /* 2/STIP : Stipple */ 488 sysbus_mmio_map(s, 1, addr + 0x04000000ULL); 489 /* 3/BLIT : Blitter */ 490 sysbus_mmio_map(s, 2, addr + 0x06000000ULL); 491 /* 5/RSTIP : Raw Stipple */ 492 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); 493 /* 6/RBLIT : Raw Blitter */ 494 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); 495 /* 7/TEC : Transform Engine */ 496 sysbus_mmio_map(s, 5, addr + 0x00700000ULL); 497 /* 8/CMAP : DAC */ 498 sysbus_mmio_map(s, 6, addr + 0x00200000ULL); 499 /* 9/THC : */ 500 if (depth == 8) { 501 sysbus_mmio_map(s, 7, addr + 0x00300000ULL); 502 } else { 503 sysbus_mmio_map(s, 7, addr + 0x00301000ULL); 504 } 505 /* 11/DHC : */ 506 sysbus_mmio_map(s, 8, addr + 0x00240000ULL); 507 /* 12/ALT : */ 508 sysbus_mmio_map(s, 9, addr + 0x00280000ULL); 509 /* 0/DFB8 : 8-bit plane */ 510 sysbus_mmio_map(s, 10, addr + 0x00800000ULL); 511 /* 1/DFB24 : 24bit plane */ 512 sysbus_mmio_map(s, 11, addr + 0x02000000ULL); 513 /* 4/RDFB32: Raw framebuffer. Control plane */ 514 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); 515 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 516 if (depth == 8) { 517 sysbus_mmio_map(s, 13, addr + 0x00301000ULL); 518 } 519 520 sysbus_connect_irq(s, 0, irq); 521 } 522 523 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 524 int height, int depth) 525 { 526 DeviceState *dev; 527 SysBusDevice *s; 528 529 dev = qdev_new("cgthree"); 530 qdev_prop_set_uint32(dev, "vram-size", vram_size); 531 qdev_prop_set_uint16(dev, "width", width); 532 qdev_prop_set_uint16(dev, "height", height); 533 qdev_prop_set_uint16(dev, "depth", depth); 534 s = SYS_BUS_DEVICE(dev); 535 sysbus_realize_and_unref(s, &error_fatal); 536 537 /* FCode ROM */ 538 sysbus_mmio_map(s, 0, addr); 539 /* DAC */ 540 sysbus_mmio_map(s, 1, addr + 0x400000ULL); 541 /* 8-bit plane */ 542 sysbus_mmio_map(s, 2, addr + 0x800000ULL); 543 544 sysbus_connect_irq(s, 0, irq); 545 } 546 547 /* NCR89C100/MACIO Internal ID register */ 548 549 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 550 551 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 552 553 static void idreg_init(hwaddr addr) 554 { 555 DeviceState *dev; 556 SysBusDevice *s; 557 558 dev = qdev_new(TYPE_MACIO_ID_REGISTER); 559 s = SYS_BUS_DEVICE(dev); 560 sysbus_realize_and_unref(s, &error_fatal); 561 562 sysbus_mmio_map(s, 0, addr); 563 address_space_write_rom(&address_space_memory, addr, 564 MEMTXATTRS_UNSPECIFIED, 565 idreg_data, sizeof(idreg_data)); 566 } 567 568 OBJECT_DECLARE_SIMPLE_TYPE(IDRegState, MACIO_ID_REGISTER) 569 570 struct IDRegState { 571 SysBusDevice parent_obj; 572 573 MemoryRegion mem; 574 }; 575 576 static void idreg_realize(DeviceState *ds, Error **errp) 577 { 578 IDRegState *s = MACIO_ID_REGISTER(ds); 579 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 580 581 if (!memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg", 582 sizeof(idreg_data), errp)) { 583 return; 584 } 585 586 vmstate_register_ram_global(&s->mem); 587 memory_region_set_readonly(&s->mem, true); 588 sysbus_init_mmio(dev, &s->mem); 589 } 590 591 static void idreg_class_init(ObjectClass *oc, void *data) 592 { 593 DeviceClass *dc = DEVICE_CLASS(oc); 594 595 dc->realize = idreg_realize; 596 } 597 598 static const TypeInfo idreg_info = { 599 .name = TYPE_MACIO_ID_REGISTER, 600 .parent = TYPE_SYS_BUS_DEVICE, 601 .instance_size = sizeof(IDRegState), 602 .class_init = idreg_class_init, 603 }; 604 605 #define TYPE_TCX_AFX "tcx_afx" 606 OBJECT_DECLARE_SIMPLE_TYPE(AFXState, TCX_AFX) 607 608 struct AFXState { 609 SysBusDevice parent_obj; 610 611 MemoryRegion mem; 612 }; 613 614 /* SS-5 TCX AFX register */ 615 static void afx_init(hwaddr addr) 616 { 617 DeviceState *dev; 618 SysBusDevice *s; 619 620 dev = qdev_new(TYPE_TCX_AFX); 621 s = SYS_BUS_DEVICE(dev); 622 sysbus_realize_and_unref(s, &error_fatal); 623 624 sysbus_mmio_map(s, 0, addr); 625 } 626 627 static void afx_realize(DeviceState *ds, Error **errp) 628 { 629 AFXState *s = TCX_AFX(ds); 630 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 631 632 if (!memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 633 4, errp)) { 634 return; 635 } 636 637 vmstate_register_ram_global(&s->mem); 638 sysbus_init_mmio(dev, &s->mem); 639 } 640 641 static void afx_class_init(ObjectClass *oc, void *data) 642 { 643 DeviceClass *dc = DEVICE_CLASS(oc); 644 645 dc->realize = afx_realize; 646 } 647 648 static const TypeInfo afx_info = { 649 .name = TYPE_TCX_AFX, 650 .parent = TYPE_SYS_BUS_DEVICE, 651 .instance_size = sizeof(AFXState), 652 .class_init = afx_class_init, 653 }; 654 655 #define TYPE_OPENPROM "openprom" 656 typedef struct PROMState PROMState; 657 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM, 658 TYPE_OPENPROM) 659 660 struct PROMState { 661 SysBusDevice parent_obj; 662 663 MemoryRegion prom; 664 }; 665 666 /* Boot PROM (OpenBIOS) */ 667 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 668 { 669 hwaddr *base_addr = (hwaddr *)opaque; 670 return addr + *base_addr - PROM_VADDR; 671 } 672 673 static void prom_init(hwaddr addr, const char *bios_name) 674 { 675 DeviceState *dev; 676 SysBusDevice *s; 677 char *filename; 678 int ret; 679 680 dev = qdev_new(TYPE_OPENPROM); 681 s = SYS_BUS_DEVICE(dev); 682 sysbus_realize_and_unref(s, &error_fatal); 683 684 sysbus_mmio_map(s, 0, addr); 685 686 /* load boot prom */ 687 if (bios_name == NULL) { 688 bios_name = PROM_FILENAME; 689 } 690 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 691 if (filename) { 692 ret = load_elf(filename, NULL, 693 translate_prom_address, &addr, NULL, 694 NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 695 if (ret < 0 || ret > PROM_SIZE_MAX) { 696 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 697 } 698 g_free(filename); 699 } else { 700 ret = -1; 701 } 702 if (ret < 0 || ret > PROM_SIZE_MAX) { 703 error_report("could not load prom '%s'", bios_name); 704 exit(1); 705 } 706 } 707 708 static void prom_realize(DeviceState *ds, Error **errp) 709 { 710 PROMState *s = OPENPROM(ds); 711 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 712 713 if (!memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom", 714 PROM_SIZE_MAX, errp)) { 715 return; 716 } 717 718 vmstate_register_ram_global(&s->prom); 719 memory_region_set_readonly(&s->prom, true); 720 sysbus_init_mmio(dev, &s->prom); 721 } 722 723 static Property prom_properties[] = { 724 {/* end of property list */}, 725 }; 726 727 static void prom_class_init(ObjectClass *klass, void *data) 728 { 729 DeviceClass *dc = DEVICE_CLASS(klass); 730 731 device_class_set_props(dc, prom_properties); 732 dc->realize = prom_realize; 733 } 734 735 static const TypeInfo prom_info = { 736 .name = TYPE_OPENPROM, 737 .parent = TYPE_SYS_BUS_DEVICE, 738 .instance_size = sizeof(PROMState), 739 .class_init = prom_class_init, 740 }; 741 742 #define TYPE_SUN4M_MEMORY "memory" 743 typedef struct RamDevice RamDevice; 744 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4M_RAM, 745 TYPE_SUN4M_MEMORY) 746 747 struct RamDevice { 748 SysBusDevice parent_obj; 749 HostMemoryBackend *memdev; 750 }; 751 752 /* System RAM */ 753 static void ram_realize(DeviceState *dev, Error **errp) 754 { 755 RamDevice *d = SUN4M_RAM(dev); 756 MemoryRegion *ram = host_memory_backend_get_memory(d->memdev); 757 758 sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram); 759 } 760 761 static void ram_initfn(Object *obj) 762 { 763 RamDevice *d = SUN4M_RAM(obj); 764 object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND, 765 (Object **)&d->memdev, 766 object_property_allow_set_link, 767 OBJ_PROP_LINK_STRONG); 768 object_property_set_description(obj, "memdev", "Set RAM backend" 769 "Valid value is ID of a hostmem backend"); 770 } 771 772 static void ram_class_init(ObjectClass *klass, void *data) 773 { 774 DeviceClass *dc = DEVICE_CLASS(klass); 775 776 dc->realize = ram_realize; 777 } 778 779 static const TypeInfo ram_info = { 780 .name = TYPE_SUN4M_MEMORY, 781 .parent = TYPE_SYS_BUS_DEVICE, 782 .instance_size = sizeof(RamDevice), 783 .instance_init = ram_initfn, 784 .class_init = ram_class_init, 785 }; 786 787 static void cpu_devinit(const char *cpu_type, unsigned int id, 788 uint64_t prom_addr, qemu_irq **cpu_irqs) 789 { 790 SPARCCPU *cpu; 791 CPUSPARCState *env; 792 793 cpu = SPARC_CPU(object_new(cpu_type)); 794 env = &cpu->env; 795 796 qemu_register_reset(sun4m_cpu_reset, cpu); 797 object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0, 798 &error_abort); 799 qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); 800 cpu_sparc_set_id(env, id); 801 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 802 env->prom_addr = prom_addr; 803 } 804 805 static void dummy_fdc_tc(void *opaque, int irq, int level) 806 { 807 } 808 809 static void sun4m_hw_init(MachineState *machine) 810 { 811 const struct sun4m_hwdef *hwdef = SUN4M_MACHINE_GET_CLASS(machine)->hwdef; 812 DeviceState *slavio_intctl; 813 unsigned int i; 814 Nvram *nvram; 815 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; 816 qemu_irq fdc_tc; 817 unsigned long kernel_size; 818 uint32_t initrd_size; 819 DriveInfo *fd[MAX_FD]; 820 FWCfgState *fw_cfg; 821 DeviceState *dev, *ms_kb_orgate, *serial_orgate; 822 SysBusDevice *s; 823 unsigned int smp_cpus = machine->smp.cpus; 824 unsigned int max_cpus = machine->smp.max_cpus; 825 HostMemoryBackend *ram_memdev = machine->memdev; 826 NICInfo *nd = &nd_table[0]; 827 828 if (machine->ram_size > hwdef->max_mem) { 829 error_report("Too much memory for this machine: %" PRId64 "," 830 " maximum %" PRId64, 831 machine->ram_size / MiB, hwdef->max_mem / MiB); 832 exit(1); 833 } 834 835 /* init CPUs */ 836 for(i = 0; i < smp_cpus; i++) { 837 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); 838 } 839 840 for (i = smp_cpus; i < MAX_CPUS; i++) 841 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 842 843 /* Create and map RAM frontend */ 844 dev = qdev_new("memory"); 845 object_property_set_link(OBJECT(dev), "memdev", OBJECT(ram_memdev), &error_fatal); 846 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 847 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0); 848 849 /* models without ECC don't trap when missing ram is accessed */ 850 if (!hwdef->ecc_base) { 851 empty_slot_init("ecc", machine->ram_size, 852 hwdef->max_mem - machine->ram_size); 853 } 854 855 prom_init(hwdef->slavio_base, machine->firmware); 856 857 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 858 hwdef->intctl_base + 0x10000ULL, 859 cpu_irqs); 860 861 for (i = 0; i < 32; i++) { 862 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 863 } 864 for (i = 0; i < MAX_CPUS; i++) { 865 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 866 } 867 868 if (hwdef->idreg_base) { 869 idreg_init(hwdef->idreg_base); 870 } 871 872 if (hwdef->afx_base) { 873 afx_init(hwdef->afx_base); 874 } 875 876 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]); 877 878 if (hwdef->iommu_pad_base) { 879 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 880 Software shouldn't use aliased addresses, neither should it crash 881 when does. Using empty_slot instead of aliasing can help with 882 debugging such accesses */ 883 empty_slot_init("iommu.alias", 884 hwdef->iommu_pad_base, hwdef->iommu_pad_len); 885 } 886 887 qemu_check_nic_model(nd, TYPE_LANCE); 888 sparc32_dma_init(hwdef->dma_base, 889 hwdef->esp_base, slavio_irq[18], 890 hwdef->le_base, slavio_irq[16], nd); 891 892 if (graphic_depth != 8 && graphic_depth != 24) { 893 error_report("Unsupported depth: %d", graphic_depth); 894 exit (1); 895 } 896 if (vga_interface_type != VGA_NONE) { 897 if (vga_interface_type == VGA_CG3) { 898 if (graphic_depth != 8) { 899 error_report("Unsupported depth: %d", graphic_depth); 900 exit(1); 901 } 902 903 if (!(graphic_width == 1024 && graphic_height == 768) && 904 !(graphic_width == 1152 && graphic_height == 900)) { 905 error_report("Unsupported resolution: %d x %d", graphic_width, 906 graphic_height); 907 exit(1); 908 } 909 910 /* sbus irq 5 */ 911 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 912 graphic_width, graphic_height, graphic_depth); 913 vga_interface_created = true; 914 } else { 915 /* If no display specified, default to TCX */ 916 if (graphic_depth != 8 && graphic_depth != 24) { 917 error_report("Unsupported depth: %d", graphic_depth); 918 exit(1); 919 } 920 921 if (!(graphic_width == 1024 && graphic_height == 768)) { 922 error_report("Unsupported resolution: %d x %d", 923 graphic_width, graphic_height); 924 exit(1); 925 } 926 927 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 928 graphic_width, graphic_height, graphic_depth); 929 vga_interface_created = true; 930 } 931 } 932 933 for (i = 0; i < MAX_VSIMMS; i++) { 934 /* vsimm registers probed by OBP */ 935 if (hwdef->vsimm[i].reg_base) { 936 char *name = g_strdup_printf("vsimm[%d]", i); 937 empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000); 938 g_free(name); 939 } 940 } 941 942 if (hwdef->sx_base) { 943 create_unimplemented_device("sun-sx", hwdef->sx_base, 0x2000); 944 } 945 946 dev = qdev_new("sysbus-m48t08"); 947 qdev_prop_set_int32(dev, "base-year", 1968); 948 s = SYS_BUS_DEVICE(dev); 949 sysbus_realize_and_unref(s, &error_fatal); 950 sysbus_connect_irq(s, 0, slavio_irq[0]); 951 sysbus_mmio_map(s, 0, hwdef->nvram_base); 952 nvram = NVRAM(dev); 953 954 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 955 956 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 957 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 958 dev = qdev_new(TYPE_ESCC); 959 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics); 960 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 961 qdev_prop_set_uint32(dev, "it_shift", 1); 962 qdev_prop_set_chr(dev, "chrB", NULL); 963 qdev_prop_set_chr(dev, "chrA", NULL); 964 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse); 965 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd); 966 s = SYS_BUS_DEVICE(dev); 967 sysbus_realize_and_unref(s, &error_fatal); 968 sysbus_mmio_map(s, 0, hwdef->ms_kb_base); 969 970 /* Logically OR both its IRQs together */ 971 ms_kb_orgate = DEVICE(object_new(TYPE_OR_IRQ)); 972 object_property_set_int(OBJECT(ms_kb_orgate), "num-lines", 2, &error_fatal); 973 qdev_realize_and_unref(ms_kb_orgate, NULL, &error_fatal); 974 sysbus_connect_irq(s, 0, qdev_get_gpio_in(ms_kb_orgate, 0)); 975 sysbus_connect_irq(s, 1, qdev_get_gpio_in(ms_kb_orgate, 1)); 976 qdev_connect_gpio_out(ms_kb_orgate, 0, slavio_irq[14]); 977 978 dev = qdev_new(TYPE_ESCC); 979 qdev_prop_set_uint32(dev, "disabled", 0); 980 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 981 qdev_prop_set_uint32(dev, "it_shift", 1); 982 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 983 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 984 qdev_prop_set_uint32(dev, "chnBtype", escc_serial); 985 qdev_prop_set_uint32(dev, "chnAtype", escc_serial); 986 987 s = SYS_BUS_DEVICE(dev); 988 sysbus_realize_and_unref(s, &error_fatal); 989 sysbus_mmio_map(s, 0, hwdef->serial_base); 990 991 /* Logically OR both its IRQs together */ 992 serial_orgate = DEVICE(object_new(TYPE_OR_IRQ)); 993 object_property_set_int(OBJECT(serial_orgate), "num-lines", 2, 994 &error_fatal); 995 qdev_realize_and_unref(serial_orgate, NULL, &error_fatal); 996 sysbus_connect_irq(s, 0, qdev_get_gpio_in(serial_orgate, 0)); 997 sysbus_connect_irq(s, 1, qdev_get_gpio_in(serial_orgate, 1)); 998 qdev_connect_gpio_out(serial_orgate, 0, slavio_irq[15]); 999 1000 if (hwdef->apc_base) { 1001 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); 1002 } 1003 1004 if (hwdef->fd_base) { 1005 /* there is zero or one floppy drive */ 1006 memset(fd, 0, sizeof(fd)); 1007 fd[0] = drive_get(IF_FLOPPY, 0, 0); 1008 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 1009 &fdc_tc); 1010 } else { 1011 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); 1012 } 1013 1014 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 1015 slavio_irq[30], fdc_tc); 1016 1017 if (hwdef->cs_base) { 1018 sysbus_create_simple("sun-CS4231", hwdef->cs_base, 1019 slavio_irq[5]); 1020 } 1021 1022 if (hwdef->dbri_base) { 1023 /* ISDN chip with attached CS4215 audio codec */ 1024 /* prom space */ 1025 create_unimplemented_device("sun-DBRI.prom", 1026 hwdef->dbri_base + 0x1000, 0x30); 1027 /* reg space */ 1028 create_unimplemented_device("sun-DBRI", 1029 hwdef->dbri_base + 0x10000, 0x100); 1030 } 1031 1032 if (hwdef->bpp_base) { 1033 /* parallel port */ 1034 create_unimplemented_device("sun-bpp", hwdef->bpp_base, 0x20); 1035 } 1036 1037 initrd_size = 0; 1038 kernel_size = sun4m_load_kernel(machine->kernel_filename, 1039 machine->initrd_filename, 1040 machine->ram_size, &initrd_size); 1041 1042 nvram_init(nvram, (uint8_t *)&nd->macaddr, machine->kernel_cmdline, 1043 machine->boot_config.order, machine->ram_size, kernel_size, 1044 graphic_width, graphic_height, graphic_depth, 1045 hwdef->nvram_machine_id, "Sun4m"); 1046 1047 if (hwdef->ecc_base) 1048 ecc_init(hwdef->ecc_base, slavio_irq[28], 1049 hwdef->ecc_version); 1050 1051 dev = qdev_new(TYPE_FW_CFG_MEM); 1052 fw_cfg = FW_CFG(dev); 1053 qdev_prop_set_uint32(dev, "data_width", 1); 1054 qdev_prop_set_bit(dev, "dma_enabled", false); 1055 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1056 OBJECT(fw_cfg)); 1057 s = SYS_BUS_DEVICE(dev); 1058 sysbus_realize_and_unref(s, &error_fatal); 1059 sysbus_mmio_map(s, 0, CFG_ADDR); 1060 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 1061 1062 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 1063 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1064 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 1065 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1066 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1067 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1068 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1069 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1070 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1071 if (machine->kernel_cmdline) { 1072 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1073 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1074 machine->kernel_cmdline); 1075 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 1076 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1077 strlen(machine->kernel_cmdline) + 1); 1078 } else { 1079 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1080 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1081 } 1082 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1083 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1084 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_config.order[0]); 1085 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1086 } 1087 1088 enum { 1089 ss5_id = 32, 1090 vger_id, 1091 lx_id, 1092 ss4_id, 1093 scls_id, 1094 sbook_id, 1095 ss10_id = 64, 1096 ss20_id, 1097 ss600mp_id, 1098 }; 1099 1100 static void sun4m_machine_class_init(ObjectClass *oc, void *data) 1101 { 1102 MachineClass *mc = MACHINE_CLASS(oc); 1103 1104 mc->init = sun4m_hw_init; 1105 mc->block_default_type = IF_SCSI; 1106 mc->default_boot_order = "c"; 1107 mc->default_display = "tcx"; 1108 mc->default_ram_id = "sun4m.ram"; 1109 } 1110 1111 static void ss5_class_init(ObjectClass *oc, void *data) 1112 { 1113 MachineClass *mc = MACHINE_CLASS(oc); 1114 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1115 static const struct sun4m_hwdef ss5_hwdef = { 1116 .iommu_base = 0x10000000, 1117 .iommu_pad_base = 0x10004000, 1118 .iommu_pad_len = 0x0fffb000, 1119 .tcx_base = 0x50000000, 1120 .cs_base = 0x6c000000, 1121 .slavio_base = 0x70000000, 1122 .ms_kb_base = 0x71000000, 1123 .serial_base = 0x71100000, 1124 .nvram_base = 0x71200000, 1125 .fd_base = 0x71400000, 1126 .counter_base = 0x71d00000, 1127 .intctl_base = 0x71e00000, 1128 .idreg_base = 0x78000000, 1129 .dma_base = 0x78400000, 1130 .esp_base = 0x78800000, 1131 .le_base = 0x78c00000, 1132 .apc_base = 0x6a000000, 1133 .afx_base = 0x6e000000, 1134 .aux1_base = 0x71900000, 1135 .aux2_base = 0x71910000, 1136 .nvram_machine_id = 0x80, 1137 .machine_id = ss5_id, 1138 .iommu_version = 0x05000000, 1139 .max_mem = 0x10000000, 1140 }; 1141 1142 mc->desc = "Sun4m platform, SPARCstation 5"; 1143 mc->is_default = true; 1144 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1145 smc->hwdef = &ss5_hwdef; 1146 } 1147 1148 static void ss10_class_init(ObjectClass *oc, void *data) 1149 { 1150 MachineClass *mc = MACHINE_CLASS(oc); 1151 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1152 static const struct sun4m_hwdef ss10_hwdef = { 1153 .iommu_base = 0xfe0000000ULL, 1154 .tcx_base = 0xe20000000ULL, 1155 .slavio_base = 0xff0000000ULL, 1156 .ms_kb_base = 0xff1000000ULL, 1157 .serial_base = 0xff1100000ULL, 1158 .nvram_base = 0xff1200000ULL, 1159 .fd_base = 0xff1700000ULL, 1160 .counter_base = 0xff1300000ULL, 1161 .intctl_base = 0xff1400000ULL, 1162 .idreg_base = 0xef0000000ULL, 1163 .dma_base = 0xef0400000ULL, 1164 .esp_base = 0xef0800000ULL, 1165 .le_base = 0xef0c00000ULL, 1166 .apc_base = 0xefa000000ULL, /* XXX should not exist */ 1167 .aux1_base = 0xff1800000ULL, 1168 .aux2_base = 0xff1a01000ULL, 1169 .ecc_base = 0xf00000000ULL, 1170 .ecc_version = 0x10000000, /* version 0, implementation 1 */ 1171 .nvram_machine_id = 0x72, 1172 .machine_id = ss10_id, 1173 .iommu_version = 0x03000000, 1174 .max_mem = 0xf00000000ULL, 1175 }; 1176 1177 mc->desc = "Sun4m platform, SPARCstation 10"; 1178 mc->max_cpus = 4; 1179 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1180 smc->hwdef = &ss10_hwdef; 1181 } 1182 1183 static void ss600mp_class_init(ObjectClass *oc, void *data) 1184 { 1185 MachineClass *mc = MACHINE_CLASS(oc); 1186 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1187 static const struct sun4m_hwdef ss600mp_hwdef = { 1188 .iommu_base = 0xfe0000000ULL, 1189 .tcx_base = 0xe20000000ULL, 1190 .slavio_base = 0xff0000000ULL, 1191 .ms_kb_base = 0xff1000000ULL, 1192 .serial_base = 0xff1100000ULL, 1193 .nvram_base = 0xff1200000ULL, 1194 .counter_base = 0xff1300000ULL, 1195 .intctl_base = 0xff1400000ULL, 1196 .dma_base = 0xef0081000ULL, 1197 .esp_base = 0xef0080000ULL, 1198 .le_base = 0xef0060000ULL, 1199 .apc_base = 0xefa000000ULL, /* XXX should not exist */ 1200 .aux1_base = 0xff1800000ULL, 1201 .aux2_base = 0xff1a01000ULL, /* XXX should not exist */ 1202 .ecc_base = 0xf00000000ULL, 1203 .ecc_version = 0x00000000, /* version 0, implementation 0 */ 1204 .nvram_machine_id = 0x71, 1205 .machine_id = ss600mp_id, 1206 .iommu_version = 0x01000000, 1207 .max_mem = 0xf00000000ULL, 1208 }; 1209 1210 mc->desc = "Sun4m platform, SPARCserver 600MP"; 1211 mc->max_cpus = 4; 1212 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1213 smc->hwdef = &ss600mp_hwdef; 1214 } 1215 1216 static void ss20_class_init(ObjectClass *oc, void *data) 1217 { 1218 MachineClass *mc = MACHINE_CLASS(oc); 1219 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1220 static const struct sun4m_hwdef ss20_hwdef = { 1221 .iommu_base = 0xfe0000000ULL, 1222 .tcx_base = 0xe20000000ULL, 1223 .slavio_base = 0xff0000000ULL, 1224 .ms_kb_base = 0xff1000000ULL, 1225 .serial_base = 0xff1100000ULL, 1226 .nvram_base = 0xff1200000ULL, 1227 .fd_base = 0xff1700000ULL, 1228 .counter_base = 0xff1300000ULL, 1229 .intctl_base = 0xff1400000ULL, 1230 .idreg_base = 0xef0000000ULL, 1231 .dma_base = 0xef0400000ULL, 1232 .esp_base = 0xef0800000ULL, 1233 .le_base = 0xef0c00000ULL, 1234 .bpp_base = 0xef4800000ULL, 1235 .apc_base = 0xefa000000ULL, /* XXX should not exist */ 1236 .aux1_base = 0xff1800000ULL, 1237 .aux2_base = 0xff1a01000ULL, 1238 .dbri_base = 0xee0000000ULL, 1239 .sx_base = 0xf80000000ULL, 1240 .vsimm = { 1241 { 1242 .reg_base = 0x9c000000ULL, 1243 .vram_base = 0xfc000000ULL 1244 }, { 1245 .reg_base = 0x90000000ULL, 1246 .vram_base = 0xf0000000ULL 1247 }, { 1248 .reg_base = 0x94000000ULL 1249 }, { 1250 .reg_base = 0x98000000ULL 1251 } 1252 }, 1253 .ecc_base = 0xf00000000ULL, 1254 .ecc_version = 0x20000000, /* version 0, implementation 2 */ 1255 .nvram_machine_id = 0x72, 1256 .machine_id = ss20_id, 1257 .iommu_version = 0x13000000, 1258 .max_mem = 0xf00000000ULL, 1259 }; 1260 1261 mc->desc = "Sun4m platform, SPARCstation 20"; 1262 mc->max_cpus = 4; 1263 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1264 smc->hwdef = &ss20_hwdef; 1265 } 1266 1267 static void voyager_class_init(ObjectClass *oc, void *data) 1268 { 1269 MachineClass *mc = MACHINE_CLASS(oc); 1270 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1271 static const struct sun4m_hwdef voyager_hwdef = { 1272 .iommu_base = 0x10000000, 1273 .tcx_base = 0x50000000, 1274 .slavio_base = 0x70000000, 1275 .ms_kb_base = 0x71000000, 1276 .serial_base = 0x71100000, 1277 .nvram_base = 0x71200000, 1278 .fd_base = 0x71400000, 1279 .counter_base = 0x71d00000, 1280 .intctl_base = 0x71e00000, 1281 .idreg_base = 0x78000000, 1282 .dma_base = 0x78400000, 1283 .esp_base = 0x78800000, 1284 .le_base = 0x78c00000, 1285 .apc_base = 0x71300000, /* pmc */ 1286 .aux1_base = 0x71900000, 1287 .aux2_base = 0x71910000, 1288 .nvram_machine_id = 0x80, 1289 .machine_id = vger_id, 1290 .iommu_version = 0x05000000, 1291 .max_mem = 0x10000000, 1292 }; 1293 1294 mc->desc = "Sun4m platform, SPARCstation Voyager"; 1295 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1296 smc->hwdef = &voyager_hwdef; 1297 } 1298 1299 static void ss_lx_class_init(ObjectClass *oc, void *data) 1300 { 1301 MachineClass *mc = MACHINE_CLASS(oc); 1302 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1303 static const struct sun4m_hwdef ss_lx_hwdef = { 1304 .iommu_base = 0x10000000, 1305 .iommu_pad_base = 0x10004000, 1306 .iommu_pad_len = 0x0fffb000, 1307 .tcx_base = 0x50000000, 1308 .slavio_base = 0x70000000, 1309 .ms_kb_base = 0x71000000, 1310 .serial_base = 0x71100000, 1311 .nvram_base = 0x71200000, 1312 .fd_base = 0x71400000, 1313 .counter_base = 0x71d00000, 1314 .intctl_base = 0x71e00000, 1315 .idreg_base = 0x78000000, 1316 .dma_base = 0x78400000, 1317 .esp_base = 0x78800000, 1318 .le_base = 0x78c00000, 1319 .aux1_base = 0x71900000, 1320 .aux2_base = 0x71910000, 1321 .nvram_machine_id = 0x80, 1322 .machine_id = lx_id, 1323 .iommu_version = 0x04000000, 1324 .max_mem = 0x10000000, 1325 }; 1326 1327 mc->desc = "Sun4m platform, SPARCstation LX"; 1328 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1329 smc->hwdef = &ss_lx_hwdef; 1330 } 1331 1332 static void ss4_class_init(ObjectClass *oc, void *data) 1333 { 1334 MachineClass *mc = MACHINE_CLASS(oc); 1335 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1336 static const struct sun4m_hwdef ss4_hwdef = { 1337 .iommu_base = 0x10000000, 1338 .tcx_base = 0x50000000, 1339 .cs_base = 0x6c000000, 1340 .slavio_base = 0x70000000, 1341 .ms_kb_base = 0x71000000, 1342 .serial_base = 0x71100000, 1343 .nvram_base = 0x71200000, 1344 .fd_base = 0x71400000, 1345 .counter_base = 0x71d00000, 1346 .intctl_base = 0x71e00000, 1347 .idreg_base = 0x78000000, 1348 .dma_base = 0x78400000, 1349 .esp_base = 0x78800000, 1350 .le_base = 0x78c00000, 1351 .apc_base = 0x6a000000, 1352 .aux1_base = 0x71900000, 1353 .aux2_base = 0x71910000, 1354 .nvram_machine_id = 0x80, 1355 .machine_id = ss4_id, 1356 .iommu_version = 0x05000000, 1357 .max_mem = 0x10000000, 1358 }; 1359 1360 mc->desc = "Sun4m platform, SPARCstation 4"; 1361 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1362 smc->hwdef = &ss4_hwdef; 1363 } 1364 1365 static void scls_class_init(ObjectClass *oc, void *data) 1366 { 1367 MachineClass *mc = MACHINE_CLASS(oc); 1368 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1369 static const struct sun4m_hwdef scls_hwdef = { 1370 .iommu_base = 0x10000000, 1371 .tcx_base = 0x50000000, 1372 .slavio_base = 0x70000000, 1373 .ms_kb_base = 0x71000000, 1374 .serial_base = 0x71100000, 1375 .nvram_base = 0x71200000, 1376 .fd_base = 0x71400000, 1377 .counter_base = 0x71d00000, 1378 .intctl_base = 0x71e00000, 1379 .idreg_base = 0x78000000, 1380 .dma_base = 0x78400000, 1381 .esp_base = 0x78800000, 1382 .le_base = 0x78c00000, 1383 .apc_base = 0x6a000000, 1384 .aux1_base = 0x71900000, 1385 .aux2_base = 0x71910000, 1386 .nvram_machine_id = 0x80, 1387 .machine_id = scls_id, 1388 .iommu_version = 0x05000000, 1389 .max_mem = 0x10000000, 1390 }; 1391 1392 mc->desc = "Sun4m platform, SPARCClassic"; 1393 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1394 smc->hwdef = &scls_hwdef; 1395 } 1396 1397 static void sbook_class_init(ObjectClass *oc, void *data) 1398 { 1399 MachineClass *mc = MACHINE_CLASS(oc); 1400 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1401 static const struct sun4m_hwdef sbook_hwdef = { 1402 .iommu_base = 0x10000000, 1403 .tcx_base = 0x50000000, /* XXX */ 1404 .slavio_base = 0x70000000, 1405 .ms_kb_base = 0x71000000, 1406 .serial_base = 0x71100000, 1407 .nvram_base = 0x71200000, 1408 .fd_base = 0x71400000, 1409 .counter_base = 0x71d00000, 1410 .intctl_base = 0x71e00000, 1411 .idreg_base = 0x78000000, 1412 .dma_base = 0x78400000, 1413 .esp_base = 0x78800000, 1414 .le_base = 0x78c00000, 1415 .apc_base = 0x6a000000, 1416 .aux1_base = 0x71900000, 1417 .aux2_base = 0x71910000, 1418 .nvram_machine_id = 0x80, 1419 .machine_id = sbook_id, 1420 .iommu_version = 0x05000000, 1421 .max_mem = 0x10000000, 1422 }; 1423 1424 mc->desc = "Sun4m platform, SPARCbook"; 1425 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1426 smc->hwdef = &sbook_hwdef; 1427 } 1428 1429 static const TypeInfo sun4m_machine_types[] = { 1430 { 1431 .name = MACHINE_TYPE_NAME("SS-5"), 1432 .parent = TYPE_SUN4M_MACHINE, 1433 .class_init = ss5_class_init, 1434 }, { 1435 .name = MACHINE_TYPE_NAME("SS-10"), 1436 .parent = TYPE_SUN4M_MACHINE, 1437 .class_init = ss10_class_init, 1438 }, { 1439 .name = MACHINE_TYPE_NAME("SS-600MP"), 1440 .parent = TYPE_SUN4M_MACHINE, 1441 .class_init = ss600mp_class_init, 1442 }, { 1443 .name = MACHINE_TYPE_NAME("SS-20"), 1444 .parent = TYPE_SUN4M_MACHINE, 1445 .class_init = ss20_class_init, 1446 }, { 1447 .name = MACHINE_TYPE_NAME("Voyager"), 1448 .parent = TYPE_SUN4M_MACHINE, 1449 .class_init = voyager_class_init, 1450 }, { 1451 .name = MACHINE_TYPE_NAME("LX"), 1452 .parent = TYPE_SUN4M_MACHINE, 1453 .class_init = ss_lx_class_init, 1454 }, { 1455 .name = MACHINE_TYPE_NAME("SS-4"), 1456 .parent = TYPE_SUN4M_MACHINE, 1457 .class_init = ss4_class_init, 1458 }, { 1459 .name = MACHINE_TYPE_NAME("SPARCClassic"), 1460 .parent = TYPE_SUN4M_MACHINE, 1461 .class_init = scls_class_init, 1462 }, { 1463 .name = MACHINE_TYPE_NAME("SPARCbook"), 1464 .parent = TYPE_SUN4M_MACHINE, 1465 .class_init = sbook_class_init, 1466 }, { 1467 .name = TYPE_SUN4M_MACHINE, 1468 .parent = TYPE_MACHINE, 1469 .class_size = sizeof(Sun4mMachineClass), 1470 .class_init = sun4m_machine_class_init, 1471 .abstract = true, 1472 } 1473 }; 1474 1475 DEFINE_TYPES(sun4m_machine_types) 1476 1477 static void sun4m_register_types(void) 1478 { 1479 type_register_static(&idreg_info); 1480 type_register_static(&afx_info); 1481 type_register_static(&prom_info); 1482 type_register_static(&ram_info); 1483 } 1484 1485 type_init(sun4m_register_types) 1486