1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qemu/units.h" 26 #include "qapi/error.h" 27 #include "qemu-common.h" 28 #include "cpu.h" 29 #include "hw/sysbus.h" 30 #include "qemu/error-report.h" 31 #include "qemu/timer.h" 32 #include "hw/sparc/sun4m_iommu.h" 33 #include "hw/timer/m48t59.h" 34 #include "hw/sparc/sparc32_dma.h" 35 #include "hw/block/fdc.h" 36 #include "sysemu/sysemu.h" 37 #include "net/net.h" 38 #include "hw/boards.h" 39 #include "hw/scsi/esp.h" 40 #include "hw/nvram/sun_nvram.h" 41 #include "hw/nvram/chrp_nvram.h" 42 #include "hw/nvram/fw_cfg.h" 43 #include "hw/char/escc.h" 44 #include "hw/empty_slot.h" 45 #include "hw/loader.h" 46 #include "elf.h" 47 #include "trace.h" 48 49 /* 50 * Sun4m architecture was used in the following machines: 51 * 52 * SPARCserver 6xxMP/xx 53 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 54 * SPARCclassic X (4/10) 55 * SPARCstation LX/ZX (4/30) 56 * SPARCstation Voyager 57 * SPARCstation 10/xx, SPARCserver 10/xx 58 * SPARCstation 5, SPARCserver 5 59 * SPARCstation 20/xx, SPARCserver 20 60 * SPARCstation 4 61 * 62 * See for example: http://www.sunhelp.org/faq/sunref1.html 63 */ 64 65 #define KERNEL_LOAD_ADDR 0x00004000 66 #define CMDLINE_ADDR 0x007ff000 67 #define INITRD_LOAD_ADDR 0x00800000 68 #define PROM_SIZE_MAX (1 * MiB) 69 #define PROM_VADDR 0xffd00000 70 #define PROM_FILENAME "openbios-sparc32" 71 #define CFG_ADDR 0xd00000510ULL 72 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 73 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 74 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 75 76 #define MAX_CPUS 16 77 #define MAX_PILS 16 78 #define MAX_VSIMMS 4 79 80 #define ESCC_CLOCK 4915200 81 82 struct sun4m_hwdef { 83 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 84 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 85 hwaddr serial_base, fd_base; 86 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 87 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 88 hwaddr bpp_base, dbri_base, sx_base; 89 struct { 90 hwaddr reg_base, vram_base; 91 } vsimm[MAX_VSIMMS]; 92 hwaddr ecc_base; 93 uint64_t max_mem; 94 uint32_t ecc_version; 95 uint32_t iommu_version; 96 uint16_t machine_id; 97 uint8_t nvram_machine_id; 98 }; 99 100 const char *fw_cfg_arch_key_name(uint16_t key) 101 { 102 static const struct { 103 uint16_t key; 104 const char *name; 105 } fw_cfg_arch_wellknown_keys[] = { 106 {FW_CFG_SUN4M_DEPTH, "depth"}, 107 {FW_CFG_SUN4M_WIDTH, "width"}, 108 {FW_CFG_SUN4M_HEIGHT, "height"}, 109 }; 110 111 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { 112 if (fw_cfg_arch_wellknown_keys[i].key == key) { 113 return fw_cfg_arch_wellknown_keys[i].name; 114 } 115 } 116 return NULL; 117 } 118 119 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 120 Error **errp) 121 { 122 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 123 } 124 125 static void nvram_init(Nvram *nvram, uint8_t *macaddr, 126 const char *cmdline, const char *boot_devices, 127 ram_addr_t RAM_size, uint32_t kernel_size, 128 int width, int height, int depth, 129 int nvram_machine_id, const char *arch) 130 { 131 unsigned int i; 132 int sysp_end; 133 uint8_t image[0x1ff0]; 134 NvramClass *k = NVRAM_GET_CLASS(nvram); 135 136 memset(image, '\0', sizeof(image)); 137 138 /* OpenBIOS nvram variables partition */ 139 sysp_end = chrp_nvram_create_system_partition(image, 0); 140 141 /* Free space partition */ 142 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 143 144 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 145 nvram_machine_id); 146 147 for (i = 0; i < sizeof(image); i++) { 148 (k->write)(nvram, i, image[i]); 149 } 150 } 151 152 void cpu_check_irqs(CPUSPARCState *env) 153 { 154 CPUState *cs; 155 156 /* We should be holding the BQL before we mess with IRQs */ 157 g_assert(qemu_mutex_iothread_locked()); 158 159 if (env->pil_in && (env->interrupt_index == 0 || 160 (env->interrupt_index & ~15) == TT_EXTINT)) { 161 unsigned int i; 162 163 for (i = 15; i > 0; i--) { 164 if (env->pil_in & (1 << i)) { 165 int old_interrupt = env->interrupt_index; 166 167 env->interrupt_index = TT_EXTINT | i; 168 if (old_interrupt != env->interrupt_index) { 169 cs = env_cpu(env); 170 trace_sun4m_cpu_interrupt(i); 171 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 172 } 173 break; 174 } 175 } 176 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 177 cs = env_cpu(env); 178 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 179 env->interrupt_index = 0; 180 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 181 } 182 } 183 184 static void cpu_kick_irq(SPARCCPU *cpu) 185 { 186 CPUSPARCState *env = &cpu->env; 187 CPUState *cs = CPU(cpu); 188 189 cs->halted = 0; 190 cpu_check_irqs(env); 191 qemu_cpu_kick(cs); 192 } 193 194 static void cpu_set_irq(void *opaque, int irq, int level) 195 { 196 SPARCCPU *cpu = opaque; 197 CPUSPARCState *env = &cpu->env; 198 199 if (level) { 200 trace_sun4m_cpu_set_irq_raise(irq); 201 env->pil_in |= 1 << irq; 202 cpu_kick_irq(cpu); 203 } else { 204 trace_sun4m_cpu_set_irq_lower(irq); 205 env->pil_in &= ~(1 << irq); 206 cpu_check_irqs(env); 207 } 208 } 209 210 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 211 { 212 } 213 214 static void main_cpu_reset(void *opaque) 215 { 216 SPARCCPU *cpu = opaque; 217 CPUState *cs = CPU(cpu); 218 219 cpu_reset(cs); 220 cs->halted = 0; 221 } 222 223 static void secondary_cpu_reset(void *opaque) 224 { 225 SPARCCPU *cpu = opaque; 226 CPUState *cs = CPU(cpu); 227 228 cpu_reset(cs); 229 cs->halted = 1; 230 } 231 232 static void cpu_halt_signal(void *opaque, int irq, int level) 233 { 234 if (level && current_cpu) { 235 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 236 } 237 } 238 239 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 240 { 241 return addr - 0xf0000000ULL; 242 } 243 244 static unsigned long sun4m_load_kernel(const char *kernel_filename, 245 const char *initrd_filename, 246 ram_addr_t RAM_size, 247 uint32_t *initrd_size) 248 { 249 int linux_boot; 250 unsigned int i; 251 long kernel_size; 252 uint8_t *ptr; 253 254 linux_boot = (kernel_filename != NULL); 255 256 kernel_size = 0; 257 if (linux_boot) { 258 int bswap_needed; 259 260 #ifdef BSWAP_NEEDED 261 bswap_needed = 1; 262 #else 263 bswap_needed = 0; 264 #endif 265 kernel_size = load_elf(kernel_filename, NULL, 266 translate_kernel_address, NULL, 267 NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 268 if (kernel_size < 0) 269 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 270 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 271 TARGET_PAGE_SIZE); 272 if (kernel_size < 0) 273 kernel_size = load_image_targphys(kernel_filename, 274 KERNEL_LOAD_ADDR, 275 RAM_size - KERNEL_LOAD_ADDR); 276 if (kernel_size < 0) { 277 error_report("could not load kernel '%s'", kernel_filename); 278 exit(1); 279 } 280 281 /* load initrd */ 282 *initrd_size = 0; 283 if (initrd_filename) { 284 *initrd_size = load_image_targphys(initrd_filename, 285 INITRD_LOAD_ADDR, 286 RAM_size - INITRD_LOAD_ADDR); 287 if ((int)*initrd_size < 0) { 288 error_report("could not load initial ram disk '%s'", 289 initrd_filename); 290 exit(1); 291 } 292 } 293 if (*initrd_size > 0) { 294 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 295 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24); 296 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */ 297 stl_p(ptr + 16, INITRD_LOAD_ADDR); 298 stl_p(ptr + 20, *initrd_size); 299 break; 300 } 301 } 302 } 303 } 304 return kernel_size; 305 } 306 307 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 308 { 309 DeviceState *dev; 310 SysBusDevice *s; 311 312 dev = qdev_create(NULL, TYPE_SUN4M_IOMMU); 313 qdev_prop_set_uint32(dev, "version", version); 314 qdev_init_nofail(dev); 315 s = SYS_BUS_DEVICE(dev); 316 sysbus_connect_irq(s, 0, irq); 317 sysbus_mmio_map(s, 0, addr); 318 319 return s; 320 } 321 322 static void *sparc32_dma_init(hwaddr dma_base, 323 hwaddr esp_base, qemu_irq espdma_irq, 324 hwaddr le_base, qemu_irq ledma_irq) 325 { 326 DeviceState *dma; 327 ESPDMADeviceState *espdma; 328 LEDMADeviceState *ledma; 329 SysBusESPState *esp; 330 SysBusPCNetState *lance; 331 332 dma = qdev_create(NULL, TYPE_SPARC32_DMA); 333 qdev_init_nofail(dma); 334 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); 335 336 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( 337 OBJECT(dma), "espdma")); 338 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); 339 340 esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp")); 341 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base); 342 scsi_bus_legacy_handle_cmdline(&esp->esp.bus); 343 344 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( 345 OBJECT(dma), "ledma")); 346 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq); 347 348 lance = SYSBUS_PCNET(object_resolve_path_component( 349 OBJECT(ledma), "lance")); 350 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base); 351 352 return dma; 353 } 354 355 static DeviceState *slavio_intctl_init(hwaddr addr, 356 hwaddr addrg, 357 qemu_irq **parent_irq) 358 { 359 DeviceState *dev; 360 SysBusDevice *s; 361 unsigned int i, j; 362 363 dev = qdev_create(NULL, "slavio_intctl"); 364 qdev_init_nofail(dev); 365 366 s = SYS_BUS_DEVICE(dev); 367 368 for (i = 0; i < MAX_CPUS; i++) { 369 for (j = 0; j < MAX_PILS; j++) { 370 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 371 } 372 } 373 sysbus_mmio_map(s, 0, addrg); 374 for (i = 0; i < MAX_CPUS; i++) { 375 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 376 } 377 378 return dev; 379 } 380 381 #define SYS_TIMER_OFFSET 0x10000ULL 382 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 383 384 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 385 qemu_irq *cpu_irqs, unsigned int num_cpus) 386 { 387 DeviceState *dev; 388 SysBusDevice *s; 389 unsigned int i; 390 391 dev = qdev_create(NULL, "slavio_timer"); 392 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 393 qdev_init_nofail(dev); 394 s = SYS_BUS_DEVICE(dev); 395 sysbus_connect_irq(s, 0, master_irq); 396 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 397 398 for (i = 0; i < MAX_CPUS; i++) { 399 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 400 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 401 } 402 } 403 404 static qemu_irq slavio_system_powerdown; 405 406 static void slavio_powerdown_req(Notifier *n, void *opaque) 407 { 408 qemu_irq_raise(slavio_system_powerdown); 409 } 410 411 static Notifier slavio_system_powerdown_notifier = { 412 .notify = slavio_powerdown_req 413 }; 414 415 #define MISC_LEDS 0x01600000 416 #define MISC_CFG 0x01800000 417 #define MISC_DIAG 0x01a00000 418 #define MISC_MDM 0x01b00000 419 #define MISC_SYS 0x01f00000 420 421 static void slavio_misc_init(hwaddr base, 422 hwaddr aux1_base, 423 hwaddr aux2_base, qemu_irq irq, 424 qemu_irq fdc_tc) 425 { 426 DeviceState *dev; 427 SysBusDevice *s; 428 429 dev = qdev_create(NULL, "slavio_misc"); 430 qdev_init_nofail(dev); 431 s = SYS_BUS_DEVICE(dev); 432 if (base) { 433 /* 8 bit registers */ 434 /* Slavio control */ 435 sysbus_mmio_map(s, 0, base + MISC_CFG); 436 /* Diagnostics */ 437 sysbus_mmio_map(s, 1, base + MISC_DIAG); 438 /* Modem control */ 439 sysbus_mmio_map(s, 2, base + MISC_MDM); 440 /* 16 bit registers */ 441 /* ss600mp diag LEDs */ 442 sysbus_mmio_map(s, 3, base + MISC_LEDS); 443 /* 32 bit registers */ 444 /* System control */ 445 sysbus_mmio_map(s, 4, base + MISC_SYS); 446 } 447 if (aux1_base) { 448 /* AUX 1 (Misc System Functions) */ 449 sysbus_mmio_map(s, 5, aux1_base); 450 } 451 if (aux2_base) { 452 /* AUX 2 (Software Powerdown Control) */ 453 sysbus_mmio_map(s, 6, aux2_base); 454 } 455 sysbus_connect_irq(s, 0, irq); 456 sysbus_connect_irq(s, 1, fdc_tc); 457 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 458 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 459 } 460 461 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 462 { 463 DeviceState *dev; 464 SysBusDevice *s; 465 466 dev = qdev_create(NULL, "eccmemctl"); 467 qdev_prop_set_uint32(dev, "version", version); 468 qdev_init_nofail(dev); 469 s = SYS_BUS_DEVICE(dev); 470 sysbus_connect_irq(s, 0, irq); 471 sysbus_mmio_map(s, 0, base); 472 if (version == 0) { // SS-600MP only 473 sysbus_mmio_map(s, 1, base + 0x1000); 474 } 475 } 476 477 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 478 { 479 DeviceState *dev; 480 SysBusDevice *s; 481 482 dev = qdev_create(NULL, "apc"); 483 qdev_init_nofail(dev); 484 s = SYS_BUS_DEVICE(dev); 485 /* Power management (APC) XXX: not a Slavio device */ 486 sysbus_mmio_map(s, 0, power_base); 487 sysbus_connect_irq(s, 0, cpu_halt); 488 } 489 490 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 491 int height, int depth) 492 { 493 DeviceState *dev; 494 SysBusDevice *s; 495 496 dev = qdev_create(NULL, "SUNW,tcx"); 497 qdev_prop_set_uint32(dev, "vram_size", vram_size); 498 qdev_prop_set_uint16(dev, "width", width); 499 qdev_prop_set_uint16(dev, "height", height); 500 qdev_prop_set_uint16(dev, "depth", depth); 501 qdev_init_nofail(dev); 502 s = SYS_BUS_DEVICE(dev); 503 504 /* 10/ROM : FCode ROM */ 505 sysbus_mmio_map(s, 0, addr); 506 /* 2/STIP : Stipple */ 507 sysbus_mmio_map(s, 1, addr + 0x04000000ULL); 508 /* 3/BLIT : Blitter */ 509 sysbus_mmio_map(s, 2, addr + 0x06000000ULL); 510 /* 5/RSTIP : Raw Stipple */ 511 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); 512 /* 6/RBLIT : Raw Blitter */ 513 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); 514 /* 7/TEC : Transform Engine */ 515 sysbus_mmio_map(s, 5, addr + 0x00700000ULL); 516 /* 8/CMAP : DAC */ 517 sysbus_mmio_map(s, 6, addr + 0x00200000ULL); 518 /* 9/THC : */ 519 if (depth == 8) { 520 sysbus_mmio_map(s, 7, addr + 0x00300000ULL); 521 } else { 522 sysbus_mmio_map(s, 7, addr + 0x00301000ULL); 523 } 524 /* 11/DHC : */ 525 sysbus_mmio_map(s, 8, addr + 0x00240000ULL); 526 /* 12/ALT : */ 527 sysbus_mmio_map(s, 9, addr + 0x00280000ULL); 528 /* 0/DFB8 : 8-bit plane */ 529 sysbus_mmio_map(s, 10, addr + 0x00800000ULL); 530 /* 1/DFB24 : 24bit plane */ 531 sysbus_mmio_map(s, 11, addr + 0x02000000ULL); 532 /* 4/RDFB32: Raw framebuffer. Control plane */ 533 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); 534 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 535 if (depth == 8) { 536 sysbus_mmio_map(s, 13, addr + 0x00301000ULL); 537 } 538 539 sysbus_connect_irq(s, 0, irq); 540 } 541 542 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 543 int height, int depth) 544 { 545 DeviceState *dev; 546 SysBusDevice *s; 547 548 dev = qdev_create(NULL, "cgthree"); 549 qdev_prop_set_uint32(dev, "vram-size", vram_size); 550 qdev_prop_set_uint16(dev, "width", width); 551 qdev_prop_set_uint16(dev, "height", height); 552 qdev_prop_set_uint16(dev, "depth", depth); 553 qdev_init_nofail(dev); 554 s = SYS_BUS_DEVICE(dev); 555 556 /* FCode ROM */ 557 sysbus_mmio_map(s, 0, addr); 558 /* DAC */ 559 sysbus_mmio_map(s, 1, addr + 0x400000ULL); 560 /* 8-bit plane */ 561 sysbus_mmio_map(s, 2, addr + 0x800000ULL); 562 563 sysbus_connect_irq(s, 0, irq); 564 } 565 566 /* NCR89C100/MACIO Internal ID register */ 567 568 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 569 570 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 571 572 static void idreg_init(hwaddr addr) 573 { 574 DeviceState *dev; 575 SysBusDevice *s; 576 577 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER); 578 qdev_init_nofail(dev); 579 s = SYS_BUS_DEVICE(dev); 580 581 sysbus_mmio_map(s, 0, addr); 582 address_space_write_rom(&address_space_memory, addr, 583 MEMTXATTRS_UNSPECIFIED, 584 idreg_data, sizeof(idreg_data)); 585 } 586 587 #define MACIO_ID_REGISTER(obj) \ 588 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER) 589 590 typedef struct IDRegState { 591 SysBusDevice parent_obj; 592 593 MemoryRegion mem; 594 } IDRegState; 595 596 static void idreg_realize(DeviceState *ds, Error **errp) 597 { 598 IDRegState *s = MACIO_ID_REGISTER(ds); 599 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 600 Error *local_err = NULL; 601 602 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg", 603 sizeof(idreg_data), &local_err); 604 if (local_err) { 605 error_propagate(errp, local_err); 606 return; 607 } 608 609 vmstate_register_ram_global(&s->mem); 610 memory_region_set_readonly(&s->mem, true); 611 sysbus_init_mmio(dev, &s->mem); 612 } 613 614 static void idreg_class_init(ObjectClass *oc, void *data) 615 { 616 DeviceClass *dc = DEVICE_CLASS(oc); 617 618 dc->realize = idreg_realize; 619 } 620 621 static const TypeInfo idreg_info = { 622 .name = TYPE_MACIO_ID_REGISTER, 623 .parent = TYPE_SYS_BUS_DEVICE, 624 .instance_size = sizeof(IDRegState), 625 .class_init = idreg_class_init, 626 }; 627 628 #define TYPE_TCX_AFX "tcx_afx" 629 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX) 630 631 typedef struct AFXState { 632 SysBusDevice parent_obj; 633 634 MemoryRegion mem; 635 } AFXState; 636 637 /* SS-5 TCX AFX register */ 638 static void afx_init(hwaddr addr) 639 { 640 DeviceState *dev; 641 SysBusDevice *s; 642 643 dev = qdev_create(NULL, TYPE_TCX_AFX); 644 qdev_init_nofail(dev); 645 s = SYS_BUS_DEVICE(dev); 646 647 sysbus_mmio_map(s, 0, addr); 648 } 649 650 static void afx_realize(DeviceState *ds, Error **errp) 651 { 652 AFXState *s = TCX_AFX(ds); 653 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 654 Error *local_err = NULL; 655 656 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4, 657 &local_err); 658 if (local_err) { 659 error_propagate(errp, local_err); 660 return; 661 } 662 663 vmstate_register_ram_global(&s->mem); 664 sysbus_init_mmio(dev, &s->mem); 665 } 666 667 static void afx_class_init(ObjectClass *oc, void *data) 668 { 669 DeviceClass *dc = DEVICE_CLASS(oc); 670 671 dc->realize = afx_realize; 672 } 673 674 static const TypeInfo afx_info = { 675 .name = TYPE_TCX_AFX, 676 .parent = TYPE_SYS_BUS_DEVICE, 677 .instance_size = sizeof(AFXState), 678 .class_init = afx_class_init, 679 }; 680 681 #define TYPE_OPENPROM "openprom" 682 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 683 684 typedef struct PROMState { 685 SysBusDevice parent_obj; 686 687 MemoryRegion prom; 688 } PROMState; 689 690 /* Boot PROM (OpenBIOS) */ 691 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 692 { 693 hwaddr *base_addr = (hwaddr *)opaque; 694 return addr + *base_addr - PROM_VADDR; 695 } 696 697 static void prom_init(hwaddr addr, const char *bios_name) 698 { 699 DeviceState *dev; 700 SysBusDevice *s; 701 char *filename; 702 int ret; 703 704 dev = qdev_create(NULL, TYPE_OPENPROM); 705 qdev_init_nofail(dev); 706 s = SYS_BUS_DEVICE(dev); 707 708 sysbus_mmio_map(s, 0, addr); 709 710 /* load boot prom */ 711 if (bios_name == NULL) { 712 bios_name = PROM_FILENAME; 713 } 714 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 715 if (filename) { 716 ret = load_elf(filename, NULL, 717 translate_prom_address, &addr, NULL, 718 NULL, NULL, 1, EM_SPARC, 0, 0); 719 if (ret < 0 || ret > PROM_SIZE_MAX) { 720 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 721 } 722 g_free(filename); 723 } else { 724 ret = -1; 725 } 726 if (ret < 0 || ret > PROM_SIZE_MAX) { 727 error_report("could not load prom '%s'", bios_name); 728 exit(1); 729 } 730 } 731 732 static void prom_realize(DeviceState *ds, Error **errp) 733 { 734 PROMState *s = OPENPROM(ds); 735 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 736 Error *local_err = NULL; 737 738 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom", 739 PROM_SIZE_MAX, &local_err); 740 if (local_err) { 741 error_propagate(errp, local_err); 742 return; 743 } 744 745 vmstate_register_ram_global(&s->prom); 746 memory_region_set_readonly(&s->prom, true); 747 sysbus_init_mmio(dev, &s->prom); 748 } 749 750 static Property prom_properties[] = { 751 {/* end of property list */}, 752 }; 753 754 static void prom_class_init(ObjectClass *klass, void *data) 755 { 756 DeviceClass *dc = DEVICE_CLASS(klass); 757 758 dc->props = prom_properties; 759 dc->realize = prom_realize; 760 } 761 762 static const TypeInfo prom_info = { 763 .name = TYPE_OPENPROM, 764 .parent = TYPE_SYS_BUS_DEVICE, 765 .instance_size = sizeof(PROMState), 766 .class_init = prom_class_init, 767 }; 768 769 #define TYPE_SUN4M_MEMORY "memory" 770 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY) 771 772 typedef struct RamDevice { 773 SysBusDevice parent_obj; 774 775 MemoryRegion ram; 776 uint64_t size; 777 } RamDevice; 778 779 /* System RAM */ 780 static void ram_realize(DeviceState *dev, Error **errp) 781 { 782 RamDevice *d = SUN4M_RAM(dev); 783 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 784 785 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram", 786 d->size); 787 sysbus_init_mmio(sbd, &d->ram); 788 } 789 790 static void ram_init(hwaddr addr, ram_addr_t RAM_size, 791 uint64_t max_mem) 792 { 793 DeviceState *dev; 794 SysBusDevice *s; 795 RamDevice *d; 796 797 /* allocate RAM */ 798 if ((uint64_t)RAM_size > max_mem) { 799 error_report("Too much memory for this machine: %" PRId64 "," 800 " maximum %" PRId64, 801 RAM_size / MiB, max_mem / MiB); 802 exit(1); 803 } 804 dev = qdev_create(NULL, "memory"); 805 s = SYS_BUS_DEVICE(dev); 806 807 d = SUN4M_RAM(dev); 808 d->size = RAM_size; 809 qdev_init_nofail(dev); 810 811 sysbus_mmio_map(s, 0, addr); 812 } 813 814 static Property ram_properties[] = { 815 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 816 DEFINE_PROP_END_OF_LIST(), 817 }; 818 819 static void ram_class_init(ObjectClass *klass, void *data) 820 { 821 DeviceClass *dc = DEVICE_CLASS(klass); 822 823 dc->realize = ram_realize; 824 dc->props = ram_properties; 825 } 826 827 static const TypeInfo ram_info = { 828 .name = TYPE_SUN4M_MEMORY, 829 .parent = TYPE_SYS_BUS_DEVICE, 830 .instance_size = sizeof(RamDevice), 831 .class_init = ram_class_init, 832 }; 833 834 static void cpu_devinit(const char *cpu_type, unsigned int id, 835 uint64_t prom_addr, qemu_irq **cpu_irqs) 836 { 837 CPUState *cs; 838 SPARCCPU *cpu; 839 CPUSPARCState *env; 840 841 cpu = SPARC_CPU(cpu_create(cpu_type)); 842 env = &cpu->env; 843 844 cpu_sparc_set_id(env, id); 845 if (id == 0) { 846 qemu_register_reset(main_cpu_reset, cpu); 847 } else { 848 qemu_register_reset(secondary_cpu_reset, cpu); 849 cs = CPU(cpu); 850 cs->halted = 1; 851 } 852 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 853 env->prom_addr = prom_addr; 854 } 855 856 static void dummy_fdc_tc(void *opaque, int irq, int level) 857 { 858 } 859 860 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, 861 MachineState *machine) 862 { 863 DeviceState *slavio_intctl; 864 unsigned int i; 865 void *nvram; 866 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; 867 qemu_irq fdc_tc; 868 unsigned long kernel_size; 869 uint32_t initrd_size; 870 DriveInfo *fd[MAX_FD]; 871 FWCfgState *fw_cfg; 872 DeviceState *dev; 873 SysBusDevice *s; 874 875 /* init CPUs */ 876 for(i = 0; i < smp_cpus; i++) { 877 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); 878 } 879 880 for (i = smp_cpus; i < MAX_CPUS; i++) 881 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 882 883 884 /* set up devices */ 885 ram_init(0, machine->ram_size, hwdef->max_mem); 886 /* models without ECC don't trap when missing ram is accessed */ 887 if (!hwdef->ecc_base) { 888 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size); 889 } 890 891 prom_init(hwdef->slavio_base, bios_name); 892 893 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 894 hwdef->intctl_base + 0x10000ULL, 895 cpu_irqs); 896 897 for (i = 0; i < 32; i++) { 898 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 899 } 900 for (i = 0; i < MAX_CPUS; i++) { 901 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 902 } 903 904 if (hwdef->idreg_base) { 905 idreg_init(hwdef->idreg_base); 906 } 907 908 if (hwdef->afx_base) { 909 afx_init(hwdef->afx_base); 910 } 911 912 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]); 913 914 if (hwdef->iommu_pad_base) { 915 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 916 Software shouldn't use aliased addresses, neither should it crash 917 when does. Using empty_slot instead of aliasing can help with 918 debugging such accesses */ 919 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); 920 } 921 922 sparc32_dma_init(hwdef->dma_base, 923 hwdef->esp_base, slavio_irq[18], 924 hwdef->le_base, slavio_irq[16]); 925 926 if (graphic_depth != 8 && graphic_depth != 24) { 927 error_report("Unsupported depth: %d", graphic_depth); 928 exit (1); 929 } 930 if (vga_interface_type != VGA_NONE) { 931 if (vga_interface_type == VGA_CG3) { 932 if (graphic_depth != 8) { 933 error_report("Unsupported depth: %d", graphic_depth); 934 exit(1); 935 } 936 937 if (!(graphic_width == 1024 && graphic_height == 768) && 938 !(graphic_width == 1152 && graphic_height == 900)) { 939 error_report("Unsupported resolution: %d x %d", graphic_width, 940 graphic_height); 941 exit(1); 942 } 943 944 /* sbus irq 5 */ 945 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 946 graphic_width, graphic_height, graphic_depth); 947 } else { 948 /* If no display specified, default to TCX */ 949 if (graphic_depth != 8 && graphic_depth != 24) { 950 error_report("Unsupported depth: %d", graphic_depth); 951 exit(1); 952 } 953 954 if (!(graphic_width == 1024 && graphic_height == 768)) { 955 error_report("Unsupported resolution: %d x %d", 956 graphic_width, graphic_height); 957 exit(1); 958 } 959 960 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 961 graphic_width, graphic_height, graphic_depth); 962 } 963 } 964 965 for (i = 0; i < MAX_VSIMMS; i++) { 966 /* vsimm registers probed by OBP */ 967 if (hwdef->vsimm[i].reg_base) { 968 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); 969 } 970 } 971 972 if (hwdef->sx_base) { 973 empty_slot_init(hwdef->sx_base, 0x2000); 974 } 975 976 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8); 977 978 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 979 980 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 981 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 982 dev = qdev_create(NULL, TYPE_ESCC); 983 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics); 984 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 985 qdev_prop_set_uint32(dev, "it_shift", 1); 986 qdev_prop_set_chr(dev, "chrB", NULL); 987 qdev_prop_set_chr(dev, "chrA", NULL); 988 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse); 989 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd); 990 qdev_init_nofail(dev); 991 s = SYS_BUS_DEVICE(dev); 992 sysbus_connect_irq(s, 0, slavio_irq[14]); 993 sysbus_connect_irq(s, 1, slavio_irq[14]); 994 sysbus_mmio_map(s, 0, hwdef->ms_kb_base); 995 996 dev = qdev_create(NULL, TYPE_ESCC); 997 qdev_prop_set_uint32(dev, "disabled", 0); 998 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 999 qdev_prop_set_uint32(dev, "it_shift", 1); 1000 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 1001 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 1002 qdev_prop_set_uint32(dev, "chnBtype", escc_serial); 1003 qdev_prop_set_uint32(dev, "chnAtype", escc_serial); 1004 qdev_init_nofail(dev); 1005 1006 s = SYS_BUS_DEVICE(dev); 1007 sysbus_connect_irq(s, 0, slavio_irq[15]); 1008 sysbus_connect_irq(s, 1, slavio_irq[15]); 1009 sysbus_mmio_map(s, 0, hwdef->serial_base); 1010 1011 if (hwdef->apc_base) { 1012 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); 1013 } 1014 1015 if (hwdef->fd_base) { 1016 /* there is zero or one floppy drive */ 1017 memset(fd, 0, sizeof(fd)); 1018 fd[0] = drive_get(IF_FLOPPY, 0, 0); 1019 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 1020 &fdc_tc); 1021 } else { 1022 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); 1023 } 1024 1025 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 1026 slavio_irq[30], fdc_tc); 1027 1028 if (hwdef->cs_base) { 1029 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, 1030 slavio_irq[5]); 1031 } 1032 1033 if (hwdef->dbri_base) { 1034 /* ISDN chip with attached CS4215 audio codec */ 1035 /* prom space */ 1036 empty_slot_init(hwdef->dbri_base+0x1000, 0x30); 1037 /* reg space */ 1038 empty_slot_init(hwdef->dbri_base+0x10000, 0x100); 1039 } 1040 1041 if (hwdef->bpp_base) { 1042 /* parallel port */ 1043 empty_slot_init(hwdef->bpp_base, 0x20); 1044 } 1045 1046 initrd_size = 0; 1047 kernel_size = sun4m_load_kernel(machine->kernel_filename, 1048 machine->initrd_filename, 1049 machine->ram_size, &initrd_size); 1050 1051 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline, 1052 machine->boot_order, machine->ram_size, kernel_size, 1053 graphic_width, graphic_height, graphic_depth, 1054 hwdef->nvram_machine_id, "Sun4m"); 1055 1056 if (hwdef->ecc_base) 1057 ecc_init(hwdef->ecc_base, slavio_irq[28], 1058 hwdef->ecc_version); 1059 1060 dev = qdev_create(NULL, TYPE_FW_CFG_MEM); 1061 fw_cfg = FW_CFG(dev); 1062 qdev_prop_set_uint32(dev, "data_width", 1); 1063 qdev_prop_set_bit(dev, "dma_enabled", false); 1064 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1065 OBJECT(fw_cfg), NULL); 1066 qdev_init_nofail(dev); 1067 s = SYS_BUS_DEVICE(dev); 1068 sysbus_mmio_map(s, 0, CFG_ADDR); 1069 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 1070 1071 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 1072 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1073 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1074 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1075 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1076 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1077 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1078 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1079 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1080 if (machine->kernel_cmdline) { 1081 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1082 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1083 machine->kernel_cmdline); 1084 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 1085 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1086 strlen(machine->kernel_cmdline) + 1); 1087 } else { 1088 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1089 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1090 } 1091 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1092 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1093 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 1094 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1095 } 1096 1097 enum { 1098 ss5_id = 32, 1099 vger_id, 1100 lx_id, 1101 ss4_id, 1102 scls_id, 1103 sbook_id, 1104 ss10_id = 64, 1105 ss20_id, 1106 ss600mp_id, 1107 }; 1108 1109 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1110 /* SS-5 */ 1111 { 1112 .iommu_base = 0x10000000, 1113 .iommu_pad_base = 0x10004000, 1114 .iommu_pad_len = 0x0fffb000, 1115 .tcx_base = 0x50000000, 1116 .cs_base = 0x6c000000, 1117 .slavio_base = 0x70000000, 1118 .ms_kb_base = 0x71000000, 1119 .serial_base = 0x71100000, 1120 .nvram_base = 0x71200000, 1121 .fd_base = 0x71400000, 1122 .counter_base = 0x71d00000, 1123 .intctl_base = 0x71e00000, 1124 .idreg_base = 0x78000000, 1125 .dma_base = 0x78400000, 1126 .esp_base = 0x78800000, 1127 .le_base = 0x78c00000, 1128 .apc_base = 0x6a000000, 1129 .afx_base = 0x6e000000, 1130 .aux1_base = 0x71900000, 1131 .aux2_base = 0x71910000, 1132 .nvram_machine_id = 0x80, 1133 .machine_id = ss5_id, 1134 .iommu_version = 0x05000000, 1135 .max_mem = 0x10000000, 1136 }, 1137 /* SS-10 */ 1138 { 1139 .iommu_base = 0xfe0000000ULL, 1140 .tcx_base = 0xe20000000ULL, 1141 .slavio_base = 0xff0000000ULL, 1142 .ms_kb_base = 0xff1000000ULL, 1143 .serial_base = 0xff1100000ULL, 1144 .nvram_base = 0xff1200000ULL, 1145 .fd_base = 0xff1700000ULL, 1146 .counter_base = 0xff1300000ULL, 1147 .intctl_base = 0xff1400000ULL, 1148 .idreg_base = 0xef0000000ULL, 1149 .dma_base = 0xef0400000ULL, 1150 .esp_base = 0xef0800000ULL, 1151 .le_base = 0xef0c00000ULL, 1152 .apc_base = 0xefa000000ULL, // XXX should not exist 1153 .aux1_base = 0xff1800000ULL, 1154 .aux2_base = 0xff1a01000ULL, 1155 .ecc_base = 0xf00000000ULL, 1156 .ecc_version = 0x10000000, // version 0, implementation 1 1157 .nvram_machine_id = 0x72, 1158 .machine_id = ss10_id, 1159 .iommu_version = 0x03000000, 1160 .max_mem = 0xf00000000ULL, 1161 }, 1162 /* SS-600MP */ 1163 { 1164 .iommu_base = 0xfe0000000ULL, 1165 .tcx_base = 0xe20000000ULL, 1166 .slavio_base = 0xff0000000ULL, 1167 .ms_kb_base = 0xff1000000ULL, 1168 .serial_base = 0xff1100000ULL, 1169 .nvram_base = 0xff1200000ULL, 1170 .counter_base = 0xff1300000ULL, 1171 .intctl_base = 0xff1400000ULL, 1172 .dma_base = 0xef0081000ULL, 1173 .esp_base = 0xef0080000ULL, 1174 .le_base = 0xef0060000ULL, 1175 .apc_base = 0xefa000000ULL, // XXX should not exist 1176 .aux1_base = 0xff1800000ULL, 1177 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1178 .ecc_base = 0xf00000000ULL, 1179 .ecc_version = 0x00000000, // version 0, implementation 0 1180 .nvram_machine_id = 0x71, 1181 .machine_id = ss600mp_id, 1182 .iommu_version = 0x01000000, 1183 .max_mem = 0xf00000000ULL, 1184 }, 1185 /* SS-20 */ 1186 { 1187 .iommu_base = 0xfe0000000ULL, 1188 .tcx_base = 0xe20000000ULL, 1189 .slavio_base = 0xff0000000ULL, 1190 .ms_kb_base = 0xff1000000ULL, 1191 .serial_base = 0xff1100000ULL, 1192 .nvram_base = 0xff1200000ULL, 1193 .fd_base = 0xff1700000ULL, 1194 .counter_base = 0xff1300000ULL, 1195 .intctl_base = 0xff1400000ULL, 1196 .idreg_base = 0xef0000000ULL, 1197 .dma_base = 0xef0400000ULL, 1198 .esp_base = 0xef0800000ULL, 1199 .le_base = 0xef0c00000ULL, 1200 .bpp_base = 0xef4800000ULL, 1201 .apc_base = 0xefa000000ULL, // XXX should not exist 1202 .aux1_base = 0xff1800000ULL, 1203 .aux2_base = 0xff1a01000ULL, 1204 .dbri_base = 0xee0000000ULL, 1205 .sx_base = 0xf80000000ULL, 1206 .vsimm = { 1207 { 1208 .reg_base = 0x9c000000ULL, 1209 .vram_base = 0xfc000000ULL 1210 }, { 1211 .reg_base = 0x90000000ULL, 1212 .vram_base = 0xf0000000ULL 1213 }, { 1214 .reg_base = 0x94000000ULL 1215 }, { 1216 .reg_base = 0x98000000ULL 1217 } 1218 }, 1219 .ecc_base = 0xf00000000ULL, 1220 .ecc_version = 0x20000000, // version 0, implementation 2 1221 .nvram_machine_id = 0x72, 1222 .machine_id = ss20_id, 1223 .iommu_version = 0x13000000, 1224 .max_mem = 0xf00000000ULL, 1225 }, 1226 /* Voyager */ 1227 { 1228 .iommu_base = 0x10000000, 1229 .tcx_base = 0x50000000, 1230 .slavio_base = 0x70000000, 1231 .ms_kb_base = 0x71000000, 1232 .serial_base = 0x71100000, 1233 .nvram_base = 0x71200000, 1234 .fd_base = 0x71400000, 1235 .counter_base = 0x71d00000, 1236 .intctl_base = 0x71e00000, 1237 .idreg_base = 0x78000000, 1238 .dma_base = 0x78400000, 1239 .esp_base = 0x78800000, 1240 .le_base = 0x78c00000, 1241 .apc_base = 0x71300000, // pmc 1242 .aux1_base = 0x71900000, 1243 .aux2_base = 0x71910000, 1244 .nvram_machine_id = 0x80, 1245 .machine_id = vger_id, 1246 .iommu_version = 0x05000000, 1247 .max_mem = 0x10000000, 1248 }, 1249 /* LX */ 1250 { 1251 .iommu_base = 0x10000000, 1252 .iommu_pad_base = 0x10004000, 1253 .iommu_pad_len = 0x0fffb000, 1254 .tcx_base = 0x50000000, 1255 .slavio_base = 0x70000000, 1256 .ms_kb_base = 0x71000000, 1257 .serial_base = 0x71100000, 1258 .nvram_base = 0x71200000, 1259 .fd_base = 0x71400000, 1260 .counter_base = 0x71d00000, 1261 .intctl_base = 0x71e00000, 1262 .idreg_base = 0x78000000, 1263 .dma_base = 0x78400000, 1264 .esp_base = 0x78800000, 1265 .le_base = 0x78c00000, 1266 .aux1_base = 0x71900000, 1267 .aux2_base = 0x71910000, 1268 .nvram_machine_id = 0x80, 1269 .machine_id = lx_id, 1270 .iommu_version = 0x04000000, 1271 .max_mem = 0x10000000, 1272 }, 1273 /* SS-4 */ 1274 { 1275 .iommu_base = 0x10000000, 1276 .tcx_base = 0x50000000, 1277 .cs_base = 0x6c000000, 1278 .slavio_base = 0x70000000, 1279 .ms_kb_base = 0x71000000, 1280 .serial_base = 0x71100000, 1281 .nvram_base = 0x71200000, 1282 .fd_base = 0x71400000, 1283 .counter_base = 0x71d00000, 1284 .intctl_base = 0x71e00000, 1285 .idreg_base = 0x78000000, 1286 .dma_base = 0x78400000, 1287 .esp_base = 0x78800000, 1288 .le_base = 0x78c00000, 1289 .apc_base = 0x6a000000, 1290 .aux1_base = 0x71900000, 1291 .aux2_base = 0x71910000, 1292 .nvram_machine_id = 0x80, 1293 .machine_id = ss4_id, 1294 .iommu_version = 0x05000000, 1295 .max_mem = 0x10000000, 1296 }, 1297 /* SPARCClassic */ 1298 { 1299 .iommu_base = 0x10000000, 1300 .tcx_base = 0x50000000, 1301 .slavio_base = 0x70000000, 1302 .ms_kb_base = 0x71000000, 1303 .serial_base = 0x71100000, 1304 .nvram_base = 0x71200000, 1305 .fd_base = 0x71400000, 1306 .counter_base = 0x71d00000, 1307 .intctl_base = 0x71e00000, 1308 .idreg_base = 0x78000000, 1309 .dma_base = 0x78400000, 1310 .esp_base = 0x78800000, 1311 .le_base = 0x78c00000, 1312 .apc_base = 0x6a000000, 1313 .aux1_base = 0x71900000, 1314 .aux2_base = 0x71910000, 1315 .nvram_machine_id = 0x80, 1316 .machine_id = scls_id, 1317 .iommu_version = 0x05000000, 1318 .max_mem = 0x10000000, 1319 }, 1320 /* SPARCbook */ 1321 { 1322 .iommu_base = 0x10000000, 1323 .tcx_base = 0x50000000, // XXX 1324 .slavio_base = 0x70000000, 1325 .ms_kb_base = 0x71000000, 1326 .serial_base = 0x71100000, 1327 .nvram_base = 0x71200000, 1328 .fd_base = 0x71400000, 1329 .counter_base = 0x71d00000, 1330 .intctl_base = 0x71e00000, 1331 .idreg_base = 0x78000000, 1332 .dma_base = 0x78400000, 1333 .esp_base = 0x78800000, 1334 .le_base = 0x78c00000, 1335 .apc_base = 0x6a000000, 1336 .aux1_base = 0x71900000, 1337 .aux2_base = 0x71910000, 1338 .nvram_machine_id = 0x80, 1339 .machine_id = sbook_id, 1340 .iommu_version = 0x05000000, 1341 .max_mem = 0x10000000, 1342 }, 1343 }; 1344 1345 /* SPARCstation 5 hardware initialisation */ 1346 static void ss5_init(MachineState *machine) 1347 { 1348 sun4m_hw_init(&sun4m_hwdefs[0], machine); 1349 } 1350 1351 /* SPARCstation 10 hardware initialisation */ 1352 static void ss10_init(MachineState *machine) 1353 { 1354 sun4m_hw_init(&sun4m_hwdefs[1], machine); 1355 } 1356 1357 /* SPARCserver 600MP hardware initialisation */ 1358 static void ss600mp_init(MachineState *machine) 1359 { 1360 sun4m_hw_init(&sun4m_hwdefs[2], machine); 1361 } 1362 1363 /* SPARCstation 20 hardware initialisation */ 1364 static void ss20_init(MachineState *machine) 1365 { 1366 sun4m_hw_init(&sun4m_hwdefs[3], machine); 1367 } 1368 1369 /* SPARCstation Voyager hardware initialisation */ 1370 static void vger_init(MachineState *machine) 1371 { 1372 sun4m_hw_init(&sun4m_hwdefs[4], machine); 1373 } 1374 1375 /* SPARCstation LX hardware initialisation */ 1376 static void ss_lx_init(MachineState *machine) 1377 { 1378 sun4m_hw_init(&sun4m_hwdefs[5], machine); 1379 } 1380 1381 /* SPARCstation 4 hardware initialisation */ 1382 static void ss4_init(MachineState *machine) 1383 { 1384 sun4m_hw_init(&sun4m_hwdefs[6], machine); 1385 } 1386 1387 /* SPARCClassic hardware initialisation */ 1388 static void scls_init(MachineState *machine) 1389 { 1390 sun4m_hw_init(&sun4m_hwdefs[7], machine); 1391 } 1392 1393 /* SPARCbook hardware initialisation */ 1394 static void sbook_init(MachineState *machine) 1395 { 1396 sun4m_hw_init(&sun4m_hwdefs[8], machine); 1397 } 1398 1399 static void ss5_class_init(ObjectClass *oc, void *data) 1400 { 1401 MachineClass *mc = MACHINE_CLASS(oc); 1402 1403 mc->desc = "Sun4m platform, SPARCstation 5"; 1404 mc->init = ss5_init; 1405 mc->block_default_type = IF_SCSI; 1406 mc->is_default = 1; 1407 mc->default_boot_order = "c"; 1408 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1409 } 1410 1411 static const TypeInfo ss5_type = { 1412 .name = MACHINE_TYPE_NAME("SS-5"), 1413 .parent = TYPE_MACHINE, 1414 .class_init = ss5_class_init, 1415 }; 1416 1417 static void ss10_class_init(ObjectClass *oc, void *data) 1418 { 1419 MachineClass *mc = MACHINE_CLASS(oc); 1420 1421 mc->desc = "Sun4m platform, SPARCstation 10"; 1422 mc->init = ss10_init; 1423 mc->block_default_type = IF_SCSI; 1424 mc->max_cpus = 4; 1425 mc->default_boot_order = "c"; 1426 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1427 } 1428 1429 static const TypeInfo ss10_type = { 1430 .name = MACHINE_TYPE_NAME("SS-10"), 1431 .parent = TYPE_MACHINE, 1432 .class_init = ss10_class_init, 1433 }; 1434 1435 static void ss600mp_class_init(ObjectClass *oc, void *data) 1436 { 1437 MachineClass *mc = MACHINE_CLASS(oc); 1438 1439 mc->desc = "Sun4m platform, SPARCserver 600MP"; 1440 mc->init = ss600mp_init; 1441 mc->block_default_type = IF_SCSI; 1442 mc->max_cpus = 4; 1443 mc->default_boot_order = "c"; 1444 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1445 } 1446 1447 static const TypeInfo ss600mp_type = { 1448 .name = MACHINE_TYPE_NAME("SS-600MP"), 1449 .parent = TYPE_MACHINE, 1450 .class_init = ss600mp_class_init, 1451 }; 1452 1453 static void ss20_class_init(ObjectClass *oc, void *data) 1454 { 1455 MachineClass *mc = MACHINE_CLASS(oc); 1456 1457 mc->desc = "Sun4m platform, SPARCstation 20"; 1458 mc->init = ss20_init; 1459 mc->block_default_type = IF_SCSI; 1460 mc->max_cpus = 4; 1461 mc->default_boot_order = "c"; 1462 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1463 } 1464 1465 static const TypeInfo ss20_type = { 1466 .name = MACHINE_TYPE_NAME("SS-20"), 1467 .parent = TYPE_MACHINE, 1468 .class_init = ss20_class_init, 1469 }; 1470 1471 static void voyager_class_init(ObjectClass *oc, void *data) 1472 { 1473 MachineClass *mc = MACHINE_CLASS(oc); 1474 1475 mc->desc = "Sun4m platform, SPARCstation Voyager"; 1476 mc->init = vger_init; 1477 mc->block_default_type = IF_SCSI; 1478 mc->default_boot_order = "c"; 1479 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1480 } 1481 1482 static const TypeInfo voyager_type = { 1483 .name = MACHINE_TYPE_NAME("Voyager"), 1484 .parent = TYPE_MACHINE, 1485 .class_init = voyager_class_init, 1486 }; 1487 1488 static void ss_lx_class_init(ObjectClass *oc, void *data) 1489 { 1490 MachineClass *mc = MACHINE_CLASS(oc); 1491 1492 mc->desc = "Sun4m platform, SPARCstation LX"; 1493 mc->init = ss_lx_init; 1494 mc->block_default_type = IF_SCSI; 1495 mc->default_boot_order = "c"; 1496 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1497 } 1498 1499 static const TypeInfo ss_lx_type = { 1500 .name = MACHINE_TYPE_NAME("LX"), 1501 .parent = TYPE_MACHINE, 1502 .class_init = ss_lx_class_init, 1503 }; 1504 1505 static void ss4_class_init(ObjectClass *oc, void *data) 1506 { 1507 MachineClass *mc = MACHINE_CLASS(oc); 1508 1509 mc->desc = "Sun4m platform, SPARCstation 4"; 1510 mc->init = ss4_init; 1511 mc->block_default_type = IF_SCSI; 1512 mc->default_boot_order = "c"; 1513 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1514 } 1515 1516 static const TypeInfo ss4_type = { 1517 .name = MACHINE_TYPE_NAME("SS-4"), 1518 .parent = TYPE_MACHINE, 1519 .class_init = ss4_class_init, 1520 }; 1521 1522 static void scls_class_init(ObjectClass *oc, void *data) 1523 { 1524 MachineClass *mc = MACHINE_CLASS(oc); 1525 1526 mc->desc = "Sun4m platform, SPARCClassic"; 1527 mc->init = scls_init; 1528 mc->block_default_type = IF_SCSI; 1529 mc->default_boot_order = "c"; 1530 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1531 } 1532 1533 static const TypeInfo scls_type = { 1534 .name = MACHINE_TYPE_NAME("SPARCClassic"), 1535 .parent = TYPE_MACHINE, 1536 .class_init = scls_class_init, 1537 }; 1538 1539 static void sbook_class_init(ObjectClass *oc, void *data) 1540 { 1541 MachineClass *mc = MACHINE_CLASS(oc); 1542 1543 mc->desc = "Sun4m platform, SPARCbook"; 1544 mc->init = sbook_init; 1545 mc->block_default_type = IF_SCSI; 1546 mc->default_boot_order = "c"; 1547 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1548 } 1549 1550 static const TypeInfo sbook_type = { 1551 .name = MACHINE_TYPE_NAME("SPARCbook"), 1552 .parent = TYPE_MACHINE, 1553 .class_init = sbook_class_init, 1554 }; 1555 1556 static void sun4m_register_types(void) 1557 { 1558 type_register_static(&idreg_info); 1559 type_register_static(&afx_info); 1560 type_register_static(&prom_info); 1561 type_register_static(&ram_info); 1562 1563 type_register_static(&ss5_type); 1564 type_register_static(&ss10_type); 1565 type_register_static(&ss600mp_type); 1566 type_register_static(&ss20_type); 1567 type_register_static(&voyager_type); 1568 type_register_static(&ss_lx_type); 1569 type_register_static(&ss4_type); 1570 type_register_static(&scls_type); 1571 type_register_static(&sbook_type); 1572 } 1573 1574 type_init(sun4m_register_types) 1575