1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/sysbus.h" 29 #include "qemu/error-report.h" 30 #include "qemu/timer.h" 31 #include "hw/sparc/sun4m.h" 32 #include "hw/timer/m48t59.h" 33 #include "hw/sparc/sparc32_dma.h" 34 #include "hw/block/fdc.h" 35 #include "sysemu/sysemu.h" 36 #include "net/net.h" 37 #include "hw/boards.h" 38 #include "hw/scsi/esp.h" 39 #include "hw/i386/pc.h" 40 #include "hw/isa/isa.h" 41 #include "hw/nvram/sun_nvram.h" 42 #include "hw/nvram/chrp_nvram.h" 43 #include "hw/nvram/fw_cfg.h" 44 #include "hw/char/escc.h" 45 #include "hw/empty_slot.h" 46 #include "hw/loader.h" 47 #include "elf.h" 48 #include "sysemu/block-backend.h" 49 #include "trace.h" 50 #include "qemu/cutils.h" 51 52 /* 53 * Sun4m architecture was used in the following machines: 54 * 55 * SPARCserver 6xxMP/xx 56 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 57 * SPARCclassic X (4/10) 58 * SPARCstation LX/ZX (4/30) 59 * SPARCstation Voyager 60 * SPARCstation 10/xx, SPARCserver 10/xx 61 * SPARCstation 5, SPARCserver 5 62 * SPARCstation 20/xx, SPARCserver 20 63 * SPARCstation 4 64 * 65 * See for example: http://www.sunhelp.org/faq/sunref1.html 66 */ 67 68 #define KERNEL_LOAD_ADDR 0x00004000 69 #define CMDLINE_ADDR 0x007ff000 70 #define INITRD_LOAD_ADDR 0x00800000 71 #define PROM_SIZE_MAX (1024 * 1024) 72 #define PROM_VADDR 0xffd00000 73 #define PROM_FILENAME "openbios-sparc32" 74 #define CFG_ADDR 0xd00000510ULL 75 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 76 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 77 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 78 79 #define MAX_CPUS 16 80 #define MAX_PILS 16 81 #define MAX_VSIMMS 4 82 83 #define ESCC_CLOCK 4915200 84 85 struct sun4m_hwdef { 86 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 87 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 88 hwaddr serial_base, fd_base; 89 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 90 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 91 hwaddr bpp_base, dbri_base, sx_base; 92 struct { 93 hwaddr reg_base, vram_base; 94 } vsimm[MAX_VSIMMS]; 95 hwaddr ecc_base; 96 uint64_t max_mem; 97 uint32_t ecc_version; 98 uint32_t iommu_version; 99 uint16_t machine_id; 100 uint8_t nvram_machine_id; 101 }; 102 103 void DMA_init(ISABus *bus, int high_page_enable) 104 { 105 } 106 107 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 108 Error **errp) 109 { 110 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 111 } 112 113 static void nvram_init(Nvram *nvram, uint8_t *macaddr, 114 const char *cmdline, const char *boot_devices, 115 ram_addr_t RAM_size, uint32_t kernel_size, 116 int width, int height, int depth, 117 int nvram_machine_id, const char *arch) 118 { 119 unsigned int i; 120 int sysp_end; 121 uint8_t image[0x1ff0]; 122 NvramClass *k = NVRAM_GET_CLASS(nvram); 123 124 memset(image, '\0', sizeof(image)); 125 126 /* OpenBIOS nvram variables partition */ 127 sysp_end = chrp_nvram_create_system_partition(image, 0); 128 129 /* Free space partition */ 130 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 131 132 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 133 nvram_machine_id); 134 135 for (i = 0; i < sizeof(image); i++) { 136 (k->write)(nvram, i, image[i]); 137 } 138 } 139 140 void cpu_check_irqs(CPUSPARCState *env) 141 { 142 CPUState *cs; 143 144 /* We should be holding the BQL before we mess with IRQs */ 145 g_assert(qemu_mutex_iothread_locked()); 146 147 if (env->pil_in && (env->interrupt_index == 0 || 148 (env->interrupt_index & ~15) == TT_EXTINT)) { 149 unsigned int i; 150 151 for (i = 15; i > 0; i--) { 152 if (env->pil_in & (1 << i)) { 153 int old_interrupt = env->interrupt_index; 154 155 env->interrupt_index = TT_EXTINT | i; 156 if (old_interrupt != env->interrupt_index) { 157 cs = CPU(sparc_env_get_cpu(env)); 158 trace_sun4m_cpu_interrupt(i); 159 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 160 } 161 break; 162 } 163 } 164 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 165 cs = CPU(sparc_env_get_cpu(env)); 166 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 167 env->interrupt_index = 0; 168 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 169 } 170 } 171 172 static void cpu_kick_irq(SPARCCPU *cpu) 173 { 174 CPUSPARCState *env = &cpu->env; 175 CPUState *cs = CPU(cpu); 176 177 cs->halted = 0; 178 cpu_check_irqs(env); 179 qemu_cpu_kick(cs); 180 } 181 182 static void cpu_set_irq(void *opaque, int irq, int level) 183 { 184 SPARCCPU *cpu = opaque; 185 CPUSPARCState *env = &cpu->env; 186 187 if (level) { 188 trace_sun4m_cpu_set_irq_raise(irq); 189 env->pil_in |= 1 << irq; 190 cpu_kick_irq(cpu); 191 } else { 192 trace_sun4m_cpu_set_irq_lower(irq); 193 env->pil_in &= ~(1 << irq); 194 cpu_check_irqs(env); 195 } 196 } 197 198 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 199 { 200 } 201 202 static void main_cpu_reset(void *opaque) 203 { 204 SPARCCPU *cpu = opaque; 205 CPUState *cs = CPU(cpu); 206 207 cpu_reset(cs); 208 cs->halted = 0; 209 } 210 211 static void secondary_cpu_reset(void *opaque) 212 { 213 SPARCCPU *cpu = opaque; 214 CPUState *cs = CPU(cpu); 215 216 cpu_reset(cs); 217 cs->halted = 1; 218 } 219 220 static void cpu_halt_signal(void *opaque, int irq, int level) 221 { 222 if (level && current_cpu) { 223 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 224 } 225 } 226 227 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 228 { 229 return addr - 0xf0000000ULL; 230 } 231 232 static unsigned long sun4m_load_kernel(const char *kernel_filename, 233 const char *initrd_filename, 234 ram_addr_t RAM_size) 235 { 236 int linux_boot; 237 unsigned int i; 238 long initrd_size, kernel_size; 239 uint8_t *ptr; 240 241 linux_boot = (kernel_filename != NULL); 242 243 kernel_size = 0; 244 if (linux_boot) { 245 int bswap_needed; 246 247 #ifdef BSWAP_NEEDED 248 bswap_needed = 1; 249 #else 250 bswap_needed = 0; 251 #endif 252 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 253 NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 254 if (kernel_size < 0) 255 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 256 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 257 TARGET_PAGE_SIZE); 258 if (kernel_size < 0) 259 kernel_size = load_image_targphys(kernel_filename, 260 KERNEL_LOAD_ADDR, 261 RAM_size - KERNEL_LOAD_ADDR); 262 if (kernel_size < 0) { 263 fprintf(stderr, "qemu: could not load kernel '%s'\n", 264 kernel_filename); 265 exit(1); 266 } 267 268 /* load initrd */ 269 initrd_size = 0; 270 if (initrd_filename) { 271 initrd_size = load_image_targphys(initrd_filename, 272 INITRD_LOAD_ADDR, 273 RAM_size - INITRD_LOAD_ADDR); 274 if (initrd_size < 0) { 275 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 276 initrd_filename); 277 exit(1); 278 } 279 } 280 if (initrd_size > 0) { 281 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 282 ptr = rom_ptr(KERNEL_LOAD_ADDR + i); 283 if (ldl_p(ptr) == 0x48647253) { // HdrS 284 stl_p(ptr + 16, INITRD_LOAD_ADDR); 285 stl_p(ptr + 20, initrd_size); 286 break; 287 } 288 } 289 } 290 } 291 return kernel_size; 292 } 293 294 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 295 { 296 DeviceState *dev; 297 SysBusDevice *s; 298 299 dev = qdev_create(NULL, "iommu"); 300 qdev_prop_set_uint32(dev, "version", version); 301 qdev_init_nofail(dev); 302 s = SYS_BUS_DEVICE(dev); 303 sysbus_connect_irq(s, 0, irq); 304 sysbus_mmio_map(s, 0, addr); 305 306 return s; 307 } 308 309 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq, 310 void *iommu, qemu_irq *dev_irq, int is_ledma) 311 { 312 DeviceState *dev; 313 SysBusDevice *s; 314 315 dev = qdev_create(NULL, "sparc32_dma"); 316 qdev_prop_set_ptr(dev, "iommu_opaque", iommu); 317 qdev_prop_set_uint32(dev, "is_ledma", is_ledma); 318 qdev_init_nofail(dev); 319 s = SYS_BUS_DEVICE(dev); 320 sysbus_connect_irq(s, 0, parent_irq); 321 *dev_irq = qdev_get_gpio_in(dev, 0); 322 sysbus_mmio_map(s, 0, daddr); 323 324 return s; 325 } 326 327 static void lance_init(NICInfo *nd, hwaddr leaddr, 328 void *dma_opaque, qemu_irq irq) 329 { 330 DeviceState *dev; 331 SysBusDevice *s; 332 qemu_irq reset; 333 334 qemu_check_nic_model(&nd_table[0], "lance"); 335 336 dev = qdev_create(NULL, "lance"); 337 qdev_set_nic_properties(dev, nd); 338 qdev_prop_set_ptr(dev, "dma", dma_opaque); 339 qdev_init_nofail(dev); 340 s = SYS_BUS_DEVICE(dev); 341 sysbus_mmio_map(s, 0, leaddr); 342 sysbus_connect_irq(s, 0, irq); 343 reset = qdev_get_gpio_in(dev, 0); 344 qdev_connect_gpio_out(dma_opaque, 0, reset); 345 } 346 347 static DeviceState *slavio_intctl_init(hwaddr addr, 348 hwaddr addrg, 349 qemu_irq **parent_irq) 350 { 351 DeviceState *dev; 352 SysBusDevice *s; 353 unsigned int i, j; 354 355 dev = qdev_create(NULL, "slavio_intctl"); 356 qdev_init_nofail(dev); 357 358 s = SYS_BUS_DEVICE(dev); 359 360 for (i = 0; i < MAX_CPUS; i++) { 361 for (j = 0; j < MAX_PILS; j++) { 362 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 363 } 364 } 365 sysbus_mmio_map(s, 0, addrg); 366 for (i = 0; i < MAX_CPUS; i++) { 367 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 368 } 369 370 return dev; 371 } 372 373 #define SYS_TIMER_OFFSET 0x10000ULL 374 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 375 376 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 377 qemu_irq *cpu_irqs, unsigned int num_cpus) 378 { 379 DeviceState *dev; 380 SysBusDevice *s; 381 unsigned int i; 382 383 dev = qdev_create(NULL, "slavio_timer"); 384 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 385 qdev_init_nofail(dev); 386 s = SYS_BUS_DEVICE(dev); 387 sysbus_connect_irq(s, 0, master_irq); 388 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 389 390 for (i = 0; i < MAX_CPUS; i++) { 391 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 392 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 393 } 394 } 395 396 static qemu_irq slavio_system_powerdown; 397 398 static void slavio_powerdown_req(Notifier *n, void *opaque) 399 { 400 qemu_irq_raise(slavio_system_powerdown); 401 } 402 403 static Notifier slavio_system_powerdown_notifier = { 404 .notify = slavio_powerdown_req 405 }; 406 407 #define MISC_LEDS 0x01600000 408 #define MISC_CFG 0x01800000 409 #define MISC_DIAG 0x01a00000 410 #define MISC_MDM 0x01b00000 411 #define MISC_SYS 0x01f00000 412 413 static void slavio_misc_init(hwaddr base, 414 hwaddr aux1_base, 415 hwaddr aux2_base, qemu_irq irq, 416 qemu_irq fdc_tc) 417 { 418 DeviceState *dev; 419 SysBusDevice *s; 420 421 dev = qdev_create(NULL, "slavio_misc"); 422 qdev_init_nofail(dev); 423 s = SYS_BUS_DEVICE(dev); 424 if (base) { 425 /* 8 bit registers */ 426 /* Slavio control */ 427 sysbus_mmio_map(s, 0, base + MISC_CFG); 428 /* Diagnostics */ 429 sysbus_mmio_map(s, 1, base + MISC_DIAG); 430 /* Modem control */ 431 sysbus_mmio_map(s, 2, base + MISC_MDM); 432 /* 16 bit registers */ 433 /* ss600mp diag LEDs */ 434 sysbus_mmio_map(s, 3, base + MISC_LEDS); 435 /* 32 bit registers */ 436 /* System control */ 437 sysbus_mmio_map(s, 4, base + MISC_SYS); 438 } 439 if (aux1_base) { 440 /* AUX 1 (Misc System Functions) */ 441 sysbus_mmio_map(s, 5, aux1_base); 442 } 443 if (aux2_base) { 444 /* AUX 2 (Software Powerdown Control) */ 445 sysbus_mmio_map(s, 6, aux2_base); 446 } 447 sysbus_connect_irq(s, 0, irq); 448 sysbus_connect_irq(s, 1, fdc_tc); 449 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 450 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 451 } 452 453 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 454 { 455 DeviceState *dev; 456 SysBusDevice *s; 457 458 dev = qdev_create(NULL, "eccmemctl"); 459 qdev_prop_set_uint32(dev, "version", version); 460 qdev_init_nofail(dev); 461 s = SYS_BUS_DEVICE(dev); 462 sysbus_connect_irq(s, 0, irq); 463 sysbus_mmio_map(s, 0, base); 464 if (version == 0) { // SS-600MP only 465 sysbus_mmio_map(s, 1, base + 0x1000); 466 } 467 } 468 469 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 470 { 471 DeviceState *dev; 472 SysBusDevice *s; 473 474 dev = qdev_create(NULL, "apc"); 475 qdev_init_nofail(dev); 476 s = SYS_BUS_DEVICE(dev); 477 /* Power management (APC) XXX: not a Slavio device */ 478 sysbus_mmio_map(s, 0, power_base); 479 sysbus_connect_irq(s, 0, cpu_halt); 480 } 481 482 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 483 int height, int depth) 484 { 485 DeviceState *dev; 486 SysBusDevice *s; 487 488 dev = qdev_create(NULL, "SUNW,tcx"); 489 qdev_prop_set_uint32(dev, "vram_size", vram_size); 490 qdev_prop_set_uint16(dev, "width", width); 491 qdev_prop_set_uint16(dev, "height", height); 492 qdev_prop_set_uint16(dev, "depth", depth); 493 qdev_init_nofail(dev); 494 s = SYS_BUS_DEVICE(dev); 495 496 /* 10/ROM : FCode ROM */ 497 sysbus_mmio_map(s, 0, addr); 498 /* 2/STIP : Stipple */ 499 sysbus_mmio_map(s, 1, addr + 0x04000000ULL); 500 /* 3/BLIT : Blitter */ 501 sysbus_mmio_map(s, 2, addr + 0x06000000ULL); 502 /* 5/RSTIP : Raw Stipple */ 503 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); 504 /* 6/RBLIT : Raw Blitter */ 505 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); 506 /* 7/TEC : Transform Engine */ 507 sysbus_mmio_map(s, 5, addr + 0x00700000ULL); 508 /* 8/CMAP : DAC */ 509 sysbus_mmio_map(s, 6, addr + 0x00200000ULL); 510 /* 9/THC : */ 511 if (depth == 8) { 512 sysbus_mmio_map(s, 7, addr + 0x00300000ULL); 513 } else { 514 sysbus_mmio_map(s, 7, addr + 0x00301000ULL); 515 } 516 /* 11/DHC : */ 517 sysbus_mmio_map(s, 8, addr + 0x00240000ULL); 518 /* 12/ALT : */ 519 sysbus_mmio_map(s, 9, addr + 0x00280000ULL); 520 /* 0/DFB8 : 8-bit plane */ 521 sysbus_mmio_map(s, 10, addr + 0x00800000ULL); 522 /* 1/DFB24 : 24bit plane */ 523 sysbus_mmio_map(s, 11, addr + 0x02000000ULL); 524 /* 4/RDFB32: Raw framebuffer. Control plane */ 525 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); 526 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 527 if (depth == 8) { 528 sysbus_mmio_map(s, 13, addr + 0x00301000ULL); 529 } 530 531 sysbus_connect_irq(s, 0, irq); 532 } 533 534 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 535 int height, int depth) 536 { 537 DeviceState *dev; 538 SysBusDevice *s; 539 540 dev = qdev_create(NULL, "cgthree"); 541 qdev_prop_set_uint32(dev, "vram-size", vram_size); 542 qdev_prop_set_uint16(dev, "width", width); 543 qdev_prop_set_uint16(dev, "height", height); 544 qdev_prop_set_uint16(dev, "depth", depth); 545 qdev_init_nofail(dev); 546 s = SYS_BUS_DEVICE(dev); 547 548 /* FCode ROM */ 549 sysbus_mmio_map(s, 0, addr); 550 /* DAC */ 551 sysbus_mmio_map(s, 1, addr + 0x400000ULL); 552 /* 8-bit plane */ 553 sysbus_mmio_map(s, 2, addr + 0x800000ULL); 554 555 sysbus_connect_irq(s, 0, irq); 556 } 557 558 /* NCR89C100/MACIO Internal ID register */ 559 560 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 561 562 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 563 564 static void idreg_init(hwaddr addr) 565 { 566 DeviceState *dev; 567 SysBusDevice *s; 568 569 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER); 570 qdev_init_nofail(dev); 571 s = SYS_BUS_DEVICE(dev); 572 573 sysbus_mmio_map(s, 0, addr); 574 cpu_physical_memory_write_rom(&address_space_memory, 575 addr, idreg_data, sizeof(idreg_data)); 576 } 577 578 #define MACIO_ID_REGISTER(obj) \ 579 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER) 580 581 typedef struct IDRegState { 582 SysBusDevice parent_obj; 583 584 MemoryRegion mem; 585 } IDRegState; 586 587 static void idreg_init1(Object *obj) 588 { 589 IDRegState *s = MACIO_ID_REGISTER(obj); 590 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 591 592 memory_region_init_ram_nomigrate(&s->mem, obj, 593 "sun4m.idreg", sizeof(idreg_data), &error_fatal); 594 vmstate_register_ram_global(&s->mem); 595 memory_region_set_readonly(&s->mem, true); 596 sysbus_init_mmio(dev, &s->mem); 597 } 598 599 static const TypeInfo idreg_info = { 600 .name = TYPE_MACIO_ID_REGISTER, 601 .parent = TYPE_SYS_BUS_DEVICE, 602 .instance_size = sizeof(IDRegState), 603 .instance_init = idreg_init1, 604 }; 605 606 #define TYPE_TCX_AFX "tcx_afx" 607 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX) 608 609 typedef struct AFXState { 610 SysBusDevice parent_obj; 611 612 MemoryRegion mem; 613 } AFXState; 614 615 /* SS-5 TCX AFX register */ 616 static void afx_init(hwaddr addr) 617 { 618 DeviceState *dev; 619 SysBusDevice *s; 620 621 dev = qdev_create(NULL, TYPE_TCX_AFX); 622 qdev_init_nofail(dev); 623 s = SYS_BUS_DEVICE(dev); 624 625 sysbus_mmio_map(s, 0, addr); 626 } 627 628 static void afx_init1(Object *obj) 629 { 630 AFXState *s = TCX_AFX(obj); 631 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 632 633 memory_region_init_ram_nomigrate(&s->mem, obj, "sun4m.afx", 4, &error_fatal); 634 vmstate_register_ram_global(&s->mem); 635 sysbus_init_mmio(dev, &s->mem); 636 } 637 638 static const TypeInfo afx_info = { 639 .name = TYPE_TCX_AFX, 640 .parent = TYPE_SYS_BUS_DEVICE, 641 .instance_size = sizeof(AFXState), 642 .instance_init = afx_init1, 643 }; 644 645 #define TYPE_OPENPROM "openprom" 646 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 647 648 typedef struct PROMState { 649 SysBusDevice parent_obj; 650 651 MemoryRegion prom; 652 } PROMState; 653 654 /* Boot PROM (OpenBIOS) */ 655 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 656 { 657 hwaddr *base_addr = (hwaddr *)opaque; 658 return addr + *base_addr - PROM_VADDR; 659 } 660 661 static void prom_init(hwaddr addr, const char *bios_name) 662 { 663 DeviceState *dev; 664 SysBusDevice *s; 665 char *filename; 666 int ret; 667 668 dev = qdev_create(NULL, TYPE_OPENPROM); 669 qdev_init_nofail(dev); 670 s = SYS_BUS_DEVICE(dev); 671 672 sysbus_mmio_map(s, 0, addr); 673 674 /* load boot prom */ 675 if (bios_name == NULL) { 676 bios_name = PROM_FILENAME; 677 } 678 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 679 if (filename) { 680 ret = load_elf(filename, translate_prom_address, &addr, NULL, 681 NULL, NULL, 1, EM_SPARC, 0, 0); 682 if (ret < 0 || ret > PROM_SIZE_MAX) { 683 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 684 } 685 g_free(filename); 686 } else { 687 ret = -1; 688 } 689 if (ret < 0 || ret > PROM_SIZE_MAX) { 690 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 691 exit(1); 692 } 693 } 694 695 static void prom_init1(Object *obj) 696 { 697 PROMState *s = OPENPROM(obj); 698 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 699 700 memory_region_init_ram_nomigrate(&s->prom, obj, "sun4m.prom", PROM_SIZE_MAX, 701 &error_fatal); 702 vmstate_register_ram_global(&s->prom); 703 memory_region_set_readonly(&s->prom, true); 704 sysbus_init_mmio(dev, &s->prom); 705 } 706 707 static Property prom_properties[] = { 708 {/* end of property list */}, 709 }; 710 711 static void prom_class_init(ObjectClass *klass, void *data) 712 { 713 DeviceClass *dc = DEVICE_CLASS(klass); 714 715 dc->props = prom_properties; 716 } 717 718 static const TypeInfo prom_info = { 719 .name = TYPE_OPENPROM, 720 .parent = TYPE_SYS_BUS_DEVICE, 721 .instance_size = sizeof(PROMState), 722 .class_init = prom_class_init, 723 .instance_init = prom_init1, 724 }; 725 726 #define TYPE_SUN4M_MEMORY "memory" 727 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY) 728 729 typedef struct RamDevice { 730 SysBusDevice parent_obj; 731 732 MemoryRegion ram; 733 uint64_t size; 734 } RamDevice; 735 736 /* System RAM */ 737 static void ram_realize(DeviceState *dev, Error **errp) 738 { 739 RamDevice *d = SUN4M_RAM(dev); 740 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 741 742 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram", 743 d->size); 744 sysbus_init_mmio(sbd, &d->ram); 745 } 746 747 static void ram_init(hwaddr addr, ram_addr_t RAM_size, 748 uint64_t max_mem) 749 { 750 DeviceState *dev; 751 SysBusDevice *s; 752 RamDevice *d; 753 754 /* allocate RAM */ 755 if ((uint64_t)RAM_size > max_mem) { 756 fprintf(stderr, 757 "qemu: Too much memory for this machine: %d, maximum %d\n", 758 (unsigned int)(RAM_size / (1024 * 1024)), 759 (unsigned int)(max_mem / (1024 * 1024))); 760 exit(1); 761 } 762 dev = qdev_create(NULL, "memory"); 763 s = SYS_BUS_DEVICE(dev); 764 765 d = SUN4M_RAM(dev); 766 d->size = RAM_size; 767 qdev_init_nofail(dev); 768 769 sysbus_mmio_map(s, 0, addr); 770 } 771 772 static Property ram_properties[] = { 773 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 774 DEFINE_PROP_END_OF_LIST(), 775 }; 776 777 static void ram_class_init(ObjectClass *klass, void *data) 778 { 779 DeviceClass *dc = DEVICE_CLASS(klass); 780 781 dc->realize = ram_realize; 782 dc->props = ram_properties; 783 } 784 785 static const TypeInfo ram_info = { 786 .name = TYPE_SUN4M_MEMORY, 787 .parent = TYPE_SYS_BUS_DEVICE, 788 .instance_size = sizeof(RamDevice), 789 .class_init = ram_class_init, 790 }; 791 792 static void cpu_devinit(const char *cpu_type, unsigned int id, 793 uint64_t prom_addr, qemu_irq **cpu_irqs) 794 { 795 CPUState *cs; 796 SPARCCPU *cpu; 797 CPUSPARCState *env; 798 799 cpu = SPARC_CPU(cpu_create(cpu_type)); 800 env = &cpu->env; 801 802 cpu_sparc_set_id(env, id); 803 if (id == 0) { 804 qemu_register_reset(main_cpu_reset, cpu); 805 } else { 806 qemu_register_reset(secondary_cpu_reset, cpu); 807 cs = CPU(cpu); 808 cs->halted = 1; 809 } 810 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 811 env->prom_addr = prom_addr; 812 } 813 814 static void dummy_fdc_tc(void *opaque, int irq, int level) 815 { 816 } 817 818 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, 819 MachineState *machine) 820 { 821 DeviceState *slavio_intctl; 822 unsigned int i; 823 void *iommu, *espdma, *ledma, *nvram; 824 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS], 825 espdma_irq, ledma_irq; 826 qemu_irq esp_reset, dma_enable; 827 qemu_irq fdc_tc; 828 unsigned long kernel_size; 829 DriveInfo *fd[MAX_FD]; 830 FWCfgState *fw_cfg; 831 unsigned int num_vsimms; 832 833 /* init CPUs */ 834 for(i = 0; i < smp_cpus; i++) { 835 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); 836 } 837 838 for (i = smp_cpus; i < MAX_CPUS; i++) 839 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 840 841 842 /* set up devices */ 843 ram_init(0, machine->ram_size, hwdef->max_mem); 844 /* models without ECC don't trap when missing ram is accessed */ 845 if (!hwdef->ecc_base) { 846 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size); 847 } 848 849 prom_init(hwdef->slavio_base, bios_name); 850 851 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 852 hwdef->intctl_base + 0x10000ULL, 853 cpu_irqs); 854 855 for (i = 0; i < 32; i++) { 856 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 857 } 858 for (i = 0; i < MAX_CPUS; i++) { 859 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 860 } 861 862 if (hwdef->idreg_base) { 863 idreg_init(hwdef->idreg_base); 864 } 865 866 if (hwdef->afx_base) { 867 afx_init(hwdef->afx_base); 868 } 869 870 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, 871 slavio_irq[30]); 872 873 if (hwdef->iommu_pad_base) { 874 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 875 Software shouldn't use aliased addresses, neither should it crash 876 when does. Using empty_slot instead of aliasing can help with 877 debugging such accesses */ 878 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); 879 } 880 881 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18], 882 iommu, &espdma_irq, 0); 883 884 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, 885 slavio_irq[16], iommu, &ledma_irq, 1); 886 887 if (graphic_depth != 8 && graphic_depth != 24) { 888 error_report("Unsupported depth: %d", graphic_depth); 889 exit (1); 890 } 891 num_vsimms = 0; 892 if (num_vsimms == 0) { 893 if (vga_interface_type == VGA_CG3) { 894 if (graphic_depth != 8) { 895 error_report("Unsupported depth: %d", graphic_depth); 896 exit(1); 897 } 898 899 if (!(graphic_width == 1024 && graphic_height == 768) && 900 !(graphic_width == 1152 && graphic_height == 900)) { 901 error_report("Unsupported resolution: %d x %d", graphic_width, 902 graphic_height); 903 exit(1); 904 } 905 906 /* sbus irq 5 */ 907 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 908 graphic_width, graphic_height, graphic_depth); 909 } else { 910 /* If no display specified, default to TCX */ 911 if (graphic_depth != 8 && graphic_depth != 24) { 912 error_report("Unsupported depth: %d", graphic_depth); 913 exit(1); 914 } 915 916 if (!(graphic_width == 1024 && graphic_height == 768)) { 917 error_report("Unsupported resolution: %d x %d", 918 graphic_width, graphic_height); 919 exit(1); 920 } 921 922 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 923 graphic_width, graphic_height, graphic_depth); 924 } 925 } 926 927 for (i = num_vsimms; i < MAX_VSIMMS; i++) { 928 /* vsimm registers probed by OBP */ 929 if (hwdef->vsimm[i].reg_base) { 930 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); 931 } 932 } 933 934 if (hwdef->sx_base) { 935 empty_slot_init(hwdef->sx_base, 0x2000); 936 } 937 938 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq); 939 940 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8); 941 942 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 943 944 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14], 945 !machine->enable_graphics, ESCC_CLOCK, 1); 946 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 947 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 948 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], 949 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); 950 951 if (hwdef->apc_base) { 952 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); 953 } 954 955 if (hwdef->fd_base) { 956 /* there is zero or one floppy drive */ 957 memset(fd, 0, sizeof(fd)); 958 fd[0] = drive_get(IF_FLOPPY, 0, 0); 959 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 960 &fdc_tc); 961 } else { 962 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); 963 } 964 965 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 966 slavio_irq[30], fdc_tc); 967 968 esp_init(hwdef->esp_base, 2, 969 espdma_memory_read, espdma_memory_write, 970 espdma, espdma_irq, &esp_reset, &dma_enable); 971 972 qdev_connect_gpio_out(espdma, 0, esp_reset); 973 qdev_connect_gpio_out(espdma, 1, dma_enable); 974 975 if (hwdef->cs_base) { 976 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, 977 slavio_irq[5]); 978 } 979 980 if (hwdef->dbri_base) { 981 /* ISDN chip with attached CS4215 audio codec */ 982 /* prom space */ 983 empty_slot_init(hwdef->dbri_base+0x1000, 0x30); 984 /* reg space */ 985 empty_slot_init(hwdef->dbri_base+0x10000, 0x100); 986 } 987 988 if (hwdef->bpp_base) { 989 /* parallel port */ 990 empty_slot_init(hwdef->bpp_base, 0x20); 991 } 992 993 kernel_size = sun4m_load_kernel(machine->kernel_filename, 994 machine->initrd_filename, 995 machine->ram_size); 996 997 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline, 998 machine->boot_order, machine->ram_size, kernel_size, 999 graphic_width, graphic_height, graphic_depth, 1000 hwdef->nvram_machine_id, "Sun4m"); 1001 1002 if (hwdef->ecc_base) 1003 ecc_init(hwdef->ecc_base, slavio_irq[28], 1004 hwdef->ecc_version); 1005 1006 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 1007 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 1008 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1009 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1010 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1011 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1012 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1013 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1014 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1015 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1016 if (machine->kernel_cmdline) { 1017 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1018 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1019 machine->kernel_cmdline); 1020 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 1021 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1022 strlen(machine->kernel_cmdline) + 1); 1023 } else { 1024 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1025 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1026 } 1027 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1028 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used 1029 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 1030 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1031 } 1032 1033 enum { 1034 ss5_id = 32, 1035 vger_id, 1036 lx_id, 1037 ss4_id, 1038 scls_id, 1039 sbook_id, 1040 ss10_id = 64, 1041 ss20_id, 1042 ss600mp_id, 1043 }; 1044 1045 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1046 /* SS-5 */ 1047 { 1048 .iommu_base = 0x10000000, 1049 .iommu_pad_base = 0x10004000, 1050 .iommu_pad_len = 0x0fffb000, 1051 .tcx_base = 0x50000000, 1052 .cs_base = 0x6c000000, 1053 .slavio_base = 0x70000000, 1054 .ms_kb_base = 0x71000000, 1055 .serial_base = 0x71100000, 1056 .nvram_base = 0x71200000, 1057 .fd_base = 0x71400000, 1058 .counter_base = 0x71d00000, 1059 .intctl_base = 0x71e00000, 1060 .idreg_base = 0x78000000, 1061 .dma_base = 0x78400000, 1062 .esp_base = 0x78800000, 1063 .le_base = 0x78c00000, 1064 .apc_base = 0x6a000000, 1065 .afx_base = 0x6e000000, 1066 .aux1_base = 0x71900000, 1067 .aux2_base = 0x71910000, 1068 .nvram_machine_id = 0x80, 1069 .machine_id = ss5_id, 1070 .iommu_version = 0x05000000, 1071 .max_mem = 0x10000000, 1072 }, 1073 /* SS-10 */ 1074 { 1075 .iommu_base = 0xfe0000000ULL, 1076 .tcx_base = 0xe20000000ULL, 1077 .slavio_base = 0xff0000000ULL, 1078 .ms_kb_base = 0xff1000000ULL, 1079 .serial_base = 0xff1100000ULL, 1080 .nvram_base = 0xff1200000ULL, 1081 .fd_base = 0xff1700000ULL, 1082 .counter_base = 0xff1300000ULL, 1083 .intctl_base = 0xff1400000ULL, 1084 .idreg_base = 0xef0000000ULL, 1085 .dma_base = 0xef0400000ULL, 1086 .esp_base = 0xef0800000ULL, 1087 .le_base = 0xef0c00000ULL, 1088 .apc_base = 0xefa000000ULL, // XXX should not exist 1089 .aux1_base = 0xff1800000ULL, 1090 .aux2_base = 0xff1a01000ULL, 1091 .ecc_base = 0xf00000000ULL, 1092 .ecc_version = 0x10000000, // version 0, implementation 1 1093 .nvram_machine_id = 0x72, 1094 .machine_id = ss10_id, 1095 .iommu_version = 0x03000000, 1096 .max_mem = 0xf00000000ULL, 1097 }, 1098 /* SS-600MP */ 1099 { 1100 .iommu_base = 0xfe0000000ULL, 1101 .tcx_base = 0xe20000000ULL, 1102 .slavio_base = 0xff0000000ULL, 1103 .ms_kb_base = 0xff1000000ULL, 1104 .serial_base = 0xff1100000ULL, 1105 .nvram_base = 0xff1200000ULL, 1106 .counter_base = 0xff1300000ULL, 1107 .intctl_base = 0xff1400000ULL, 1108 .dma_base = 0xef0081000ULL, 1109 .esp_base = 0xef0080000ULL, 1110 .le_base = 0xef0060000ULL, 1111 .apc_base = 0xefa000000ULL, // XXX should not exist 1112 .aux1_base = 0xff1800000ULL, 1113 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1114 .ecc_base = 0xf00000000ULL, 1115 .ecc_version = 0x00000000, // version 0, implementation 0 1116 .nvram_machine_id = 0x71, 1117 .machine_id = ss600mp_id, 1118 .iommu_version = 0x01000000, 1119 .max_mem = 0xf00000000ULL, 1120 }, 1121 /* SS-20 */ 1122 { 1123 .iommu_base = 0xfe0000000ULL, 1124 .tcx_base = 0xe20000000ULL, 1125 .slavio_base = 0xff0000000ULL, 1126 .ms_kb_base = 0xff1000000ULL, 1127 .serial_base = 0xff1100000ULL, 1128 .nvram_base = 0xff1200000ULL, 1129 .fd_base = 0xff1700000ULL, 1130 .counter_base = 0xff1300000ULL, 1131 .intctl_base = 0xff1400000ULL, 1132 .idreg_base = 0xef0000000ULL, 1133 .dma_base = 0xef0400000ULL, 1134 .esp_base = 0xef0800000ULL, 1135 .le_base = 0xef0c00000ULL, 1136 .bpp_base = 0xef4800000ULL, 1137 .apc_base = 0xefa000000ULL, // XXX should not exist 1138 .aux1_base = 0xff1800000ULL, 1139 .aux2_base = 0xff1a01000ULL, 1140 .dbri_base = 0xee0000000ULL, 1141 .sx_base = 0xf80000000ULL, 1142 .vsimm = { 1143 { 1144 .reg_base = 0x9c000000ULL, 1145 .vram_base = 0xfc000000ULL 1146 }, { 1147 .reg_base = 0x90000000ULL, 1148 .vram_base = 0xf0000000ULL 1149 }, { 1150 .reg_base = 0x94000000ULL 1151 }, { 1152 .reg_base = 0x98000000ULL 1153 } 1154 }, 1155 .ecc_base = 0xf00000000ULL, 1156 .ecc_version = 0x20000000, // version 0, implementation 2 1157 .nvram_machine_id = 0x72, 1158 .machine_id = ss20_id, 1159 .iommu_version = 0x13000000, 1160 .max_mem = 0xf00000000ULL, 1161 }, 1162 /* Voyager */ 1163 { 1164 .iommu_base = 0x10000000, 1165 .tcx_base = 0x50000000, 1166 .slavio_base = 0x70000000, 1167 .ms_kb_base = 0x71000000, 1168 .serial_base = 0x71100000, 1169 .nvram_base = 0x71200000, 1170 .fd_base = 0x71400000, 1171 .counter_base = 0x71d00000, 1172 .intctl_base = 0x71e00000, 1173 .idreg_base = 0x78000000, 1174 .dma_base = 0x78400000, 1175 .esp_base = 0x78800000, 1176 .le_base = 0x78c00000, 1177 .apc_base = 0x71300000, // pmc 1178 .aux1_base = 0x71900000, 1179 .aux2_base = 0x71910000, 1180 .nvram_machine_id = 0x80, 1181 .machine_id = vger_id, 1182 .iommu_version = 0x05000000, 1183 .max_mem = 0x10000000, 1184 }, 1185 /* LX */ 1186 { 1187 .iommu_base = 0x10000000, 1188 .iommu_pad_base = 0x10004000, 1189 .iommu_pad_len = 0x0fffb000, 1190 .tcx_base = 0x50000000, 1191 .slavio_base = 0x70000000, 1192 .ms_kb_base = 0x71000000, 1193 .serial_base = 0x71100000, 1194 .nvram_base = 0x71200000, 1195 .fd_base = 0x71400000, 1196 .counter_base = 0x71d00000, 1197 .intctl_base = 0x71e00000, 1198 .idreg_base = 0x78000000, 1199 .dma_base = 0x78400000, 1200 .esp_base = 0x78800000, 1201 .le_base = 0x78c00000, 1202 .aux1_base = 0x71900000, 1203 .aux2_base = 0x71910000, 1204 .nvram_machine_id = 0x80, 1205 .machine_id = lx_id, 1206 .iommu_version = 0x04000000, 1207 .max_mem = 0x10000000, 1208 }, 1209 /* SS-4 */ 1210 { 1211 .iommu_base = 0x10000000, 1212 .tcx_base = 0x50000000, 1213 .cs_base = 0x6c000000, 1214 .slavio_base = 0x70000000, 1215 .ms_kb_base = 0x71000000, 1216 .serial_base = 0x71100000, 1217 .nvram_base = 0x71200000, 1218 .fd_base = 0x71400000, 1219 .counter_base = 0x71d00000, 1220 .intctl_base = 0x71e00000, 1221 .idreg_base = 0x78000000, 1222 .dma_base = 0x78400000, 1223 .esp_base = 0x78800000, 1224 .le_base = 0x78c00000, 1225 .apc_base = 0x6a000000, 1226 .aux1_base = 0x71900000, 1227 .aux2_base = 0x71910000, 1228 .nvram_machine_id = 0x80, 1229 .machine_id = ss4_id, 1230 .iommu_version = 0x05000000, 1231 .max_mem = 0x10000000, 1232 }, 1233 /* SPARCClassic */ 1234 { 1235 .iommu_base = 0x10000000, 1236 .tcx_base = 0x50000000, 1237 .slavio_base = 0x70000000, 1238 .ms_kb_base = 0x71000000, 1239 .serial_base = 0x71100000, 1240 .nvram_base = 0x71200000, 1241 .fd_base = 0x71400000, 1242 .counter_base = 0x71d00000, 1243 .intctl_base = 0x71e00000, 1244 .idreg_base = 0x78000000, 1245 .dma_base = 0x78400000, 1246 .esp_base = 0x78800000, 1247 .le_base = 0x78c00000, 1248 .apc_base = 0x6a000000, 1249 .aux1_base = 0x71900000, 1250 .aux2_base = 0x71910000, 1251 .nvram_machine_id = 0x80, 1252 .machine_id = scls_id, 1253 .iommu_version = 0x05000000, 1254 .max_mem = 0x10000000, 1255 }, 1256 /* SPARCbook */ 1257 { 1258 .iommu_base = 0x10000000, 1259 .tcx_base = 0x50000000, // XXX 1260 .slavio_base = 0x70000000, 1261 .ms_kb_base = 0x71000000, 1262 .serial_base = 0x71100000, 1263 .nvram_base = 0x71200000, 1264 .fd_base = 0x71400000, 1265 .counter_base = 0x71d00000, 1266 .intctl_base = 0x71e00000, 1267 .idreg_base = 0x78000000, 1268 .dma_base = 0x78400000, 1269 .esp_base = 0x78800000, 1270 .le_base = 0x78c00000, 1271 .apc_base = 0x6a000000, 1272 .aux1_base = 0x71900000, 1273 .aux2_base = 0x71910000, 1274 .nvram_machine_id = 0x80, 1275 .machine_id = sbook_id, 1276 .iommu_version = 0x05000000, 1277 .max_mem = 0x10000000, 1278 }, 1279 }; 1280 1281 /* SPARCstation 5 hardware initialisation */ 1282 static void ss5_init(MachineState *machine) 1283 { 1284 sun4m_hw_init(&sun4m_hwdefs[0], machine); 1285 } 1286 1287 /* SPARCstation 10 hardware initialisation */ 1288 static void ss10_init(MachineState *machine) 1289 { 1290 sun4m_hw_init(&sun4m_hwdefs[1], machine); 1291 } 1292 1293 /* SPARCserver 600MP hardware initialisation */ 1294 static void ss600mp_init(MachineState *machine) 1295 { 1296 sun4m_hw_init(&sun4m_hwdefs[2], machine); 1297 } 1298 1299 /* SPARCstation 20 hardware initialisation */ 1300 static void ss20_init(MachineState *machine) 1301 { 1302 sun4m_hw_init(&sun4m_hwdefs[3], machine); 1303 } 1304 1305 /* SPARCstation Voyager hardware initialisation */ 1306 static void vger_init(MachineState *machine) 1307 { 1308 sun4m_hw_init(&sun4m_hwdefs[4], machine); 1309 } 1310 1311 /* SPARCstation LX hardware initialisation */ 1312 static void ss_lx_init(MachineState *machine) 1313 { 1314 sun4m_hw_init(&sun4m_hwdefs[5], machine); 1315 } 1316 1317 /* SPARCstation 4 hardware initialisation */ 1318 static void ss4_init(MachineState *machine) 1319 { 1320 sun4m_hw_init(&sun4m_hwdefs[6], machine); 1321 } 1322 1323 /* SPARCClassic hardware initialisation */ 1324 static void scls_init(MachineState *machine) 1325 { 1326 sun4m_hw_init(&sun4m_hwdefs[7], machine); 1327 } 1328 1329 /* SPARCbook hardware initialisation */ 1330 static void sbook_init(MachineState *machine) 1331 { 1332 sun4m_hw_init(&sun4m_hwdefs[8], machine); 1333 } 1334 1335 static void ss5_class_init(ObjectClass *oc, void *data) 1336 { 1337 MachineClass *mc = MACHINE_CLASS(oc); 1338 1339 mc->desc = "Sun4m platform, SPARCstation 5"; 1340 mc->init = ss5_init; 1341 mc->block_default_type = IF_SCSI; 1342 mc->is_default = 1; 1343 mc->default_boot_order = "c"; 1344 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1345 } 1346 1347 static const TypeInfo ss5_type = { 1348 .name = MACHINE_TYPE_NAME("SS-5"), 1349 .parent = TYPE_MACHINE, 1350 .class_init = ss5_class_init, 1351 }; 1352 1353 static void ss10_class_init(ObjectClass *oc, void *data) 1354 { 1355 MachineClass *mc = MACHINE_CLASS(oc); 1356 1357 mc->desc = "Sun4m platform, SPARCstation 10"; 1358 mc->init = ss10_init; 1359 mc->block_default_type = IF_SCSI; 1360 mc->max_cpus = 4; 1361 mc->default_boot_order = "c"; 1362 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1363 } 1364 1365 static const TypeInfo ss10_type = { 1366 .name = MACHINE_TYPE_NAME("SS-10"), 1367 .parent = TYPE_MACHINE, 1368 .class_init = ss10_class_init, 1369 }; 1370 1371 static void ss600mp_class_init(ObjectClass *oc, void *data) 1372 { 1373 MachineClass *mc = MACHINE_CLASS(oc); 1374 1375 mc->desc = "Sun4m platform, SPARCserver 600MP"; 1376 mc->init = ss600mp_init; 1377 mc->block_default_type = IF_SCSI; 1378 mc->max_cpus = 4; 1379 mc->default_boot_order = "c"; 1380 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1381 } 1382 1383 static const TypeInfo ss600mp_type = { 1384 .name = MACHINE_TYPE_NAME("SS-600MP"), 1385 .parent = TYPE_MACHINE, 1386 .class_init = ss600mp_class_init, 1387 }; 1388 1389 static void ss20_class_init(ObjectClass *oc, void *data) 1390 { 1391 MachineClass *mc = MACHINE_CLASS(oc); 1392 1393 mc->desc = "Sun4m platform, SPARCstation 20"; 1394 mc->init = ss20_init; 1395 mc->block_default_type = IF_SCSI; 1396 mc->max_cpus = 4; 1397 mc->default_boot_order = "c"; 1398 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1399 } 1400 1401 static const TypeInfo ss20_type = { 1402 .name = MACHINE_TYPE_NAME("SS-20"), 1403 .parent = TYPE_MACHINE, 1404 .class_init = ss20_class_init, 1405 }; 1406 1407 static void voyager_class_init(ObjectClass *oc, void *data) 1408 { 1409 MachineClass *mc = MACHINE_CLASS(oc); 1410 1411 mc->desc = "Sun4m platform, SPARCstation Voyager"; 1412 mc->init = vger_init; 1413 mc->block_default_type = IF_SCSI; 1414 mc->default_boot_order = "c"; 1415 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1416 } 1417 1418 static const TypeInfo voyager_type = { 1419 .name = MACHINE_TYPE_NAME("Voyager"), 1420 .parent = TYPE_MACHINE, 1421 .class_init = voyager_class_init, 1422 }; 1423 1424 static void ss_lx_class_init(ObjectClass *oc, void *data) 1425 { 1426 MachineClass *mc = MACHINE_CLASS(oc); 1427 1428 mc->desc = "Sun4m platform, SPARCstation LX"; 1429 mc->init = ss_lx_init; 1430 mc->block_default_type = IF_SCSI; 1431 mc->default_boot_order = "c"; 1432 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1433 } 1434 1435 static const TypeInfo ss_lx_type = { 1436 .name = MACHINE_TYPE_NAME("LX"), 1437 .parent = TYPE_MACHINE, 1438 .class_init = ss_lx_class_init, 1439 }; 1440 1441 static void ss4_class_init(ObjectClass *oc, void *data) 1442 { 1443 MachineClass *mc = MACHINE_CLASS(oc); 1444 1445 mc->desc = "Sun4m platform, SPARCstation 4"; 1446 mc->init = ss4_init; 1447 mc->block_default_type = IF_SCSI; 1448 mc->default_boot_order = "c"; 1449 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1450 } 1451 1452 static const TypeInfo ss4_type = { 1453 .name = MACHINE_TYPE_NAME("SS-4"), 1454 .parent = TYPE_MACHINE, 1455 .class_init = ss4_class_init, 1456 }; 1457 1458 static void scls_class_init(ObjectClass *oc, void *data) 1459 { 1460 MachineClass *mc = MACHINE_CLASS(oc); 1461 1462 mc->desc = "Sun4m platform, SPARCClassic"; 1463 mc->init = scls_init; 1464 mc->block_default_type = IF_SCSI; 1465 mc->default_boot_order = "c"; 1466 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1467 } 1468 1469 static const TypeInfo scls_type = { 1470 .name = MACHINE_TYPE_NAME("SPARCClassic"), 1471 .parent = TYPE_MACHINE, 1472 .class_init = scls_class_init, 1473 }; 1474 1475 static void sbook_class_init(ObjectClass *oc, void *data) 1476 { 1477 MachineClass *mc = MACHINE_CLASS(oc); 1478 1479 mc->desc = "Sun4m platform, SPARCbook"; 1480 mc->init = sbook_init; 1481 mc->block_default_type = IF_SCSI; 1482 mc->default_boot_order = "c"; 1483 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1484 } 1485 1486 static const TypeInfo sbook_type = { 1487 .name = MACHINE_TYPE_NAME("SPARCbook"), 1488 .parent = TYPE_MACHINE, 1489 .class_init = sbook_class_init, 1490 }; 1491 1492 static void sun4m_register_types(void) 1493 { 1494 type_register_static(&idreg_info); 1495 type_register_static(&afx_info); 1496 type_register_static(&prom_info); 1497 type_register_static(&ram_info); 1498 1499 type_register_static(&ss5_type); 1500 type_register_static(&ss10_type); 1501 type_register_static(&ss600mp_type); 1502 type_register_static(&ss20_type); 1503 type_register_static(&voyager_type); 1504 type_register_static(&ss_lx_type); 1505 type_register_static(&ss4_type); 1506 type_register_static(&scls_type); 1507 type_register_static(&sbook_type); 1508 } 1509 1510 type_init(sun4m_register_types) 1511