1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/sysbus.h" 29 #include "qemu/error-report.h" 30 #include "qemu/timer.h" 31 #include "hw/sparc/sun4m.h" 32 #include "hw/timer/m48t59.h" 33 #include "hw/sparc/sparc32_dma.h" 34 #include "hw/block/fdc.h" 35 #include "sysemu/sysemu.h" 36 #include "net/net.h" 37 #include "hw/boards.h" 38 #include "hw/nvram/openbios_firmware_abi.h" 39 #include "hw/scsi/esp.h" 40 #include "hw/i386/pc.h" 41 #include "hw/isa/isa.h" 42 #include "hw/nvram/fw_cfg.h" 43 #include "hw/char/escc.h" 44 #include "hw/empty_slot.h" 45 #include "hw/loader.h" 46 #include "elf.h" 47 #include "sysemu/block-backend.h" 48 #include "trace.h" 49 50 /* 51 * Sun4m architecture was used in the following machines: 52 * 53 * SPARCserver 6xxMP/xx 54 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 55 * SPARCclassic X (4/10) 56 * SPARCstation LX/ZX (4/30) 57 * SPARCstation Voyager 58 * SPARCstation 10/xx, SPARCserver 10/xx 59 * SPARCstation 5, SPARCserver 5 60 * SPARCstation 20/xx, SPARCserver 20 61 * SPARCstation 4 62 * 63 * See for example: http://www.sunhelp.org/faq/sunref1.html 64 */ 65 66 #define KERNEL_LOAD_ADDR 0x00004000 67 #define CMDLINE_ADDR 0x007ff000 68 #define INITRD_LOAD_ADDR 0x00800000 69 #define PROM_SIZE_MAX (1024 * 1024) 70 #define PROM_VADDR 0xffd00000 71 #define PROM_FILENAME "openbios-sparc32" 72 #define CFG_ADDR 0xd00000510ULL 73 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 74 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 75 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 76 77 #define MAX_CPUS 16 78 #define MAX_PILS 16 79 #define MAX_VSIMMS 4 80 81 #define ESCC_CLOCK 4915200 82 83 struct sun4m_hwdef { 84 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 85 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 86 hwaddr serial_base, fd_base; 87 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 88 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 89 hwaddr bpp_base, dbri_base, sx_base; 90 struct { 91 hwaddr reg_base, vram_base; 92 } vsimm[MAX_VSIMMS]; 93 hwaddr ecc_base; 94 uint64_t max_mem; 95 const char * const default_cpu_model; 96 uint32_t ecc_version; 97 uint32_t iommu_version; 98 uint16_t machine_id; 99 uint8_t nvram_machine_id; 100 }; 101 102 void DMA_init(ISABus *bus, int high_page_enable) 103 { 104 } 105 106 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 107 Error **errp) 108 { 109 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 110 } 111 112 static void nvram_init(Nvram *nvram, uint8_t *macaddr, 113 const char *cmdline, const char *boot_devices, 114 ram_addr_t RAM_size, uint32_t kernel_size, 115 int width, int height, int depth, 116 int nvram_machine_id, const char *arch) 117 { 118 unsigned int i; 119 uint32_t start, end; 120 uint8_t image[0x1ff0]; 121 struct OpenBIOS_nvpart_v1 *part_header; 122 NvramClass *k = NVRAM_GET_CLASS(nvram); 123 124 memset(image, '\0', sizeof(image)); 125 126 start = 0; 127 128 // OpenBIOS nvram variables 129 // Variable partition 130 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 131 part_header->signature = OPENBIOS_PART_SYSTEM; 132 pstrcpy(part_header->name, sizeof(part_header->name), "system"); 133 134 end = start + sizeof(struct OpenBIOS_nvpart_v1); 135 for (i = 0; i < nb_prom_envs; i++) 136 end = OpenBIOS_set_var(image, end, prom_envs[i]); 137 138 // End marker 139 image[end++] = '\0'; 140 141 end = start + ((end - start + 15) & ~15); 142 OpenBIOS_finish_partition(part_header, end - start); 143 144 // free partition 145 start = end; 146 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 147 part_header->signature = OPENBIOS_PART_FREE; 148 pstrcpy(part_header->name, sizeof(part_header->name), "free"); 149 150 end = 0x1fd0; 151 OpenBIOS_finish_partition(part_header, end - start); 152 153 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 154 nvram_machine_id); 155 156 for (i = 0; i < sizeof(image); i++) { 157 (k->write)(nvram, i, image[i]); 158 } 159 } 160 161 static DeviceState *slavio_intctl; 162 163 void sun4m_hmp_info_pic(Monitor *mon, const QDict *qdict) 164 { 165 if (slavio_intctl) 166 slavio_pic_info(mon, slavio_intctl); 167 } 168 169 void sun4m_hmp_info_irq(Monitor *mon, const QDict *qdict) 170 { 171 if (slavio_intctl) 172 slavio_irq_info(mon, slavio_intctl); 173 } 174 175 void cpu_check_irqs(CPUSPARCState *env) 176 { 177 CPUState *cs; 178 179 if (env->pil_in && (env->interrupt_index == 0 || 180 (env->interrupt_index & ~15) == TT_EXTINT)) { 181 unsigned int i; 182 183 for (i = 15; i > 0; i--) { 184 if (env->pil_in & (1 << i)) { 185 int old_interrupt = env->interrupt_index; 186 187 env->interrupt_index = TT_EXTINT | i; 188 if (old_interrupt != env->interrupt_index) { 189 cs = CPU(sparc_env_get_cpu(env)); 190 trace_sun4m_cpu_interrupt(i); 191 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 192 } 193 break; 194 } 195 } 196 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 197 cs = CPU(sparc_env_get_cpu(env)); 198 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 199 env->interrupt_index = 0; 200 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 201 } 202 } 203 204 static void cpu_kick_irq(SPARCCPU *cpu) 205 { 206 CPUSPARCState *env = &cpu->env; 207 CPUState *cs = CPU(cpu); 208 209 cs->halted = 0; 210 cpu_check_irqs(env); 211 qemu_cpu_kick(cs); 212 } 213 214 static void cpu_set_irq(void *opaque, int irq, int level) 215 { 216 SPARCCPU *cpu = opaque; 217 CPUSPARCState *env = &cpu->env; 218 219 if (level) { 220 trace_sun4m_cpu_set_irq_raise(irq); 221 env->pil_in |= 1 << irq; 222 cpu_kick_irq(cpu); 223 } else { 224 trace_sun4m_cpu_set_irq_lower(irq); 225 env->pil_in &= ~(1 << irq); 226 cpu_check_irqs(env); 227 } 228 } 229 230 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 231 { 232 } 233 234 static void main_cpu_reset(void *opaque) 235 { 236 SPARCCPU *cpu = opaque; 237 CPUState *cs = CPU(cpu); 238 239 cpu_reset(cs); 240 cs->halted = 0; 241 } 242 243 static void secondary_cpu_reset(void *opaque) 244 { 245 SPARCCPU *cpu = opaque; 246 CPUState *cs = CPU(cpu); 247 248 cpu_reset(cs); 249 cs->halted = 1; 250 } 251 252 static void cpu_halt_signal(void *opaque, int irq, int level) 253 { 254 if (level && current_cpu) { 255 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 256 } 257 } 258 259 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 260 { 261 return addr - 0xf0000000ULL; 262 } 263 264 static unsigned long sun4m_load_kernel(const char *kernel_filename, 265 const char *initrd_filename, 266 ram_addr_t RAM_size) 267 { 268 int linux_boot; 269 unsigned int i; 270 long initrd_size, kernel_size; 271 uint8_t *ptr; 272 273 linux_boot = (kernel_filename != NULL); 274 275 kernel_size = 0; 276 if (linux_boot) { 277 int bswap_needed; 278 279 #ifdef BSWAP_NEEDED 280 bswap_needed = 1; 281 #else 282 bswap_needed = 0; 283 #endif 284 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 285 NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 286 if (kernel_size < 0) 287 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 288 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 289 TARGET_PAGE_SIZE); 290 if (kernel_size < 0) 291 kernel_size = load_image_targphys(kernel_filename, 292 KERNEL_LOAD_ADDR, 293 RAM_size - KERNEL_LOAD_ADDR); 294 if (kernel_size < 0) { 295 fprintf(stderr, "qemu: could not load kernel '%s'\n", 296 kernel_filename); 297 exit(1); 298 } 299 300 /* load initrd */ 301 initrd_size = 0; 302 if (initrd_filename) { 303 initrd_size = load_image_targphys(initrd_filename, 304 INITRD_LOAD_ADDR, 305 RAM_size - INITRD_LOAD_ADDR); 306 if (initrd_size < 0) { 307 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 308 initrd_filename); 309 exit(1); 310 } 311 } 312 if (initrd_size > 0) { 313 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 314 ptr = rom_ptr(KERNEL_LOAD_ADDR + i); 315 if (ldl_p(ptr) == 0x48647253) { // HdrS 316 stl_p(ptr + 16, INITRD_LOAD_ADDR); 317 stl_p(ptr + 20, initrd_size); 318 break; 319 } 320 } 321 } 322 } 323 return kernel_size; 324 } 325 326 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 327 { 328 DeviceState *dev; 329 SysBusDevice *s; 330 331 dev = qdev_create(NULL, "iommu"); 332 qdev_prop_set_uint32(dev, "version", version); 333 qdev_init_nofail(dev); 334 s = SYS_BUS_DEVICE(dev); 335 sysbus_connect_irq(s, 0, irq); 336 sysbus_mmio_map(s, 0, addr); 337 338 return s; 339 } 340 341 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq, 342 void *iommu, qemu_irq *dev_irq, int is_ledma) 343 { 344 DeviceState *dev; 345 SysBusDevice *s; 346 347 dev = qdev_create(NULL, "sparc32_dma"); 348 qdev_prop_set_ptr(dev, "iommu_opaque", iommu); 349 qdev_prop_set_uint32(dev, "is_ledma", is_ledma); 350 qdev_init_nofail(dev); 351 s = SYS_BUS_DEVICE(dev); 352 sysbus_connect_irq(s, 0, parent_irq); 353 *dev_irq = qdev_get_gpio_in(dev, 0); 354 sysbus_mmio_map(s, 0, daddr); 355 356 return s; 357 } 358 359 static void lance_init(NICInfo *nd, hwaddr leaddr, 360 void *dma_opaque, qemu_irq irq) 361 { 362 DeviceState *dev; 363 SysBusDevice *s; 364 qemu_irq reset; 365 366 qemu_check_nic_model(&nd_table[0], "lance"); 367 368 dev = qdev_create(NULL, "lance"); 369 qdev_set_nic_properties(dev, nd); 370 qdev_prop_set_ptr(dev, "dma", dma_opaque); 371 qdev_init_nofail(dev); 372 s = SYS_BUS_DEVICE(dev); 373 sysbus_mmio_map(s, 0, leaddr); 374 sysbus_connect_irq(s, 0, irq); 375 reset = qdev_get_gpio_in(dev, 0); 376 qdev_connect_gpio_out(dma_opaque, 0, reset); 377 } 378 379 static DeviceState *slavio_intctl_init(hwaddr addr, 380 hwaddr addrg, 381 qemu_irq **parent_irq) 382 { 383 DeviceState *dev; 384 SysBusDevice *s; 385 unsigned int i, j; 386 387 dev = qdev_create(NULL, "slavio_intctl"); 388 qdev_init_nofail(dev); 389 390 s = SYS_BUS_DEVICE(dev); 391 392 for (i = 0; i < MAX_CPUS; i++) { 393 for (j = 0; j < MAX_PILS; j++) { 394 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 395 } 396 } 397 sysbus_mmio_map(s, 0, addrg); 398 for (i = 0; i < MAX_CPUS; i++) { 399 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 400 } 401 402 return dev; 403 } 404 405 #define SYS_TIMER_OFFSET 0x10000ULL 406 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 407 408 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 409 qemu_irq *cpu_irqs, unsigned int num_cpus) 410 { 411 DeviceState *dev; 412 SysBusDevice *s; 413 unsigned int i; 414 415 dev = qdev_create(NULL, "slavio_timer"); 416 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 417 qdev_init_nofail(dev); 418 s = SYS_BUS_DEVICE(dev); 419 sysbus_connect_irq(s, 0, master_irq); 420 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 421 422 for (i = 0; i < MAX_CPUS; i++) { 423 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 424 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 425 } 426 } 427 428 static qemu_irq slavio_system_powerdown; 429 430 static void slavio_powerdown_req(Notifier *n, void *opaque) 431 { 432 qemu_irq_raise(slavio_system_powerdown); 433 } 434 435 static Notifier slavio_system_powerdown_notifier = { 436 .notify = slavio_powerdown_req 437 }; 438 439 #define MISC_LEDS 0x01600000 440 #define MISC_CFG 0x01800000 441 #define MISC_DIAG 0x01a00000 442 #define MISC_MDM 0x01b00000 443 #define MISC_SYS 0x01f00000 444 445 static void slavio_misc_init(hwaddr base, 446 hwaddr aux1_base, 447 hwaddr aux2_base, qemu_irq irq, 448 qemu_irq fdc_tc) 449 { 450 DeviceState *dev; 451 SysBusDevice *s; 452 453 dev = qdev_create(NULL, "slavio_misc"); 454 qdev_init_nofail(dev); 455 s = SYS_BUS_DEVICE(dev); 456 if (base) { 457 /* 8 bit registers */ 458 /* Slavio control */ 459 sysbus_mmio_map(s, 0, base + MISC_CFG); 460 /* Diagnostics */ 461 sysbus_mmio_map(s, 1, base + MISC_DIAG); 462 /* Modem control */ 463 sysbus_mmio_map(s, 2, base + MISC_MDM); 464 /* 16 bit registers */ 465 /* ss600mp diag LEDs */ 466 sysbus_mmio_map(s, 3, base + MISC_LEDS); 467 /* 32 bit registers */ 468 /* System control */ 469 sysbus_mmio_map(s, 4, base + MISC_SYS); 470 } 471 if (aux1_base) { 472 /* AUX 1 (Misc System Functions) */ 473 sysbus_mmio_map(s, 5, aux1_base); 474 } 475 if (aux2_base) { 476 /* AUX 2 (Software Powerdown Control) */ 477 sysbus_mmio_map(s, 6, aux2_base); 478 } 479 sysbus_connect_irq(s, 0, irq); 480 sysbus_connect_irq(s, 1, fdc_tc); 481 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 482 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 483 } 484 485 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 486 { 487 DeviceState *dev; 488 SysBusDevice *s; 489 490 dev = qdev_create(NULL, "eccmemctl"); 491 qdev_prop_set_uint32(dev, "version", version); 492 qdev_init_nofail(dev); 493 s = SYS_BUS_DEVICE(dev); 494 sysbus_connect_irq(s, 0, irq); 495 sysbus_mmio_map(s, 0, base); 496 if (version == 0) { // SS-600MP only 497 sysbus_mmio_map(s, 1, base + 0x1000); 498 } 499 } 500 501 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 502 { 503 DeviceState *dev; 504 SysBusDevice *s; 505 506 dev = qdev_create(NULL, "apc"); 507 qdev_init_nofail(dev); 508 s = SYS_BUS_DEVICE(dev); 509 /* Power management (APC) XXX: not a Slavio device */ 510 sysbus_mmio_map(s, 0, power_base); 511 sysbus_connect_irq(s, 0, cpu_halt); 512 } 513 514 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 515 int height, int depth) 516 { 517 DeviceState *dev; 518 SysBusDevice *s; 519 520 dev = qdev_create(NULL, "SUNW,tcx"); 521 qdev_prop_set_uint32(dev, "vram_size", vram_size); 522 qdev_prop_set_uint16(dev, "width", width); 523 qdev_prop_set_uint16(dev, "height", height); 524 qdev_prop_set_uint16(dev, "depth", depth); 525 qdev_prop_set_uint64(dev, "prom_addr", addr); 526 qdev_init_nofail(dev); 527 s = SYS_BUS_DEVICE(dev); 528 529 /* 10/ROM : FCode ROM */ 530 sysbus_mmio_map(s, 0, addr); 531 /* 2/STIP : Stipple */ 532 sysbus_mmio_map(s, 1, addr + 0x04000000ULL); 533 /* 3/BLIT : Blitter */ 534 sysbus_mmio_map(s, 2, addr + 0x06000000ULL); 535 /* 5/RSTIP : Raw Stipple */ 536 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); 537 /* 6/RBLIT : Raw Blitter */ 538 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); 539 /* 7/TEC : Transform Engine */ 540 sysbus_mmio_map(s, 5, addr + 0x00700000ULL); 541 /* 8/CMAP : DAC */ 542 sysbus_mmio_map(s, 6, addr + 0x00200000ULL); 543 /* 9/THC : */ 544 if (depth == 8) { 545 sysbus_mmio_map(s, 7, addr + 0x00300000ULL); 546 } else { 547 sysbus_mmio_map(s, 7, addr + 0x00301000ULL); 548 } 549 /* 11/DHC : */ 550 sysbus_mmio_map(s, 8, addr + 0x00240000ULL); 551 /* 12/ALT : */ 552 sysbus_mmio_map(s, 9, addr + 0x00280000ULL); 553 /* 0/DFB8 : 8-bit plane */ 554 sysbus_mmio_map(s, 10, addr + 0x00800000ULL); 555 /* 1/DFB24 : 24bit plane */ 556 sysbus_mmio_map(s, 11, addr + 0x02000000ULL); 557 /* 4/RDFB32: Raw framebuffer. Control plane */ 558 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); 559 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 560 if (depth == 8) { 561 sysbus_mmio_map(s, 13, addr + 0x00301000ULL); 562 } 563 564 sysbus_connect_irq(s, 0, irq); 565 } 566 567 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 568 int height, int depth) 569 { 570 DeviceState *dev; 571 SysBusDevice *s; 572 573 dev = qdev_create(NULL, "cgthree"); 574 qdev_prop_set_uint32(dev, "vram-size", vram_size); 575 qdev_prop_set_uint16(dev, "width", width); 576 qdev_prop_set_uint16(dev, "height", height); 577 qdev_prop_set_uint16(dev, "depth", depth); 578 qdev_prop_set_uint64(dev, "prom-addr", addr); 579 qdev_init_nofail(dev); 580 s = SYS_BUS_DEVICE(dev); 581 582 /* FCode ROM */ 583 sysbus_mmio_map(s, 0, addr); 584 /* DAC */ 585 sysbus_mmio_map(s, 1, addr + 0x400000ULL); 586 /* 8-bit plane */ 587 sysbus_mmio_map(s, 2, addr + 0x800000ULL); 588 589 sysbus_connect_irq(s, 0, irq); 590 } 591 592 /* NCR89C100/MACIO Internal ID register */ 593 594 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 595 596 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 597 598 static void idreg_init(hwaddr addr) 599 { 600 DeviceState *dev; 601 SysBusDevice *s; 602 603 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER); 604 qdev_init_nofail(dev); 605 s = SYS_BUS_DEVICE(dev); 606 607 sysbus_mmio_map(s, 0, addr); 608 cpu_physical_memory_write_rom(&address_space_memory, 609 addr, idreg_data, sizeof(idreg_data)); 610 } 611 612 #define MACIO_ID_REGISTER(obj) \ 613 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER) 614 615 typedef struct IDRegState { 616 SysBusDevice parent_obj; 617 618 MemoryRegion mem; 619 } IDRegState; 620 621 static int idreg_init1(SysBusDevice *dev) 622 { 623 IDRegState *s = MACIO_ID_REGISTER(dev); 624 625 memory_region_init_ram(&s->mem, OBJECT(s), 626 "sun4m.idreg", sizeof(idreg_data), &error_fatal); 627 vmstate_register_ram_global(&s->mem); 628 memory_region_set_readonly(&s->mem, true); 629 sysbus_init_mmio(dev, &s->mem); 630 return 0; 631 } 632 633 static void idreg_class_init(ObjectClass *klass, void *data) 634 { 635 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 636 637 k->init = idreg_init1; 638 } 639 640 static const TypeInfo idreg_info = { 641 .name = TYPE_MACIO_ID_REGISTER, 642 .parent = TYPE_SYS_BUS_DEVICE, 643 .instance_size = sizeof(IDRegState), 644 .class_init = idreg_class_init, 645 }; 646 647 #define TYPE_TCX_AFX "tcx_afx" 648 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX) 649 650 typedef struct AFXState { 651 SysBusDevice parent_obj; 652 653 MemoryRegion mem; 654 } AFXState; 655 656 /* SS-5 TCX AFX register */ 657 static void afx_init(hwaddr addr) 658 { 659 DeviceState *dev; 660 SysBusDevice *s; 661 662 dev = qdev_create(NULL, TYPE_TCX_AFX); 663 qdev_init_nofail(dev); 664 s = SYS_BUS_DEVICE(dev); 665 666 sysbus_mmio_map(s, 0, addr); 667 } 668 669 static int afx_init1(SysBusDevice *dev) 670 { 671 AFXState *s = TCX_AFX(dev); 672 673 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4, &error_fatal); 674 vmstate_register_ram_global(&s->mem); 675 sysbus_init_mmio(dev, &s->mem); 676 return 0; 677 } 678 679 static void afx_class_init(ObjectClass *klass, void *data) 680 { 681 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 682 683 k->init = afx_init1; 684 } 685 686 static const TypeInfo afx_info = { 687 .name = TYPE_TCX_AFX, 688 .parent = TYPE_SYS_BUS_DEVICE, 689 .instance_size = sizeof(AFXState), 690 .class_init = afx_class_init, 691 }; 692 693 #define TYPE_OPENPROM "openprom" 694 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 695 696 typedef struct PROMState { 697 SysBusDevice parent_obj; 698 699 MemoryRegion prom; 700 } PROMState; 701 702 /* Boot PROM (OpenBIOS) */ 703 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 704 { 705 hwaddr *base_addr = (hwaddr *)opaque; 706 return addr + *base_addr - PROM_VADDR; 707 } 708 709 static void prom_init(hwaddr addr, const char *bios_name) 710 { 711 DeviceState *dev; 712 SysBusDevice *s; 713 char *filename; 714 int ret; 715 716 dev = qdev_create(NULL, TYPE_OPENPROM); 717 qdev_init_nofail(dev); 718 s = SYS_BUS_DEVICE(dev); 719 720 sysbus_mmio_map(s, 0, addr); 721 722 /* load boot prom */ 723 if (bios_name == NULL) { 724 bios_name = PROM_FILENAME; 725 } 726 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 727 if (filename) { 728 ret = load_elf(filename, translate_prom_address, &addr, NULL, 729 NULL, NULL, 1, EM_SPARC, 0, 0); 730 if (ret < 0 || ret > PROM_SIZE_MAX) { 731 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 732 } 733 g_free(filename); 734 } else { 735 ret = -1; 736 } 737 if (ret < 0 || ret > PROM_SIZE_MAX) { 738 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 739 exit(1); 740 } 741 } 742 743 static int prom_init1(SysBusDevice *dev) 744 { 745 PROMState *s = OPENPROM(dev); 746 747 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX, 748 &error_fatal); 749 vmstate_register_ram_global(&s->prom); 750 memory_region_set_readonly(&s->prom, true); 751 sysbus_init_mmio(dev, &s->prom); 752 return 0; 753 } 754 755 static Property prom_properties[] = { 756 {/* end of property list */}, 757 }; 758 759 static void prom_class_init(ObjectClass *klass, void *data) 760 { 761 DeviceClass *dc = DEVICE_CLASS(klass); 762 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 763 764 k->init = prom_init1; 765 dc->props = prom_properties; 766 } 767 768 static const TypeInfo prom_info = { 769 .name = TYPE_OPENPROM, 770 .parent = TYPE_SYS_BUS_DEVICE, 771 .instance_size = sizeof(PROMState), 772 .class_init = prom_class_init, 773 }; 774 775 #define TYPE_SUN4M_MEMORY "memory" 776 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY) 777 778 typedef struct RamDevice { 779 SysBusDevice parent_obj; 780 781 MemoryRegion ram; 782 uint64_t size; 783 } RamDevice; 784 785 /* System RAM */ 786 static int ram_init1(SysBusDevice *dev) 787 { 788 RamDevice *d = SUN4M_RAM(dev); 789 790 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram", 791 d->size); 792 sysbus_init_mmio(dev, &d->ram); 793 return 0; 794 } 795 796 static void ram_init(hwaddr addr, ram_addr_t RAM_size, 797 uint64_t max_mem) 798 { 799 DeviceState *dev; 800 SysBusDevice *s; 801 RamDevice *d; 802 803 /* allocate RAM */ 804 if ((uint64_t)RAM_size > max_mem) { 805 fprintf(stderr, 806 "qemu: Too much memory for this machine: %d, maximum %d\n", 807 (unsigned int)(RAM_size / (1024 * 1024)), 808 (unsigned int)(max_mem / (1024 * 1024))); 809 exit(1); 810 } 811 dev = qdev_create(NULL, "memory"); 812 s = SYS_BUS_DEVICE(dev); 813 814 d = SUN4M_RAM(dev); 815 d->size = RAM_size; 816 qdev_init_nofail(dev); 817 818 sysbus_mmio_map(s, 0, addr); 819 } 820 821 static Property ram_properties[] = { 822 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 823 DEFINE_PROP_END_OF_LIST(), 824 }; 825 826 static void ram_class_init(ObjectClass *klass, void *data) 827 { 828 DeviceClass *dc = DEVICE_CLASS(klass); 829 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 830 831 k->init = ram_init1; 832 dc->props = ram_properties; 833 } 834 835 static const TypeInfo ram_info = { 836 .name = TYPE_SUN4M_MEMORY, 837 .parent = TYPE_SYS_BUS_DEVICE, 838 .instance_size = sizeof(RamDevice), 839 .class_init = ram_class_init, 840 }; 841 842 static void cpu_devinit(const char *cpu_model, unsigned int id, 843 uint64_t prom_addr, qemu_irq **cpu_irqs) 844 { 845 CPUState *cs; 846 SPARCCPU *cpu; 847 CPUSPARCState *env; 848 849 cpu = cpu_sparc_init(cpu_model); 850 if (cpu == NULL) { 851 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); 852 exit(1); 853 } 854 env = &cpu->env; 855 856 cpu_sparc_set_id(env, id); 857 if (id == 0) { 858 qemu_register_reset(main_cpu_reset, cpu); 859 } else { 860 qemu_register_reset(secondary_cpu_reset, cpu); 861 cs = CPU(cpu); 862 cs->halted = 1; 863 } 864 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 865 env->prom_addr = prom_addr; 866 } 867 868 static void dummy_fdc_tc(void *opaque, int irq, int level) 869 { 870 } 871 872 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, 873 MachineState *machine) 874 { 875 const char *cpu_model = machine->cpu_model; 876 unsigned int i; 877 void *iommu, *espdma, *ledma, *nvram; 878 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS], 879 espdma_irq, ledma_irq; 880 qemu_irq esp_reset, dma_enable; 881 qemu_irq fdc_tc; 882 unsigned long kernel_size; 883 DriveInfo *fd[MAX_FD]; 884 FWCfgState *fw_cfg; 885 unsigned int num_vsimms; 886 887 /* init CPUs */ 888 if (!cpu_model) 889 cpu_model = hwdef->default_cpu_model; 890 891 for(i = 0; i < smp_cpus; i++) { 892 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); 893 } 894 895 for (i = smp_cpus; i < MAX_CPUS; i++) 896 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 897 898 899 /* set up devices */ 900 ram_init(0, machine->ram_size, hwdef->max_mem); 901 /* models without ECC don't trap when missing ram is accessed */ 902 if (!hwdef->ecc_base) { 903 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size); 904 } 905 906 prom_init(hwdef->slavio_base, bios_name); 907 908 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 909 hwdef->intctl_base + 0x10000ULL, 910 cpu_irqs); 911 912 for (i = 0; i < 32; i++) { 913 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 914 } 915 for (i = 0; i < MAX_CPUS; i++) { 916 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 917 } 918 919 if (hwdef->idreg_base) { 920 idreg_init(hwdef->idreg_base); 921 } 922 923 if (hwdef->afx_base) { 924 afx_init(hwdef->afx_base); 925 } 926 927 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, 928 slavio_irq[30]); 929 930 if (hwdef->iommu_pad_base) { 931 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 932 Software shouldn't use aliased addresses, neither should it crash 933 when does. Using empty_slot instead of aliasing can help with 934 debugging such accesses */ 935 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); 936 } 937 938 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18], 939 iommu, &espdma_irq, 0); 940 941 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, 942 slavio_irq[16], iommu, &ledma_irq, 1); 943 944 if (graphic_depth != 8 && graphic_depth != 24) { 945 error_report("Unsupported depth: %d", graphic_depth); 946 exit (1); 947 } 948 num_vsimms = 0; 949 if (num_vsimms == 0) { 950 if (vga_interface_type == VGA_CG3) { 951 if (graphic_depth != 8) { 952 error_report("Unsupported depth: %d", graphic_depth); 953 exit(1); 954 } 955 956 if (!(graphic_width == 1024 && graphic_height == 768) && 957 !(graphic_width == 1152 && graphic_height == 900)) { 958 error_report("Unsupported resolution: %d x %d", graphic_width, 959 graphic_height); 960 exit(1); 961 } 962 963 /* sbus irq 5 */ 964 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 965 graphic_width, graphic_height, graphic_depth); 966 } else { 967 /* If no display specified, default to TCX */ 968 if (graphic_depth != 8 && graphic_depth != 24) { 969 error_report("Unsupported depth: %d", graphic_depth); 970 exit(1); 971 } 972 973 if (!(graphic_width == 1024 && graphic_height == 768)) { 974 error_report("Unsupported resolution: %d x %d", 975 graphic_width, graphic_height); 976 exit(1); 977 } 978 979 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 980 graphic_width, graphic_height, graphic_depth); 981 } 982 } 983 984 for (i = num_vsimms; i < MAX_VSIMMS; i++) { 985 /* vsimm registers probed by OBP */ 986 if (hwdef->vsimm[i].reg_base) { 987 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); 988 } 989 } 990 991 if (hwdef->sx_base) { 992 empty_slot_init(hwdef->sx_base, 0x2000); 993 } 994 995 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq); 996 997 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8); 998 999 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 1000 1001 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14], 1002 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1); 1003 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 1004 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 1005 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], 1006 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); 1007 1008 if (hwdef->apc_base) { 1009 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); 1010 } 1011 1012 if (hwdef->fd_base) { 1013 /* there is zero or one floppy drive */ 1014 memset(fd, 0, sizeof(fd)); 1015 fd[0] = drive_get(IF_FLOPPY, 0, 0); 1016 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 1017 &fdc_tc); 1018 } else { 1019 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); 1020 } 1021 1022 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 1023 slavio_irq[30], fdc_tc); 1024 1025 if (drive_get_max_bus(IF_SCSI) > 0) { 1026 fprintf(stderr, "qemu: too many SCSI bus\n"); 1027 exit(1); 1028 } 1029 1030 esp_init(hwdef->esp_base, 2, 1031 espdma_memory_read, espdma_memory_write, 1032 espdma, espdma_irq, &esp_reset, &dma_enable); 1033 1034 qdev_connect_gpio_out(espdma, 0, esp_reset); 1035 qdev_connect_gpio_out(espdma, 1, dma_enable); 1036 1037 if (hwdef->cs_base) { 1038 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, 1039 slavio_irq[5]); 1040 } 1041 1042 if (hwdef->dbri_base) { 1043 /* ISDN chip with attached CS4215 audio codec */ 1044 /* prom space */ 1045 empty_slot_init(hwdef->dbri_base+0x1000, 0x30); 1046 /* reg space */ 1047 empty_slot_init(hwdef->dbri_base+0x10000, 0x100); 1048 } 1049 1050 if (hwdef->bpp_base) { 1051 /* parallel port */ 1052 empty_slot_init(hwdef->bpp_base, 0x20); 1053 } 1054 1055 kernel_size = sun4m_load_kernel(machine->kernel_filename, 1056 machine->initrd_filename, 1057 machine->ram_size); 1058 1059 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline, 1060 machine->boot_order, machine->ram_size, kernel_size, 1061 graphic_width, graphic_height, graphic_depth, 1062 hwdef->nvram_machine_id, "Sun4m"); 1063 1064 if (hwdef->ecc_base) 1065 ecc_init(hwdef->ecc_base, slavio_irq[28], 1066 hwdef->ecc_version); 1067 1068 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 1069 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1070 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1071 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1072 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1073 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1074 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1075 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1076 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1077 if (machine->kernel_cmdline) { 1078 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1079 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1080 machine->kernel_cmdline); 1081 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 1082 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1083 strlen(machine->kernel_cmdline) + 1); 1084 } else { 1085 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1086 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1087 } 1088 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1089 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used 1090 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 1091 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1092 } 1093 1094 enum { 1095 ss5_id = 32, 1096 vger_id, 1097 lx_id, 1098 ss4_id, 1099 scls_id, 1100 sbook_id, 1101 ss10_id = 64, 1102 ss20_id, 1103 ss600mp_id, 1104 }; 1105 1106 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1107 /* SS-5 */ 1108 { 1109 .iommu_base = 0x10000000, 1110 .iommu_pad_base = 0x10004000, 1111 .iommu_pad_len = 0x0fffb000, 1112 .tcx_base = 0x50000000, 1113 .cs_base = 0x6c000000, 1114 .slavio_base = 0x70000000, 1115 .ms_kb_base = 0x71000000, 1116 .serial_base = 0x71100000, 1117 .nvram_base = 0x71200000, 1118 .fd_base = 0x71400000, 1119 .counter_base = 0x71d00000, 1120 .intctl_base = 0x71e00000, 1121 .idreg_base = 0x78000000, 1122 .dma_base = 0x78400000, 1123 .esp_base = 0x78800000, 1124 .le_base = 0x78c00000, 1125 .apc_base = 0x6a000000, 1126 .afx_base = 0x6e000000, 1127 .aux1_base = 0x71900000, 1128 .aux2_base = 0x71910000, 1129 .nvram_machine_id = 0x80, 1130 .machine_id = ss5_id, 1131 .iommu_version = 0x05000000, 1132 .max_mem = 0x10000000, 1133 .default_cpu_model = "Fujitsu MB86904", 1134 }, 1135 /* SS-10 */ 1136 { 1137 .iommu_base = 0xfe0000000ULL, 1138 .tcx_base = 0xe20000000ULL, 1139 .slavio_base = 0xff0000000ULL, 1140 .ms_kb_base = 0xff1000000ULL, 1141 .serial_base = 0xff1100000ULL, 1142 .nvram_base = 0xff1200000ULL, 1143 .fd_base = 0xff1700000ULL, 1144 .counter_base = 0xff1300000ULL, 1145 .intctl_base = 0xff1400000ULL, 1146 .idreg_base = 0xef0000000ULL, 1147 .dma_base = 0xef0400000ULL, 1148 .esp_base = 0xef0800000ULL, 1149 .le_base = 0xef0c00000ULL, 1150 .apc_base = 0xefa000000ULL, // XXX should not exist 1151 .aux1_base = 0xff1800000ULL, 1152 .aux2_base = 0xff1a01000ULL, 1153 .ecc_base = 0xf00000000ULL, 1154 .ecc_version = 0x10000000, // version 0, implementation 1 1155 .nvram_machine_id = 0x72, 1156 .machine_id = ss10_id, 1157 .iommu_version = 0x03000000, 1158 .max_mem = 0xf00000000ULL, 1159 .default_cpu_model = "TI SuperSparc II", 1160 }, 1161 /* SS-600MP */ 1162 { 1163 .iommu_base = 0xfe0000000ULL, 1164 .tcx_base = 0xe20000000ULL, 1165 .slavio_base = 0xff0000000ULL, 1166 .ms_kb_base = 0xff1000000ULL, 1167 .serial_base = 0xff1100000ULL, 1168 .nvram_base = 0xff1200000ULL, 1169 .counter_base = 0xff1300000ULL, 1170 .intctl_base = 0xff1400000ULL, 1171 .dma_base = 0xef0081000ULL, 1172 .esp_base = 0xef0080000ULL, 1173 .le_base = 0xef0060000ULL, 1174 .apc_base = 0xefa000000ULL, // XXX should not exist 1175 .aux1_base = 0xff1800000ULL, 1176 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1177 .ecc_base = 0xf00000000ULL, 1178 .ecc_version = 0x00000000, // version 0, implementation 0 1179 .nvram_machine_id = 0x71, 1180 .machine_id = ss600mp_id, 1181 .iommu_version = 0x01000000, 1182 .max_mem = 0xf00000000ULL, 1183 .default_cpu_model = "TI SuperSparc II", 1184 }, 1185 /* SS-20 */ 1186 { 1187 .iommu_base = 0xfe0000000ULL, 1188 .tcx_base = 0xe20000000ULL, 1189 .slavio_base = 0xff0000000ULL, 1190 .ms_kb_base = 0xff1000000ULL, 1191 .serial_base = 0xff1100000ULL, 1192 .nvram_base = 0xff1200000ULL, 1193 .fd_base = 0xff1700000ULL, 1194 .counter_base = 0xff1300000ULL, 1195 .intctl_base = 0xff1400000ULL, 1196 .idreg_base = 0xef0000000ULL, 1197 .dma_base = 0xef0400000ULL, 1198 .esp_base = 0xef0800000ULL, 1199 .le_base = 0xef0c00000ULL, 1200 .bpp_base = 0xef4800000ULL, 1201 .apc_base = 0xefa000000ULL, // XXX should not exist 1202 .aux1_base = 0xff1800000ULL, 1203 .aux2_base = 0xff1a01000ULL, 1204 .dbri_base = 0xee0000000ULL, 1205 .sx_base = 0xf80000000ULL, 1206 .vsimm = { 1207 { 1208 .reg_base = 0x9c000000ULL, 1209 .vram_base = 0xfc000000ULL 1210 }, { 1211 .reg_base = 0x90000000ULL, 1212 .vram_base = 0xf0000000ULL 1213 }, { 1214 .reg_base = 0x94000000ULL 1215 }, { 1216 .reg_base = 0x98000000ULL 1217 } 1218 }, 1219 .ecc_base = 0xf00000000ULL, 1220 .ecc_version = 0x20000000, // version 0, implementation 2 1221 .nvram_machine_id = 0x72, 1222 .machine_id = ss20_id, 1223 .iommu_version = 0x13000000, 1224 .max_mem = 0xf00000000ULL, 1225 .default_cpu_model = "TI SuperSparc II", 1226 }, 1227 /* Voyager */ 1228 { 1229 .iommu_base = 0x10000000, 1230 .tcx_base = 0x50000000, 1231 .slavio_base = 0x70000000, 1232 .ms_kb_base = 0x71000000, 1233 .serial_base = 0x71100000, 1234 .nvram_base = 0x71200000, 1235 .fd_base = 0x71400000, 1236 .counter_base = 0x71d00000, 1237 .intctl_base = 0x71e00000, 1238 .idreg_base = 0x78000000, 1239 .dma_base = 0x78400000, 1240 .esp_base = 0x78800000, 1241 .le_base = 0x78c00000, 1242 .apc_base = 0x71300000, // pmc 1243 .aux1_base = 0x71900000, 1244 .aux2_base = 0x71910000, 1245 .nvram_machine_id = 0x80, 1246 .machine_id = vger_id, 1247 .iommu_version = 0x05000000, 1248 .max_mem = 0x10000000, 1249 .default_cpu_model = "Fujitsu MB86904", 1250 }, 1251 /* LX */ 1252 { 1253 .iommu_base = 0x10000000, 1254 .iommu_pad_base = 0x10004000, 1255 .iommu_pad_len = 0x0fffb000, 1256 .tcx_base = 0x50000000, 1257 .slavio_base = 0x70000000, 1258 .ms_kb_base = 0x71000000, 1259 .serial_base = 0x71100000, 1260 .nvram_base = 0x71200000, 1261 .fd_base = 0x71400000, 1262 .counter_base = 0x71d00000, 1263 .intctl_base = 0x71e00000, 1264 .idreg_base = 0x78000000, 1265 .dma_base = 0x78400000, 1266 .esp_base = 0x78800000, 1267 .le_base = 0x78c00000, 1268 .aux1_base = 0x71900000, 1269 .aux2_base = 0x71910000, 1270 .nvram_machine_id = 0x80, 1271 .machine_id = lx_id, 1272 .iommu_version = 0x04000000, 1273 .max_mem = 0x10000000, 1274 .default_cpu_model = "TI MicroSparc I", 1275 }, 1276 /* SS-4 */ 1277 { 1278 .iommu_base = 0x10000000, 1279 .tcx_base = 0x50000000, 1280 .cs_base = 0x6c000000, 1281 .slavio_base = 0x70000000, 1282 .ms_kb_base = 0x71000000, 1283 .serial_base = 0x71100000, 1284 .nvram_base = 0x71200000, 1285 .fd_base = 0x71400000, 1286 .counter_base = 0x71d00000, 1287 .intctl_base = 0x71e00000, 1288 .idreg_base = 0x78000000, 1289 .dma_base = 0x78400000, 1290 .esp_base = 0x78800000, 1291 .le_base = 0x78c00000, 1292 .apc_base = 0x6a000000, 1293 .aux1_base = 0x71900000, 1294 .aux2_base = 0x71910000, 1295 .nvram_machine_id = 0x80, 1296 .machine_id = ss4_id, 1297 .iommu_version = 0x05000000, 1298 .max_mem = 0x10000000, 1299 .default_cpu_model = "Fujitsu MB86904", 1300 }, 1301 /* SPARCClassic */ 1302 { 1303 .iommu_base = 0x10000000, 1304 .tcx_base = 0x50000000, 1305 .slavio_base = 0x70000000, 1306 .ms_kb_base = 0x71000000, 1307 .serial_base = 0x71100000, 1308 .nvram_base = 0x71200000, 1309 .fd_base = 0x71400000, 1310 .counter_base = 0x71d00000, 1311 .intctl_base = 0x71e00000, 1312 .idreg_base = 0x78000000, 1313 .dma_base = 0x78400000, 1314 .esp_base = 0x78800000, 1315 .le_base = 0x78c00000, 1316 .apc_base = 0x6a000000, 1317 .aux1_base = 0x71900000, 1318 .aux2_base = 0x71910000, 1319 .nvram_machine_id = 0x80, 1320 .machine_id = scls_id, 1321 .iommu_version = 0x05000000, 1322 .max_mem = 0x10000000, 1323 .default_cpu_model = "TI MicroSparc I", 1324 }, 1325 /* SPARCbook */ 1326 { 1327 .iommu_base = 0x10000000, 1328 .tcx_base = 0x50000000, // XXX 1329 .slavio_base = 0x70000000, 1330 .ms_kb_base = 0x71000000, 1331 .serial_base = 0x71100000, 1332 .nvram_base = 0x71200000, 1333 .fd_base = 0x71400000, 1334 .counter_base = 0x71d00000, 1335 .intctl_base = 0x71e00000, 1336 .idreg_base = 0x78000000, 1337 .dma_base = 0x78400000, 1338 .esp_base = 0x78800000, 1339 .le_base = 0x78c00000, 1340 .apc_base = 0x6a000000, 1341 .aux1_base = 0x71900000, 1342 .aux2_base = 0x71910000, 1343 .nvram_machine_id = 0x80, 1344 .machine_id = sbook_id, 1345 .iommu_version = 0x05000000, 1346 .max_mem = 0x10000000, 1347 .default_cpu_model = "TI MicroSparc I", 1348 }, 1349 }; 1350 1351 /* SPARCstation 5 hardware initialisation */ 1352 static void ss5_init(MachineState *machine) 1353 { 1354 sun4m_hw_init(&sun4m_hwdefs[0], machine); 1355 } 1356 1357 /* SPARCstation 10 hardware initialisation */ 1358 static void ss10_init(MachineState *machine) 1359 { 1360 sun4m_hw_init(&sun4m_hwdefs[1], machine); 1361 } 1362 1363 /* SPARCserver 600MP hardware initialisation */ 1364 static void ss600mp_init(MachineState *machine) 1365 { 1366 sun4m_hw_init(&sun4m_hwdefs[2], machine); 1367 } 1368 1369 /* SPARCstation 20 hardware initialisation */ 1370 static void ss20_init(MachineState *machine) 1371 { 1372 sun4m_hw_init(&sun4m_hwdefs[3], machine); 1373 } 1374 1375 /* SPARCstation Voyager hardware initialisation */ 1376 static void vger_init(MachineState *machine) 1377 { 1378 sun4m_hw_init(&sun4m_hwdefs[4], machine); 1379 } 1380 1381 /* SPARCstation LX hardware initialisation */ 1382 static void ss_lx_init(MachineState *machine) 1383 { 1384 sun4m_hw_init(&sun4m_hwdefs[5], machine); 1385 } 1386 1387 /* SPARCstation 4 hardware initialisation */ 1388 static void ss4_init(MachineState *machine) 1389 { 1390 sun4m_hw_init(&sun4m_hwdefs[6], machine); 1391 } 1392 1393 /* SPARCClassic hardware initialisation */ 1394 static void scls_init(MachineState *machine) 1395 { 1396 sun4m_hw_init(&sun4m_hwdefs[7], machine); 1397 } 1398 1399 /* SPARCbook hardware initialisation */ 1400 static void sbook_init(MachineState *machine) 1401 { 1402 sun4m_hw_init(&sun4m_hwdefs[8], machine); 1403 } 1404 1405 static void ss5_class_init(ObjectClass *oc, void *data) 1406 { 1407 MachineClass *mc = MACHINE_CLASS(oc); 1408 1409 mc->desc = "Sun4m platform, SPARCstation 5"; 1410 mc->init = ss5_init; 1411 mc->block_default_type = IF_SCSI; 1412 mc->is_default = 1; 1413 mc->default_boot_order = "c"; 1414 } 1415 1416 static const TypeInfo ss5_type = { 1417 .name = MACHINE_TYPE_NAME("SS-5"), 1418 .parent = TYPE_MACHINE, 1419 .class_init = ss5_class_init, 1420 }; 1421 1422 static void ss10_class_init(ObjectClass *oc, void *data) 1423 { 1424 MachineClass *mc = MACHINE_CLASS(oc); 1425 1426 mc->desc = "Sun4m platform, SPARCstation 10"; 1427 mc->init = ss10_init; 1428 mc->block_default_type = IF_SCSI; 1429 mc->max_cpus = 4; 1430 mc->default_boot_order = "c"; 1431 } 1432 1433 static const TypeInfo ss10_type = { 1434 .name = MACHINE_TYPE_NAME("SS-10"), 1435 .parent = TYPE_MACHINE, 1436 .class_init = ss10_class_init, 1437 }; 1438 1439 static void ss600mp_class_init(ObjectClass *oc, void *data) 1440 { 1441 MachineClass *mc = MACHINE_CLASS(oc); 1442 1443 mc->desc = "Sun4m platform, SPARCserver 600MP"; 1444 mc->init = ss600mp_init; 1445 mc->block_default_type = IF_SCSI; 1446 mc->max_cpus = 4; 1447 mc->default_boot_order = "c"; 1448 } 1449 1450 static const TypeInfo ss600mp_type = { 1451 .name = MACHINE_TYPE_NAME("SS-600MP"), 1452 .parent = TYPE_MACHINE, 1453 .class_init = ss600mp_class_init, 1454 }; 1455 1456 static void ss20_class_init(ObjectClass *oc, void *data) 1457 { 1458 MachineClass *mc = MACHINE_CLASS(oc); 1459 1460 mc->desc = "Sun4m platform, SPARCstation 20"; 1461 mc->init = ss20_init; 1462 mc->block_default_type = IF_SCSI; 1463 mc->max_cpus = 4; 1464 mc->default_boot_order = "c"; 1465 } 1466 1467 static const TypeInfo ss20_type = { 1468 .name = MACHINE_TYPE_NAME("SS-20"), 1469 .parent = TYPE_MACHINE, 1470 .class_init = ss20_class_init, 1471 }; 1472 1473 static void voyager_class_init(ObjectClass *oc, void *data) 1474 { 1475 MachineClass *mc = MACHINE_CLASS(oc); 1476 1477 mc->desc = "Sun4m platform, SPARCstation Voyager"; 1478 mc->init = vger_init; 1479 mc->block_default_type = IF_SCSI; 1480 mc->default_boot_order = "c"; 1481 } 1482 1483 static const TypeInfo voyager_type = { 1484 .name = MACHINE_TYPE_NAME("Voyager"), 1485 .parent = TYPE_MACHINE, 1486 .class_init = voyager_class_init, 1487 }; 1488 1489 static void ss_lx_class_init(ObjectClass *oc, void *data) 1490 { 1491 MachineClass *mc = MACHINE_CLASS(oc); 1492 1493 mc->desc = "Sun4m platform, SPARCstation LX"; 1494 mc->init = ss_lx_init; 1495 mc->block_default_type = IF_SCSI; 1496 mc->default_boot_order = "c"; 1497 } 1498 1499 static const TypeInfo ss_lx_type = { 1500 .name = MACHINE_TYPE_NAME("LX"), 1501 .parent = TYPE_MACHINE, 1502 .class_init = ss_lx_class_init, 1503 }; 1504 1505 static void ss4_class_init(ObjectClass *oc, void *data) 1506 { 1507 MachineClass *mc = MACHINE_CLASS(oc); 1508 1509 mc->desc = "Sun4m platform, SPARCstation 4"; 1510 mc->init = ss4_init; 1511 mc->block_default_type = IF_SCSI; 1512 mc->default_boot_order = "c"; 1513 } 1514 1515 static const TypeInfo ss4_type = { 1516 .name = MACHINE_TYPE_NAME("SS-4"), 1517 .parent = TYPE_MACHINE, 1518 .class_init = ss4_class_init, 1519 }; 1520 1521 static void scls_class_init(ObjectClass *oc, void *data) 1522 { 1523 MachineClass *mc = MACHINE_CLASS(oc); 1524 1525 mc->desc = "Sun4m platform, SPARCClassic"; 1526 mc->init = scls_init; 1527 mc->block_default_type = IF_SCSI; 1528 mc->default_boot_order = "c"; 1529 } 1530 1531 static const TypeInfo scls_type = { 1532 .name = MACHINE_TYPE_NAME("SPARCClassic"), 1533 .parent = TYPE_MACHINE, 1534 .class_init = scls_class_init, 1535 }; 1536 1537 static void sbook_class_init(ObjectClass *oc, void *data) 1538 { 1539 MachineClass *mc = MACHINE_CLASS(oc); 1540 1541 mc->desc = "Sun4m platform, SPARCbook"; 1542 mc->init = sbook_init; 1543 mc->block_default_type = IF_SCSI; 1544 mc->default_boot_order = "c"; 1545 } 1546 1547 static const TypeInfo sbook_type = { 1548 .name = MACHINE_TYPE_NAME("SPARCbook"), 1549 .parent = TYPE_MACHINE, 1550 .class_init = sbook_class_init, 1551 }; 1552 1553 static void sun4m_register_types(void) 1554 { 1555 type_register_static(&idreg_info); 1556 type_register_static(&afx_info); 1557 type_register_static(&prom_info); 1558 type_register_static(&ram_info); 1559 1560 type_register_static(&ss5_type); 1561 type_register_static(&ss10_type); 1562 type_register_static(&ss600mp_type); 1563 type_register_static(&ss20_type); 1564 type_register_static(&voyager_type); 1565 type_register_static(&ss_lx_type); 1566 type_register_static(&ss4_type); 1567 type_register_static(&scls_type); 1568 type_register_static(&sbook_type); 1569 } 1570 1571 type_init(sun4m_register_types) 1572