1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "hw/sysbus.h" 27 #include "qemu/error-report.h" 28 #include "qemu/timer.h" 29 #include "hw/sparc/sun4m.h" 30 #include "hw/timer/m48t59.h" 31 #include "hw/sparc/sparc32_dma.h" 32 #include "hw/block/fdc.h" 33 #include "sysemu/sysemu.h" 34 #include "net/net.h" 35 #include "hw/boards.h" 36 #include "hw/nvram/openbios_firmware_abi.h" 37 #include "hw/scsi/esp.h" 38 #include "hw/i386/pc.h" 39 #include "hw/isa/isa.h" 40 #include "hw/nvram/fw_cfg.h" 41 #include "hw/char/escc.h" 42 #include "hw/empty_slot.h" 43 #include "hw/loader.h" 44 #include "elf.h" 45 #include "sysemu/block-backend.h" 46 #include "trace.h" 47 48 /* 49 * Sun4m architecture was used in the following machines: 50 * 51 * SPARCserver 6xxMP/xx 52 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 53 * SPARCclassic X (4/10) 54 * SPARCstation LX/ZX (4/30) 55 * SPARCstation Voyager 56 * SPARCstation 10/xx, SPARCserver 10/xx 57 * SPARCstation 5, SPARCserver 5 58 * SPARCstation 20/xx, SPARCserver 20 59 * SPARCstation 4 60 * 61 * See for example: http://www.sunhelp.org/faq/sunref1.html 62 */ 63 64 #define KERNEL_LOAD_ADDR 0x00004000 65 #define CMDLINE_ADDR 0x007ff000 66 #define INITRD_LOAD_ADDR 0x00800000 67 #define PROM_SIZE_MAX (1024 * 1024) 68 #define PROM_VADDR 0xffd00000 69 #define PROM_FILENAME "openbios-sparc32" 70 #define CFG_ADDR 0xd00000510ULL 71 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 72 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 73 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 74 75 #define MAX_CPUS 16 76 #define MAX_PILS 16 77 #define MAX_VSIMMS 4 78 79 #define ESCC_CLOCK 4915200 80 81 struct sun4m_hwdef { 82 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 83 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 84 hwaddr serial_base, fd_base; 85 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 86 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 87 hwaddr bpp_base, dbri_base, sx_base; 88 struct { 89 hwaddr reg_base, vram_base; 90 } vsimm[MAX_VSIMMS]; 91 hwaddr ecc_base; 92 uint64_t max_mem; 93 const char * const default_cpu_model; 94 uint32_t ecc_version; 95 uint32_t iommu_version; 96 uint16_t machine_id; 97 uint8_t nvram_machine_id; 98 }; 99 100 void DMA_init(ISABus *bus, int high_page_enable) 101 { 102 } 103 104 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 105 Error **errp) 106 { 107 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 108 } 109 110 static void nvram_init(Nvram *nvram, uint8_t *macaddr, 111 const char *cmdline, const char *boot_devices, 112 ram_addr_t RAM_size, uint32_t kernel_size, 113 int width, int height, int depth, 114 int nvram_machine_id, const char *arch) 115 { 116 unsigned int i; 117 uint32_t start, end; 118 uint8_t image[0x1ff0]; 119 struct OpenBIOS_nvpart_v1 *part_header; 120 NvramClass *k = NVRAM_GET_CLASS(nvram); 121 122 memset(image, '\0', sizeof(image)); 123 124 start = 0; 125 126 // OpenBIOS nvram variables 127 // Variable partition 128 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 129 part_header->signature = OPENBIOS_PART_SYSTEM; 130 pstrcpy(part_header->name, sizeof(part_header->name), "system"); 131 132 end = start + sizeof(struct OpenBIOS_nvpart_v1); 133 for (i = 0; i < nb_prom_envs; i++) 134 end = OpenBIOS_set_var(image, end, prom_envs[i]); 135 136 // End marker 137 image[end++] = '\0'; 138 139 end = start + ((end - start + 15) & ~15); 140 OpenBIOS_finish_partition(part_header, end - start); 141 142 // free partition 143 start = end; 144 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 145 part_header->signature = OPENBIOS_PART_FREE; 146 pstrcpy(part_header->name, sizeof(part_header->name), "free"); 147 148 end = 0x1fd0; 149 OpenBIOS_finish_partition(part_header, end - start); 150 151 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 152 nvram_machine_id); 153 154 for (i = 0; i < sizeof(image); i++) { 155 (k->write)(nvram, i, image[i]); 156 } 157 } 158 159 static DeviceState *slavio_intctl; 160 161 void sun4m_hmp_info_pic(Monitor *mon, const QDict *qdict) 162 { 163 if (slavio_intctl) 164 slavio_pic_info(mon, slavio_intctl); 165 } 166 167 void sun4m_hmp_info_irq(Monitor *mon, const QDict *qdict) 168 { 169 if (slavio_intctl) 170 slavio_irq_info(mon, slavio_intctl); 171 } 172 173 void cpu_check_irqs(CPUSPARCState *env) 174 { 175 CPUState *cs; 176 177 if (env->pil_in && (env->interrupt_index == 0 || 178 (env->interrupt_index & ~15) == TT_EXTINT)) { 179 unsigned int i; 180 181 for (i = 15; i > 0; i--) { 182 if (env->pil_in & (1 << i)) { 183 int old_interrupt = env->interrupt_index; 184 185 env->interrupt_index = TT_EXTINT | i; 186 if (old_interrupt != env->interrupt_index) { 187 cs = CPU(sparc_env_get_cpu(env)); 188 trace_sun4m_cpu_interrupt(i); 189 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 190 } 191 break; 192 } 193 } 194 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 195 cs = CPU(sparc_env_get_cpu(env)); 196 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 197 env->interrupt_index = 0; 198 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 199 } 200 } 201 202 static void cpu_kick_irq(SPARCCPU *cpu) 203 { 204 CPUSPARCState *env = &cpu->env; 205 CPUState *cs = CPU(cpu); 206 207 cs->halted = 0; 208 cpu_check_irqs(env); 209 qemu_cpu_kick(cs); 210 } 211 212 static void cpu_set_irq(void *opaque, int irq, int level) 213 { 214 SPARCCPU *cpu = opaque; 215 CPUSPARCState *env = &cpu->env; 216 217 if (level) { 218 trace_sun4m_cpu_set_irq_raise(irq); 219 env->pil_in |= 1 << irq; 220 cpu_kick_irq(cpu); 221 } else { 222 trace_sun4m_cpu_set_irq_lower(irq); 223 env->pil_in &= ~(1 << irq); 224 cpu_check_irqs(env); 225 } 226 } 227 228 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 229 { 230 } 231 232 static void main_cpu_reset(void *opaque) 233 { 234 SPARCCPU *cpu = opaque; 235 CPUState *cs = CPU(cpu); 236 237 cpu_reset(cs); 238 cs->halted = 0; 239 } 240 241 static void secondary_cpu_reset(void *opaque) 242 { 243 SPARCCPU *cpu = opaque; 244 CPUState *cs = CPU(cpu); 245 246 cpu_reset(cs); 247 cs->halted = 1; 248 } 249 250 static void cpu_halt_signal(void *opaque, int irq, int level) 251 { 252 if (level && current_cpu) { 253 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 254 } 255 } 256 257 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 258 { 259 return addr - 0xf0000000ULL; 260 } 261 262 static unsigned long sun4m_load_kernel(const char *kernel_filename, 263 const char *initrd_filename, 264 ram_addr_t RAM_size) 265 { 266 int linux_boot; 267 unsigned int i; 268 long initrd_size, kernel_size; 269 uint8_t *ptr; 270 271 linux_boot = (kernel_filename != NULL); 272 273 kernel_size = 0; 274 if (linux_boot) { 275 int bswap_needed; 276 277 #ifdef BSWAP_NEEDED 278 bswap_needed = 1; 279 #else 280 bswap_needed = 0; 281 #endif 282 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 283 NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 284 if (kernel_size < 0) 285 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 286 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 287 TARGET_PAGE_SIZE); 288 if (kernel_size < 0) 289 kernel_size = load_image_targphys(kernel_filename, 290 KERNEL_LOAD_ADDR, 291 RAM_size - KERNEL_LOAD_ADDR); 292 if (kernel_size < 0) { 293 fprintf(stderr, "qemu: could not load kernel '%s'\n", 294 kernel_filename); 295 exit(1); 296 } 297 298 /* load initrd */ 299 initrd_size = 0; 300 if (initrd_filename) { 301 initrd_size = load_image_targphys(initrd_filename, 302 INITRD_LOAD_ADDR, 303 RAM_size - INITRD_LOAD_ADDR); 304 if (initrd_size < 0) { 305 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 306 initrd_filename); 307 exit(1); 308 } 309 } 310 if (initrd_size > 0) { 311 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 312 ptr = rom_ptr(KERNEL_LOAD_ADDR + i); 313 if (ldl_p(ptr) == 0x48647253) { // HdrS 314 stl_p(ptr + 16, INITRD_LOAD_ADDR); 315 stl_p(ptr + 20, initrd_size); 316 break; 317 } 318 } 319 } 320 } 321 return kernel_size; 322 } 323 324 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 325 { 326 DeviceState *dev; 327 SysBusDevice *s; 328 329 dev = qdev_create(NULL, "iommu"); 330 qdev_prop_set_uint32(dev, "version", version); 331 qdev_init_nofail(dev); 332 s = SYS_BUS_DEVICE(dev); 333 sysbus_connect_irq(s, 0, irq); 334 sysbus_mmio_map(s, 0, addr); 335 336 return s; 337 } 338 339 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq, 340 void *iommu, qemu_irq *dev_irq, int is_ledma) 341 { 342 DeviceState *dev; 343 SysBusDevice *s; 344 345 dev = qdev_create(NULL, "sparc32_dma"); 346 qdev_prop_set_ptr(dev, "iommu_opaque", iommu); 347 qdev_prop_set_uint32(dev, "is_ledma", is_ledma); 348 qdev_init_nofail(dev); 349 s = SYS_BUS_DEVICE(dev); 350 sysbus_connect_irq(s, 0, parent_irq); 351 *dev_irq = qdev_get_gpio_in(dev, 0); 352 sysbus_mmio_map(s, 0, daddr); 353 354 return s; 355 } 356 357 static void lance_init(NICInfo *nd, hwaddr leaddr, 358 void *dma_opaque, qemu_irq irq) 359 { 360 DeviceState *dev; 361 SysBusDevice *s; 362 qemu_irq reset; 363 364 qemu_check_nic_model(&nd_table[0], "lance"); 365 366 dev = qdev_create(NULL, "lance"); 367 qdev_set_nic_properties(dev, nd); 368 qdev_prop_set_ptr(dev, "dma", dma_opaque); 369 qdev_init_nofail(dev); 370 s = SYS_BUS_DEVICE(dev); 371 sysbus_mmio_map(s, 0, leaddr); 372 sysbus_connect_irq(s, 0, irq); 373 reset = qdev_get_gpio_in(dev, 0); 374 qdev_connect_gpio_out(dma_opaque, 0, reset); 375 } 376 377 static DeviceState *slavio_intctl_init(hwaddr addr, 378 hwaddr addrg, 379 qemu_irq **parent_irq) 380 { 381 DeviceState *dev; 382 SysBusDevice *s; 383 unsigned int i, j; 384 385 dev = qdev_create(NULL, "slavio_intctl"); 386 qdev_init_nofail(dev); 387 388 s = SYS_BUS_DEVICE(dev); 389 390 for (i = 0; i < MAX_CPUS; i++) { 391 for (j = 0; j < MAX_PILS; j++) { 392 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 393 } 394 } 395 sysbus_mmio_map(s, 0, addrg); 396 for (i = 0; i < MAX_CPUS; i++) { 397 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 398 } 399 400 return dev; 401 } 402 403 #define SYS_TIMER_OFFSET 0x10000ULL 404 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 405 406 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 407 qemu_irq *cpu_irqs, unsigned int num_cpus) 408 { 409 DeviceState *dev; 410 SysBusDevice *s; 411 unsigned int i; 412 413 dev = qdev_create(NULL, "slavio_timer"); 414 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 415 qdev_init_nofail(dev); 416 s = SYS_BUS_DEVICE(dev); 417 sysbus_connect_irq(s, 0, master_irq); 418 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 419 420 for (i = 0; i < MAX_CPUS; i++) { 421 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 422 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 423 } 424 } 425 426 static qemu_irq slavio_system_powerdown; 427 428 static void slavio_powerdown_req(Notifier *n, void *opaque) 429 { 430 qemu_irq_raise(slavio_system_powerdown); 431 } 432 433 static Notifier slavio_system_powerdown_notifier = { 434 .notify = slavio_powerdown_req 435 }; 436 437 #define MISC_LEDS 0x01600000 438 #define MISC_CFG 0x01800000 439 #define MISC_DIAG 0x01a00000 440 #define MISC_MDM 0x01b00000 441 #define MISC_SYS 0x01f00000 442 443 static void slavio_misc_init(hwaddr base, 444 hwaddr aux1_base, 445 hwaddr aux2_base, qemu_irq irq, 446 qemu_irq fdc_tc) 447 { 448 DeviceState *dev; 449 SysBusDevice *s; 450 451 dev = qdev_create(NULL, "slavio_misc"); 452 qdev_init_nofail(dev); 453 s = SYS_BUS_DEVICE(dev); 454 if (base) { 455 /* 8 bit registers */ 456 /* Slavio control */ 457 sysbus_mmio_map(s, 0, base + MISC_CFG); 458 /* Diagnostics */ 459 sysbus_mmio_map(s, 1, base + MISC_DIAG); 460 /* Modem control */ 461 sysbus_mmio_map(s, 2, base + MISC_MDM); 462 /* 16 bit registers */ 463 /* ss600mp diag LEDs */ 464 sysbus_mmio_map(s, 3, base + MISC_LEDS); 465 /* 32 bit registers */ 466 /* System control */ 467 sysbus_mmio_map(s, 4, base + MISC_SYS); 468 } 469 if (aux1_base) { 470 /* AUX 1 (Misc System Functions) */ 471 sysbus_mmio_map(s, 5, aux1_base); 472 } 473 if (aux2_base) { 474 /* AUX 2 (Software Powerdown Control) */ 475 sysbus_mmio_map(s, 6, aux2_base); 476 } 477 sysbus_connect_irq(s, 0, irq); 478 sysbus_connect_irq(s, 1, fdc_tc); 479 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 480 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 481 } 482 483 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 484 { 485 DeviceState *dev; 486 SysBusDevice *s; 487 488 dev = qdev_create(NULL, "eccmemctl"); 489 qdev_prop_set_uint32(dev, "version", version); 490 qdev_init_nofail(dev); 491 s = SYS_BUS_DEVICE(dev); 492 sysbus_connect_irq(s, 0, irq); 493 sysbus_mmio_map(s, 0, base); 494 if (version == 0) { // SS-600MP only 495 sysbus_mmio_map(s, 1, base + 0x1000); 496 } 497 } 498 499 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 500 { 501 DeviceState *dev; 502 SysBusDevice *s; 503 504 dev = qdev_create(NULL, "apc"); 505 qdev_init_nofail(dev); 506 s = SYS_BUS_DEVICE(dev); 507 /* Power management (APC) XXX: not a Slavio device */ 508 sysbus_mmio_map(s, 0, power_base); 509 sysbus_connect_irq(s, 0, cpu_halt); 510 } 511 512 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 513 int height, int depth) 514 { 515 DeviceState *dev; 516 SysBusDevice *s; 517 518 dev = qdev_create(NULL, "SUNW,tcx"); 519 qdev_prop_set_uint32(dev, "vram_size", vram_size); 520 qdev_prop_set_uint16(dev, "width", width); 521 qdev_prop_set_uint16(dev, "height", height); 522 qdev_prop_set_uint16(dev, "depth", depth); 523 qdev_prop_set_uint64(dev, "prom_addr", addr); 524 qdev_init_nofail(dev); 525 s = SYS_BUS_DEVICE(dev); 526 527 /* 10/ROM : FCode ROM */ 528 sysbus_mmio_map(s, 0, addr); 529 /* 2/STIP : Stipple */ 530 sysbus_mmio_map(s, 1, addr + 0x04000000ULL); 531 /* 3/BLIT : Blitter */ 532 sysbus_mmio_map(s, 2, addr + 0x06000000ULL); 533 /* 5/RSTIP : Raw Stipple */ 534 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); 535 /* 6/RBLIT : Raw Blitter */ 536 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); 537 /* 7/TEC : Transform Engine */ 538 sysbus_mmio_map(s, 5, addr + 0x00700000ULL); 539 /* 8/CMAP : DAC */ 540 sysbus_mmio_map(s, 6, addr + 0x00200000ULL); 541 /* 9/THC : */ 542 if (depth == 8) { 543 sysbus_mmio_map(s, 7, addr + 0x00300000ULL); 544 } else { 545 sysbus_mmio_map(s, 7, addr + 0x00301000ULL); 546 } 547 /* 11/DHC : */ 548 sysbus_mmio_map(s, 8, addr + 0x00240000ULL); 549 /* 12/ALT : */ 550 sysbus_mmio_map(s, 9, addr + 0x00280000ULL); 551 /* 0/DFB8 : 8-bit plane */ 552 sysbus_mmio_map(s, 10, addr + 0x00800000ULL); 553 /* 1/DFB24 : 24bit plane */ 554 sysbus_mmio_map(s, 11, addr + 0x02000000ULL); 555 /* 4/RDFB32: Raw framebuffer. Control plane */ 556 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); 557 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 558 if (depth == 8) { 559 sysbus_mmio_map(s, 13, addr + 0x00301000ULL); 560 } 561 562 sysbus_connect_irq(s, 0, irq); 563 } 564 565 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 566 int height, int depth) 567 { 568 DeviceState *dev; 569 SysBusDevice *s; 570 571 dev = qdev_create(NULL, "cgthree"); 572 qdev_prop_set_uint32(dev, "vram-size", vram_size); 573 qdev_prop_set_uint16(dev, "width", width); 574 qdev_prop_set_uint16(dev, "height", height); 575 qdev_prop_set_uint16(dev, "depth", depth); 576 qdev_prop_set_uint64(dev, "prom-addr", addr); 577 qdev_init_nofail(dev); 578 s = SYS_BUS_DEVICE(dev); 579 580 /* FCode ROM */ 581 sysbus_mmio_map(s, 0, addr); 582 /* DAC */ 583 sysbus_mmio_map(s, 1, addr + 0x400000ULL); 584 /* 8-bit plane */ 585 sysbus_mmio_map(s, 2, addr + 0x800000ULL); 586 587 sysbus_connect_irq(s, 0, irq); 588 } 589 590 /* NCR89C100/MACIO Internal ID register */ 591 592 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 593 594 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 595 596 static void idreg_init(hwaddr addr) 597 { 598 DeviceState *dev; 599 SysBusDevice *s; 600 601 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER); 602 qdev_init_nofail(dev); 603 s = SYS_BUS_DEVICE(dev); 604 605 sysbus_mmio_map(s, 0, addr); 606 cpu_physical_memory_write_rom(&address_space_memory, 607 addr, idreg_data, sizeof(idreg_data)); 608 } 609 610 #define MACIO_ID_REGISTER(obj) \ 611 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER) 612 613 typedef struct IDRegState { 614 SysBusDevice parent_obj; 615 616 MemoryRegion mem; 617 } IDRegState; 618 619 static int idreg_init1(SysBusDevice *dev) 620 { 621 IDRegState *s = MACIO_ID_REGISTER(dev); 622 623 memory_region_init_ram(&s->mem, OBJECT(s), 624 "sun4m.idreg", sizeof(idreg_data), &error_fatal); 625 vmstate_register_ram_global(&s->mem); 626 memory_region_set_readonly(&s->mem, true); 627 sysbus_init_mmio(dev, &s->mem); 628 return 0; 629 } 630 631 static void idreg_class_init(ObjectClass *klass, void *data) 632 { 633 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 634 635 k->init = idreg_init1; 636 } 637 638 static const TypeInfo idreg_info = { 639 .name = TYPE_MACIO_ID_REGISTER, 640 .parent = TYPE_SYS_BUS_DEVICE, 641 .instance_size = sizeof(IDRegState), 642 .class_init = idreg_class_init, 643 }; 644 645 #define TYPE_TCX_AFX "tcx_afx" 646 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX) 647 648 typedef struct AFXState { 649 SysBusDevice parent_obj; 650 651 MemoryRegion mem; 652 } AFXState; 653 654 /* SS-5 TCX AFX register */ 655 static void afx_init(hwaddr addr) 656 { 657 DeviceState *dev; 658 SysBusDevice *s; 659 660 dev = qdev_create(NULL, TYPE_TCX_AFX); 661 qdev_init_nofail(dev); 662 s = SYS_BUS_DEVICE(dev); 663 664 sysbus_mmio_map(s, 0, addr); 665 } 666 667 static int afx_init1(SysBusDevice *dev) 668 { 669 AFXState *s = TCX_AFX(dev); 670 671 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4, &error_fatal); 672 vmstate_register_ram_global(&s->mem); 673 sysbus_init_mmio(dev, &s->mem); 674 return 0; 675 } 676 677 static void afx_class_init(ObjectClass *klass, void *data) 678 { 679 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 680 681 k->init = afx_init1; 682 } 683 684 static const TypeInfo afx_info = { 685 .name = TYPE_TCX_AFX, 686 .parent = TYPE_SYS_BUS_DEVICE, 687 .instance_size = sizeof(AFXState), 688 .class_init = afx_class_init, 689 }; 690 691 #define TYPE_OPENPROM "openprom" 692 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 693 694 typedef struct PROMState { 695 SysBusDevice parent_obj; 696 697 MemoryRegion prom; 698 } PROMState; 699 700 /* Boot PROM (OpenBIOS) */ 701 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 702 { 703 hwaddr *base_addr = (hwaddr *)opaque; 704 return addr + *base_addr - PROM_VADDR; 705 } 706 707 static void prom_init(hwaddr addr, const char *bios_name) 708 { 709 DeviceState *dev; 710 SysBusDevice *s; 711 char *filename; 712 int ret; 713 714 dev = qdev_create(NULL, TYPE_OPENPROM); 715 qdev_init_nofail(dev); 716 s = SYS_BUS_DEVICE(dev); 717 718 sysbus_mmio_map(s, 0, addr); 719 720 /* load boot prom */ 721 if (bios_name == NULL) { 722 bios_name = PROM_FILENAME; 723 } 724 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 725 if (filename) { 726 ret = load_elf(filename, translate_prom_address, &addr, NULL, 727 NULL, NULL, 1, EM_SPARC, 0, 0); 728 if (ret < 0 || ret > PROM_SIZE_MAX) { 729 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 730 } 731 g_free(filename); 732 } else { 733 ret = -1; 734 } 735 if (ret < 0 || ret > PROM_SIZE_MAX) { 736 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 737 exit(1); 738 } 739 } 740 741 static int prom_init1(SysBusDevice *dev) 742 { 743 PROMState *s = OPENPROM(dev); 744 745 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX, 746 &error_fatal); 747 vmstate_register_ram_global(&s->prom); 748 memory_region_set_readonly(&s->prom, true); 749 sysbus_init_mmio(dev, &s->prom); 750 return 0; 751 } 752 753 static Property prom_properties[] = { 754 {/* end of property list */}, 755 }; 756 757 static void prom_class_init(ObjectClass *klass, void *data) 758 { 759 DeviceClass *dc = DEVICE_CLASS(klass); 760 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 761 762 k->init = prom_init1; 763 dc->props = prom_properties; 764 } 765 766 static const TypeInfo prom_info = { 767 .name = TYPE_OPENPROM, 768 .parent = TYPE_SYS_BUS_DEVICE, 769 .instance_size = sizeof(PROMState), 770 .class_init = prom_class_init, 771 }; 772 773 #define TYPE_SUN4M_MEMORY "memory" 774 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY) 775 776 typedef struct RamDevice { 777 SysBusDevice parent_obj; 778 779 MemoryRegion ram; 780 uint64_t size; 781 } RamDevice; 782 783 /* System RAM */ 784 static int ram_init1(SysBusDevice *dev) 785 { 786 RamDevice *d = SUN4M_RAM(dev); 787 788 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram", 789 d->size); 790 sysbus_init_mmio(dev, &d->ram); 791 return 0; 792 } 793 794 static void ram_init(hwaddr addr, ram_addr_t RAM_size, 795 uint64_t max_mem) 796 { 797 DeviceState *dev; 798 SysBusDevice *s; 799 RamDevice *d; 800 801 /* allocate RAM */ 802 if ((uint64_t)RAM_size > max_mem) { 803 fprintf(stderr, 804 "qemu: Too much memory for this machine: %d, maximum %d\n", 805 (unsigned int)(RAM_size / (1024 * 1024)), 806 (unsigned int)(max_mem / (1024 * 1024))); 807 exit(1); 808 } 809 dev = qdev_create(NULL, "memory"); 810 s = SYS_BUS_DEVICE(dev); 811 812 d = SUN4M_RAM(dev); 813 d->size = RAM_size; 814 qdev_init_nofail(dev); 815 816 sysbus_mmio_map(s, 0, addr); 817 } 818 819 static Property ram_properties[] = { 820 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 821 DEFINE_PROP_END_OF_LIST(), 822 }; 823 824 static void ram_class_init(ObjectClass *klass, void *data) 825 { 826 DeviceClass *dc = DEVICE_CLASS(klass); 827 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 828 829 k->init = ram_init1; 830 dc->props = ram_properties; 831 } 832 833 static const TypeInfo ram_info = { 834 .name = TYPE_SUN4M_MEMORY, 835 .parent = TYPE_SYS_BUS_DEVICE, 836 .instance_size = sizeof(RamDevice), 837 .class_init = ram_class_init, 838 }; 839 840 static void cpu_devinit(const char *cpu_model, unsigned int id, 841 uint64_t prom_addr, qemu_irq **cpu_irqs) 842 { 843 CPUState *cs; 844 SPARCCPU *cpu; 845 CPUSPARCState *env; 846 847 cpu = cpu_sparc_init(cpu_model); 848 if (cpu == NULL) { 849 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); 850 exit(1); 851 } 852 env = &cpu->env; 853 854 cpu_sparc_set_id(env, id); 855 if (id == 0) { 856 qemu_register_reset(main_cpu_reset, cpu); 857 } else { 858 qemu_register_reset(secondary_cpu_reset, cpu); 859 cs = CPU(cpu); 860 cs->halted = 1; 861 } 862 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 863 env->prom_addr = prom_addr; 864 } 865 866 static void dummy_fdc_tc(void *opaque, int irq, int level) 867 { 868 } 869 870 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, 871 MachineState *machine) 872 { 873 const char *cpu_model = machine->cpu_model; 874 unsigned int i; 875 void *iommu, *espdma, *ledma, *nvram; 876 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS], 877 espdma_irq, ledma_irq; 878 qemu_irq esp_reset, dma_enable; 879 qemu_irq fdc_tc; 880 unsigned long kernel_size; 881 DriveInfo *fd[MAX_FD]; 882 FWCfgState *fw_cfg; 883 unsigned int num_vsimms; 884 885 /* init CPUs */ 886 if (!cpu_model) 887 cpu_model = hwdef->default_cpu_model; 888 889 for(i = 0; i < smp_cpus; i++) { 890 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); 891 } 892 893 for (i = smp_cpus; i < MAX_CPUS; i++) 894 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 895 896 897 /* set up devices */ 898 ram_init(0, machine->ram_size, hwdef->max_mem); 899 /* models without ECC don't trap when missing ram is accessed */ 900 if (!hwdef->ecc_base) { 901 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size); 902 } 903 904 prom_init(hwdef->slavio_base, bios_name); 905 906 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 907 hwdef->intctl_base + 0x10000ULL, 908 cpu_irqs); 909 910 for (i = 0; i < 32; i++) { 911 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 912 } 913 for (i = 0; i < MAX_CPUS; i++) { 914 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 915 } 916 917 if (hwdef->idreg_base) { 918 idreg_init(hwdef->idreg_base); 919 } 920 921 if (hwdef->afx_base) { 922 afx_init(hwdef->afx_base); 923 } 924 925 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, 926 slavio_irq[30]); 927 928 if (hwdef->iommu_pad_base) { 929 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 930 Software shouldn't use aliased addresses, neither should it crash 931 when does. Using empty_slot instead of aliasing can help with 932 debugging such accesses */ 933 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); 934 } 935 936 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18], 937 iommu, &espdma_irq, 0); 938 939 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, 940 slavio_irq[16], iommu, &ledma_irq, 1); 941 942 if (graphic_depth != 8 && graphic_depth != 24) { 943 error_report("Unsupported depth: %d", graphic_depth); 944 exit (1); 945 } 946 num_vsimms = 0; 947 if (num_vsimms == 0) { 948 if (vga_interface_type == VGA_CG3) { 949 if (graphic_depth != 8) { 950 error_report("Unsupported depth: %d", graphic_depth); 951 exit(1); 952 } 953 954 if (!(graphic_width == 1024 && graphic_height == 768) && 955 !(graphic_width == 1152 && graphic_height == 900)) { 956 error_report("Unsupported resolution: %d x %d", graphic_width, 957 graphic_height); 958 exit(1); 959 } 960 961 /* sbus irq 5 */ 962 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 963 graphic_width, graphic_height, graphic_depth); 964 } else { 965 /* If no display specified, default to TCX */ 966 if (graphic_depth != 8 && graphic_depth != 24) { 967 error_report("Unsupported depth: %d", graphic_depth); 968 exit(1); 969 } 970 971 if (!(graphic_width == 1024 && graphic_height == 768)) { 972 error_report("Unsupported resolution: %d x %d", 973 graphic_width, graphic_height); 974 exit(1); 975 } 976 977 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 978 graphic_width, graphic_height, graphic_depth); 979 } 980 } 981 982 for (i = num_vsimms; i < MAX_VSIMMS; i++) { 983 /* vsimm registers probed by OBP */ 984 if (hwdef->vsimm[i].reg_base) { 985 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); 986 } 987 } 988 989 if (hwdef->sx_base) { 990 empty_slot_init(hwdef->sx_base, 0x2000); 991 } 992 993 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq); 994 995 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8); 996 997 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 998 999 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14], 1000 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1); 1001 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 1002 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 1003 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], 1004 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); 1005 1006 if (hwdef->apc_base) { 1007 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); 1008 } 1009 1010 if (hwdef->fd_base) { 1011 /* there is zero or one floppy drive */ 1012 memset(fd, 0, sizeof(fd)); 1013 fd[0] = drive_get(IF_FLOPPY, 0, 0); 1014 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 1015 &fdc_tc); 1016 } else { 1017 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); 1018 } 1019 1020 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 1021 slavio_irq[30], fdc_tc); 1022 1023 if (drive_get_max_bus(IF_SCSI) > 0) { 1024 fprintf(stderr, "qemu: too many SCSI bus\n"); 1025 exit(1); 1026 } 1027 1028 esp_init(hwdef->esp_base, 2, 1029 espdma_memory_read, espdma_memory_write, 1030 espdma, espdma_irq, &esp_reset, &dma_enable); 1031 1032 qdev_connect_gpio_out(espdma, 0, esp_reset); 1033 qdev_connect_gpio_out(espdma, 1, dma_enable); 1034 1035 if (hwdef->cs_base) { 1036 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, 1037 slavio_irq[5]); 1038 } 1039 1040 if (hwdef->dbri_base) { 1041 /* ISDN chip with attached CS4215 audio codec */ 1042 /* prom space */ 1043 empty_slot_init(hwdef->dbri_base+0x1000, 0x30); 1044 /* reg space */ 1045 empty_slot_init(hwdef->dbri_base+0x10000, 0x100); 1046 } 1047 1048 if (hwdef->bpp_base) { 1049 /* parallel port */ 1050 empty_slot_init(hwdef->bpp_base, 0x20); 1051 } 1052 1053 kernel_size = sun4m_load_kernel(machine->kernel_filename, 1054 machine->initrd_filename, 1055 machine->ram_size); 1056 1057 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline, 1058 machine->boot_order, machine->ram_size, kernel_size, 1059 graphic_width, graphic_height, graphic_depth, 1060 hwdef->nvram_machine_id, "Sun4m"); 1061 1062 if (hwdef->ecc_base) 1063 ecc_init(hwdef->ecc_base, slavio_irq[28], 1064 hwdef->ecc_version); 1065 1066 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 1067 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1068 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1069 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1070 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1071 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1072 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1073 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1074 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1075 if (machine->kernel_cmdline) { 1076 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1077 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1078 machine->kernel_cmdline); 1079 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 1080 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1081 strlen(machine->kernel_cmdline) + 1); 1082 } else { 1083 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1084 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1085 } 1086 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1087 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used 1088 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 1089 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1090 } 1091 1092 enum { 1093 ss5_id = 32, 1094 vger_id, 1095 lx_id, 1096 ss4_id, 1097 scls_id, 1098 sbook_id, 1099 ss10_id = 64, 1100 ss20_id, 1101 ss600mp_id, 1102 }; 1103 1104 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1105 /* SS-5 */ 1106 { 1107 .iommu_base = 0x10000000, 1108 .iommu_pad_base = 0x10004000, 1109 .iommu_pad_len = 0x0fffb000, 1110 .tcx_base = 0x50000000, 1111 .cs_base = 0x6c000000, 1112 .slavio_base = 0x70000000, 1113 .ms_kb_base = 0x71000000, 1114 .serial_base = 0x71100000, 1115 .nvram_base = 0x71200000, 1116 .fd_base = 0x71400000, 1117 .counter_base = 0x71d00000, 1118 .intctl_base = 0x71e00000, 1119 .idreg_base = 0x78000000, 1120 .dma_base = 0x78400000, 1121 .esp_base = 0x78800000, 1122 .le_base = 0x78c00000, 1123 .apc_base = 0x6a000000, 1124 .afx_base = 0x6e000000, 1125 .aux1_base = 0x71900000, 1126 .aux2_base = 0x71910000, 1127 .nvram_machine_id = 0x80, 1128 .machine_id = ss5_id, 1129 .iommu_version = 0x05000000, 1130 .max_mem = 0x10000000, 1131 .default_cpu_model = "Fujitsu MB86904", 1132 }, 1133 /* SS-10 */ 1134 { 1135 .iommu_base = 0xfe0000000ULL, 1136 .tcx_base = 0xe20000000ULL, 1137 .slavio_base = 0xff0000000ULL, 1138 .ms_kb_base = 0xff1000000ULL, 1139 .serial_base = 0xff1100000ULL, 1140 .nvram_base = 0xff1200000ULL, 1141 .fd_base = 0xff1700000ULL, 1142 .counter_base = 0xff1300000ULL, 1143 .intctl_base = 0xff1400000ULL, 1144 .idreg_base = 0xef0000000ULL, 1145 .dma_base = 0xef0400000ULL, 1146 .esp_base = 0xef0800000ULL, 1147 .le_base = 0xef0c00000ULL, 1148 .apc_base = 0xefa000000ULL, // XXX should not exist 1149 .aux1_base = 0xff1800000ULL, 1150 .aux2_base = 0xff1a01000ULL, 1151 .ecc_base = 0xf00000000ULL, 1152 .ecc_version = 0x10000000, // version 0, implementation 1 1153 .nvram_machine_id = 0x72, 1154 .machine_id = ss10_id, 1155 .iommu_version = 0x03000000, 1156 .max_mem = 0xf00000000ULL, 1157 .default_cpu_model = "TI SuperSparc II", 1158 }, 1159 /* SS-600MP */ 1160 { 1161 .iommu_base = 0xfe0000000ULL, 1162 .tcx_base = 0xe20000000ULL, 1163 .slavio_base = 0xff0000000ULL, 1164 .ms_kb_base = 0xff1000000ULL, 1165 .serial_base = 0xff1100000ULL, 1166 .nvram_base = 0xff1200000ULL, 1167 .counter_base = 0xff1300000ULL, 1168 .intctl_base = 0xff1400000ULL, 1169 .dma_base = 0xef0081000ULL, 1170 .esp_base = 0xef0080000ULL, 1171 .le_base = 0xef0060000ULL, 1172 .apc_base = 0xefa000000ULL, // XXX should not exist 1173 .aux1_base = 0xff1800000ULL, 1174 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1175 .ecc_base = 0xf00000000ULL, 1176 .ecc_version = 0x00000000, // version 0, implementation 0 1177 .nvram_machine_id = 0x71, 1178 .machine_id = ss600mp_id, 1179 .iommu_version = 0x01000000, 1180 .max_mem = 0xf00000000ULL, 1181 .default_cpu_model = "TI SuperSparc II", 1182 }, 1183 /* SS-20 */ 1184 { 1185 .iommu_base = 0xfe0000000ULL, 1186 .tcx_base = 0xe20000000ULL, 1187 .slavio_base = 0xff0000000ULL, 1188 .ms_kb_base = 0xff1000000ULL, 1189 .serial_base = 0xff1100000ULL, 1190 .nvram_base = 0xff1200000ULL, 1191 .fd_base = 0xff1700000ULL, 1192 .counter_base = 0xff1300000ULL, 1193 .intctl_base = 0xff1400000ULL, 1194 .idreg_base = 0xef0000000ULL, 1195 .dma_base = 0xef0400000ULL, 1196 .esp_base = 0xef0800000ULL, 1197 .le_base = 0xef0c00000ULL, 1198 .bpp_base = 0xef4800000ULL, 1199 .apc_base = 0xefa000000ULL, // XXX should not exist 1200 .aux1_base = 0xff1800000ULL, 1201 .aux2_base = 0xff1a01000ULL, 1202 .dbri_base = 0xee0000000ULL, 1203 .sx_base = 0xf80000000ULL, 1204 .vsimm = { 1205 { 1206 .reg_base = 0x9c000000ULL, 1207 .vram_base = 0xfc000000ULL 1208 }, { 1209 .reg_base = 0x90000000ULL, 1210 .vram_base = 0xf0000000ULL 1211 }, { 1212 .reg_base = 0x94000000ULL 1213 }, { 1214 .reg_base = 0x98000000ULL 1215 } 1216 }, 1217 .ecc_base = 0xf00000000ULL, 1218 .ecc_version = 0x20000000, // version 0, implementation 2 1219 .nvram_machine_id = 0x72, 1220 .machine_id = ss20_id, 1221 .iommu_version = 0x13000000, 1222 .max_mem = 0xf00000000ULL, 1223 .default_cpu_model = "TI SuperSparc II", 1224 }, 1225 /* Voyager */ 1226 { 1227 .iommu_base = 0x10000000, 1228 .tcx_base = 0x50000000, 1229 .slavio_base = 0x70000000, 1230 .ms_kb_base = 0x71000000, 1231 .serial_base = 0x71100000, 1232 .nvram_base = 0x71200000, 1233 .fd_base = 0x71400000, 1234 .counter_base = 0x71d00000, 1235 .intctl_base = 0x71e00000, 1236 .idreg_base = 0x78000000, 1237 .dma_base = 0x78400000, 1238 .esp_base = 0x78800000, 1239 .le_base = 0x78c00000, 1240 .apc_base = 0x71300000, // pmc 1241 .aux1_base = 0x71900000, 1242 .aux2_base = 0x71910000, 1243 .nvram_machine_id = 0x80, 1244 .machine_id = vger_id, 1245 .iommu_version = 0x05000000, 1246 .max_mem = 0x10000000, 1247 .default_cpu_model = "Fujitsu MB86904", 1248 }, 1249 /* LX */ 1250 { 1251 .iommu_base = 0x10000000, 1252 .iommu_pad_base = 0x10004000, 1253 .iommu_pad_len = 0x0fffb000, 1254 .tcx_base = 0x50000000, 1255 .slavio_base = 0x70000000, 1256 .ms_kb_base = 0x71000000, 1257 .serial_base = 0x71100000, 1258 .nvram_base = 0x71200000, 1259 .fd_base = 0x71400000, 1260 .counter_base = 0x71d00000, 1261 .intctl_base = 0x71e00000, 1262 .idreg_base = 0x78000000, 1263 .dma_base = 0x78400000, 1264 .esp_base = 0x78800000, 1265 .le_base = 0x78c00000, 1266 .aux1_base = 0x71900000, 1267 .aux2_base = 0x71910000, 1268 .nvram_machine_id = 0x80, 1269 .machine_id = lx_id, 1270 .iommu_version = 0x04000000, 1271 .max_mem = 0x10000000, 1272 .default_cpu_model = "TI MicroSparc I", 1273 }, 1274 /* SS-4 */ 1275 { 1276 .iommu_base = 0x10000000, 1277 .tcx_base = 0x50000000, 1278 .cs_base = 0x6c000000, 1279 .slavio_base = 0x70000000, 1280 .ms_kb_base = 0x71000000, 1281 .serial_base = 0x71100000, 1282 .nvram_base = 0x71200000, 1283 .fd_base = 0x71400000, 1284 .counter_base = 0x71d00000, 1285 .intctl_base = 0x71e00000, 1286 .idreg_base = 0x78000000, 1287 .dma_base = 0x78400000, 1288 .esp_base = 0x78800000, 1289 .le_base = 0x78c00000, 1290 .apc_base = 0x6a000000, 1291 .aux1_base = 0x71900000, 1292 .aux2_base = 0x71910000, 1293 .nvram_machine_id = 0x80, 1294 .machine_id = ss4_id, 1295 .iommu_version = 0x05000000, 1296 .max_mem = 0x10000000, 1297 .default_cpu_model = "Fujitsu MB86904", 1298 }, 1299 /* SPARCClassic */ 1300 { 1301 .iommu_base = 0x10000000, 1302 .tcx_base = 0x50000000, 1303 .slavio_base = 0x70000000, 1304 .ms_kb_base = 0x71000000, 1305 .serial_base = 0x71100000, 1306 .nvram_base = 0x71200000, 1307 .fd_base = 0x71400000, 1308 .counter_base = 0x71d00000, 1309 .intctl_base = 0x71e00000, 1310 .idreg_base = 0x78000000, 1311 .dma_base = 0x78400000, 1312 .esp_base = 0x78800000, 1313 .le_base = 0x78c00000, 1314 .apc_base = 0x6a000000, 1315 .aux1_base = 0x71900000, 1316 .aux2_base = 0x71910000, 1317 .nvram_machine_id = 0x80, 1318 .machine_id = scls_id, 1319 .iommu_version = 0x05000000, 1320 .max_mem = 0x10000000, 1321 .default_cpu_model = "TI MicroSparc I", 1322 }, 1323 /* SPARCbook */ 1324 { 1325 .iommu_base = 0x10000000, 1326 .tcx_base = 0x50000000, // XXX 1327 .slavio_base = 0x70000000, 1328 .ms_kb_base = 0x71000000, 1329 .serial_base = 0x71100000, 1330 .nvram_base = 0x71200000, 1331 .fd_base = 0x71400000, 1332 .counter_base = 0x71d00000, 1333 .intctl_base = 0x71e00000, 1334 .idreg_base = 0x78000000, 1335 .dma_base = 0x78400000, 1336 .esp_base = 0x78800000, 1337 .le_base = 0x78c00000, 1338 .apc_base = 0x6a000000, 1339 .aux1_base = 0x71900000, 1340 .aux2_base = 0x71910000, 1341 .nvram_machine_id = 0x80, 1342 .machine_id = sbook_id, 1343 .iommu_version = 0x05000000, 1344 .max_mem = 0x10000000, 1345 .default_cpu_model = "TI MicroSparc I", 1346 }, 1347 }; 1348 1349 /* SPARCstation 5 hardware initialisation */ 1350 static void ss5_init(MachineState *machine) 1351 { 1352 sun4m_hw_init(&sun4m_hwdefs[0], machine); 1353 } 1354 1355 /* SPARCstation 10 hardware initialisation */ 1356 static void ss10_init(MachineState *machine) 1357 { 1358 sun4m_hw_init(&sun4m_hwdefs[1], machine); 1359 } 1360 1361 /* SPARCserver 600MP hardware initialisation */ 1362 static void ss600mp_init(MachineState *machine) 1363 { 1364 sun4m_hw_init(&sun4m_hwdefs[2], machine); 1365 } 1366 1367 /* SPARCstation 20 hardware initialisation */ 1368 static void ss20_init(MachineState *machine) 1369 { 1370 sun4m_hw_init(&sun4m_hwdefs[3], machine); 1371 } 1372 1373 /* SPARCstation Voyager hardware initialisation */ 1374 static void vger_init(MachineState *machine) 1375 { 1376 sun4m_hw_init(&sun4m_hwdefs[4], machine); 1377 } 1378 1379 /* SPARCstation LX hardware initialisation */ 1380 static void ss_lx_init(MachineState *machine) 1381 { 1382 sun4m_hw_init(&sun4m_hwdefs[5], machine); 1383 } 1384 1385 /* SPARCstation 4 hardware initialisation */ 1386 static void ss4_init(MachineState *machine) 1387 { 1388 sun4m_hw_init(&sun4m_hwdefs[6], machine); 1389 } 1390 1391 /* SPARCClassic hardware initialisation */ 1392 static void scls_init(MachineState *machine) 1393 { 1394 sun4m_hw_init(&sun4m_hwdefs[7], machine); 1395 } 1396 1397 /* SPARCbook hardware initialisation */ 1398 static void sbook_init(MachineState *machine) 1399 { 1400 sun4m_hw_init(&sun4m_hwdefs[8], machine); 1401 } 1402 1403 static void ss5_class_init(ObjectClass *oc, void *data) 1404 { 1405 MachineClass *mc = MACHINE_CLASS(oc); 1406 1407 mc->desc = "Sun4m platform, SPARCstation 5"; 1408 mc->init = ss5_init; 1409 mc->block_default_type = IF_SCSI; 1410 mc->is_default = 1; 1411 mc->default_boot_order = "c"; 1412 } 1413 1414 static const TypeInfo ss5_type = { 1415 .name = MACHINE_TYPE_NAME("SS-5"), 1416 .parent = TYPE_MACHINE, 1417 .class_init = ss5_class_init, 1418 }; 1419 1420 static void ss10_class_init(ObjectClass *oc, void *data) 1421 { 1422 MachineClass *mc = MACHINE_CLASS(oc); 1423 1424 mc->desc = "Sun4m platform, SPARCstation 10"; 1425 mc->init = ss10_init; 1426 mc->block_default_type = IF_SCSI; 1427 mc->max_cpus = 4; 1428 mc->default_boot_order = "c"; 1429 } 1430 1431 static const TypeInfo ss10_type = { 1432 .name = MACHINE_TYPE_NAME("SS-10"), 1433 .parent = TYPE_MACHINE, 1434 .class_init = ss10_class_init, 1435 }; 1436 1437 static void ss600mp_class_init(ObjectClass *oc, void *data) 1438 { 1439 MachineClass *mc = MACHINE_CLASS(oc); 1440 1441 mc->desc = "Sun4m platform, SPARCserver 600MP"; 1442 mc->init = ss600mp_init; 1443 mc->block_default_type = IF_SCSI; 1444 mc->max_cpus = 4; 1445 mc->default_boot_order = "c"; 1446 } 1447 1448 static const TypeInfo ss600mp_type = { 1449 .name = MACHINE_TYPE_NAME("SS-600MP"), 1450 .parent = TYPE_MACHINE, 1451 .class_init = ss600mp_class_init, 1452 }; 1453 1454 static void ss20_class_init(ObjectClass *oc, void *data) 1455 { 1456 MachineClass *mc = MACHINE_CLASS(oc); 1457 1458 mc->desc = "Sun4m platform, SPARCstation 20"; 1459 mc->init = ss20_init; 1460 mc->block_default_type = IF_SCSI; 1461 mc->max_cpus = 4; 1462 mc->default_boot_order = "c"; 1463 } 1464 1465 static const TypeInfo ss20_type = { 1466 .name = MACHINE_TYPE_NAME("SS-20"), 1467 .parent = TYPE_MACHINE, 1468 .class_init = ss20_class_init, 1469 }; 1470 1471 static void voyager_class_init(ObjectClass *oc, void *data) 1472 { 1473 MachineClass *mc = MACHINE_CLASS(oc); 1474 1475 mc->desc = "Sun4m platform, SPARCstation Voyager"; 1476 mc->init = vger_init; 1477 mc->block_default_type = IF_SCSI; 1478 mc->default_boot_order = "c"; 1479 } 1480 1481 static const TypeInfo voyager_type = { 1482 .name = MACHINE_TYPE_NAME("Voyager"), 1483 .parent = TYPE_MACHINE, 1484 .class_init = voyager_class_init, 1485 }; 1486 1487 static void ss_lx_class_init(ObjectClass *oc, void *data) 1488 { 1489 MachineClass *mc = MACHINE_CLASS(oc); 1490 1491 mc->desc = "Sun4m platform, SPARCstation LX"; 1492 mc->init = ss_lx_init; 1493 mc->block_default_type = IF_SCSI; 1494 mc->default_boot_order = "c"; 1495 } 1496 1497 static const TypeInfo ss_lx_type = { 1498 .name = MACHINE_TYPE_NAME("LX"), 1499 .parent = TYPE_MACHINE, 1500 .class_init = ss_lx_class_init, 1501 }; 1502 1503 static void ss4_class_init(ObjectClass *oc, void *data) 1504 { 1505 MachineClass *mc = MACHINE_CLASS(oc); 1506 1507 mc->desc = "Sun4m platform, SPARCstation 4"; 1508 mc->init = ss4_init; 1509 mc->block_default_type = IF_SCSI; 1510 mc->default_boot_order = "c"; 1511 } 1512 1513 static const TypeInfo ss4_type = { 1514 .name = MACHINE_TYPE_NAME("SS-4"), 1515 .parent = TYPE_MACHINE, 1516 .class_init = ss4_class_init, 1517 }; 1518 1519 static void scls_class_init(ObjectClass *oc, void *data) 1520 { 1521 MachineClass *mc = MACHINE_CLASS(oc); 1522 1523 mc->desc = "Sun4m platform, SPARCClassic"; 1524 mc->init = scls_init; 1525 mc->block_default_type = IF_SCSI; 1526 mc->default_boot_order = "c"; 1527 } 1528 1529 static const TypeInfo scls_type = { 1530 .name = MACHINE_TYPE_NAME("SPARCClassic"), 1531 .parent = TYPE_MACHINE, 1532 .class_init = scls_class_init, 1533 }; 1534 1535 static void sbook_class_init(ObjectClass *oc, void *data) 1536 { 1537 MachineClass *mc = MACHINE_CLASS(oc); 1538 1539 mc->desc = "Sun4m platform, SPARCbook"; 1540 mc->init = sbook_init; 1541 mc->block_default_type = IF_SCSI; 1542 mc->default_boot_order = "c"; 1543 } 1544 1545 static const TypeInfo sbook_type = { 1546 .name = MACHINE_TYPE_NAME("SPARCbook"), 1547 .parent = TYPE_MACHINE, 1548 .class_init = sbook_class_init, 1549 }; 1550 1551 static void sun4m_register_types(void) 1552 { 1553 type_register_static(&idreg_info); 1554 type_register_static(&afx_info); 1555 type_register_static(&prom_info); 1556 type_register_static(&ram_info); 1557 1558 type_register_static(&ss5_type); 1559 type_register_static(&ss10_type); 1560 type_register_static(&ss600mp_type); 1561 type_register_static(&ss20_type); 1562 type_register_static(&voyager_type); 1563 type_register_static(&ss_lx_type); 1564 type_register_static(&ss4_type); 1565 type_register_static(&scls_type); 1566 type_register_static(&sbook_type); 1567 } 1568 1569 type_init(sun4m_register_types) 1570