1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/sysbus.h" 25 #include "qemu/timer.h" 26 #include "hw/sparc/sun4m.h" 27 #include "hw/timer/m48t59.h" 28 #include "hw/sparc/sparc32_dma.h" 29 #include "hw/block/fdc.h" 30 #include "sysemu/sysemu.h" 31 #include "net/net.h" 32 #include "hw/boards.h" 33 #include "hw/nvram/openbios_firmware_abi.h" 34 #include "hw/scsi/esp.h" 35 #include "hw/i386/pc.h" 36 #include "hw/isa/isa.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/char/escc.h" 39 #include "hw/empty_slot.h" 40 #include "hw/loader.h" 41 #include "elf.h" 42 #include "sysemu/blockdev.h" 43 #include "trace.h" 44 45 /* 46 * Sun4m architecture was used in the following machines: 47 * 48 * SPARCserver 6xxMP/xx 49 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 50 * SPARCclassic X (4/10) 51 * SPARCstation LX/ZX (4/30) 52 * SPARCstation Voyager 53 * SPARCstation 10/xx, SPARCserver 10/xx 54 * SPARCstation 5, SPARCserver 5 55 * SPARCstation 20/xx, SPARCserver 20 56 * SPARCstation 4 57 * 58 * See for example: http://www.sunhelp.org/faq/sunref1.html 59 */ 60 61 #define KERNEL_LOAD_ADDR 0x00004000 62 #define CMDLINE_ADDR 0x007ff000 63 #define INITRD_LOAD_ADDR 0x00800000 64 #define PROM_SIZE_MAX (1024 * 1024) 65 #define PROM_VADDR 0xffd00000 66 #define PROM_FILENAME "openbios-sparc32" 67 #define CFG_ADDR 0xd00000510ULL 68 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 69 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 70 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 71 72 #define MAX_CPUS 16 73 #define MAX_PILS 16 74 #define MAX_VSIMMS 4 75 76 #define ESCC_CLOCK 4915200 77 78 struct sun4m_hwdef { 79 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 80 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 81 hwaddr serial_base, fd_base; 82 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 83 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 84 hwaddr bpp_base, dbri_base, sx_base; 85 struct { 86 hwaddr reg_base, vram_base; 87 } vsimm[MAX_VSIMMS]; 88 hwaddr ecc_base; 89 uint64_t max_mem; 90 const char * const default_cpu_model; 91 uint32_t ecc_version; 92 uint32_t iommu_version; 93 uint16_t machine_id; 94 uint8_t nvram_machine_id; 95 }; 96 97 int DMA_get_channel_mode (int nchan) 98 { 99 return 0; 100 } 101 int DMA_read_memory (int nchan, void *buf, int pos, int size) 102 { 103 return 0; 104 } 105 int DMA_write_memory (int nchan, void *buf, int pos, int size) 106 { 107 return 0; 108 } 109 void DMA_hold_DREQ (int nchan) {} 110 void DMA_release_DREQ (int nchan) {} 111 void DMA_schedule(int nchan) {} 112 113 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) 114 { 115 } 116 117 void DMA_register_channel (int nchan, 118 DMA_transfer_handler transfer_handler, 119 void *opaque) 120 { 121 } 122 123 static int fw_cfg_boot_set(void *opaque, const char *boot_device) 124 { 125 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 126 return 0; 127 } 128 129 static void nvram_init(M48t59State *nvram, uint8_t *macaddr, 130 const char *cmdline, const char *boot_devices, 131 ram_addr_t RAM_size, uint32_t kernel_size, 132 int width, int height, int depth, 133 int nvram_machine_id, const char *arch) 134 { 135 unsigned int i; 136 uint32_t start, end; 137 uint8_t image[0x1ff0]; 138 struct OpenBIOS_nvpart_v1 *part_header; 139 140 memset(image, '\0', sizeof(image)); 141 142 start = 0; 143 144 // OpenBIOS nvram variables 145 // Variable partition 146 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 147 part_header->signature = OPENBIOS_PART_SYSTEM; 148 pstrcpy(part_header->name, sizeof(part_header->name), "system"); 149 150 end = start + sizeof(struct OpenBIOS_nvpart_v1); 151 for (i = 0; i < nb_prom_envs; i++) 152 end = OpenBIOS_set_var(image, end, prom_envs[i]); 153 154 // End marker 155 image[end++] = '\0'; 156 157 end = start + ((end - start + 15) & ~15); 158 OpenBIOS_finish_partition(part_header, end - start); 159 160 // free partition 161 start = end; 162 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 163 part_header->signature = OPENBIOS_PART_FREE; 164 pstrcpy(part_header->name, sizeof(part_header->name), "free"); 165 166 end = 0x1fd0; 167 OpenBIOS_finish_partition(part_header, end - start); 168 169 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 170 nvram_machine_id); 171 172 for (i = 0; i < sizeof(image); i++) 173 m48t59_write(nvram, i, image[i]); 174 } 175 176 static DeviceState *slavio_intctl; 177 178 void sun4m_pic_info(Monitor *mon, const QDict *qdict) 179 { 180 if (slavio_intctl) 181 slavio_pic_info(mon, slavio_intctl); 182 } 183 184 void sun4m_irq_info(Monitor *mon, const QDict *qdict) 185 { 186 if (slavio_intctl) 187 slavio_irq_info(mon, slavio_intctl); 188 } 189 190 void cpu_check_irqs(CPUSPARCState *env) 191 { 192 CPUState *cs; 193 194 if (env->pil_in && (env->interrupt_index == 0 || 195 (env->interrupt_index & ~15) == TT_EXTINT)) { 196 unsigned int i; 197 198 for (i = 15; i > 0; i--) { 199 if (env->pil_in & (1 << i)) { 200 int old_interrupt = env->interrupt_index; 201 202 env->interrupt_index = TT_EXTINT | i; 203 if (old_interrupt != env->interrupt_index) { 204 cs = CPU(sparc_env_get_cpu(env)); 205 trace_sun4m_cpu_interrupt(i); 206 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 207 } 208 break; 209 } 210 } 211 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 212 cs = CPU(sparc_env_get_cpu(env)); 213 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 214 env->interrupt_index = 0; 215 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 216 } 217 } 218 219 static void cpu_kick_irq(SPARCCPU *cpu) 220 { 221 CPUSPARCState *env = &cpu->env; 222 CPUState *cs = CPU(cpu); 223 224 cs->halted = 0; 225 cpu_check_irqs(env); 226 qemu_cpu_kick(cs); 227 } 228 229 static void cpu_set_irq(void *opaque, int irq, int level) 230 { 231 SPARCCPU *cpu = opaque; 232 CPUSPARCState *env = &cpu->env; 233 234 if (level) { 235 trace_sun4m_cpu_set_irq_raise(irq); 236 env->pil_in |= 1 << irq; 237 cpu_kick_irq(cpu); 238 } else { 239 trace_sun4m_cpu_set_irq_lower(irq); 240 env->pil_in &= ~(1 << irq); 241 cpu_check_irqs(env); 242 } 243 } 244 245 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 246 { 247 } 248 249 static void main_cpu_reset(void *opaque) 250 { 251 SPARCCPU *cpu = opaque; 252 CPUState *cs = CPU(cpu); 253 254 cpu_reset(cs); 255 cs->halted = 0; 256 } 257 258 static void secondary_cpu_reset(void *opaque) 259 { 260 SPARCCPU *cpu = opaque; 261 CPUState *cs = CPU(cpu); 262 263 cpu_reset(cs); 264 cs->halted = 1; 265 } 266 267 static void cpu_halt_signal(void *opaque, int irq, int level) 268 { 269 if (level && current_cpu) { 270 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 271 } 272 } 273 274 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 275 { 276 return addr - 0xf0000000ULL; 277 } 278 279 static unsigned long sun4m_load_kernel(const char *kernel_filename, 280 const char *initrd_filename, 281 ram_addr_t RAM_size) 282 { 283 int linux_boot; 284 unsigned int i; 285 long initrd_size, kernel_size; 286 uint8_t *ptr; 287 288 linux_boot = (kernel_filename != NULL); 289 290 kernel_size = 0; 291 if (linux_boot) { 292 int bswap_needed; 293 294 #ifdef BSWAP_NEEDED 295 bswap_needed = 1; 296 #else 297 bswap_needed = 0; 298 #endif 299 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 300 NULL, NULL, NULL, 1, ELF_MACHINE, 0); 301 if (kernel_size < 0) 302 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 303 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 304 TARGET_PAGE_SIZE); 305 if (kernel_size < 0) 306 kernel_size = load_image_targphys(kernel_filename, 307 KERNEL_LOAD_ADDR, 308 RAM_size - KERNEL_LOAD_ADDR); 309 if (kernel_size < 0) { 310 fprintf(stderr, "qemu: could not load kernel '%s'\n", 311 kernel_filename); 312 exit(1); 313 } 314 315 /* load initrd */ 316 initrd_size = 0; 317 if (initrd_filename) { 318 initrd_size = load_image_targphys(initrd_filename, 319 INITRD_LOAD_ADDR, 320 RAM_size - INITRD_LOAD_ADDR); 321 if (initrd_size < 0) { 322 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 323 initrd_filename); 324 exit(1); 325 } 326 } 327 if (initrd_size > 0) { 328 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 329 ptr = rom_ptr(KERNEL_LOAD_ADDR + i); 330 if (ldl_p(ptr) == 0x48647253) { // HdrS 331 stl_p(ptr + 16, INITRD_LOAD_ADDR); 332 stl_p(ptr + 20, initrd_size); 333 break; 334 } 335 } 336 } 337 } 338 return kernel_size; 339 } 340 341 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 342 { 343 DeviceState *dev; 344 SysBusDevice *s; 345 346 dev = qdev_create(NULL, "iommu"); 347 qdev_prop_set_uint32(dev, "version", version); 348 qdev_init_nofail(dev); 349 s = SYS_BUS_DEVICE(dev); 350 sysbus_connect_irq(s, 0, irq); 351 sysbus_mmio_map(s, 0, addr); 352 353 return s; 354 } 355 356 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq, 357 void *iommu, qemu_irq *dev_irq, int is_ledma) 358 { 359 DeviceState *dev; 360 SysBusDevice *s; 361 362 dev = qdev_create(NULL, "sparc32_dma"); 363 qdev_prop_set_ptr(dev, "iommu_opaque", iommu); 364 qdev_prop_set_uint32(dev, "is_ledma", is_ledma); 365 qdev_init_nofail(dev); 366 s = SYS_BUS_DEVICE(dev); 367 sysbus_connect_irq(s, 0, parent_irq); 368 *dev_irq = qdev_get_gpio_in(dev, 0); 369 sysbus_mmio_map(s, 0, daddr); 370 371 return s; 372 } 373 374 static void lance_init(NICInfo *nd, hwaddr leaddr, 375 void *dma_opaque, qemu_irq irq) 376 { 377 DeviceState *dev; 378 SysBusDevice *s; 379 qemu_irq reset; 380 381 qemu_check_nic_model(&nd_table[0], "lance"); 382 383 dev = qdev_create(NULL, "lance"); 384 qdev_set_nic_properties(dev, nd); 385 qdev_prop_set_ptr(dev, "dma", dma_opaque); 386 qdev_init_nofail(dev); 387 s = SYS_BUS_DEVICE(dev); 388 sysbus_mmio_map(s, 0, leaddr); 389 sysbus_connect_irq(s, 0, irq); 390 reset = qdev_get_gpio_in(dev, 0); 391 qdev_connect_gpio_out(dma_opaque, 0, reset); 392 } 393 394 static DeviceState *slavio_intctl_init(hwaddr addr, 395 hwaddr addrg, 396 qemu_irq **parent_irq) 397 { 398 DeviceState *dev; 399 SysBusDevice *s; 400 unsigned int i, j; 401 402 dev = qdev_create(NULL, "slavio_intctl"); 403 qdev_init_nofail(dev); 404 405 s = SYS_BUS_DEVICE(dev); 406 407 for (i = 0; i < MAX_CPUS; i++) { 408 for (j = 0; j < MAX_PILS; j++) { 409 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 410 } 411 } 412 sysbus_mmio_map(s, 0, addrg); 413 for (i = 0; i < MAX_CPUS; i++) { 414 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 415 } 416 417 return dev; 418 } 419 420 #define SYS_TIMER_OFFSET 0x10000ULL 421 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 422 423 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 424 qemu_irq *cpu_irqs, unsigned int num_cpus) 425 { 426 DeviceState *dev; 427 SysBusDevice *s; 428 unsigned int i; 429 430 dev = qdev_create(NULL, "slavio_timer"); 431 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 432 qdev_init_nofail(dev); 433 s = SYS_BUS_DEVICE(dev); 434 sysbus_connect_irq(s, 0, master_irq); 435 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 436 437 for (i = 0; i < MAX_CPUS; i++) { 438 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 439 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 440 } 441 } 442 443 static qemu_irq slavio_system_powerdown; 444 445 static void slavio_powerdown_req(Notifier *n, void *opaque) 446 { 447 qemu_irq_raise(slavio_system_powerdown); 448 } 449 450 static Notifier slavio_system_powerdown_notifier = { 451 .notify = slavio_powerdown_req 452 }; 453 454 #define MISC_LEDS 0x01600000 455 #define MISC_CFG 0x01800000 456 #define MISC_DIAG 0x01a00000 457 #define MISC_MDM 0x01b00000 458 #define MISC_SYS 0x01f00000 459 460 static void slavio_misc_init(hwaddr base, 461 hwaddr aux1_base, 462 hwaddr aux2_base, qemu_irq irq, 463 qemu_irq fdc_tc) 464 { 465 DeviceState *dev; 466 SysBusDevice *s; 467 468 dev = qdev_create(NULL, "slavio_misc"); 469 qdev_init_nofail(dev); 470 s = SYS_BUS_DEVICE(dev); 471 if (base) { 472 /* 8 bit registers */ 473 /* Slavio control */ 474 sysbus_mmio_map(s, 0, base + MISC_CFG); 475 /* Diagnostics */ 476 sysbus_mmio_map(s, 1, base + MISC_DIAG); 477 /* Modem control */ 478 sysbus_mmio_map(s, 2, base + MISC_MDM); 479 /* 16 bit registers */ 480 /* ss600mp diag LEDs */ 481 sysbus_mmio_map(s, 3, base + MISC_LEDS); 482 /* 32 bit registers */ 483 /* System control */ 484 sysbus_mmio_map(s, 4, base + MISC_SYS); 485 } 486 if (aux1_base) { 487 /* AUX 1 (Misc System Functions) */ 488 sysbus_mmio_map(s, 5, aux1_base); 489 } 490 if (aux2_base) { 491 /* AUX 2 (Software Powerdown Control) */ 492 sysbus_mmio_map(s, 6, aux2_base); 493 } 494 sysbus_connect_irq(s, 0, irq); 495 sysbus_connect_irq(s, 1, fdc_tc); 496 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 497 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 498 } 499 500 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 501 { 502 DeviceState *dev; 503 SysBusDevice *s; 504 505 dev = qdev_create(NULL, "eccmemctl"); 506 qdev_prop_set_uint32(dev, "version", version); 507 qdev_init_nofail(dev); 508 s = SYS_BUS_DEVICE(dev); 509 sysbus_connect_irq(s, 0, irq); 510 sysbus_mmio_map(s, 0, base); 511 if (version == 0) { // SS-600MP only 512 sysbus_mmio_map(s, 1, base + 0x1000); 513 } 514 } 515 516 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 517 { 518 DeviceState *dev; 519 SysBusDevice *s; 520 521 dev = qdev_create(NULL, "apc"); 522 qdev_init_nofail(dev); 523 s = SYS_BUS_DEVICE(dev); 524 /* Power management (APC) XXX: not a Slavio device */ 525 sysbus_mmio_map(s, 0, power_base); 526 sysbus_connect_irq(s, 0, cpu_halt); 527 } 528 529 static void tcx_init(hwaddr addr, int vram_size, int width, 530 int height, int depth) 531 { 532 DeviceState *dev; 533 SysBusDevice *s; 534 535 dev = qdev_create(NULL, "SUNW,tcx"); 536 qdev_prop_set_uint32(dev, "vram_size", vram_size); 537 qdev_prop_set_uint16(dev, "width", width); 538 qdev_prop_set_uint16(dev, "height", height); 539 qdev_prop_set_uint16(dev, "depth", depth); 540 qdev_prop_set_uint64(dev, "prom_addr", addr); 541 qdev_init_nofail(dev); 542 s = SYS_BUS_DEVICE(dev); 543 /* FCode ROM */ 544 sysbus_mmio_map(s, 0, addr); 545 /* 8-bit plane */ 546 sysbus_mmio_map(s, 1, addr + 0x00800000ULL); 547 /* DAC */ 548 sysbus_mmio_map(s, 2, addr + 0x00200000ULL); 549 /* TEC (dummy) */ 550 sysbus_mmio_map(s, 3, addr + 0x00700000ULL); 551 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */ 552 sysbus_mmio_map(s, 4, addr + 0x00301000ULL); 553 if (depth == 24) { 554 /* 24-bit plane */ 555 sysbus_mmio_map(s, 5, addr + 0x02000000ULL); 556 /* Control plane */ 557 sysbus_mmio_map(s, 6, addr + 0x0a000000ULL); 558 } else { 559 /* THC 8 bit (dummy) */ 560 sysbus_mmio_map(s, 5, addr + 0x00300000ULL); 561 } 562 } 563 564 /* NCR89C100/MACIO Internal ID register */ 565 566 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 567 568 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 569 570 static void idreg_init(hwaddr addr) 571 { 572 DeviceState *dev; 573 SysBusDevice *s; 574 575 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER); 576 qdev_init_nofail(dev); 577 s = SYS_BUS_DEVICE(dev); 578 579 sysbus_mmio_map(s, 0, addr); 580 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data)); 581 } 582 583 #define MACIO_ID_REGISTER(obj) \ 584 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER) 585 586 typedef struct IDRegState { 587 SysBusDevice parent_obj; 588 589 MemoryRegion mem; 590 } IDRegState; 591 592 static int idreg_init1(SysBusDevice *dev) 593 { 594 IDRegState *s = MACIO_ID_REGISTER(dev); 595 596 memory_region_init_ram(&s->mem, OBJECT(s), 597 "sun4m.idreg", sizeof(idreg_data)); 598 vmstate_register_ram_global(&s->mem); 599 memory_region_set_readonly(&s->mem, true); 600 sysbus_init_mmio(dev, &s->mem); 601 return 0; 602 } 603 604 static void idreg_class_init(ObjectClass *klass, void *data) 605 { 606 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 607 608 k->init = idreg_init1; 609 } 610 611 static const TypeInfo idreg_info = { 612 .name = TYPE_MACIO_ID_REGISTER, 613 .parent = TYPE_SYS_BUS_DEVICE, 614 .instance_size = sizeof(IDRegState), 615 .class_init = idreg_class_init, 616 }; 617 618 #define TYPE_TCX_AFX "tcx_afx" 619 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX) 620 621 typedef struct AFXState { 622 SysBusDevice parent_obj; 623 624 MemoryRegion mem; 625 } AFXState; 626 627 /* SS-5 TCX AFX register */ 628 static void afx_init(hwaddr addr) 629 { 630 DeviceState *dev; 631 SysBusDevice *s; 632 633 dev = qdev_create(NULL, TYPE_TCX_AFX); 634 qdev_init_nofail(dev); 635 s = SYS_BUS_DEVICE(dev); 636 637 sysbus_mmio_map(s, 0, addr); 638 } 639 640 static int afx_init1(SysBusDevice *dev) 641 { 642 AFXState *s = TCX_AFX(dev); 643 644 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4); 645 vmstate_register_ram_global(&s->mem); 646 sysbus_init_mmio(dev, &s->mem); 647 return 0; 648 } 649 650 static void afx_class_init(ObjectClass *klass, void *data) 651 { 652 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 653 654 k->init = afx_init1; 655 } 656 657 static const TypeInfo afx_info = { 658 .name = TYPE_TCX_AFX, 659 .parent = TYPE_SYS_BUS_DEVICE, 660 .instance_size = sizeof(AFXState), 661 .class_init = afx_class_init, 662 }; 663 664 #define TYPE_OPENPROM "openprom" 665 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 666 667 typedef struct PROMState { 668 SysBusDevice parent_obj; 669 670 MemoryRegion prom; 671 } PROMState; 672 673 /* Boot PROM (OpenBIOS) */ 674 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 675 { 676 hwaddr *base_addr = (hwaddr *)opaque; 677 return addr + *base_addr - PROM_VADDR; 678 } 679 680 static void prom_init(hwaddr addr, const char *bios_name) 681 { 682 DeviceState *dev; 683 SysBusDevice *s; 684 char *filename; 685 int ret; 686 687 dev = qdev_create(NULL, TYPE_OPENPROM); 688 qdev_init_nofail(dev); 689 s = SYS_BUS_DEVICE(dev); 690 691 sysbus_mmio_map(s, 0, addr); 692 693 /* load boot prom */ 694 if (bios_name == NULL) { 695 bios_name = PROM_FILENAME; 696 } 697 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 698 if (filename) { 699 ret = load_elf(filename, translate_prom_address, &addr, NULL, 700 NULL, NULL, 1, ELF_MACHINE, 0); 701 if (ret < 0 || ret > PROM_SIZE_MAX) { 702 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 703 } 704 g_free(filename); 705 } else { 706 ret = -1; 707 } 708 if (ret < 0 || ret > PROM_SIZE_MAX) { 709 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 710 exit(1); 711 } 712 } 713 714 static int prom_init1(SysBusDevice *dev) 715 { 716 PROMState *s = OPENPROM(dev); 717 718 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX); 719 vmstate_register_ram_global(&s->prom); 720 memory_region_set_readonly(&s->prom, true); 721 sysbus_init_mmio(dev, &s->prom); 722 return 0; 723 } 724 725 static Property prom_properties[] = { 726 {/* end of property list */}, 727 }; 728 729 static void prom_class_init(ObjectClass *klass, void *data) 730 { 731 DeviceClass *dc = DEVICE_CLASS(klass); 732 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 733 734 k->init = prom_init1; 735 dc->props = prom_properties; 736 } 737 738 static const TypeInfo prom_info = { 739 .name = TYPE_OPENPROM, 740 .parent = TYPE_SYS_BUS_DEVICE, 741 .instance_size = sizeof(PROMState), 742 .class_init = prom_class_init, 743 }; 744 745 #define TYPE_SUN4M_MEMORY "memory" 746 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY) 747 748 typedef struct RamDevice { 749 SysBusDevice parent_obj; 750 751 MemoryRegion ram; 752 uint64_t size; 753 } RamDevice; 754 755 /* System RAM */ 756 static int ram_init1(SysBusDevice *dev) 757 { 758 RamDevice *d = SUN4M_RAM(dev); 759 760 memory_region_init_ram(&d->ram, OBJECT(d), "sun4m.ram", d->size); 761 vmstate_register_ram_global(&d->ram); 762 sysbus_init_mmio(dev, &d->ram); 763 return 0; 764 } 765 766 static void ram_init(hwaddr addr, ram_addr_t RAM_size, 767 uint64_t max_mem) 768 { 769 DeviceState *dev; 770 SysBusDevice *s; 771 RamDevice *d; 772 773 /* allocate RAM */ 774 if ((uint64_t)RAM_size > max_mem) { 775 fprintf(stderr, 776 "qemu: Too much memory for this machine: %d, maximum %d\n", 777 (unsigned int)(RAM_size / (1024 * 1024)), 778 (unsigned int)(max_mem / (1024 * 1024))); 779 exit(1); 780 } 781 dev = qdev_create(NULL, "memory"); 782 s = SYS_BUS_DEVICE(dev); 783 784 d = SUN4M_RAM(dev); 785 d->size = RAM_size; 786 qdev_init_nofail(dev); 787 788 sysbus_mmio_map(s, 0, addr); 789 } 790 791 static Property ram_properties[] = { 792 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 793 DEFINE_PROP_END_OF_LIST(), 794 }; 795 796 static void ram_class_init(ObjectClass *klass, void *data) 797 { 798 DeviceClass *dc = DEVICE_CLASS(klass); 799 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 800 801 k->init = ram_init1; 802 dc->props = ram_properties; 803 } 804 805 static const TypeInfo ram_info = { 806 .name = TYPE_SUN4M_MEMORY, 807 .parent = TYPE_SYS_BUS_DEVICE, 808 .instance_size = sizeof(RamDevice), 809 .class_init = ram_class_init, 810 }; 811 812 static void cpu_devinit(const char *cpu_model, unsigned int id, 813 uint64_t prom_addr, qemu_irq **cpu_irqs) 814 { 815 CPUState *cs; 816 SPARCCPU *cpu; 817 CPUSPARCState *env; 818 819 cpu = cpu_sparc_init(cpu_model); 820 if (cpu == NULL) { 821 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); 822 exit(1); 823 } 824 env = &cpu->env; 825 826 cpu_sparc_set_id(env, id); 827 if (id == 0) { 828 qemu_register_reset(main_cpu_reset, cpu); 829 } else { 830 qemu_register_reset(secondary_cpu_reset, cpu); 831 cs = CPU(cpu); 832 cs->halted = 1; 833 } 834 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 835 env->prom_addr = prom_addr; 836 } 837 838 static void dummy_fdc_tc(void *opaque, int irq, int level) 839 { 840 } 841 842 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, 843 QEMUMachineInitArgs *args) 844 { 845 const char *cpu_model = args->cpu_model; 846 unsigned int i; 847 void *iommu, *espdma, *ledma, *nvram; 848 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS], 849 espdma_irq, ledma_irq; 850 qemu_irq esp_reset, dma_enable; 851 qemu_irq fdc_tc; 852 qemu_irq *cpu_halt; 853 unsigned long kernel_size; 854 DriveInfo *fd[MAX_FD]; 855 FWCfgState *fw_cfg; 856 unsigned int num_vsimms; 857 858 /* init CPUs */ 859 if (!cpu_model) 860 cpu_model = hwdef->default_cpu_model; 861 862 for(i = 0; i < smp_cpus; i++) { 863 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); 864 } 865 866 for (i = smp_cpus; i < MAX_CPUS; i++) 867 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 868 869 870 /* set up devices */ 871 ram_init(0, args->ram_size, hwdef->max_mem); 872 /* models without ECC don't trap when missing ram is accessed */ 873 if (!hwdef->ecc_base) { 874 empty_slot_init(args->ram_size, hwdef->max_mem - args->ram_size); 875 } 876 877 prom_init(hwdef->slavio_base, bios_name); 878 879 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 880 hwdef->intctl_base + 0x10000ULL, 881 cpu_irqs); 882 883 for (i = 0; i < 32; i++) { 884 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 885 } 886 for (i = 0; i < MAX_CPUS; i++) { 887 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 888 } 889 890 if (hwdef->idreg_base) { 891 idreg_init(hwdef->idreg_base); 892 } 893 894 if (hwdef->afx_base) { 895 afx_init(hwdef->afx_base); 896 } 897 898 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, 899 slavio_irq[30]); 900 901 if (hwdef->iommu_pad_base) { 902 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 903 Software shouldn't use aliased addresses, neither should it crash 904 when does. Using empty_slot instead of aliasing can help with 905 debugging such accesses */ 906 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); 907 } 908 909 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18], 910 iommu, &espdma_irq, 0); 911 912 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, 913 slavio_irq[16], iommu, &ledma_irq, 1); 914 915 if (graphic_depth != 8 && graphic_depth != 24) { 916 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); 917 exit (1); 918 } 919 num_vsimms = 0; 920 if (num_vsimms == 0) { 921 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height, 922 graphic_depth); 923 } 924 925 for (i = num_vsimms; i < MAX_VSIMMS; i++) { 926 /* vsimm registers probed by OBP */ 927 if (hwdef->vsimm[i].reg_base) { 928 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); 929 } 930 } 931 932 if (hwdef->sx_base) { 933 empty_slot_init(hwdef->sx_base, 0x2000); 934 } 935 936 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq); 937 938 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8); 939 940 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 941 942 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14], 943 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1); 944 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 945 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 946 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], 947 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); 948 949 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); 950 if (hwdef->apc_base) { 951 apc_init(hwdef->apc_base, cpu_halt[0]); 952 } 953 954 if (hwdef->fd_base) { 955 /* there is zero or one floppy drive */ 956 memset(fd, 0, sizeof(fd)); 957 fd[0] = drive_get(IF_FLOPPY, 0, 0); 958 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 959 &fdc_tc); 960 } else { 961 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1); 962 } 963 964 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 965 slavio_irq[30], fdc_tc); 966 967 if (drive_get_max_bus(IF_SCSI) > 0) { 968 fprintf(stderr, "qemu: too many SCSI bus\n"); 969 exit(1); 970 } 971 972 esp_init(hwdef->esp_base, 2, 973 espdma_memory_read, espdma_memory_write, 974 espdma, espdma_irq, &esp_reset, &dma_enable); 975 976 qdev_connect_gpio_out(espdma, 0, esp_reset); 977 qdev_connect_gpio_out(espdma, 1, dma_enable); 978 979 if (hwdef->cs_base) { 980 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, 981 slavio_irq[5]); 982 } 983 984 if (hwdef->dbri_base) { 985 /* ISDN chip with attached CS4215 audio codec */ 986 /* prom space */ 987 empty_slot_init(hwdef->dbri_base+0x1000, 0x30); 988 /* reg space */ 989 empty_slot_init(hwdef->dbri_base+0x10000, 0x100); 990 } 991 992 if (hwdef->bpp_base) { 993 /* parallel port */ 994 empty_slot_init(hwdef->bpp_base, 0x20); 995 } 996 997 kernel_size = sun4m_load_kernel(args->kernel_filename, 998 args->initrd_filename, 999 args->ram_size); 1000 1001 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, args->kernel_cmdline, 1002 args->boot_order, args->ram_size, kernel_size, graphic_width, 1003 graphic_height, graphic_depth, hwdef->nvram_machine_id, 1004 "Sun4m"); 1005 1006 if (hwdef->ecc_base) 1007 ecc_init(hwdef->ecc_base, slavio_irq[28], 1008 hwdef->ecc_version); 1009 1010 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); 1011 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1012 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 1013 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1014 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1015 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1016 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1017 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1018 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1019 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1020 if (args->kernel_cmdline) { 1021 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1022 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1023 args->kernel_cmdline); 1024 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, args->kernel_cmdline); 1025 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1026 strlen(args->kernel_cmdline) + 1); 1027 } else { 1028 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1029 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1030 } 1031 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1032 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used 1033 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, args->boot_order[0]); 1034 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1035 } 1036 1037 enum { 1038 ss5_id = 32, 1039 vger_id, 1040 lx_id, 1041 ss4_id, 1042 scls_id, 1043 sbook_id, 1044 ss10_id = 64, 1045 ss20_id, 1046 ss600mp_id, 1047 }; 1048 1049 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1050 /* SS-5 */ 1051 { 1052 .iommu_base = 0x10000000, 1053 .iommu_pad_base = 0x10004000, 1054 .iommu_pad_len = 0x0fffb000, 1055 .tcx_base = 0x50000000, 1056 .cs_base = 0x6c000000, 1057 .slavio_base = 0x70000000, 1058 .ms_kb_base = 0x71000000, 1059 .serial_base = 0x71100000, 1060 .nvram_base = 0x71200000, 1061 .fd_base = 0x71400000, 1062 .counter_base = 0x71d00000, 1063 .intctl_base = 0x71e00000, 1064 .idreg_base = 0x78000000, 1065 .dma_base = 0x78400000, 1066 .esp_base = 0x78800000, 1067 .le_base = 0x78c00000, 1068 .apc_base = 0x6a000000, 1069 .afx_base = 0x6e000000, 1070 .aux1_base = 0x71900000, 1071 .aux2_base = 0x71910000, 1072 .nvram_machine_id = 0x80, 1073 .machine_id = ss5_id, 1074 .iommu_version = 0x05000000, 1075 .max_mem = 0x10000000, 1076 .default_cpu_model = "Fujitsu MB86904", 1077 }, 1078 /* SS-10 */ 1079 { 1080 .iommu_base = 0xfe0000000ULL, 1081 .tcx_base = 0xe20000000ULL, 1082 .slavio_base = 0xff0000000ULL, 1083 .ms_kb_base = 0xff1000000ULL, 1084 .serial_base = 0xff1100000ULL, 1085 .nvram_base = 0xff1200000ULL, 1086 .fd_base = 0xff1700000ULL, 1087 .counter_base = 0xff1300000ULL, 1088 .intctl_base = 0xff1400000ULL, 1089 .idreg_base = 0xef0000000ULL, 1090 .dma_base = 0xef0400000ULL, 1091 .esp_base = 0xef0800000ULL, 1092 .le_base = 0xef0c00000ULL, 1093 .apc_base = 0xefa000000ULL, // XXX should not exist 1094 .aux1_base = 0xff1800000ULL, 1095 .aux2_base = 0xff1a01000ULL, 1096 .ecc_base = 0xf00000000ULL, 1097 .ecc_version = 0x10000000, // version 0, implementation 1 1098 .nvram_machine_id = 0x72, 1099 .machine_id = ss10_id, 1100 .iommu_version = 0x03000000, 1101 .max_mem = 0xf00000000ULL, 1102 .default_cpu_model = "TI SuperSparc II", 1103 }, 1104 /* SS-600MP */ 1105 { 1106 .iommu_base = 0xfe0000000ULL, 1107 .tcx_base = 0xe20000000ULL, 1108 .slavio_base = 0xff0000000ULL, 1109 .ms_kb_base = 0xff1000000ULL, 1110 .serial_base = 0xff1100000ULL, 1111 .nvram_base = 0xff1200000ULL, 1112 .counter_base = 0xff1300000ULL, 1113 .intctl_base = 0xff1400000ULL, 1114 .dma_base = 0xef0081000ULL, 1115 .esp_base = 0xef0080000ULL, 1116 .le_base = 0xef0060000ULL, 1117 .apc_base = 0xefa000000ULL, // XXX should not exist 1118 .aux1_base = 0xff1800000ULL, 1119 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1120 .ecc_base = 0xf00000000ULL, 1121 .ecc_version = 0x00000000, // version 0, implementation 0 1122 .nvram_machine_id = 0x71, 1123 .machine_id = ss600mp_id, 1124 .iommu_version = 0x01000000, 1125 .max_mem = 0xf00000000ULL, 1126 .default_cpu_model = "TI SuperSparc II", 1127 }, 1128 /* SS-20 */ 1129 { 1130 .iommu_base = 0xfe0000000ULL, 1131 .tcx_base = 0xe20000000ULL, 1132 .slavio_base = 0xff0000000ULL, 1133 .ms_kb_base = 0xff1000000ULL, 1134 .serial_base = 0xff1100000ULL, 1135 .nvram_base = 0xff1200000ULL, 1136 .fd_base = 0xff1700000ULL, 1137 .counter_base = 0xff1300000ULL, 1138 .intctl_base = 0xff1400000ULL, 1139 .idreg_base = 0xef0000000ULL, 1140 .dma_base = 0xef0400000ULL, 1141 .esp_base = 0xef0800000ULL, 1142 .le_base = 0xef0c00000ULL, 1143 .bpp_base = 0xef4800000ULL, 1144 .apc_base = 0xefa000000ULL, // XXX should not exist 1145 .aux1_base = 0xff1800000ULL, 1146 .aux2_base = 0xff1a01000ULL, 1147 .dbri_base = 0xee0000000ULL, 1148 .sx_base = 0xf80000000ULL, 1149 .vsimm = { 1150 { 1151 .reg_base = 0x9c000000ULL, 1152 .vram_base = 0xfc000000ULL 1153 }, { 1154 .reg_base = 0x90000000ULL, 1155 .vram_base = 0xf0000000ULL 1156 }, { 1157 .reg_base = 0x94000000ULL 1158 }, { 1159 .reg_base = 0x98000000ULL 1160 } 1161 }, 1162 .ecc_base = 0xf00000000ULL, 1163 .ecc_version = 0x20000000, // version 0, implementation 2 1164 .nvram_machine_id = 0x72, 1165 .machine_id = ss20_id, 1166 .iommu_version = 0x13000000, 1167 .max_mem = 0xf00000000ULL, 1168 .default_cpu_model = "TI SuperSparc II", 1169 }, 1170 /* Voyager */ 1171 { 1172 .iommu_base = 0x10000000, 1173 .tcx_base = 0x50000000, 1174 .slavio_base = 0x70000000, 1175 .ms_kb_base = 0x71000000, 1176 .serial_base = 0x71100000, 1177 .nvram_base = 0x71200000, 1178 .fd_base = 0x71400000, 1179 .counter_base = 0x71d00000, 1180 .intctl_base = 0x71e00000, 1181 .idreg_base = 0x78000000, 1182 .dma_base = 0x78400000, 1183 .esp_base = 0x78800000, 1184 .le_base = 0x78c00000, 1185 .apc_base = 0x71300000, // pmc 1186 .aux1_base = 0x71900000, 1187 .aux2_base = 0x71910000, 1188 .nvram_machine_id = 0x80, 1189 .machine_id = vger_id, 1190 .iommu_version = 0x05000000, 1191 .max_mem = 0x10000000, 1192 .default_cpu_model = "Fujitsu MB86904", 1193 }, 1194 /* LX */ 1195 { 1196 .iommu_base = 0x10000000, 1197 .iommu_pad_base = 0x10004000, 1198 .iommu_pad_len = 0x0fffb000, 1199 .tcx_base = 0x50000000, 1200 .slavio_base = 0x70000000, 1201 .ms_kb_base = 0x71000000, 1202 .serial_base = 0x71100000, 1203 .nvram_base = 0x71200000, 1204 .fd_base = 0x71400000, 1205 .counter_base = 0x71d00000, 1206 .intctl_base = 0x71e00000, 1207 .idreg_base = 0x78000000, 1208 .dma_base = 0x78400000, 1209 .esp_base = 0x78800000, 1210 .le_base = 0x78c00000, 1211 .aux1_base = 0x71900000, 1212 .aux2_base = 0x71910000, 1213 .nvram_machine_id = 0x80, 1214 .machine_id = lx_id, 1215 .iommu_version = 0x04000000, 1216 .max_mem = 0x10000000, 1217 .default_cpu_model = "TI MicroSparc I", 1218 }, 1219 /* SS-4 */ 1220 { 1221 .iommu_base = 0x10000000, 1222 .tcx_base = 0x50000000, 1223 .cs_base = 0x6c000000, 1224 .slavio_base = 0x70000000, 1225 .ms_kb_base = 0x71000000, 1226 .serial_base = 0x71100000, 1227 .nvram_base = 0x71200000, 1228 .fd_base = 0x71400000, 1229 .counter_base = 0x71d00000, 1230 .intctl_base = 0x71e00000, 1231 .idreg_base = 0x78000000, 1232 .dma_base = 0x78400000, 1233 .esp_base = 0x78800000, 1234 .le_base = 0x78c00000, 1235 .apc_base = 0x6a000000, 1236 .aux1_base = 0x71900000, 1237 .aux2_base = 0x71910000, 1238 .nvram_machine_id = 0x80, 1239 .machine_id = ss4_id, 1240 .iommu_version = 0x05000000, 1241 .max_mem = 0x10000000, 1242 .default_cpu_model = "Fujitsu MB86904", 1243 }, 1244 /* SPARCClassic */ 1245 { 1246 .iommu_base = 0x10000000, 1247 .tcx_base = 0x50000000, 1248 .slavio_base = 0x70000000, 1249 .ms_kb_base = 0x71000000, 1250 .serial_base = 0x71100000, 1251 .nvram_base = 0x71200000, 1252 .fd_base = 0x71400000, 1253 .counter_base = 0x71d00000, 1254 .intctl_base = 0x71e00000, 1255 .idreg_base = 0x78000000, 1256 .dma_base = 0x78400000, 1257 .esp_base = 0x78800000, 1258 .le_base = 0x78c00000, 1259 .apc_base = 0x6a000000, 1260 .aux1_base = 0x71900000, 1261 .aux2_base = 0x71910000, 1262 .nvram_machine_id = 0x80, 1263 .machine_id = scls_id, 1264 .iommu_version = 0x05000000, 1265 .max_mem = 0x10000000, 1266 .default_cpu_model = "TI MicroSparc I", 1267 }, 1268 /* SPARCbook */ 1269 { 1270 .iommu_base = 0x10000000, 1271 .tcx_base = 0x50000000, // XXX 1272 .slavio_base = 0x70000000, 1273 .ms_kb_base = 0x71000000, 1274 .serial_base = 0x71100000, 1275 .nvram_base = 0x71200000, 1276 .fd_base = 0x71400000, 1277 .counter_base = 0x71d00000, 1278 .intctl_base = 0x71e00000, 1279 .idreg_base = 0x78000000, 1280 .dma_base = 0x78400000, 1281 .esp_base = 0x78800000, 1282 .le_base = 0x78c00000, 1283 .apc_base = 0x6a000000, 1284 .aux1_base = 0x71900000, 1285 .aux2_base = 0x71910000, 1286 .nvram_machine_id = 0x80, 1287 .machine_id = sbook_id, 1288 .iommu_version = 0x05000000, 1289 .max_mem = 0x10000000, 1290 .default_cpu_model = "TI MicroSparc I", 1291 }, 1292 }; 1293 1294 /* SPARCstation 5 hardware initialisation */ 1295 static void ss5_init(QEMUMachineInitArgs *args) 1296 { 1297 sun4m_hw_init(&sun4m_hwdefs[0], args); 1298 } 1299 1300 /* SPARCstation 10 hardware initialisation */ 1301 static void ss10_init(QEMUMachineInitArgs *args) 1302 { 1303 sun4m_hw_init(&sun4m_hwdefs[1], args); 1304 } 1305 1306 /* SPARCserver 600MP hardware initialisation */ 1307 static void ss600mp_init(QEMUMachineInitArgs *args) 1308 { 1309 sun4m_hw_init(&sun4m_hwdefs[2], args); 1310 } 1311 1312 /* SPARCstation 20 hardware initialisation */ 1313 static void ss20_init(QEMUMachineInitArgs *args) 1314 { 1315 sun4m_hw_init(&sun4m_hwdefs[3], args); 1316 } 1317 1318 /* SPARCstation Voyager hardware initialisation */ 1319 static void vger_init(QEMUMachineInitArgs *args) 1320 { 1321 sun4m_hw_init(&sun4m_hwdefs[4], args); 1322 } 1323 1324 /* SPARCstation LX hardware initialisation */ 1325 static void ss_lx_init(QEMUMachineInitArgs *args) 1326 { 1327 sun4m_hw_init(&sun4m_hwdefs[5], args); 1328 } 1329 1330 /* SPARCstation 4 hardware initialisation */ 1331 static void ss4_init(QEMUMachineInitArgs *args) 1332 { 1333 sun4m_hw_init(&sun4m_hwdefs[6], args); 1334 } 1335 1336 /* SPARCClassic hardware initialisation */ 1337 static void scls_init(QEMUMachineInitArgs *args) 1338 { 1339 sun4m_hw_init(&sun4m_hwdefs[7], args); 1340 } 1341 1342 /* SPARCbook hardware initialisation */ 1343 static void sbook_init(QEMUMachineInitArgs *args) 1344 { 1345 sun4m_hw_init(&sun4m_hwdefs[8], args); 1346 } 1347 1348 static QEMUMachine ss5_machine = { 1349 .name = "SS-5", 1350 .desc = "Sun4m platform, SPARCstation 5", 1351 .init = ss5_init, 1352 .block_default_type = IF_SCSI, 1353 .is_default = 1, 1354 .default_boot_order = "c", 1355 }; 1356 1357 static QEMUMachine ss10_machine = { 1358 .name = "SS-10", 1359 .desc = "Sun4m platform, SPARCstation 10", 1360 .init = ss10_init, 1361 .block_default_type = IF_SCSI, 1362 .max_cpus = 4, 1363 .default_boot_order = "c", 1364 }; 1365 1366 static QEMUMachine ss600mp_machine = { 1367 .name = "SS-600MP", 1368 .desc = "Sun4m platform, SPARCserver 600MP", 1369 .init = ss600mp_init, 1370 .block_default_type = IF_SCSI, 1371 .max_cpus = 4, 1372 .default_boot_order = "c", 1373 }; 1374 1375 static QEMUMachine ss20_machine = { 1376 .name = "SS-20", 1377 .desc = "Sun4m platform, SPARCstation 20", 1378 .init = ss20_init, 1379 .block_default_type = IF_SCSI, 1380 .max_cpus = 4, 1381 .default_boot_order = "c", 1382 }; 1383 1384 static QEMUMachine voyager_machine = { 1385 .name = "Voyager", 1386 .desc = "Sun4m platform, SPARCstation Voyager", 1387 .init = vger_init, 1388 .block_default_type = IF_SCSI, 1389 .default_boot_order = "c", 1390 }; 1391 1392 static QEMUMachine ss_lx_machine = { 1393 .name = "LX", 1394 .desc = "Sun4m platform, SPARCstation LX", 1395 .init = ss_lx_init, 1396 .block_default_type = IF_SCSI, 1397 .default_boot_order = "c", 1398 }; 1399 1400 static QEMUMachine ss4_machine = { 1401 .name = "SS-4", 1402 .desc = "Sun4m platform, SPARCstation 4", 1403 .init = ss4_init, 1404 .block_default_type = IF_SCSI, 1405 .default_boot_order = "c", 1406 }; 1407 1408 static QEMUMachine scls_machine = { 1409 .name = "SPARCClassic", 1410 .desc = "Sun4m platform, SPARCClassic", 1411 .init = scls_init, 1412 .block_default_type = IF_SCSI, 1413 .default_boot_order = "c", 1414 }; 1415 1416 static QEMUMachine sbook_machine = { 1417 .name = "SPARCbook", 1418 .desc = "Sun4m platform, SPARCbook", 1419 .init = sbook_init, 1420 .block_default_type = IF_SCSI, 1421 .default_boot_order = "c", 1422 }; 1423 1424 static void sun4m_register_types(void) 1425 { 1426 type_register_static(&idreg_info); 1427 type_register_static(&afx_info); 1428 type_register_static(&prom_info); 1429 type_register_static(&ram_info); 1430 } 1431 1432 static void sun4m_machine_init(void) 1433 { 1434 qemu_register_machine(&ss5_machine); 1435 qemu_register_machine(&ss10_machine); 1436 qemu_register_machine(&ss600mp_machine); 1437 qemu_register_machine(&ss20_machine); 1438 qemu_register_machine(&voyager_machine); 1439 qemu_register_machine(&ss_lx_machine); 1440 qemu_register_machine(&ss4_machine); 1441 qemu_register_machine(&scls_machine); 1442 qemu_register_machine(&sbook_machine); 1443 } 1444 1445 type_init(sun4m_register_types) 1446 machine_init(sun4m_machine_init); 1447