1 /* 2 * SMBIOS Support 3 * 4 * Copyright (C) 2009 Hewlett-Packard Development Company, L.P. 5 * Copyright (C) 2013 Red Hat, Inc. 6 * 7 * Authors: 8 * Alex Williamson <alex.williamson@hp.com> 9 * Markus Armbruster <armbru@redhat.com> 10 * 11 * This work is licensed under the terms of the GNU GPL, version 2. See 12 * the COPYING file in the top-level directory. 13 * 14 * Contributions after 2012-01-13 are licensed under the terms of the 15 * GNU GPL, version 2 or (at your option) any later version. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/units.h" 20 #include "qapi/error.h" 21 #include "qemu/config-file.h" 22 #include "qemu/error-report.h" 23 #include "qemu/module.h" 24 #include "qemu/option.h" 25 #include "sysemu/sysemu.h" 26 #include "qemu/uuid.h" 27 #include "hw/firmware/smbios.h" 28 #include "hw/loader.h" 29 #include "hw/boards.h" 30 #include "hw/pci/pci_bus.h" 31 #include "hw/pci/pci_device.h" 32 #include "smbios_build.h" 33 34 /* legacy structures and constants for <= 2.0 machines */ 35 struct smbios_header { 36 uint16_t length; 37 uint8_t type; 38 } QEMU_PACKED; 39 40 struct smbios_field { 41 struct smbios_header header; 42 uint8_t type; 43 uint16_t offset; 44 uint8_t data[]; 45 } QEMU_PACKED; 46 47 struct smbios_table { 48 struct smbios_header header; 49 uint8_t data[]; 50 } QEMU_PACKED; 51 52 #define SMBIOS_FIELD_ENTRY 0 53 #define SMBIOS_TABLE_ENTRY 1 54 55 static uint8_t *smbios_entries; 56 static size_t smbios_entries_len; 57 static bool smbios_uuid_encoded = true; 58 /* end: legacy structures & constants for <= 2.0 machines */ 59 60 /* 61 * SMBIOS tables provided by user with '-smbios file=<foo>' option 62 */ 63 uint8_t *usr_blobs; 64 size_t usr_blobs_len; 65 static GArray *usr_blobs_sizes; 66 static unsigned usr_table_max; 67 static unsigned usr_table_cnt; 68 69 uint8_t *smbios_tables; 70 size_t smbios_tables_len; 71 unsigned smbios_table_max; 72 unsigned smbios_table_cnt; 73 static SmbiosEntryPointType smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32; 74 75 static SmbiosEntryPoint ep; 76 77 static int smbios_type4_count = 0; 78 static bool smbios_have_defaults; 79 static uint32_t smbios_cpuid_version, smbios_cpuid_features; 80 81 static DECLARE_BITMAP(have_binfile_bitmap, SMBIOS_MAX_TYPE+1); 82 static DECLARE_BITMAP(have_fields_bitmap, SMBIOS_MAX_TYPE+1); 83 84 static struct { 85 const char *vendor, *version, *date; 86 bool have_major_minor, uefi; 87 uint8_t major, minor; 88 } type0; 89 90 static struct { 91 const char *manufacturer, *product, *version, *serial, *sku, *family; 92 /* uuid is in qemu_uuid */ 93 } type1; 94 95 static struct { 96 const char *manufacturer, *product, *version, *serial, *asset, *location; 97 } type2; 98 99 static struct { 100 const char *manufacturer, *version, *serial, *asset, *sku; 101 } type3; 102 103 /* 104 * SVVP requires max_speed and current_speed to be set and not being 105 * 0 which counts as unknown (SMBIOS 3.1.0/Table 21). Set the 106 * default value to 2000MHz as we did before. 107 */ 108 #define DEFAULT_CPU_SPEED 2000 109 110 static struct { 111 uint16_t processor_family; 112 const char *sock_pfx, *manufacturer, *version, *serial, *asset, *part; 113 uint64_t max_speed; 114 uint64_t current_speed; 115 uint64_t processor_id; 116 } type4 = { 117 .max_speed = DEFAULT_CPU_SPEED, 118 .current_speed = DEFAULT_CPU_SPEED, 119 .processor_id = 0, 120 .processor_family = 0x01, /* Other */ 121 }; 122 123 struct type8_instance { 124 const char *internal_reference, *external_reference; 125 uint8_t connector_type, port_type; 126 QTAILQ_ENTRY(type8_instance) next; 127 }; 128 static QTAILQ_HEAD(, type8_instance) type8 = QTAILQ_HEAD_INITIALIZER(type8); 129 130 /* type 9 instance for parsing */ 131 struct type9_instance { 132 const char *slot_designation, *pcidev; 133 uint8_t slot_type, slot_data_bus_width, current_usage, slot_length, 134 slot_characteristics1, slot_characteristics2; 135 uint16_t slot_id; 136 QTAILQ_ENTRY(type9_instance) next; 137 }; 138 static QTAILQ_HEAD(, type9_instance) type9 = QTAILQ_HEAD_INITIALIZER(type9); 139 140 static struct { 141 size_t nvalues; 142 char **values; 143 } type11; 144 145 static struct { 146 const char *loc_pfx, *bank, *manufacturer, *serial, *asset, *part; 147 uint16_t speed; 148 } type17; 149 150 static QEnumLookup type41_kind_lookup = { 151 .array = (const char *const[]) { 152 "other", 153 "unknown", 154 "video", 155 "scsi", 156 "ethernet", 157 "tokenring", 158 "sound", 159 "pata", 160 "sata", 161 "sas", 162 }, 163 .size = 10 164 }; 165 struct type41_instance { 166 const char *designation, *pcidev; 167 uint8_t instance, kind; 168 QTAILQ_ENTRY(type41_instance) next; 169 }; 170 static QTAILQ_HEAD(, type41_instance) type41 = QTAILQ_HEAD_INITIALIZER(type41); 171 172 static QemuOptsList qemu_smbios_opts = { 173 .name = "smbios", 174 .head = QTAILQ_HEAD_INITIALIZER(qemu_smbios_opts.head), 175 .desc = { 176 /* 177 * no elements => accept any params 178 * validation will happen later 179 */ 180 { /* end of list */ } 181 } 182 }; 183 184 static const QemuOptDesc qemu_smbios_file_opts[] = { 185 { 186 .name = "file", 187 .type = QEMU_OPT_STRING, 188 .help = "binary file containing an SMBIOS element", 189 }, 190 { /* end of list */ } 191 }; 192 193 static const QemuOptDesc qemu_smbios_type0_opts[] = { 194 { 195 .name = "type", 196 .type = QEMU_OPT_NUMBER, 197 .help = "SMBIOS element type", 198 },{ 199 .name = "vendor", 200 .type = QEMU_OPT_STRING, 201 .help = "vendor name", 202 },{ 203 .name = "version", 204 .type = QEMU_OPT_STRING, 205 .help = "version number", 206 },{ 207 .name = "date", 208 .type = QEMU_OPT_STRING, 209 .help = "release date", 210 },{ 211 .name = "release", 212 .type = QEMU_OPT_STRING, 213 .help = "revision number", 214 },{ 215 .name = "uefi", 216 .type = QEMU_OPT_BOOL, 217 .help = "uefi support", 218 }, 219 { /* end of list */ } 220 }; 221 222 static const QemuOptDesc qemu_smbios_type1_opts[] = { 223 { 224 .name = "type", 225 .type = QEMU_OPT_NUMBER, 226 .help = "SMBIOS element type", 227 },{ 228 .name = "manufacturer", 229 .type = QEMU_OPT_STRING, 230 .help = "manufacturer name", 231 },{ 232 .name = "product", 233 .type = QEMU_OPT_STRING, 234 .help = "product name", 235 },{ 236 .name = "version", 237 .type = QEMU_OPT_STRING, 238 .help = "version number", 239 },{ 240 .name = "serial", 241 .type = QEMU_OPT_STRING, 242 .help = "serial number", 243 },{ 244 .name = "uuid", 245 .type = QEMU_OPT_STRING, 246 .help = "UUID", 247 },{ 248 .name = "sku", 249 .type = QEMU_OPT_STRING, 250 .help = "SKU number", 251 },{ 252 .name = "family", 253 .type = QEMU_OPT_STRING, 254 .help = "family name", 255 }, 256 { /* end of list */ } 257 }; 258 259 static const QemuOptDesc qemu_smbios_type2_opts[] = { 260 { 261 .name = "type", 262 .type = QEMU_OPT_NUMBER, 263 .help = "SMBIOS element type", 264 },{ 265 .name = "manufacturer", 266 .type = QEMU_OPT_STRING, 267 .help = "manufacturer name", 268 },{ 269 .name = "product", 270 .type = QEMU_OPT_STRING, 271 .help = "product name", 272 },{ 273 .name = "version", 274 .type = QEMU_OPT_STRING, 275 .help = "version number", 276 },{ 277 .name = "serial", 278 .type = QEMU_OPT_STRING, 279 .help = "serial number", 280 },{ 281 .name = "asset", 282 .type = QEMU_OPT_STRING, 283 .help = "asset tag number", 284 },{ 285 .name = "location", 286 .type = QEMU_OPT_STRING, 287 .help = "location in chassis", 288 }, 289 { /* end of list */ } 290 }; 291 292 static const QemuOptDesc qemu_smbios_type3_opts[] = { 293 { 294 .name = "type", 295 .type = QEMU_OPT_NUMBER, 296 .help = "SMBIOS element type", 297 },{ 298 .name = "manufacturer", 299 .type = QEMU_OPT_STRING, 300 .help = "manufacturer name", 301 },{ 302 .name = "version", 303 .type = QEMU_OPT_STRING, 304 .help = "version number", 305 },{ 306 .name = "serial", 307 .type = QEMU_OPT_STRING, 308 .help = "serial number", 309 },{ 310 .name = "asset", 311 .type = QEMU_OPT_STRING, 312 .help = "asset tag number", 313 },{ 314 .name = "sku", 315 .type = QEMU_OPT_STRING, 316 .help = "SKU number", 317 }, 318 { /* end of list */ } 319 }; 320 321 static const QemuOptDesc qemu_smbios_type4_opts[] = { 322 { 323 .name = "type", 324 .type = QEMU_OPT_NUMBER, 325 .help = "SMBIOS element type", 326 },{ 327 .name = "sock_pfx", 328 .type = QEMU_OPT_STRING, 329 .help = "socket designation string prefix", 330 },{ 331 .name = "manufacturer", 332 .type = QEMU_OPT_STRING, 333 .help = "manufacturer name", 334 },{ 335 .name = "version", 336 .type = QEMU_OPT_STRING, 337 .help = "version number", 338 },{ 339 .name = "max-speed", 340 .type = QEMU_OPT_NUMBER, 341 .help = "max speed in MHz", 342 },{ 343 .name = "current-speed", 344 .type = QEMU_OPT_NUMBER, 345 .help = "speed at system boot in MHz", 346 },{ 347 .name = "serial", 348 .type = QEMU_OPT_STRING, 349 .help = "serial number", 350 },{ 351 .name = "asset", 352 .type = QEMU_OPT_STRING, 353 .help = "asset tag number", 354 },{ 355 .name = "part", 356 .type = QEMU_OPT_STRING, 357 .help = "part number", 358 }, { 359 .name = "processor-family", 360 .type = QEMU_OPT_NUMBER, 361 .help = "processor family", 362 }, { 363 .name = "processor-id", 364 .type = QEMU_OPT_NUMBER, 365 .help = "processor id", 366 }, 367 { /* end of list */ } 368 }; 369 370 static const QemuOptDesc qemu_smbios_type8_opts[] = { 371 { 372 .name = "type", 373 .type = QEMU_OPT_NUMBER, 374 .help = "SMBIOS element type", 375 }, 376 { 377 .name = "internal_reference", 378 .type = QEMU_OPT_STRING, 379 .help = "internal reference designator", 380 }, 381 { 382 .name = "external_reference", 383 .type = QEMU_OPT_STRING, 384 .help = "external reference designator", 385 }, 386 { 387 .name = "connector_type", 388 .type = QEMU_OPT_NUMBER, 389 .help = "connector type", 390 }, 391 { 392 .name = "port_type", 393 .type = QEMU_OPT_NUMBER, 394 .help = "port type", 395 }, 396 { /* end of list */ } 397 }; 398 399 static const QemuOptDesc qemu_smbios_type9_opts[] = { 400 { 401 .name = "type", 402 .type = QEMU_OPT_NUMBER, 403 .help = "SMBIOS element type", 404 }, 405 { 406 .name = "slot_designation", 407 .type = QEMU_OPT_STRING, 408 .help = "string number for reference designation", 409 }, 410 { 411 .name = "slot_type", 412 .type = QEMU_OPT_NUMBER, 413 .help = "connector type", 414 }, 415 { 416 .name = "slot_data_bus_width", 417 .type = QEMU_OPT_NUMBER, 418 .help = "port type", 419 }, 420 { 421 .name = "current_usage", 422 .type = QEMU_OPT_NUMBER, 423 .help = "current usage", 424 }, 425 { 426 .name = "slot_length", 427 .type = QEMU_OPT_NUMBER, 428 .help = "system slot length", 429 }, 430 { 431 .name = "slot_id", 432 .type = QEMU_OPT_NUMBER, 433 .help = "system slot id", 434 }, 435 { 436 .name = "slot_characteristics1", 437 .type = QEMU_OPT_NUMBER, 438 .help = "slot characteristics1, see the spec", 439 }, 440 { 441 .name = "slot_characteristics2", 442 .type = QEMU_OPT_NUMBER, 443 .help = "slot characteristics2, see the spec", 444 }, 445 { 446 .name = "pci_device", 447 .type = QEMU_OPT_STRING, 448 .help = "PCI device, if provided." 449 } 450 }; 451 452 static const QemuOptDesc qemu_smbios_type11_opts[] = { 453 { 454 .name = "type", 455 .type = QEMU_OPT_NUMBER, 456 .help = "SMBIOS element type", 457 }, 458 { 459 .name = "value", 460 .type = QEMU_OPT_STRING, 461 .help = "OEM string data", 462 }, 463 { 464 .name = "path", 465 .type = QEMU_OPT_STRING, 466 .help = "OEM string data from file", 467 }, 468 { /* end of list */ } 469 }; 470 471 static const QemuOptDesc qemu_smbios_type17_opts[] = { 472 { 473 .name = "type", 474 .type = QEMU_OPT_NUMBER, 475 .help = "SMBIOS element type", 476 },{ 477 .name = "loc_pfx", 478 .type = QEMU_OPT_STRING, 479 .help = "device locator string prefix", 480 },{ 481 .name = "bank", 482 .type = QEMU_OPT_STRING, 483 .help = "bank locator string", 484 },{ 485 .name = "manufacturer", 486 .type = QEMU_OPT_STRING, 487 .help = "manufacturer name", 488 },{ 489 .name = "serial", 490 .type = QEMU_OPT_STRING, 491 .help = "serial number", 492 },{ 493 .name = "asset", 494 .type = QEMU_OPT_STRING, 495 .help = "asset tag number", 496 },{ 497 .name = "part", 498 .type = QEMU_OPT_STRING, 499 .help = "part number", 500 },{ 501 .name = "speed", 502 .type = QEMU_OPT_NUMBER, 503 .help = "maximum capable speed", 504 }, 505 { /* end of list */ } 506 }; 507 508 static const QemuOptDesc qemu_smbios_type41_opts[] = { 509 { 510 .name = "type", 511 .type = QEMU_OPT_NUMBER, 512 .help = "SMBIOS element type", 513 },{ 514 .name = "designation", 515 .type = QEMU_OPT_STRING, 516 .help = "reference designation string", 517 },{ 518 .name = "kind", 519 .type = QEMU_OPT_STRING, 520 .help = "device type", 521 .def_value_str = "other", 522 },{ 523 .name = "instance", 524 .type = QEMU_OPT_NUMBER, 525 .help = "device type instance", 526 },{ 527 .name = "pcidev", 528 .type = QEMU_OPT_STRING, 529 .help = "PCI device", 530 }, 531 { /* end of list */ } 532 }; 533 534 static void smbios_register_config(void) 535 { 536 qemu_add_opts(&qemu_smbios_opts); 537 } 538 539 opts_init(smbios_register_config); 540 541 /* 542 * The SMBIOS 2.1 "structure table length" field in the 543 * entry point uses a 16-bit integer, so we're limited 544 * in total table size 545 */ 546 #define SMBIOS_21_MAX_TABLES_LEN 0xffff 547 548 static void smbios_check_type4_count(uint32_t expected_t4_count) 549 { 550 if (smbios_type4_count && smbios_type4_count != expected_t4_count) { 551 error_report("Expected %d SMBIOS Type 4 tables, got %d instead", 552 expected_t4_count, smbios_type4_count); 553 exit(1); 554 } 555 } 556 557 static void smbios_validate_table(void) 558 { 559 if (smbios_ep_type == SMBIOS_ENTRY_POINT_TYPE_32 && 560 smbios_tables_len > SMBIOS_21_MAX_TABLES_LEN) { 561 error_report("SMBIOS 2.1 table length %zu exceeds %d", 562 smbios_tables_len, SMBIOS_21_MAX_TABLES_LEN); 563 exit(1); 564 } 565 } 566 567 568 /* legacy setup functions for <= 2.0 machines */ 569 static void smbios_add_field(int type, int offset, const void *data, size_t len) 570 { 571 struct smbios_field *field; 572 573 if (!smbios_entries) { 574 smbios_entries_len = sizeof(uint16_t); 575 smbios_entries = g_malloc0(smbios_entries_len); 576 } 577 smbios_entries = g_realloc(smbios_entries, smbios_entries_len + 578 sizeof(*field) + len); 579 field = (struct smbios_field *)(smbios_entries + smbios_entries_len); 580 field->header.type = SMBIOS_FIELD_ENTRY; 581 field->header.length = cpu_to_le16(sizeof(*field) + len); 582 583 field->type = type; 584 field->offset = cpu_to_le16(offset); 585 memcpy(field->data, data, len); 586 587 smbios_entries_len += sizeof(*field) + len; 588 (*(uint16_t *)smbios_entries) = 589 cpu_to_le16(le16_to_cpu(*(uint16_t *)smbios_entries) + 1); 590 } 591 592 static void smbios_maybe_add_str(int type, int offset, const char *data) 593 { 594 if (data) { 595 smbios_add_field(type, offset, data, strlen(data) + 1); 596 } 597 } 598 599 static void smbios_build_type_0_fields(void) 600 { 601 smbios_maybe_add_str(0, offsetof(struct smbios_type_0, vendor_str), 602 type0.vendor); 603 smbios_maybe_add_str(0, offsetof(struct smbios_type_0, bios_version_str), 604 type0.version); 605 smbios_maybe_add_str(0, offsetof(struct smbios_type_0, 606 bios_release_date_str), 607 type0.date); 608 if (type0.have_major_minor) { 609 smbios_add_field(0, offsetof(struct smbios_type_0, 610 system_bios_major_release), 611 &type0.major, 1); 612 smbios_add_field(0, offsetof(struct smbios_type_0, 613 system_bios_minor_release), 614 &type0.minor, 1); 615 } 616 } 617 618 static void smbios_build_type_1_fields(void) 619 { 620 smbios_maybe_add_str(1, offsetof(struct smbios_type_1, manufacturer_str), 621 type1.manufacturer); 622 smbios_maybe_add_str(1, offsetof(struct smbios_type_1, product_name_str), 623 type1.product); 624 smbios_maybe_add_str(1, offsetof(struct smbios_type_1, version_str), 625 type1.version); 626 smbios_maybe_add_str(1, offsetof(struct smbios_type_1, serial_number_str), 627 type1.serial); 628 smbios_maybe_add_str(1, offsetof(struct smbios_type_1, sku_number_str), 629 type1.sku); 630 smbios_maybe_add_str(1, offsetof(struct smbios_type_1, family_str), 631 type1.family); 632 if (qemu_uuid_set) { 633 /* We don't encode the UUID in the "wire format" here because this 634 * function is for legacy mode and needs to keep the guest ABI, and 635 * because we don't know what's the SMBIOS version advertised by the 636 * BIOS. 637 */ 638 smbios_add_field(1, offsetof(struct smbios_type_1, uuid), 639 &qemu_uuid, 16); 640 } 641 } 642 643 uint8_t *smbios_get_table_legacy(size_t *length) 644 { 645 int i; 646 size_t usr_offset; 647 648 /* also complain if fields were given for types > 1 */ 649 if (find_next_bit(have_fields_bitmap, 650 SMBIOS_MAX_TYPE + 1, 2) < SMBIOS_MAX_TYPE + 1) { 651 error_report("can't process fields for smbios " 652 "types > 1 on machine versions < 2.1!"); 653 exit(1); 654 } 655 656 if (test_bit(4, have_binfile_bitmap)) { 657 error_report("can't process table for smbios " 658 "type 4 on machine versions < 2.1!"); 659 exit(1); 660 } 661 662 g_free(smbios_entries); 663 smbios_entries_len = sizeof(uint16_t); 664 smbios_entries = g_malloc0(smbios_entries_len); 665 666 for (i = 0, usr_offset = 0; usr_blobs_sizes && i < usr_blobs_sizes->len; 667 i++) 668 { 669 struct smbios_table *table; 670 struct smbios_structure_header *header; 671 size_t size = g_array_index(usr_blobs_sizes, size_t, i); 672 673 header = (struct smbios_structure_header *)(usr_blobs + usr_offset); 674 smbios_entries = g_realloc(smbios_entries, smbios_entries_len + 675 size + sizeof(*table)); 676 table = (struct smbios_table *)(smbios_entries + smbios_entries_len); 677 table->header.type = SMBIOS_TABLE_ENTRY; 678 table->header.length = cpu_to_le16(sizeof(*table) + size); 679 memcpy(table->data, header, size); 680 smbios_entries_len += sizeof(*table) + size; 681 (*(uint16_t *)smbios_entries) = 682 cpu_to_le16(le16_to_cpu(*(uint16_t *)smbios_entries) + 1); 683 usr_offset += size; 684 } 685 686 smbios_build_type_0_fields(); 687 smbios_build_type_1_fields(); 688 smbios_validate_table(); 689 *length = smbios_entries_len; 690 return smbios_entries; 691 } 692 /* end: legacy setup functions for <= 2.0 machines */ 693 694 695 bool smbios_skip_table(uint8_t type, bool required_table) 696 { 697 if (test_bit(type, have_binfile_bitmap)) { 698 return true; /* user provided their own binary blob(s) */ 699 } 700 if (test_bit(type, have_fields_bitmap)) { 701 return false; /* user provided fields via command line */ 702 } 703 if (smbios_have_defaults && required_table) { 704 return false; /* we're building tables, and this one's required */ 705 } 706 return true; 707 } 708 709 #define T0_BASE 0x000 710 #define T1_BASE 0x100 711 #define T2_BASE 0x200 712 #define T3_BASE 0x300 713 #define T4_BASE 0x400 714 #define T9_BASE 0x900 715 #define T11_BASE 0xe00 716 717 #define T16_BASE 0x1000 718 #define T17_BASE 0x1100 719 #define T19_BASE 0x1300 720 #define T32_BASE 0x2000 721 #define T41_BASE 0x2900 722 #define T127_BASE 0x7F00 723 724 static void smbios_build_type_0_table(void) 725 { 726 SMBIOS_BUILD_TABLE_PRE(0, T0_BASE, false); /* optional, leave up to BIOS */ 727 728 SMBIOS_TABLE_SET_STR(0, vendor_str, type0.vendor); 729 SMBIOS_TABLE_SET_STR(0, bios_version_str, type0.version); 730 731 t->bios_starting_address_segment = cpu_to_le16(0xE800); /* from SeaBIOS */ 732 733 SMBIOS_TABLE_SET_STR(0, bios_release_date_str, type0.date); 734 735 t->bios_rom_size = 0; /* hardcoded in SeaBIOS with FIXME comment */ 736 737 t->bios_characteristics = cpu_to_le64(0x08); /* Not supported */ 738 t->bios_characteristics_extension_bytes[0] = 0; 739 t->bios_characteristics_extension_bytes[1] = 0x14; /* TCD/SVVP | VM */ 740 if (type0.uefi) { 741 t->bios_characteristics_extension_bytes[1] |= 0x08; /* |= UEFI */ 742 } 743 744 if (type0.have_major_minor) { 745 t->system_bios_major_release = type0.major; 746 t->system_bios_minor_release = type0.minor; 747 } else { 748 t->system_bios_major_release = 0; 749 t->system_bios_minor_release = 0; 750 } 751 752 /* hardcoded in SeaBIOS */ 753 t->embedded_controller_major_release = 0xFF; 754 t->embedded_controller_minor_release = 0xFF; 755 756 SMBIOS_BUILD_TABLE_POST; 757 } 758 759 /* Encode UUID from the big endian encoding described on RFC4122 to the wire 760 * format specified by SMBIOS version 2.6. 761 */ 762 static void smbios_encode_uuid(struct smbios_uuid *uuid, QemuUUID *in) 763 { 764 memcpy(uuid, in, 16); 765 if (smbios_uuid_encoded) { 766 uuid->time_low = bswap32(uuid->time_low); 767 uuid->time_mid = bswap16(uuid->time_mid); 768 uuid->time_hi_and_version = bswap16(uuid->time_hi_and_version); 769 } 770 } 771 772 static void smbios_build_type_1_table(void) 773 { 774 SMBIOS_BUILD_TABLE_PRE(1, T1_BASE, true); /* required */ 775 776 SMBIOS_TABLE_SET_STR(1, manufacturer_str, type1.manufacturer); 777 SMBIOS_TABLE_SET_STR(1, product_name_str, type1.product); 778 SMBIOS_TABLE_SET_STR(1, version_str, type1.version); 779 SMBIOS_TABLE_SET_STR(1, serial_number_str, type1.serial); 780 if (qemu_uuid_set) { 781 smbios_encode_uuid(&t->uuid, &qemu_uuid); 782 } else { 783 memset(&t->uuid, 0, 16); 784 } 785 t->wake_up_type = 0x06; /* power switch */ 786 SMBIOS_TABLE_SET_STR(1, sku_number_str, type1.sku); 787 SMBIOS_TABLE_SET_STR(1, family_str, type1.family); 788 789 SMBIOS_BUILD_TABLE_POST; 790 } 791 792 static void smbios_build_type_2_table(void) 793 { 794 SMBIOS_BUILD_TABLE_PRE(2, T2_BASE, false); /* optional */ 795 796 SMBIOS_TABLE_SET_STR(2, manufacturer_str, type2.manufacturer); 797 SMBIOS_TABLE_SET_STR(2, product_str, type2.product); 798 SMBIOS_TABLE_SET_STR(2, version_str, type2.version); 799 SMBIOS_TABLE_SET_STR(2, serial_number_str, type2.serial); 800 SMBIOS_TABLE_SET_STR(2, asset_tag_number_str, type2.asset); 801 t->feature_flags = 0x01; /* Motherboard */ 802 SMBIOS_TABLE_SET_STR(2, location_str, type2.location); 803 t->chassis_handle = cpu_to_le16(0x300); /* Type 3 (System enclosure) */ 804 t->board_type = 0x0A; /* Motherboard */ 805 t->contained_element_count = 0; 806 807 SMBIOS_BUILD_TABLE_POST; 808 } 809 810 static void smbios_build_type_3_table(void) 811 { 812 SMBIOS_BUILD_TABLE_PRE(3, T3_BASE, true); /* required */ 813 814 SMBIOS_TABLE_SET_STR(3, manufacturer_str, type3.manufacturer); 815 t->type = 0x01; /* Other */ 816 SMBIOS_TABLE_SET_STR(3, version_str, type3.version); 817 SMBIOS_TABLE_SET_STR(3, serial_number_str, type3.serial); 818 SMBIOS_TABLE_SET_STR(3, asset_tag_number_str, type3.asset); 819 t->boot_up_state = 0x03; /* Safe */ 820 t->power_supply_state = 0x03; /* Safe */ 821 t->thermal_state = 0x03; /* Safe */ 822 t->security_status = 0x02; /* Unknown */ 823 t->oem_defined = cpu_to_le32(0); 824 t->height = 0; 825 t->number_of_power_cords = 0; 826 t->contained_element_count = 0; 827 t->contained_element_record_length = 0; 828 SMBIOS_TABLE_SET_STR(3, sku_number_str, type3.sku); 829 830 SMBIOS_BUILD_TABLE_POST; 831 } 832 833 static void smbios_build_type_4_table(MachineState *ms, unsigned instance) 834 { 835 char sock_str[128]; 836 size_t tbl_len = SMBIOS_TYPE_4_LEN_V28; 837 unsigned threads_per_socket; 838 unsigned cores_per_socket; 839 840 if (smbios_ep_type == SMBIOS_ENTRY_POINT_TYPE_64) { 841 tbl_len = SMBIOS_TYPE_4_LEN_V30; 842 } 843 844 SMBIOS_BUILD_TABLE_PRE_SIZE(4, T4_BASE + instance, 845 true, tbl_len); /* required */ 846 847 snprintf(sock_str, sizeof(sock_str), "%s%2x", type4.sock_pfx, instance); 848 SMBIOS_TABLE_SET_STR(4, socket_designation_str, sock_str); 849 t->processor_type = 0x03; /* CPU */ 850 t->processor_family = 0xfe; /* use Processor Family 2 field */ 851 SMBIOS_TABLE_SET_STR(4, processor_manufacturer_str, type4.manufacturer); 852 if (type4.processor_id == 0) { 853 t->processor_id[0] = cpu_to_le32(smbios_cpuid_version); 854 t->processor_id[1] = cpu_to_le32(smbios_cpuid_features); 855 } else { 856 t->processor_id[0] = cpu_to_le32((uint32_t)type4.processor_id); 857 t->processor_id[1] = cpu_to_le32(type4.processor_id >> 32); 858 } 859 SMBIOS_TABLE_SET_STR(4, processor_version_str, type4.version); 860 t->voltage = 0; 861 t->external_clock = cpu_to_le16(0); /* Unknown */ 862 t->max_speed = cpu_to_le16(type4.max_speed); 863 t->current_speed = cpu_to_le16(type4.current_speed); 864 t->status = 0x41; /* Socket populated, CPU enabled */ 865 t->processor_upgrade = 0x01; /* Other */ 866 t->l1_cache_handle = cpu_to_le16(0xFFFF); /* N/A */ 867 t->l2_cache_handle = cpu_to_le16(0xFFFF); /* N/A */ 868 t->l3_cache_handle = cpu_to_le16(0xFFFF); /* N/A */ 869 SMBIOS_TABLE_SET_STR(4, serial_number_str, type4.serial); 870 SMBIOS_TABLE_SET_STR(4, asset_tag_number_str, type4.asset); 871 SMBIOS_TABLE_SET_STR(4, part_number_str, type4.part); 872 873 threads_per_socket = machine_topo_get_threads_per_socket(ms); 874 cores_per_socket = machine_topo_get_cores_per_socket(ms); 875 876 t->core_count = (cores_per_socket > 255) ? 0xFF : cores_per_socket; 877 t->core_enabled = t->core_count; 878 879 t->thread_count = (threads_per_socket > 255) ? 0xFF : threads_per_socket; 880 881 t->processor_characteristics = cpu_to_le16(0x02); /* Unknown */ 882 t->processor_family2 = cpu_to_le16(type4.processor_family); 883 884 if (tbl_len == SMBIOS_TYPE_4_LEN_V30) { 885 t->core_count2 = t->core_enabled2 = cpu_to_le16(cores_per_socket); 886 t->thread_count2 = cpu_to_le16(threads_per_socket); 887 } 888 889 SMBIOS_BUILD_TABLE_POST; 890 smbios_type4_count++; 891 } 892 893 static void smbios_build_type_8_table(void) 894 { 895 unsigned instance = 0; 896 struct type8_instance *t8; 897 898 QTAILQ_FOREACH(t8, &type8, next) { 899 SMBIOS_BUILD_TABLE_PRE(8, T0_BASE + instance, true); 900 901 SMBIOS_TABLE_SET_STR(8, internal_reference_str, t8->internal_reference); 902 SMBIOS_TABLE_SET_STR(8, external_reference_str, t8->external_reference); 903 /* most vendors seem to set this to None */ 904 t->internal_connector_type = 0x0; 905 t->external_connector_type = t8->connector_type; 906 t->port_type = t8->port_type; 907 908 SMBIOS_BUILD_TABLE_POST; 909 instance++; 910 } 911 } 912 913 static void smbios_build_type_9_table(Error **errp) 914 { 915 unsigned instance = 0; 916 struct type9_instance *t9; 917 918 QTAILQ_FOREACH(t9, &type9, next) { 919 SMBIOS_BUILD_TABLE_PRE(9, T9_BASE + instance, true); 920 921 SMBIOS_TABLE_SET_STR(9, slot_designation, t9->slot_designation); 922 t->slot_type = t9->slot_type; 923 t->slot_data_bus_width = t9->slot_data_bus_width; 924 t->current_usage = t9->current_usage; 925 t->slot_length = t9->slot_length; 926 t->slot_id = t9->slot_id; 927 t->slot_characteristics1 = t9->slot_characteristics1; 928 t->slot_characteristics2 = t9->slot_characteristics2; 929 930 if (t9->pcidev) { 931 PCIDevice *pdev = NULL; 932 int rc = pci_qdev_find_device(t9->pcidev, &pdev); 933 if (rc != 0) { 934 error_setg(errp, 935 "No PCI device %s for SMBIOS type 9 entry %s", 936 t9->pcidev, t9->slot_designation); 937 return; 938 } 939 /* 940 * We only handle the case were the device is attached to 941 * the PCI root bus. The general case is more complex as 942 * bridges are enumerated later and the table would need 943 * to be updated at this moment. 944 */ 945 if (!pci_bus_is_root(pci_get_bus(pdev))) { 946 error_setg(errp, 947 "Cannot create type 9 entry for PCI device %s: " 948 "not attached to the root bus", 949 t9->pcidev); 950 return; 951 } 952 t->segment_group_number = cpu_to_le16(0); 953 t->bus_number = pci_dev_bus_num(pdev); 954 t->device_number = pdev->devfn; 955 } else { 956 /* 957 * Per SMBIOS spec, For slots that are not of the PCI, AGP, PCI-X, 958 * or PCI-Express type that do not have bus/device/function 959 * information, 0FFh should be populated in the fields of Segment 960 * Group Number, Bus Number, Device/Function Number. 961 */ 962 t->segment_group_number = 0xff; 963 t->bus_number = 0xff; 964 t->device_number = 0xff; 965 } 966 967 SMBIOS_BUILD_TABLE_POST; 968 instance++; 969 } 970 } 971 972 static void smbios_build_type_11_table(void) 973 { 974 char count_str[128]; 975 size_t i; 976 977 if (type11.nvalues == 0) { 978 return; 979 } 980 981 SMBIOS_BUILD_TABLE_PRE(11, T11_BASE, true); /* required */ 982 983 snprintf(count_str, sizeof(count_str), "%zu", type11.nvalues); 984 t->count = type11.nvalues; 985 986 for (i = 0; i < type11.nvalues; i++) { 987 SMBIOS_TABLE_SET_STR_LIST(11, type11.values[i]); 988 g_free(type11.values[i]); 989 type11.values[i] = NULL; 990 } 991 992 SMBIOS_BUILD_TABLE_POST; 993 } 994 995 #define MAX_T16_STD_SZ 0x80000000 /* 2T in Kilobytes */ 996 997 static void smbios_build_type_16_table(unsigned dimm_cnt) 998 { 999 uint64_t size_kb; 1000 1001 SMBIOS_BUILD_TABLE_PRE(16, T16_BASE, true); /* required */ 1002 1003 t->location = 0x01; /* Other */ 1004 t->use = 0x03; /* System memory */ 1005 t->error_correction = 0x06; /* Multi-bit ECC (for Microsoft, per SeaBIOS) */ 1006 size_kb = QEMU_ALIGN_UP(current_machine->ram_size, KiB) / KiB; 1007 if (size_kb < MAX_T16_STD_SZ) { 1008 t->maximum_capacity = cpu_to_le32(size_kb); 1009 t->extended_maximum_capacity = cpu_to_le64(0); 1010 } else { 1011 t->maximum_capacity = cpu_to_le32(MAX_T16_STD_SZ); 1012 t->extended_maximum_capacity = cpu_to_le64(current_machine->ram_size); 1013 } 1014 t->memory_error_information_handle = cpu_to_le16(0xFFFE); /* Not provided */ 1015 t->number_of_memory_devices = cpu_to_le16(dimm_cnt); 1016 1017 SMBIOS_BUILD_TABLE_POST; 1018 } 1019 1020 #define MAX_T17_STD_SZ 0x7FFF /* (32G - 1M), in Megabytes */ 1021 #define MAX_T17_EXT_SZ 0x80000000 /* 2P, in Megabytes */ 1022 1023 static void smbios_build_type_17_table(unsigned instance, uint64_t size) 1024 { 1025 char loc_str[128]; 1026 uint64_t size_mb; 1027 1028 SMBIOS_BUILD_TABLE_PRE(17, T17_BASE + instance, true); /* required */ 1029 1030 t->physical_memory_array_handle = cpu_to_le16(0x1000); /* Type 16 above */ 1031 t->memory_error_information_handle = cpu_to_le16(0xFFFE); /* Not provided */ 1032 t->total_width = cpu_to_le16(0xFFFF); /* Unknown */ 1033 t->data_width = cpu_to_le16(0xFFFF); /* Unknown */ 1034 size_mb = QEMU_ALIGN_UP(size, MiB) / MiB; 1035 if (size_mb < MAX_T17_STD_SZ) { 1036 t->size = cpu_to_le16(size_mb); 1037 t->extended_size = cpu_to_le32(0); 1038 } else { 1039 assert(size_mb < MAX_T17_EXT_SZ); 1040 t->size = cpu_to_le16(MAX_T17_STD_SZ); 1041 t->extended_size = cpu_to_le32(size_mb); 1042 } 1043 t->form_factor = 0x09; /* DIMM */ 1044 t->device_set = 0; /* Not in a set */ 1045 snprintf(loc_str, sizeof(loc_str), "%s %d", type17.loc_pfx, instance); 1046 SMBIOS_TABLE_SET_STR(17, device_locator_str, loc_str); 1047 SMBIOS_TABLE_SET_STR(17, bank_locator_str, type17.bank); 1048 t->memory_type = 0x07; /* RAM */ 1049 t->type_detail = cpu_to_le16(0x02); /* Other */ 1050 t->speed = cpu_to_le16(type17.speed); 1051 SMBIOS_TABLE_SET_STR(17, manufacturer_str, type17.manufacturer); 1052 SMBIOS_TABLE_SET_STR(17, serial_number_str, type17.serial); 1053 SMBIOS_TABLE_SET_STR(17, asset_tag_number_str, type17.asset); 1054 SMBIOS_TABLE_SET_STR(17, part_number_str, type17.part); 1055 t->attributes = 0; /* Unknown */ 1056 t->configured_clock_speed = t->speed; /* reuse value for max speed */ 1057 t->minimum_voltage = cpu_to_le16(0); /* Unknown */ 1058 t->maximum_voltage = cpu_to_le16(0); /* Unknown */ 1059 t->configured_voltage = cpu_to_le16(0); /* Unknown */ 1060 1061 SMBIOS_BUILD_TABLE_POST; 1062 } 1063 1064 static void smbios_build_type_19_table(unsigned instance, unsigned offset, 1065 uint64_t start, uint64_t size) 1066 { 1067 uint64_t end, start_kb, end_kb; 1068 1069 SMBIOS_BUILD_TABLE_PRE(19, T19_BASE + offset + instance, 1070 true); /* required */ 1071 1072 end = start + size - 1; 1073 assert(end > start); 1074 start_kb = start / KiB; 1075 end_kb = end / KiB; 1076 if (start_kb < UINT32_MAX && end_kb < UINT32_MAX) { 1077 t->starting_address = cpu_to_le32(start_kb); 1078 t->ending_address = cpu_to_le32(end_kb); 1079 t->extended_starting_address = 1080 t->extended_ending_address = cpu_to_le64(0); 1081 } else { 1082 t->starting_address = t->ending_address = cpu_to_le32(UINT32_MAX); 1083 t->extended_starting_address = cpu_to_le64(start); 1084 t->extended_ending_address = cpu_to_le64(end); 1085 } 1086 t->memory_array_handle = cpu_to_le16(0x1000); /* Type 16 above */ 1087 t->partition_width = 1; /* One device per row */ 1088 1089 SMBIOS_BUILD_TABLE_POST; 1090 } 1091 1092 static void smbios_build_type_32_table(void) 1093 { 1094 SMBIOS_BUILD_TABLE_PRE(32, T32_BASE, true); /* required */ 1095 1096 memset(t->reserved, 0, 6); 1097 t->boot_status = 0; /* No errors detected */ 1098 1099 SMBIOS_BUILD_TABLE_POST; 1100 } 1101 1102 static void smbios_build_type_41_table(Error **errp) 1103 { 1104 unsigned instance = 0; 1105 struct type41_instance *t41; 1106 1107 QTAILQ_FOREACH(t41, &type41, next) { 1108 SMBIOS_BUILD_TABLE_PRE(41, T41_BASE + instance, true); 1109 1110 SMBIOS_TABLE_SET_STR(41, reference_designation_str, t41->designation); 1111 t->device_type = t41->kind; 1112 t->device_type_instance = t41->instance; 1113 t->segment_group_number = cpu_to_le16(0); 1114 t->bus_number = 0; 1115 t->device_number = 0; 1116 1117 if (t41->pcidev) { 1118 PCIDevice *pdev = NULL; 1119 int rc = pci_qdev_find_device(t41->pcidev, &pdev); 1120 if (rc != 0) { 1121 error_setg(errp, 1122 "No PCI device %s for SMBIOS type 41 entry %s", 1123 t41->pcidev, t41->designation); 1124 return; 1125 } 1126 /* 1127 * We only handle the case were the device is attached to 1128 * the PCI root bus. The general case is more complex as 1129 * bridges are enumerated later and the table would need 1130 * to be updated at this moment. 1131 */ 1132 if (!pci_bus_is_root(pci_get_bus(pdev))) { 1133 error_setg(errp, 1134 "Cannot create type 41 entry for PCI device %s: " 1135 "not attached to the root bus", 1136 t41->pcidev); 1137 return; 1138 } 1139 t->segment_group_number = cpu_to_le16(0); 1140 t->bus_number = pci_dev_bus_num(pdev); 1141 t->device_number = pdev->devfn; 1142 } 1143 1144 SMBIOS_BUILD_TABLE_POST; 1145 instance++; 1146 } 1147 } 1148 1149 static void smbios_build_type_127_table(void) 1150 { 1151 SMBIOS_BUILD_TABLE_PRE(127, T127_BASE, true); /* required */ 1152 SMBIOS_BUILD_TABLE_POST; 1153 } 1154 1155 void smbios_set_cpuid(uint32_t version, uint32_t features) 1156 { 1157 smbios_cpuid_version = version; 1158 smbios_cpuid_features = features; 1159 } 1160 1161 #define SMBIOS_SET_DEFAULT(field, value) \ 1162 if (!field) { \ 1163 field = value; \ 1164 } 1165 1166 void smbios_set_default_processor_family(uint16_t processor_family) 1167 { 1168 if (type4.processor_family <= 0x01) { 1169 type4.processor_family = processor_family; 1170 } 1171 } 1172 1173 void smbios_set_defaults(const char *manufacturer, const char *product, 1174 const char *version, 1175 bool uuid_encoded, SmbiosEntryPointType ep_type) 1176 { 1177 smbios_have_defaults = true; 1178 smbios_uuid_encoded = uuid_encoded; 1179 smbios_ep_type = ep_type; 1180 1181 SMBIOS_SET_DEFAULT(type1.manufacturer, manufacturer); 1182 SMBIOS_SET_DEFAULT(type1.product, product); 1183 SMBIOS_SET_DEFAULT(type1.version, version); 1184 SMBIOS_SET_DEFAULT(type2.manufacturer, manufacturer); 1185 SMBIOS_SET_DEFAULT(type2.product, product); 1186 SMBIOS_SET_DEFAULT(type2.version, version); 1187 SMBIOS_SET_DEFAULT(type3.manufacturer, manufacturer); 1188 SMBIOS_SET_DEFAULT(type3.version, version); 1189 SMBIOS_SET_DEFAULT(type4.sock_pfx, "CPU"); 1190 SMBIOS_SET_DEFAULT(type4.manufacturer, manufacturer); 1191 SMBIOS_SET_DEFAULT(type4.version, version); 1192 SMBIOS_SET_DEFAULT(type17.loc_pfx, "DIMM"); 1193 SMBIOS_SET_DEFAULT(type17.manufacturer, manufacturer); 1194 } 1195 1196 static void smbios_entry_point_setup(void) 1197 { 1198 switch (smbios_ep_type) { 1199 case SMBIOS_ENTRY_POINT_TYPE_32: 1200 memcpy(ep.ep21.anchor_string, "_SM_", 4); 1201 memcpy(ep.ep21.intermediate_anchor_string, "_DMI_", 5); 1202 ep.ep21.length = sizeof(struct smbios_21_entry_point); 1203 ep.ep21.entry_point_revision = 0; /* formatted_area reserved */ 1204 memset(ep.ep21.formatted_area, 0, 5); 1205 1206 /* compliant with smbios spec v2.8 */ 1207 ep.ep21.smbios_major_version = 2; 1208 ep.ep21.smbios_minor_version = 8; 1209 ep.ep21.smbios_bcd_revision = 0x28; 1210 1211 /* set during table construction, but BIOS may override: */ 1212 ep.ep21.structure_table_length = cpu_to_le16(smbios_tables_len); 1213 ep.ep21.max_structure_size = cpu_to_le16(smbios_table_max); 1214 ep.ep21.number_of_structures = cpu_to_le16(smbios_table_cnt); 1215 1216 /* BIOS must recalculate */ 1217 ep.ep21.checksum = 0; 1218 ep.ep21.intermediate_checksum = 0; 1219 ep.ep21.structure_table_address = cpu_to_le32(0); 1220 1221 break; 1222 case SMBIOS_ENTRY_POINT_TYPE_64: 1223 memcpy(ep.ep30.anchor_string, "_SM3_", 5); 1224 ep.ep30.length = sizeof(struct smbios_30_entry_point); 1225 ep.ep30.entry_point_revision = 1; 1226 ep.ep30.reserved = 0; 1227 1228 /* compliant with smbios spec 3.0 */ 1229 ep.ep30.smbios_major_version = 3; 1230 ep.ep30.smbios_minor_version = 0; 1231 ep.ep30.smbios_doc_rev = 0; 1232 1233 /* set during table construct, but BIOS might override */ 1234 ep.ep30.structure_table_max_size = cpu_to_le32(smbios_tables_len); 1235 1236 /* BIOS must recalculate */ 1237 ep.ep30.checksum = 0; 1238 ep.ep30.structure_table_address = cpu_to_le64(0); 1239 1240 break; 1241 default: 1242 abort(); 1243 break; 1244 } 1245 } 1246 1247 void smbios_get_tables(MachineState *ms, 1248 const struct smbios_phys_mem_area *mem_array, 1249 const unsigned int mem_array_size, 1250 uint8_t **tables, size_t *tables_len, 1251 uint8_t **anchor, size_t *anchor_len, 1252 Error **errp) 1253 { 1254 unsigned i, dimm_cnt, offset; 1255 1256 g_free(smbios_tables); 1257 smbios_tables = g_memdup2(usr_blobs, usr_blobs_len); 1258 smbios_tables_len = usr_blobs_len; 1259 smbios_table_max = usr_table_max; 1260 smbios_table_cnt = usr_table_cnt; 1261 1262 smbios_build_type_0_table(); 1263 smbios_build_type_1_table(); 1264 smbios_build_type_2_table(); 1265 smbios_build_type_3_table(); 1266 1267 assert(ms->smp.sockets >= 1); 1268 1269 for (i = 0; i < ms->smp.sockets; i++) { 1270 smbios_build_type_4_table(ms, i); 1271 } 1272 1273 smbios_build_type_8_table(); 1274 smbios_build_type_9_table(errp); 1275 smbios_build_type_11_table(); 1276 1277 #define MAX_DIMM_SZ (16 * GiB) 1278 #define GET_DIMM_SZ ((i < dimm_cnt - 1) ? MAX_DIMM_SZ \ 1279 : ((current_machine->ram_size - 1) % MAX_DIMM_SZ) + 1) 1280 1281 dimm_cnt = QEMU_ALIGN_UP(current_machine->ram_size, MAX_DIMM_SZ) / 1282 MAX_DIMM_SZ; 1283 1284 /* 1285 * The offset determines if we need to keep additional space between 1286 * table 17 and table 19 header handle numbers so that they do 1287 * not overlap. For example, for a VM with larger than 8 TB guest 1288 * memory and DIMM like chunks of 16 GiB, the default space between 1289 * the two tables (T19_BASE - T17_BASE = 512) is not enough. 1290 */ 1291 offset = (dimm_cnt > (T19_BASE - T17_BASE)) ? \ 1292 dimm_cnt - (T19_BASE - T17_BASE) : 0; 1293 1294 smbios_build_type_16_table(dimm_cnt); 1295 1296 for (i = 0; i < dimm_cnt; i++) { 1297 smbios_build_type_17_table(i, GET_DIMM_SZ); 1298 } 1299 1300 for (i = 0; i < mem_array_size; i++) { 1301 smbios_build_type_19_table(i, offset, mem_array[i].address, 1302 mem_array[i].length); 1303 } 1304 1305 /* 1306 * make sure 16 bit handle numbers in the headers of tables 19 1307 * and 32 do not overlap. 1308 */ 1309 assert((mem_array_size + offset) < (T32_BASE - T19_BASE)); 1310 1311 smbios_build_type_32_table(); 1312 smbios_build_type_38_table(); 1313 smbios_build_type_41_table(errp); 1314 smbios_build_type_127_table(); 1315 1316 smbios_check_type4_count(ms->smp.sockets); 1317 smbios_validate_table(); 1318 smbios_entry_point_setup(); 1319 1320 /* return tables blob and entry point (anchor), and their sizes */ 1321 *tables = smbios_tables; 1322 *tables_len = smbios_tables_len; 1323 *anchor = (uint8_t *)&ep; 1324 1325 /* calculate length based on anchor string */ 1326 if (!strncmp((char *)&ep, "_SM_", 4)) { 1327 *anchor_len = sizeof(struct smbios_21_entry_point); 1328 } else if (!strncmp((char *)&ep, "_SM3_", 5)) { 1329 *anchor_len = sizeof(struct smbios_30_entry_point); 1330 } else { 1331 abort(); 1332 } 1333 } 1334 1335 static void save_opt(const char **dest, QemuOpts *opts, const char *name) 1336 { 1337 const char *val = qemu_opt_get(opts, name); 1338 1339 if (val) { 1340 *dest = val; 1341 } 1342 } 1343 1344 1345 struct opt_list { 1346 size_t *ndest; 1347 char ***dest; 1348 }; 1349 1350 static int save_opt_one(void *opaque, 1351 const char *name, const char *value, 1352 Error **errp) 1353 { 1354 struct opt_list *opt = opaque; 1355 1356 if (g_str_equal(name, "path")) { 1357 g_autoptr(GByteArray) data = g_byte_array_new(); 1358 g_autofree char *buf = g_new(char, 4096); 1359 ssize_t ret; 1360 int fd = qemu_open(value, O_RDONLY, errp); 1361 if (fd < 0) { 1362 return -1; 1363 } 1364 1365 while (1) { 1366 ret = read(fd, buf, 4096); 1367 if (ret == 0) { 1368 break; 1369 } 1370 if (ret < 0) { 1371 error_setg(errp, "Unable to read from %s: %s", 1372 value, strerror(errno)); 1373 qemu_close(fd); 1374 return -1; 1375 } 1376 if (memchr(buf, '\0', ret)) { 1377 error_setg(errp, "NUL in OEM strings value in %s", value); 1378 qemu_close(fd); 1379 return -1; 1380 } 1381 g_byte_array_append(data, (guint8 *)buf, ret); 1382 } 1383 1384 qemu_close(fd); 1385 1386 *opt->dest = g_renew(char *, *opt->dest, (*opt->ndest) + 1); 1387 (*opt->dest)[*opt->ndest] = (char *)g_byte_array_free(data, FALSE); 1388 (*opt->ndest)++; 1389 data = NULL; 1390 } else if (g_str_equal(name, "value")) { 1391 *opt->dest = g_renew(char *, *opt->dest, (*opt->ndest) + 1); 1392 (*opt->dest)[*opt->ndest] = g_strdup(value); 1393 (*opt->ndest)++; 1394 } else if (!g_str_equal(name, "type")) { 1395 error_setg(errp, "Unexpected option %s", name); 1396 return -1; 1397 } 1398 1399 return 0; 1400 } 1401 1402 static bool save_opt_list(size_t *ndest, char ***dest, QemuOpts *opts, 1403 Error **errp) 1404 { 1405 struct opt_list opt = { 1406 ndest, dest, 1407 }; 1408 if (!qemu_opt_foreach(opts, save_opt_one, &opt, errp)) { 1409 return false; 1410 } 1411 return true; 1412 } 1413 1414 static void smbios_add_usr_blob_size(size_t size) 1415 { 1416 if (!usr_blobs_sizes) { 1417 usr_blobs_sizes = g_array_new(false, false, sizeof(size_t)); 1418 } 1419 g_array_append_val(usr_blobs_sizes, size); 1420 } 1421 1422 void smbios_entry_add(QemuOpts *opts, Error **errp) 1423 { 1424 const char *val; 1425 1426 val = qemu_opt_get(opts, "file"); 1427 if (val) { 1428 struct smbios_structure_header *header; 1429 size_t size; 1430 1431 if (!qemu_opts_validate(opts, qemu_smbios_file_opts, errp)) { 1432 return; 1433 } 1434 1435 size = get_image_size(val); 1436 if (size == -1 || size < sizeof(struct smbios_structure_header)) { 1437 error_setg(errp, "Cannot read SMBIOS file %s", val); 1438 return; 1439 } 1440 1441 /* 1442 * NOTE: standard double '\0' terminator expected, per smbios spec. 1443 * (except in legacy mode, where the second '\0' is implicit and 1444 * will be inserted by the BIOS). 1445 */ 1446 usr_blobs = g_realloc(usr_blobs, usr_blobs_len + size); 1447 header = (struct smbios_structure_header *)(usr_blobs + 1448 usr_blobs_len); 1449 1450 if (load_image_size(val, (uint8_t *)header, size) != size) { 1451 error_setg(errp, "Failed to load SMBIOS file %s", val); 1452 return; 1453 } 1454 1455 if (header->type <= SMBIOS_MAX_TYPE) { 1456 if (test_bit(header->type, have_fields_bitmap)) { 1457 error_setg(errp, 1458 "can't load type %d struct, fields already specified!", 1459 header->type); 1460 return; 1461 } 1462 set_bit(header->type, have_binfile_bitmap); 1463 } 1464 1465 if (header->type == 4) { 1466 smbios_type4_count++; 1467 } 1468 1469 /* 1470 * preserve blob size for legacy mode so it could build its 1471 * blobs flavor from 'usr_blobs' 1472 */ 1473 smbios_add_usr_blob_size(size); 1474 1475 usr_blobs_len += size; 1476 if (size > usr_table_max) { 1477 usr_table_max = size; 1478 } 1479 usr_table_cnt++; 1480 1481 return; 1482 } 1483 1484 val = qemu_opt_get(opts, "type"); 1485 if (val) { 1486 unsigned long type = strtoul(val, NULL, 0); 1487 1488 if (type > SMBIOS_MAX_TYPE) { 1489 error_setg(errp, "out of range!"); 1490 return; 1491 } 1492 1493 if (test_bit(type, have_binfile_bitmap)) { 1494 error_setg(errp, "can't add fields, binary file already loaded!"); 1495 return; 1496 } 1497 set_bit(type, have_fields_bitmap); 1498 1499 switch (type) { 1500 case 0: 1501 if (!qemu_opts_validate(opts, qemu_smbios_type0_opts, errp)) { 1502 return; 1503 } 1504 save_opt(&type0.vendor, opts, "vendor"); 1505 save_opt(&type0.version, opts, "version"); 1506 save_opt(&type0.date, opts, "date"); 1507 type0.uefi = qemu_opt_get_bool(opts, "uefi", false); 1508 1509 val = qemu_opt_get(opts, "release"); 1510 if (val) { 1511 if (sscanf(val, "%hhu.%hhu", &type0.major, &type0.minor) != 2) { 1512 error_setg(errp, "Invalid release"); 1513 return; 1514 } 1515 type0.have_major_minor = true; 1516 } 1517 return; 1518 case 1: 1519 if (!qemu_opts_validate(opts, qemu_smbios_type1_opts, errp)) { 1520 return; 1521 } 1522 save_opt(&type1.manufacturer, opts, "manufacturer"); 1523 save_opt(&type1.product, opts, "product"); 1524 save_opt(&type1.version, opts, "version"); 1525 save_opt(&type1.serial, opts, "serial"); 1526 save_opt(&type1.sku, opts, "sku"); 1527 save_opt(&type1.family, opts, "family"); 1528 1529 val = qemu_opt_get(opts, "uuid"); 1530 if (val) { 1531 if (qemu_uuid_parse(val, &qemu_uuid) != 0) { 1532 error_setg(errp, "Invalid UUID"); 1533 return; 1534 } 1535 qemu_uuid_set = true; 1536 } 1537 return; 1538 case 2: 1539 if (!qemu_opts_validate(opts, qemu_smbios_type2_opts, errp)) { 1540 return; 1541 } 1542 save_opt(&type2.manufacturer, opts, "manufacturer"); 1543 save_opt(&type2.product, opts, "product"); 1544 save_opt(&type2.version, opts, "version"); 1545 save_opt(&type2.serial, opts, "serial"); 1546 save_opt(&type2.asset, opts, "asset"); 1547 save_opt(&type2.location, opts, "location"); 1548 return; 1549 case 3: 1550 if (!qemu_opts_validate(opts, qemu_smbios_type3_opts, errp)) { 1551 return; 1552 } 1553 save_opt(&type3.manufacturer, opts, "manufacturer"); 1554 save_opt(&type3.version, opts, "version"); 1555 save_opt(&type3.serial, opts, "serial"); 1556 save_opt(&type3.asset, opts, "asset"); 1557 save_opt(&type3.sku, opts, "sku"); 1558 return; 1559 case 4: 1560 if (!qemu_opts_validate(opts, qemu_smbios_type4_opts, errp)) { 1561 return; 1562 } 1563 save_opt(&type4.sock_pfx, opts, "sock_pfx"); 1564 type4.processor_family = qemu_opt_get_number(opts, 1565 "processor-family", 1566 0x01 /* Other */); 1567 save_opt(&type4.manufacturer, opts, "manufacturer"); 1568 save_opt(&type4.version, opts, "version"); 1569 save_opt(&type4.serial, opts, "serial"); 1570 save_opt(&type4.asset, opts, "asset"); 1571 save_opt(&type4.part, opts, "part"); 1572 /* If the value is 0, it will take the value from the CPU model. */ 1573 type4.processor_id = qemu_opt_get_number(opts, "processor-id", 0); 1574 type4.max_speed = qemu_opt_get_number(opts, "max-speed", 1575 DEFAULT_CPU_SPEED); 1576 type4.current_speed = qemu_opt_get_number(opts, "current-speed", 1577 DEFAULT_CPU_SPEED); 1578 if (type4.max_speed > UINT16_MAX || 1579 type4.current_speed > UINT16_MAX) { 1580 error_setg(errp, "SMBIOS CPU speed is too large (> %d)", 1581 UINT16_MAX); 1582 } 1583 return; 1584 case 8: 1585 if (!qemu_opts_validate(opts, qemu_smbios_type8_opts, errp)) { 1586 return; 1587 } 1588 struct type8_instance *t8_i; 1589 t8_i = g_new0(struct type8_instance, 1); 1590 save_opt(&t8_i->internal_reference, opts, "internal_reference"); 1591 save_opt(&t8_i->external_reference, opts, "external_reference"); 1592 t8_i->connector_type = qemu_opt_get_number(opts, 1593 "connector_type", 0); 1594 t8_i->port_type = qemu_opt_get_number(opts, "port_type", 0); 1595 QTAILQ_INSERT_TAIL(&type8, t8_i, next); 1596 return; 1597 case 9: { 1598 if (!qemu_opts_validate(opts, qemu_smbios_type9_opts, errp)) { 1599 return; 1600 } 1601 struct type9_instance *t; 1602 t = g_new0(struct type9_instance, 1); 1603 save_opt(&t->slot_designation, opts, "slot_designation"); 1604 t->slot_type = qemu_opt_get_number(opts, "slot_type", 0); 1605 t->slot_data_bus_width = 1606 qemu_opt_get_number(opts, "slot_data_bus_width", 0); 1607 t->current_usage = qemu_opt_get_number(opts, "current_usage", 0); 1608 t->slot_length = qemu_opt_get_number(opts, "slot_length", 0); 1609 t->slot_id = qemu_opt_get_number(opts, "slot_id", 0); 1610 t->slot_characteristics1 = 1611 qemu_opt_get_number(opts, "slot_characteristics1", 0); 1612 t->slot_characteristics2 = 1613 qemu_opt_get_number(opts, "slot_characteristics2", 0); 1614 save_opt(&t->pcidev, opts, "pcidev"); 1615 QTAILQ_INSERT_TAIL(&type9, t, next); 1616 return; 1617 } 1618 case 11: 1619 if (!qemu_opts_validate(opts, qemu_smbios_type11_opts, errp)) { 1620 return; 1621 } 1622 if (!save_opt_list(&type11.nvalues, &type11.values, opts, errp)) { 1623 return; 1624 } 1625 return; 1626 case 17: 1627 if (!qemu_opts_validate(opts, qemu_smbios_type17_opts, errp)) { 1628 return; 1629 } 1630 save_opt(&type17.loc_pfx, opts, "loc_pfx"); 1631 save_opt(&type17.bank, opts, "bank"); 1632 save_opt(&type17.manufacturer, opts, "manufacturer"); 1633 save_opt(&type17.serial, opts, "serial"); 1634 save_opt(&type17.asset, opts, "asset"); 1635 save_opt(&type17.part, opts, "part"); 1636 type17.speed = qemu_opt_get_number(opts, "speed", 0); 1637 return; 1638 case 41: { 1639 struct type41_instance *t41_i; 1640 Error *local_err = NULL; 1641 1642 if (!qemu_opts_validate(opts, qemu_smbios_type41_opts, errp)) { 1643 return; 1644 } 1645 t41_i = g_new0(struct type41_instance, 1); 1646 save_opt(&t41_i->designation, opts, "designation"); 1647 t41_i->kind = qapi_enum_parse(&type41_kind_lookup, 1648 qemu_opt_get(opts, "kind"), 1649 0, &local_err) + 1; 1650 t41_i->kind |= 0x80; /* enabled */ 1651 if (local_err != NULL) { 1652 error_propagate(errp, local_err); 1653 g_free(t41_i); 1654 return; 1655 } 1656 t41_i->instance = qemu_opt_get_number(opts, "instance", 1); 1657 save_opt(&t41_i->pcidev, opts, "pcidev"); 1658 1659 QTAILQ_INSERT_TAIL(&type41, t41_i, next); 1660 return; 1661 } 1662 default: 1663 error_setg(errp, 1664 "Don't know how to build fields for SMBIOS type %ld", 1665 type); 1666 return; 1667 } 1668 } 1669 1670 error_setg(errp, "Must specify type= or file="); 1671 } 1672