1 /* 2 * SH7750 device 3 * 4 * Copyright (c) 2007 Magnus Damm 5 * Copyright (c) 2005 Samuel Tardieu 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "hw/sysbus.h" 29 #include "hw/irq.h" 30 #include "hw/sh4/sh.h" 31 #include "sysemu/sysemu.h" 32 #include "hw/qdev-properties.h" 33 #include "hw/qdev-properties-system.h" 34 #include "sh7750_regs.h" 35 #include "sh7750_regnames.h" 36 #include "hw/sh4/sh_intc.h" 37 #include "hw/timer/tmu012.h" 38 #include "exec/exec-all.h" 39 #include "trace.h" 40 41 typedef struct SH7750State { 42 MemoryRegion iomem; 43 MemoryRegion iomem_1f0; 44 MemoryRegion iomem_ff0; 45 MemoryRegion iomem_1f8; 46 MemoryRegion iomem_ff8; 47 MemoryRegion iomem_1fc; 48 MemoryRegion iomem_ffc; 49 MemoryRegion mmct_iomem; 50 /* CPU */ 51 SuperHCPU *cpu; 52 /* Peripheral frequency in Hz */ 53 uint32_t periph_freq; 54 /* SDRAM controller */ 55 uint32_t bcr1; 56 uint16_t bcr2; 57 uint16_t bcr3; 58 uint32_t bcr4; 59 uint16_t rfcr; 60 /* PCMCIA controller */ 61 uint16_t pcr; 62 /* IO ports */ 63 uint16_t gpioic; 64 uint32_t pctra; 65 uint32_t pctrb; 66 uint16_t portdira; /* Cached */ 67 uint16_t portpullupa; /* Cached */ 68 uint16_t portdirb; /* Cached */ 69 uint16_t portpullupb; /* Cached */ 70 uint16_t pdtra; 71 uint16_t pdtrb; 72 uint16_t periph_pdtra; /* Imposed by the peripherals */ 73 uint16_t periph_portdira; /* Direction seen from the peripherals */ 74 uint16_t periph_pdtrb; /* Imposed by the peripherals */ 75 uint16_t periph_portdirb; /* Direction seen from the peripherals */ 76 77 /* Cache */ 78 uint32_t ccr; 79 80 struct intc_desc intc; 81 } SH7750State; 82 83 static inline int has_bcr3_and_bcr4(SH7750State *s) 84 { 85 return s->cpu->env.features & SH_FEATURE_BCR3_AND_BCR4; 86 } 87 88 /* 89 * I/O ports 90 */ 91 92 static uint16_t portdir(uint32_t v) 93 { 94 #define EVENPORTMASK(n) ((v & (1 << ((n) << 1))) >> (n)) 95 return 96 EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) | 97 EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) | 98 EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) | 99 EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) | 100 EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) | 101 EVENPORTMASK(0); 102 } 103 104 static uint16_t portpullup(uint32_t v) 105 { 106 #define ODDPORTMASK(n) ((v & (1 << (((n) << 1) + 1))) >> (n)) 107 return 108 ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) | 109 ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) | 110 ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) | 111 ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) | 112 ODDPORTMASK(1) | ODDPORTMASK(0); 113 } 114 115 static uint16_t porta_lines(SH7750State *s) 116 { 117 return (s->portdira & s->pdtra) | /* CPU */ 118 (s->periph_portdira & s->periph_pdtra) | /* Peripherals */ 119 (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */ 120 } 121 122 static uint16_t portb_lines(SH7750State *s) 123 { 124 return (s->portdirb & s->pdtrb) | /* CPU */ 125 (s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */ 126 (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */ 127 } 128 129 static void porta_changed(SH7750State *s, uint16_t prev) 130 { 131 uint16_t currenta; 132 133 currenta = porta_lines(s); 134 if (currenta == prev) { 135 return; 136 } 137 trace_sh7750_porta(prev, currenta, s->pdtra, s->pctra); 138 } 139 140 static void portb_changed(SH7750State *s, uint16_t prev) 141 { 142 uint16_t currentb; 143 144 currentb = portb_lines(s); 145 if (currentb == prev) { 146 return; 147 } 148 trace_sh7750_portb(prev, currentb, s->pdtrb, s->pctrb); 149 } 150 151 /* 152 * Memory 153 */ 154 155 static void error_access(const char *kind, hwaddr addr) 156 { 157 fprintf(stderr, "%s to %s (0x" HWADDR_FMT_plx ") not supported\n", 158 kind, regname(addr), addr); 159 } 160 161 static void ignore_access(const char *kind, hwaddr addr) 162 { 163 fprintf(stderr, "%s to %s (0x" HWADDR_FMT_plx ") ignored\n", 164 kind, regname(addr), addr); 165 } 166 167 static uint32_t sh7750_mem_readb(void *opaque, hwaddr addr) 168 { 169 switch (addr) { 170 default: 171 error_access("byte read", addr); 172 abort(); 173 } 174 } 175 176 static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr) 177 { 178 SH7750State *s = opaque; 179 180 switch (addr) { 181 case SH7750_BCR2_A7: 182 return s->bcr2; 183 case SH7750_BCR3_A7: 184 if (!has_bcr3_and_bcr4(s)) { 185 error_access("word read", addr); 186 } 187 return s->bcr3; 188 case SH7750_FRQCR_A7: 189 return 0; 190 case SH7750_PCR_A7: 191 return s->pcr; 192 case SH7750_RFCR_A7: 193 fprintf(stderr, 194 "Read access to refresh count register, incrementing\n"); 195 return s->rfcr++; 196 case SH7750_PDTRA_A7: 197 return porta_lines(s); 198 case SH7750_PDTRB_A7: 199 return portb_lines(s); 200 case SH7750_RTCOR_A7: 201 case SH7750_RTCNT_A7: 202 case SH7750_RTCSR_A7: 203 ignore_access("word read", addr); 204 return 0; 205 default: 206 error_access("word read", addr); 207 abort(); 208 } 209 } 210 211 static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr) 212 { 213 SH7750State *s = opaque; 214 SuperHCPUClass *scc; 215 216 switch (addr) { 217 case SH7750_BCR1_A7: 218 return s->bcr1; 219 case SH7750_BCR4_A7: 220 if (!has_bcr3_and_bcr4(s)) { 221 error_access("long read", addr); 222 } 223 return s->bcr4; 224 case SH7750_WCR1_A7: 225 case SH7750_WCR2_A7: 226 case SH7750_WCR3_A7: 227 case SH7750_MCR_A7: 228 ignore_access("long read", addr); 229 return 0; 230 case SH7750_MMUCR_A7: 231 return s->cpu->env.mmucr; 232 case SH7750_PTEH_A7: 233 return s->cpu->env.pteh; 234 case SH7750_PTEL_A7: 235 return s->cpu->env.ptel; 236 case SH7750_TTB_A7: 237 return s->cpu->env.ttb; 238 case SH7750_TEA_A7: 239 return s->cpu->env.tea; 240 case SH7750_TRA_A7: 241 return s->cpu->env.tra; 242 case SH7750_EXPEVT_A7: 243 return s->cpu->env.expevt; 244 case SH7750_INTEVT_A7: 245 return s->cpu->env.intevt; 246 case SH7750_CCR_A7: 247 return s->ccr; 248 case 0x1f000030: /* Processor version */ 249 scc = SUPERH_CPU_GET_CLASS(s->cpu); 250 return scc->pvr; 251 case 0x1f000040: /* Cache version */ 252 scc = SUPERH_CPU_GET_CLASS(s->cpu); 253 return scc->cvr; 254 case 0x1f000044: /* Processor revision */ 255 scc = SUPERH_CPU_GET_CLASS(s->cpu); 256 return scc->prr; 257 default: 258 error_access("long read", addr); 259 abort(); 260 } 261 } 262 263 #define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \ 264 && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB)) 265 static void sh7750_mem_writeb(void *opaque, hwaddr addr, 266 uint32_t mem_value) 267 { 268 269 if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) { 270 ignore_access("byte write", addr); 271 return; 272 } 273 274 error_access("byte write", addr); 275 abort(); 276 } 277 278 static void sh7750_mem_writew(void *opaque, hwaddr addr, 279 uint32_t mem_value) 280 { 281 SH7750State *s = opaque; 282 uint16_t temp; 283 284 switch (addr) { 285 /* SDRAM controller */ 286 case SH7750_BCR2_A7: 287 s->bcr2 = mem_value; 288 return; 289 case SH7750_BCR3_A7: 290 if (!has_bcr3_and_bcr4(s)) { 291 error_access("word write", addr); 292 } 293 s->bcr3 = mem_value; 294 return; 295 case SH7750_PCR_A7: 296 s->pcr = mem_value; 297 return; 298 case SH7750_RTCNT_A7: 299 case SH7750_RTCOR_A7: 300 case SH7750_RTCSR_A7: 301 ignore_access("word write", addr); 302 return; 303 /* IO ports */ 304 case SH7750_PDTRA_A7: 305 temp = porta_lines(s); 306 s->pdtra = mem_value; 307 porta_changed(s, temp); 308 return; 309 case SH7750_PDTRB_A7: 310 temp = portb_lines(s); 311 s->pdtrb = mem_value; 312 portb_changed(s, temp); 313 return; 314 case SH7750_RFCR_A7: 315 fprintf(stderr, "Write access to refresh count register\n"); 316 s->rfcr = mem_value; 317 return; 318 case SH7750_GPIOIC_A7: 319 s->gpioic = mem_value; 320 if (mem_value != 0) { 321 fprintf(stderr, "I/O interrupts not implemented\n"); 322 abort(); 323 } 324 return; 325 default: 326 error_access("word write", addr); 327 abort(); 328 } 329 } 330 331 static void sh7750_mem_writel(void *opaque, hwaddr addr, 332 uint32_t mem_value) 333 { 334 SH7750State *s = opaque; 335 uint16_t temp; 336 337 switch (addr) { 338 /* SDRAM controller */ 339 case SH7750_BCR1_A7: 340 s->bcr1 = mem_value; 341 return; 342 case SH7750_BCR4_A7: 343 if (!has_bcr3_and_bcr4(s)) { 344 error_access("long write", addr); 345 } 346 s->bcr4 = mem_value; 347 return; 348 case SH7750_WCR1_A7: 349 case SH7750_WCR2_A7: 350 case SH7750_WCR3_A7: 351 case SH7750_MCR_A7: 352 ignore_access("long write", addr); 353 return; 354 /* IO ports */ 355 case SH7750_PCTRA_A7: 356 temp = porta_lines(s); 357 s->pctra = mem_value; 358 s->portdira = portdir(mem_value); 359 s->portpullupa = portpullup(mem_value); 360 porta_changed(s, temp); 361 return; 362 case SH7750_PCTRB_A7: 363 temp = portb_lines(s); 364 s->pctrb = mem_value; 365 s->portdirb = portdir(mem_value); 366 s->portpullupb = portpullup(mem_value); 367 portb_changed(s, temp); 368 return; 369 case SH7750_MMUCR_A7: 370 if (mem_value & MMUCR_TI) { 371 cpu_sh4_invalidate_tlb(&s->cpu->env); 372 } 373 s->cpu->env.mmucr = mem_value & ~MMUCR_TI; 374 return; 375 case SH7750_PTEH_A7: 376 /* If asid changes, clear all registered tlb entries. */ 377 if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) { 378 tlb_flush(CPU(s->cpu)); 379 } 380 s->cpu->env.pteh = mem_value; 381 return; 382 case SH7750_PTEL_A7: 383 s->cpu->env.ptel = mem_value; 384 return; 385 case SH7750_PTEA_A7: 386 s->cpu->env.ptea = mem_value & 0x0000000f; 387 return; 388 case SH7750_TTB_A7: 389 s->cpu->env.ttb = mem_value; 390 return; 391 case SH7750_TEA_A7: 392 s->cpu->env.tea = mem_value; 393 return; 394 case SH7750_TRA_A7: 395 s->cpu->env.tra = mem_value & 0x000007ff; 396 return; 397 case SH7750_EXPEVT_A7: 398 s->cpu->env.expevt = mem_value & 0x000007ff; 399 return; 400 case SH7750_INTEVT_A7: 401 s->cpu->env.intevt = mem_value & 0x000007ff; 402 return; 403 case SH7750_CCR_A7: 404 s->ccr = mem_value; 405 return; 406 default: 407 error_access("long write", addr); 408 abort(); 409 } 410 } 411 412 static uint64_t sh7750_mem_readfn(void *opaque, hwaddr addr, unsigned size) 413 { 414 switch (size) { 415 case 1: 416 return sh7750_mem_readb(opaque, addr); 417 case 2: 418 return sh7750_mem_readw(opaque, addr); 419 case 4: 420 return sh7750_mem_readl(opaque, addr); 421 default: 422 g_assert_not_reached(); 423 } 424 } 425 426 static void sh7750_mem_writefn(void *opaque, hwaddr addr, 427 uint64_t value, unsigned size) 428 { 429 switch (size) { 430 case 1: 431 sh7750_mem_writeb(opaque, addr, value); 432 break; 433 case 2: 434 sh7750_mem_writew(opaque, addr, value); 435 break; 436 case 4: 437 sh7750_mem_writel(opaque, addr, value); 438 break; 439 default: 440 g_assert_not_reached(); 441 } 442 } 443 444 static const MemoryRegionOps sh7750_mem_ops = { 445 .read = sh7750_mem_readfn, 446 .write = sh7750_mem_writefn, 447 .valid.min_access_size = 1, 448 .valid.max_access_size = 4, 449 .endianness = DEVICE_NATIVE_ENDIAN, 450 }; 451 452 /* 453 * sh775x interrupt controller tables for sh_intc.c 454 * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c 455 */ 456 457 enum { 458 UNUSED = 0, 459 460 /* interrupt sources */ 461 IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7, 462 IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E, 463 IRL0, IRL1, IRL2, IRL3, 464 HUDI, GPIOI, 465 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3, 466 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7, 467 DMAC_DMAE, 468 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 469 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, 470 TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, 471 RTC_ATI, RTC_PRI, RTC_CUI, 472 SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI, 473 SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI, 474 WDT, 475 REF_RCMI, REF_ROVI, 476 477 /* interrupt groups */ 478 DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, 479 /* irl bundle */ 480 IRL, 481 482 NR_SOURCES, 483 }; 484 485 static struct intc_vect vectors[] = { 486 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 487 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 488 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 489 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 490 INTC_VECT(RTC_CUI, 0x4c0), 491 INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500), 492 INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540), 493 INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720), 494 INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760), 495 INTC_VECT(WDT, 0x560), 496 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), 497 }; 498 499 static struct intc_group groups[] = { 500 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), 501 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 502 INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI), 503 INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI), 504 INTC_GROUP(REF, REF_RCMI, REF_ROVI), 505 }; 506 507 static struct intc_prio_reg prio_registers[] = { 508 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 509 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, 510 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, 511 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, 512 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, TMU4, TMU3, 513 PCIC1, PCIC0_PCISERR } }, 514 }; 515 516 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ 517 518 static struct intc_vect vectors_dma4[] = { 519 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 520 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 521 INTC_VECT(DMAC_DMAE, 0x6c0), 522 }; 523 524 static struct intc_group groups_dma4[] = { 525 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, 526 DMAC_DMTE3, DMAC_DMAE), 527 }; 528 529 /* SH7750R and SH7751R both have 8-channel DMA controllers */ 530 531 static struct intc_vect vectors_dma8[] = { 532 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 533 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 534 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), 535 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), 536 INTC_VECT(DMAC_DMAE, 0x6c0), 537 }; 538 539 static struct intc_group groups_dma8[] = { 540 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, 541 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, 542 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), 543 }; 544 545 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */ 546 547 static struct intc_vect vectors_tmu34[] = { 548 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), 549 }; 550 551 static struct intc_mask_reg mask_registers[] = { 552 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ 553 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 554 0, 0, 0, 0, 0, 0, TMU4, TMU3, 555 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 556 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, 557 PCIC1_PCIDMA3, PCIC0_PCISERR } }, 558 }; 559 560 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ 561 562 static struct intc_vect vectors_irlm[] = { 563 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), 564 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), 565 }; 566 567 /* SH7751 and SH7751R both have PCI */ 568 569 static struct intc_vect vectors_pci[] = { 570 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), 571 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), 572 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), 573 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), 574 }; 575 576 static struct intc_group groups_pci[] = { 577 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 578 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), 579 }; 580 581 static struct intc_vect vectors_irl[] = { 582 INTC_VECT(IRL_0, 0x200), 583 INTC_VECT(IRL_1, 0x220), 584 INTC_VECT(IRL_2, 0x240), 585 INTC_VECT(IRL_3, 0x260), 586 INTC_VECT(IRL_4, 0x280), 587 INTC_VECT(IRL_5, 0x2a0), 588 INTC_VECT(IRL_6, 0x2c0), 589 INTC_VECT(IRL_7, 0x2e0), 590 INTC_VECT(IRL_8, 0x300), 591 INTC_VECT(IRL_9, 0x320), 592 INTC_VECT(IRL_A, 0x340), 593 INTC_VECT(IRL_B, 0x360), 594 INTC_VECT(IRL_C, 0x380), 595 INTC_VECT(IRL_D, 0x3a0), 596 INTC_VECT(IRL_E, 0x3c0), 597 }; 598 599 static struct intc_group groups_irl[] = { 600 INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, 601 IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E), 602 }; 603 604 /* 605 * Memory mapped cache and TLB 606 */ 607 608 #define MM_REGION_MASK 0x07000000 609 #define MM_ICACHE_ADDR (0) 610 #define MM_ICACHE_DATA (1) 611 #define MM_ITLB_ADDR (2) 612 #define MM_ITLB_DATA (3) 613 #define MM_OCACHE_ADDR (4) 614 #define MM_OCACHE_DATA (5) 615 #define MM_UTLB_ADDR (6) 616 #define MM_UTLB_DATA (7) 617 #define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24) 618 619 static uint64_t invalid_read(void *opaque, hwaddr addr) 620 { 621 abort(); 622 623 return 0; 624 } 625 626 static uint64_t sh7750_mmct_read(void *opaque, hwaddr addr, 627 unsigned size) 628 { 629 SH7750State *s = opaque; 630 uint32_t ret = 0; 631 632 if (size != 4) { 633 return invalid_read(opaque, addr); 634 } 635 636 switch (MM_REGION_TYPE(addr)) { 637 case MM_ICACHE_ADDR: 638 case MM_ICACHE_DATA: 639 /* do nothing */ 640 break; 641 case MM_ITLB_ADDR: 642 ret = cpu_sh4_read_mmaped_itlb_addr(&s->cpu->env, addr); 643 break; 644 case MM_ITLB_DATA: 645 ret = cpu_sh4_read_mmaped_itlb_data(&s->cpu->env, addr); 646 break; 647 case MM_OCACHE_ADDR: 648 case MM_OCACHE_DATA: 649 /* do nothing */ 650 break; 651 case MM_UTLB_ADDR: 652 ret = cpu_sh4_read_mmaped_utlb_addr(&s->cpu->env, addr); 653 break; 654 case MM_UTLB_DATA: 655 ret = cpu_sh4_read_mmaped_utlb_data(&s->cpu->env, addr); 656 break; 657 default: 658 abort(); 659 } 660 661 return ret; 662 } 663 664 static void invalid_write(void *opaque, hwaddr addr, 665 uint64_t mem_value) 666 { 667 abort(); 668 } 669 670 static void sh7750_mmct_write(void *opaque, hwaddr addr, 671 uint64_t mem_value, unsigned size) 672 { 673 SH7750State *s = opaque; 674 675 if (size != 4) { 676 invalid_write(opaque, addr, mem_value); 677 } 678 679 switch (MM_REGION_TYPE(addr)) { 680 case MM_ICACHE_ADDR: 681 case MM_ICACHE_DATA: 682 /* do nothing */ 683 break; 684 case MM_ITLB_ADDR: 685 cpu_sh4_write_mmaped_itlb_addr(&s->cpu->env, addr, mem_value); 686 break; 687 case MM_ITLB_DATA: 688 cpu_sh4_write_mmaped_itlb_data(&s->cpu->env, addr, mem_value); 689 abort(); 690 break; 691 case MM_OCACHE_ADDR: 692 case MM_OCACHE_DATA: 693 /* do nothing */ 694 break; 695 case MM_UTLB_ADDR: 696 cpu_sh4_write_mmaped_utlb_addr(&s->cpu->env, addr, mem_value); 697 break; 698 case MM_UTLB_DATA: 699 cpu_sh4_write_mmaped_utlb_data(&s->cpu->env, addr, mem_value); 700 break; 701 default: 702 abort(); 703 break; 704 } 705 } 706 707 static const MemoryRegionOps sh7750_mmct_ops = { 708 .read = sh7750_mmct_read, 709 .write = sh7750_mmct_write, 710 .endianness = DEVICE_NATIVE_ENDIAN, 711 }; 712 713 SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem) 714 { 715 SH7750State *s; 716 DeviceState *dev; 717 SysBusDevice *sb; 718 MemoryRegion *mr, *alias; 719 720 s = g_new0(SH7750State, 1); 721 s->cpu = cpu; 722 s->periph_freq = 60000000; /* 60MHz */ 723 memory_region_init_io(&s->iomem, NULL, &sh7750_mem_ops, s, 724 "memory", 0x1fc01000); 725 726 memory_region_init_alias(&s->iomem_1f0, NULL, "memory-1f0", 727 &s->iomem, 0x1f000000, 0x1000); 728 memory_region_add_subregion(sysmem, 0x1f000000, &s->iomem_1f0); 729 730 memory_region_init_alias(&s->iomem_ff0, NULL, "memory-ff0", 731 &s->iomem, 0x1f000000, 0x1000); 732 memory_region_add_subregion(sysmem, 0xff000000, &s->iomem_ff0); 733 734 memory_region_init_alias(&s->iomem_1f8, NULL, "memory-1f8", 735 &s->iomem, 0x1f800000, 0x1000); 736 memory_region_add_subregion(sysmem, 0x1f800000, &s->iomem_1f8); 737 738 memory_region_init_alias(&s->iomem_ff8, NULL, "memory-ff8", 739 &s->iomem, 0x1f800000, 0x1000); 740 memory_region_add_subregion(sysmem, 0xff800000, &s->iomem_ff8); 741 742 memory_region_init_alias(&s->iomem_1fc, NULL, "memory-1fc", 743 &s->iomem, 0x1fc00000, 0x1000); 744 memory_region_add_subregion(sysmem, 0x1fc00000, &s->iomem_1fc); 745 746 memory_region_init_alias(&s->iomem_ffc, NULL, "memory-ffc", 747 &s->iomem, 0x1fc00000, 0x1000); 748 memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc); 749 750 memory_region_init_io(&s->mmct_iomem, NULL, &sh7750_mmct_ops, s, 751 "cache-and-tlb", 0x08000000); 752 memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem); 753 754 sh_intc_init(sysmem, &s->intc, NR_SOURCES, 755 _INTC_ARRAY(mask_registers), 756 _INTC_ARRAY(prio_registers)); 757 758 sh_intc_register_sources(&s->intc, 759 _INTC_ARRAY(vectors), 760 _INTC_ARRAY(groups)); 761 762 cpu->env.intc_handle = &s->intc; 763 764 /* SCI */ 765 dev = qdev_new(TYPE_SH_SERIAL); 766 dev->id = g_strdup("sci"); 767 qdev_prop_set_chr(dev, "chardev", serial_hd(0)); 768 sb = SYS_BUS_DEVICE(dev); 769 sysbus_realize_and_unref(sb, &error_fatal); 770 sysbus_mmio_map(sb, 0, 0xffe00000); 771 alias = g_malloc(sizeof(*alias)); 772 mr = sysbus_mmio_get_region(sb, 0); 773 memory_region_init_alias(alias, OBJECT(dev), "sci-a7", mr, 774 0, memory_region_size(mr)); 775 memory_region_add_subregion(sysmem, A7ADDR(0xffe00000), alias); 776 qdev_connect_gpio_out_named(dev, "eri", 0, s->intc.irqs[SCI1_ERI]); 777 qdev_connect_gpio_out_named(dev, "rxi", 0, s->intc.irqs[SCI1_RXI]); 778 qdev_connect_gpio_out_named(dev, "txi", 0, s->intc.irqs[SCI1_TXI]); 779 qdev_connect_gpio_out_named(dev, "tei", 0, s->intc.irqs[SCI1_TEI]); 780 781 /* SCIF */ 782 dev = qdev_new(TYPE_SH_SERIAL); 783 dev->id = g_strdup("scif"); 784 qdev_prop_set_chr(dev, "chardev", serial_hd(1)); 785 qdev_prop_set_uint8(dev, "features", SH_SERIAL_FEAT_SCIF); 786 sb = SYS_BUS_DEVICE(dev); 787 sysbus_realize_and_unref(sb, &error_fatal); 788 sysbus_mmio_map(sb, 0, 0xffe80000); 789 alias = g_malloc(sizeof(*alias)); 790 mr = sysbus_mmio_get_region(sb, 0); 791 memory_region_init_alias(alias, OBJECT(dev), "scif-a7", mr, 792 0, memory_region_size(mr)); 793 memory_region_add_subregion(sysmem, A7ADDR(0xffe80000), alias); 794 qdev_connect_gpio_out_named(dev, "eri", 0, s->intc.irqs[SCIF_ERI]); 795 qdev_connect_gpio_out_named(dev, "rxi", 0, s->intc.irqs[SCIF_RXI]); 796 qdev_connect_gpio_out_named(dev, "txi", 0, s->intc.irqs[SCIF_TXI]); 797 qdev_connect_gpio_out_named(dev, "bri", 0, s->intc.irqs[SCIF_BRI]); 798 799 tmu012_init(sysmem, 0x1fd80000, 800 TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, 801 s->periph_freq, 802 s->intc.irqs[TMU0], 803 s->intc.irqs[TMU1], 804 s->intc.irqs[TMU2_TUNI], 805 s->intc.irqs[TMU2_TICPI]); 806 807 if (cpu->env.id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) { 808 sh_intc_register_sources(&s->intc, 809 _INTC_ARRAY(vectors_dma4), 810 _INTC_ARRAY(groups_dma4)); 811 } 812 813 if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) { 814 sh_intc_register_sources(&s->intc, 815 _INTC_ARRAY(vectors_dma8), 816 _INTC_ARRAY(groups_dma8)); 817 } 818 819 if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) { 820 sh_intc_register_sources(&s->intc, 821 _INTC_ARRAY(vectors_tmu34), 822 NULL, 0); 823 tmu012_init(sysmem, 0x1e100000, 0, s->periph_freq, 824 s->intc.irqs[TMU3], 825 s->intc.irqs[TMU4], 826 NULL, NULL); 827 } 828 829 if (cpu->env.id & (SH_CPU_SH7751_ALL)) { 830 sh_intc_register_sources(&s->intc, 831 _INTC_ARRAY(vectors_pci), 832 _INTC_ARRAY(groups_pci)); 833 } 834 835 if (cpu->env.id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) { 836 sh_intc_register_sources(&s->intc, 837 _INTC_ARRAY(vectors_irlm), 838 NULL, 0); 839 } 840 841 sh_intc_register_sources(&s->intc, 842 _INTC_ARRAY(vectors_irl), 843 _INTC_ARRAY(groups_irl)); 844 return s; 845 } 846 847 qemu_irq sh7750_irl(SH7750State *s) 848 { 849 sh_intc_toggle_source(&s->intc.sources[IRL], 1, 0); /* enable */ 850 return qemu_allocate_irq(sh_intc_set_irl, &s->intc.sources[IRL], 0); 851 } 852