1 /* 2 * Renesas SH7751R R2D-PLUS emulation 3 * 4 * Copyright (c) 2007 Magnus Damm 5 * Copyright (c) 2008 Paul Mundt 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/units.h" 28 #include "qapi/error.h" 29 #include "qemu/error-report.h" 30 #include "cpu.h" 31 #include "hw/sysbus.h" 32 #include "hw/sh4/sh.h" 33 #include "sysemu/reset.h" 34 #include "sysemu/runstate.h" 35 #include "sysemu/sysemu.h" 36 #include "hw/boards.h" 37 #include "hw/pci/pci.h" 38 #include "hw/qdev-properties.h" 39 #include "net/net.h" 40 #include "sh7750_regs.h" 41 #include "hw/ide.h" 42 #include "hw/irq.h" 43 #include "hw/loader.h" 44 #include "hw/usb.h" 45 #include "hw/block/flash.h" 46 47 #define FLASH_BASE 0x00000000 48 #define FLASH_SIZE (16 * MiB) 49 50 #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */ 51 #define SDRAM_SIZE 0x04000000 52 53 #define SM501_VRAM_SIZE 0x800000 54 55 #define BOOT_PARAMS_OFFSET 0x0010000 56 /* CONFIG_BOOT_LINK_OFFSET of Linux kernel */ 57 #define LINUX_LOAD_OFFSET 0x0800000 58 #define INITRD_LOAD_OFFSET 0x1800000 59 60 #define PA_IRLMSK 0x00 61 #define PA_POWOFF 0x30 62 #define PA_VERREG 0x32 63 #define PA_OUTPORT 0x36 64 65 typedef struct { 66 uint16_t bcr; 67 uint16_t irlmsk; 68 uint16_t irlmon; 69 uint16_t cfctl; 70 uint16_t cfpow; 71 uint16_t dispctl; 72 uint16_t sdmpow; 73 uint16_t rtcce; 74 uint16_t pcicd; 75 uint16_t voyagerrts; 76 uint16_t cfrst; 77 uint16_t admrts; 78 uint16_t extrst; 79 uint16_t cfcdintclr; 80 uint16_t keyctlclr; 81 uint16_t pad0; 82 uint16_t pad1; 83 uint16_t verreg; 84 uint16_t inport; 85 uint16_t outport; 86 uint16_t bverreg; 87 88 /* output pin */ 89 qemu_irq irl; 90 MemoryRegion iomem; 91 } r2d_fpga_t; 92 93 enum r2d_fpga_irq { 94 PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T, 95 SDCARD, PCI_INTA, PCI_INTB, EXT, TP, 96 NR_IRQS 97 }; 98 99 static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = { 100 [CF_IDE] = { 1, 1 << 9 }, 101 [CF_CD] = { 2, 1 << 8 }, 102 [PCI_INTA] = { 9, 1 << 14 }, 103 [PCI_INTB] = { 10, 1 << 13 }, 104 [PCI_INTC] = { 3, 1 << 12 }, 105 [PCI_INTD] = { 0, 1 << 11 }, 106 [SM501] = { 4, 1 << 10 }, 107 [KEY] = { 5, 1 << 6 }, 108 [RTC_A] = { 6, 1 << 5 }, 109 [RTC_T] = { 7, 1 << 4 }, 110 [SDCARD] = { 8, 1 << 7 }, 111 [EXT] = { 11, 1 << 0 }, 112 [TP] = { 12, 1 << 15 }, 113 }; 114 115 static void update_irl(r2d_fpga_t *fpga) 116 { 117 int i, irl = 15; 118 for (i = 0; i < NR_IRQS; i++) { 119 if ((fpga->irlmon & fpga->irlmsk & irqtab[i].msk) && 120 irqtab[i].irl < irl) { 121 irl = irqtab[i].irl; 122 } 123 } 124 qemu_set_irq(fpga->irl, irl ^ 15); 125 } 126 127 static void r2d_fpga_irq_set(void *opaque, int n, int level) 128 { 129 r2d_fpga_t *fpga = opaque; 130 if (level) { 131 fpga->irlmon |= irqtab[n].msk; 132 } else { 133 fpga->irlmon &= ~irqtab[n].msk; 134 } 135 update_irl(fpga); 136 } 137 138 static uint64_t r2d_fpga_read(void *opaque, hwaddr addr, unsigned int size) 139 { 140 r2d_fpga_t *s = opaque; 141 142 switch (addr) { 143 case PA_IRLMSK: 144 return s->irlmsk; 145 case PA_OUTPORT: 146 return s->outport; 147 case PA_POWOFF: 148 return 0x00; 149 case PA_VERREG: 150 return 0x10; 151 } 152 153 return 0; 154 } 155 156 static void 157 r2d_fpga_write(void *opaque, hwaddr addr, uint64_t value, unsigned int size) 158 { 159 r2d_fpga_t *s = opaque; 160 161 switch (addr) { 162 case PA_IRLMSK: 163 s->irlmsk = value; 164 update_irl(s); 165 break; 166 case PA_OUTPORT: 167 s->outport = value; 168 break; 169 case PA_POWOFF: 170 if (value & 1) { 171 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 172 } 173 break; 174 case PA_VERREG: 175 /* Discard writes */ 176 break; 177 } 178 } 179 180 static const MemoryRegionOps r2d_fpga_ops = { 181 .read = r2d_fpga_read, 182 .write = r2d_fpga_write, 183 .impl.min_access_size = 2, 184 .impl.max_access_size = 2, 185 .endianness = DEVICE_NATIVE_ENDIAN, 186 }; 187 188 static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem, 189 hwaddr base, qemu_irq irl) 190 { 191 r2d_fpga_t *s; 192 193 s = g_malloc0(sizeof(r2d_fpga_t)); 194 195 s->irl = irl; 196 197 memory_region_init_io(&s->iomem, NULL, &r2d_fpga_ops, s, "r2d-fpga", 0x40); 198 memory_region_add_subregion(sysmem, base, &s->iomem); 199 return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS); 200 } 201 202 typedef struct ResetData { 203 SuperHCPU *cpu; 204 uint32_t vector; 205 } ResetData; 206 207 static void main_cpu_reset(void *opaque) 208 { 209 ResetData *s = (ResetData *)opaque; 210 CPUSH4State *env = &s->cpu->env; 211 212 cpu_reset(CPU(s->cpu)); 213 env->pc = s->vector; 214 } 215 216 static struct QEMU_PACKED 217 { 218 int mount_root_rdonly; 219 int ramdisk_flags; 220 int orig_root_dev; 221 int loader_type; 222 int initrd_start; 223 int initrd_size; 224 225 char pad[232]; 226 227 char kernel_cmdline[256] QEMU_NONSTRING; 228 } boot_params; 229 230 static void r2d_init(MachineState *machine) 231 { 232 const char *kernel_filename = machine->kernel_filename; 233 const char *kernel_cmdline = machine->kernel_cmdline; 234 const char *initrd_filename = machine->initrd_filename; 235 SuperHCPU *cpu; 236 CPUSH4State *env; 237 ResetData *reset_info; 238 struct SH7750State *s; 239 MemoryRegion *sdram = g_new(MemoryRegion, 1); 240 qemu_irq *irq; 241 DriveInfo *dinfo; 242 int i; 243 DeviceState *dev; 244 SysBusDevice *busdev; 245 MemoryRegion *address_space_mem = get_system_memory(); 246 PCIBus *pci_bus; 247 248 cpu = SUPERH_CPU(cpu_create(machine->cpu_type)); 249 env = &cpu->env; 250 251 reset_info = g_malloc0(sizeof(ResetData)); 252 reset_info->cpu = cpu; 253 reset_info->vector = env->pc; 254 qemu_register_reset(main_cpu_reset, reset_info); 255 256 /* Allocate memory space */ 257 memory_region_init_ram(sdram, NULL, "r2d.sdram", SDRAM_SIZE, &error_fatal); 258 memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram); 259 /* Register peripherals */ 260 s = sh7750_init(cpu, address_space_mem); 261 irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s)); 262 263 dev = qdev_new("sh_pci"); 264 busdev = SYS_BUS_DEVICE(dev); 265 sysbus_realize_and_unref(busdev, &error_fatal); 266 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci")); 267 sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000)); 268 sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000)); 269 sysbus_connect_irq(busdev, 0, irq[PCI_INTA]); 270 sysbus_connect_irq(busdev, 1, irq[PCI_INTB]); 271 sysbus_connect_irq(busdev, 2, irq[PCI_INTC]); 272 sysbus_connect_irq(busdev, 3, irq[PCI_INTD]); 273 274 dev = qdev_new("sysbus-sm501"); 275 busdev = SYS_BUS_DEVICE(dev); 276 qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE); 277 qdev_prop_set_uint32(dev, "base", 0x10000000); 278 qdev_prop_set_chr(dev, "chardev", serial_hd(2)); 279 sysbus_realize_and_unref(busdev, &error_fatal); 280 sysbus_mmio_map(busdev, 0, 0x10000000); 281 sysbus_mmio_map(busdev, 1, 0x13e00000); 282 sysbus_connect_irq(busdev, 0, irq[SM501]); 283 284 /* onboard CF (True IDE mode, Master only). */ 285 dinfo = drive_get(IF_IDE, 0, 0); 286 dev = qdev_new("mmio-ide"); 287 busdev = SYS_BUS_DEVICE(dev); 288 sysbus_connect_irq(busdev, 0, irq[CF_IDE]); 289 qdev_prop_set_uint32(dev, "shift", 1); 290 sysbus_realize_and_unref(busdev, &error_fatal); 291 sysbus_mmio_map(busdev, 0, 0x14001000); 292 sysbus_mmio_map(busdev, 1, 0x1400080c); 293 mmio_ide_init_drives(dev, dinfo, NULL); 294 295 /* 296 * Onboard flash memory 297 * According to the old board user document in Japanese (under 298 * NDA) what is referred to as FROM (Area0) is connected via a 299 * 32-bit bus and CS0 to CN8. The docs mention a Cypress 300 * S29PL127J60TFI130 chipsset. Per the 'S29PL-J 002-00615 301 * Rev. *E' datasheet, it is a 128Mbit NOR parallel flash 302 * addressable in words of 16bit. 303 */ 304 dinfo = drive_get(IF_PFLASH, 0, 0); 305 pflash_cfi02_register(0x0, "r2d.flash", FLASH_SIZE, 306 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 307 64 * KiB, 1, 2, 0x0001, 0x227e, 0x2220, 0x2200, 308 0x555, 0x2aa, 0); 309 310 /* NIC: rtl8139 on-board, and 2 slots. */ 311 for (i = 0; i < nb_nics; i++) 312 pci_nic_init_nofail(&nd_table[i], pci_bus, 313 "rtl8139", i == 0 ? "2" : NULL); 314 315 /* USB keyboard */ 316 usb_create_simple(usb_bus_find(-1), "usb-kbd"); 317 318 /* Todo: register on board registers */ 319 memset(&boot_params, 0, sizeof(boot_params)); 320 321 if (kernel_filename) { 322 int kernel_size; 323 324 kernel_size = load_image_targphys(kernel_filename, 325 SDRAM_BASE + LINUX_LOAD_OFFSET, 326 INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET); 327 if (kernel_size < 0) { 328 error_report("qemu: could not load kernel '%s'", kernel_filename); 329 exit(1); 330 } 331 332 /* initialization which should be done by firmware */ 333 address_space_stl(&address_space_memory, SH7750_BCR1, 1 << 3, 334 MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 SDRAM */ 335 address_space_stw(&address_space_memory, SH7750_BCR2, 3 << (3 * 2), 336 MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 32bit */ 337 /* Start from P2 area */ 338 reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; 339 } 340 341 if (initrd_filename) { 342 int initrd_size; 343 344 initrd_size = load_image_targphys(initrd_filename, 345 SDRAM_BASE + INITRD_LOAD_OFFSET, 346 SDRAM_SIZE - INITRD_LOAD_OFFSET); 347 348 if (initrd_size < 0) { 349 error_report("qemu: could not load initrd '%s'", initrd_filename); 350 exit(1); 351 } 352 353 /* initialization which should be done by firmware */ 354 boot_params.loader_type = tswap32(1); 355 boot_params.initrd_start = tswap32(INITRD_LOAD_OFFSET); 356 boot_params.initrd_size = tswap32(initrd_size); 357 } 358 359 if (kernel_cmdline) { 360 /* 361 * I see no evidence that this .kernel_cmdline buffer requires 362 * NUL-termination, so using strncpy should be ok. 363 */ 364 strncpy(boot_params.kernel_cmdline, kernel_cmdline, 365 sizeof(boot_params.kernel_cmdline)); 366 } 367 368 rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params), 369 SDRAM_BASE + BOOT_PARAMS_OFFSET); 370 } 371 372 static void r2d_machine_init(MachineClass *mc) 373 { 374 mc->desc = "r2d-plus board"; 375 mc->init = r2d_init; 376 mc->block_default_type = IF_IDE; 377 mc->default_cpu_type = TYPE_SH7751R_CPU; 378 } 379 380 DEFINE_MACHINE("r2d", r2d_machine_init) 381