1 /* 2 * Renesas SH7751R R2D-PLUS emulation 3 * 4 * Copyright (c) 2007 Magnus Damm 5 * Copyright (c) 2008 Paul Mundt 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "hw/sysbus.h" 29 #include "hw/hw.h" 30 #include "hw/sh4/sh.h" 31 #include "hw/devices.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/boards.h" 34 #include "hw/pci/pci.h" 35 #include "net/net.h" 36 #include "sh7750_regs.h" 37 #include "hw/ide.h" 38 #include "hw/loader.h" 39 #include "hw/usb.h" 40 #include "hw/block/flash.h" 41 #include "sysemu/block-backend.h" 42 #include "exec/address-spaces.h" 43 44 #define FLASH_BASE 0x00000000 45 #define FLASH_SIZE 0x02000000 46 47 #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */ 48 #define SDRAM_SIZE 0x04000000 49 50 #define SM501_VRAM_SIZE 0x800000 51 52 #define BOOT_PARAMS_OFFSET 0x0010000 53 /* CONFIG_BOOT_LINK_OFFSET of Linux kernel */ 54 #define LINUX_LOAD_OFFSET 0x0800000 55 #define INITRD_LOAD_OFFSET 0x1800000 56 57 #define PA_IRLMSK 0x00 58 #define PA_POWOFF 0x30 59 #define PA_VERREG 0x32 60 #define PA_OUTPORT 0x36 61 62 typedef struct { 63 uint16_t bcr; 64 uint16_t irlmsk; 65 uint16_t irlmon; 66 uint16_t cfctl; 67 uint16_t cfpow; 68 uint16_t dispctl; 69 uint16_t sdmpow; 70 uint16_t rtcce; 71 uint16_t pcicd; 72 uint16_t voyagerrts; 73 uint16_t cfrst; 74 uint16_t admrts; 75 uint16_t extrst; 76 uint16_t cfcdintclr; 77 uint16_t keyctlclr; 78 uint16_t pad0; 79 uint16_t pad1; 80 uint16_t verreg; 81 uint16_t inport; 82 uint16_t outport; 83 uint16_t bverreg; 84 85 /* output pin */ 86 qemu_irq irl; 87 MemoryRegion iomem; 88 } r2d_fpga_t; 89 90 enum r2d_fpga_irq { 91 PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T, 92 SDCARD, PCI_INTA, PCI_INTB, EXT, TP, 93 NR_IRQS 94 }; 95 96 static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = { 97 [CF_IDE] = { 1, 1<<9 }, 98 [CF_CD] = { 2, 1<<8 }, 99 [PCI_INTA] = { 9, 1<<14 }, 100 [PCI_INTB] = { 10, 1<<13 }, 101 [PCI_INTC] = { 3, 1<<12 }, 102 [PCI_INTD] = { 0, 1<<11 }, 103 [SM501] = { 4, 1<<10 }, 104 [KEY] = { 5, 1<<6 }, 105 [RTC_A] = { 6, 1<<5 }, 106 [RTC_T] = { 7, 1<<4 }, 107 [SDCARD] = { 8, 1<<7 }, 108 [EXT] = { 11, 1<<0 }, 109 [TP] = { 12, 1<<15 }, 110 }; 111 112 static void update_irl(r2d_fpga_t *fpga) 113 { 114 int i, irl = 15; 115 for (i = 0; i < NR_IRQS; i++) 116 if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk) 117 if (irqtab[i].irl < irl) 118 irl = irqtab[i].irl; 119 qemu_set_irq(fpga->irl, irl ^ 15); 120 } 121 122 static void r2d_fpga_irq_set(void *opaque, int n, int level) 123 { 124 r2d_fpga_t *fpga = opaque; 125 if (level) 126 fpga->irlmon |= irqtab[n].msk; 127 else 128 fpga->irlmon &= ~irqtab[n].msk; 129 update_irl(fpga); 130 } 131 132 static uint64_t r2d_fpga_read(void *opaque, hwaddr addr, unsigned int size) 133 { 134 r2d_fpga_t *s = opaque; 135 136 switch (addr) { 137 case PA_IRLMSK: 138 return s->irlmsk; 139 case PA_OUTPORT: 140 return s->outport; 141 case PA_POWOFF: 142 return 0x00; 143 case PA_VERREG: 144 return 0x10; 145 } 146 147 return 0; 148 } 149 150 static void 151 r2d_fpga_write(void *opaque, hwaddr addr, uint64_t value, unsigned int size) 152 { 153 r2d_fpga_t *s = opaque; 154 155 switch (addr) { 156 case PA_IRLMSK: 157 s->irlmsk = value; 158 update_irl(s); 159 break; 160 case PA_OUTPORT: 161 s->outport = value; 162 break; 163 case PA_POWOFF: 164 if (value & 1) { 165 qemu_system_shutdown_request(); 166 } 167 break; 168 case PA_VERREG: 169 /* Discard writes */ 170 break; 171 } 172 } 173 174 static const MemoryRegionOps r2d_fpga_ops = { 175 .read = r2d_fpga_read, 176 .write = r2d_fpga_write, 177 .impl.min_access_size = 2, 178 .impl.max_access_size = 2, 179 .endianness = DEVICE_NATIVE_ENDIAN, 180 }; 181 182 static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem, 183 hwaddr base, qemu_irq irl) 184 { 185 r2d_fpga_t *s; 186 187 s = g_malloc0(sizeof(r2d_fpga_t)); 188 189 s->irl = irl; 190 191 memory_region_init_io(&s->iomem, NULL, &r2d_fpga_ops, s, "r2d-fpga", 0x40); 192 memory_region_add_subregion(sysmem, base, &s->iomem); 193 return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS); 194 } 195 196 typedef struct ResetData { 197 SuperHCPU *cpu; 198 uint32_t vector; 199 } ResetData; 200 201 static void main_cpu_reset(void *opaque) 202 { 203 ResetData *s = (ResetData *)opaque; 204 CPUSH4State *env = &s->cpu->env; 205 206 cpu_reset(CPU(s->cpu)); 207 env->pc = s->vector; 208 } 209 210 static struct QEMU_PACKED 211 { 212 int mount_root_rdonly; 213 int ramdisk_flags; 214 int orig_root_dev; 215 int loader_type; 216 int initrd_start; 217 int initrd_size; 218 219 char pad[232]; 220 221 char kernel_cmdline[256]; 222 } boot_params; 223 224 static void r2d_init(MachineState *machine) 225 { 226 const char *cpu_model = machine->cpu_model; 227 const char *kernel_filename = machine->kernel_filename; 228 const char *kernel_cmdline = machine->kernel_cmdline; 229 const char *initrd_filename = machine->initrd_filename; 230 SuperHCPU *cpu; 231 CPUSH4State *env; 232 ResetData *reset_info; 233 struct SH7750State *s; 234 MemoryRegion *sdram = g_new(MemoryRegion, 1); 235 qemu_irq *irq; 236 DriveInfo *dinfo; 237 int i; 238 DeviceState *dev; 239 SysBusDevice *busdev; 240 MemoryRegion *address_space_mem = get_system_memory(); 241 PCIBus *pci_bus; 242 243 if (cpu_model == NULL) { 244 cpu_model = "SH7751R"; 245 } 246 247 cpu = cpu_sh4_init(cpu_model); 248 if (cpu == NULL) { 249 fprintf(stderr, "Unable to find CPU definition\n"); 250 exit(1); 251 } 252 env = &cpu->env; 253 254 reset_info = g_malloc0(sizeof(ResetData)); 255 reset_info->cpu = cpu; 256 reset_info->vector = env->pc; 257 qemu_register_reset(main_cpu_reset, reset_info); 258 259 /* Allocate memory space */ 260 memory_region_init_ram(sdram, NULL, "r2d.sdram", SDRAM_SIZE, &error_fatal); 261 vmstate_register_ram_global(sdram); 262 memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram); 263 /* Register peripherals */ 264 s = sh7750_init(cpu, address_space_mem); 265 irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s)); 266 267 dev = qdev_create(NULL, "sh_pci"); 268 busdev = SYS_BUS_DEVICE(dev); 269 qdev_init_nofail(dev); 270 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci")); 271 sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000)); 272 sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000)); 273 sysbus_connect_irq(busdev, 0, irq[PCI_INTA]); 274 sysbus_connect_irq(busdev, 1, irq[PCI_INTB]); 275 sysbus_connect_irq(busdev, 2, irq[PCI_INTC]); 276 sysbus_connect_irq(busdev, 3, irq[PCI_INTD]); 277 278 sm501_init(address_space_mem, 0x10000000, SM501_VRAM_SIZE, 279 irq[SM501], serial_hds[2]); 280 281 /* onboard CF (True IDE mode, Master only). */ 282 dinfo = drive_get(IF_IDE, 0, 0); 283 dev = qdev_create(NULL, "mmio-ide"); 284 busdev = SYS_BUS_DEVICE(dev); 285 sysbus_connect_irq(busdev, 0, irq[CF_IDE]); 286 qdev_prop_set_uint32(dev, "shift", 1); 287 qdev_init_nofail(dev); 288 sysbus_mmio_map(busdev, 0, 0x14001000); 289 sysbus_mmio_map(busdev, 1, 0x1400080c); 290 mmio_ide_init_drives(dev, dinfo, NULL); 291 292 /* onboard flash memory */ 293 dinfo = drive_get(IF_PFLASH, 0, 0); 294 pflash_cfi02_register(0x0, NULL, "r2d.flash", FLASH_SIZE, 295 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 296 (16 * 1024), FLASH_SIZE >> 16, 297 1, 4, 0x0000, 0x0000, 0x0000, 0x0000, 298 0x555, 0x2aa, 0); 299 300 /* NIC: rtl8139 on-board, and 2 slots. */ 301 for (i = 0; i < nb_nics; i++) 302 pci_nic_init_nofail(&nd_table[i], pci_bus, 303 "rtl8139", i==0 ? "2" : NULL); 304 305 /* USB keyboard */ 306 usb_create_simple(usb_bus_find(-1), "usb-kbd"); 307 308 /* Todo: register on board registers */ 309 memset(&boot_params, 0, sizeof(boot_params)); 310 311 if (kernel_filename) { 312 int kernel_size; 313 314 kernel_size = load_image_targphys(kernel_filename, 315 SDRAM_BASE + LINUX_LOAD_OFFSET, 316 INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET); 317 if (kernel_size < 0) { 318 fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename); 319 exit(1); 320 } 321 322 /* initialization which should be done by firmware */ 323 address_space_stl(&address_space_memory, SH7750_BCR1, 1 << 3, 324 MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 SDRAM */ 325 address_space_stw(&address_space_memory, SH7750_BCR2, 3 << (3 * 2), 326 MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 32bit */ 327 reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */ 328 } 329 330 if (initrd_filename) { 331 int initrd_size; 332 333 initrd_size = load_image_targphys(initrd_filename, 334 SDRAM_BASE + INITRD_LOAD_OFFSET, 335 SDRAM_SIZE - INITRD_LOAD_OFFSET); 336 337 if (initrd_size < 0) { 338 fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename); 339 exit(1); 340 } 341 342 /* initialization which should be done by firmware */ 343 boot_params.loader_type = tswap32(1); 344 boot_params.initrd_start = tswap32(INITRD_LOAD_OFFSET); 345 boot_params.initrd_size = tswap32(initrd_size); 346 } 347 348 if (kernel_cmdline) { 349 /* I see no evidence that this .kernel_cmdline buffer requires 350 NUL-termination, so using strncpy should be ok. */ 351 strncpy(boot_params.kernel_cmdline, kernel_cmdline, 352 sizeof(boot_params.kernel_cmdline)); 353 } 354 355 rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params), 356 SDRAM_BASE + BOOT_PARAMS_OFFSET); 357 } 358 359 static void r2d_machine_init(MachineClass *mc) 360 { 361 mc->desc = "r2d-plus board"; 362 mc->init = r2d_init; 363 } 364 365 DEFINE_MACHINE("r2d", r2d_machine_init) 366