1 /* 2 * SSI to SD card adapter. 3 * 4 * Copyright (c) 2007-2009 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * Copyright (c) 2021 Wind River Systems, Inc. 8 * Improved by Bin Meng <bin.meng@windriver.com> 9 * 10 * Validated with U-Boot v2021.01 and Linux v5.10 mmc_spi driver 11 * 12 * This code is licensed under the GNU GPL v2. 13 * 14 * Contributions after 2012-01-13 are licensed under the terms of the 15 * GNU GPL, version 2 or (at your option) any later version. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "system/blockdev.h" 20 #include "hw/ssi/ssi.h" 21 #include "migration/vmstate.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/sd/sd.h" 24 #include "qapi/error.h" 25 #include "qemu/crc-ccitt.h" 26 #include "qemu/module.h" 27 #include "qom/object.h" 28 29 //#define DEBUG_SSI_SD 1 30 31 #ifdef DEBUG_SSI_SD 32 #define DPRINTF(fmt, ...) \ 33 do { printf("ssi_sd: " fmt , ## __VA_ARGS__); } while (0) 34 #define BADF(fmt, ...) \ 35 do { fprintf(stderr, "ssi_sd: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) 36 #else 37 #define DPRINTF(fmt, ...) do {} while(0) 38 #define BADF(fmt, ...) \ 39 do { fprintf(stderr, "ssi_sd: error: " fmt , ## __VA_ARGS__);} while (0) 40 #endif 41 42 typedef enum { 43 SSI_SD_CMD = 0, 44 SSI_SD_CMDARG, 45 SSI_SD_PREP_RESP, 46 SSI_SD_RESPONSE, 47 SSI_SD_PREP_DATA, 48 SSI_SD_DATA_START, 49 SSI_SD_DATA_READ, 50 SSI_SD_DATA_CRC16, 51 SSI_SD_DATA_WRITE, 52 SSI_SD_SKIP_CRC16, 53 } ssi_sd_mode; 54 55 struct ssi_sd_state { 56 SSIPeripheral ssidev; 57 uint32_t mode; 58 int cmd; 59 uint8_t cmdarg[4]; 60 uint8_t response[5]; 61 uint16_t crc16; 62 int32_t read_bytes; 63 int32_t write_bytes; 64 int32_t arglen; 65 int32_t response_pos; 66 int32_t stopping; 67 SDBus sdbus; 68 }; 69 70 #define TYPE_SSI_SD "ssi-sd" 71 OBJECT_DECLARE_SIMPLE_TYPE(ssi_sd_state, SSI_SD) 72 73 /* multiple block write */ 74 #define SSI_TOKEN_MULTI_WRITE 0xfc 75 /* terminate multiple block write */ 76 #define SSI_TOKEN_STOP_TRAN 0xfd 77 /* single block read/write, multiple block read */ 78 #define SSI_TOKEN_SINGLE 0xfe 79 80 /* dummy value - don't care */ 81 #define SSI_DUMMY 0xff 82 83 /* data accepted */ 84 #define DATA_RESPONSE_ACCEPTED 0x05 85 86 static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) 87 { 88 ssi_sd_state *s = SSI_SD(dev); 89 SDRequest request; 90 uint8_t longresp[5]; 91 92 if (!sdbus_get_inserted(&s->sdbus)) { 93 return SSI_DUMMY; 94 } 95 96 /* 97 * Special case: allow CMD12 (STOP TRANSMISSION) while reading data. 98 * 99 * See "Physical Layer Specification Version 8.00" chapter 7.5.2.2, 100 * to avoid conflict between CMD12 response and next data block, 101 * timing of CMD12 should be controlled as follows: 102 * 103 * - CMD12 issued at the timing that end bit of CMD12 and end bit of 104 * data block is overlapped 105 * - CMD12 issued after one clock cycle after host receives a token 106 * (either Start Block token or Data Error token) 107 * 108 * We need to catch CMD12 in all of the data read states. 109 */ 110 if (s->mode >= SSI_SD_PREP_DATA && s->mode <= SSI_SD_DATA_CRC16) { 111 if (val == 0x4c) { 112 s->mode = SSI_SD_CMD; 113 /* There must be at least one byte delay before the card responds */ 114 s->stopping = 1; 115 } 116 } 117 118 switch (s->mode) { 119 case SSI_SD_CMD: 120 switch (val) { 121 case SSI_DUMMY: 122 DPRINTF("NULL command\n"); 123 return SSI_DUMMY; 124 break; 125 case SSI_TOKEN_SINGLE: 126 case SSI_TOKEN_MULTI_WRITE: 127 DPRINTF("Start write block\n"); 128 s->mode = SSI_SD_DATA_WRITE; 129 return SSI_DUMMY; 130 case SSI_TOKEN_STOP_TRAN: 131 DPRINTF("Stop multiple write\n"); 132 133 /* manually issue cmd12 to stop the transfer */ 134 request.cmd = 12; 135 request.arg = 0; 136 s->arglen = sdbus_do_command(&s->sdbus, &request, 137 longresp, sizeof(longresp)); 138 if (s->arglen == 0) { 139 s->arglen = 1; 140 /* a zero value indicates the card is busy */ 141 s->response[0] = 0; 142 DPRINTF("SD card busy\n"); 143 } else { 144 s->arglen = 1; 145 /* a non-zero value indicates the card is ready */ 146 s->response[0] = SSI_DUMMY; 147 } 148 149 return SSI_DUMMY; 150 } 151 152 s->cmd = val & 0x3f; 153 s->mode = SSI_SD_CMDARG; 154 s->arglen = 0; 155 return SSI_DUMMY; 156 case SSI_SD_CMDARG: 157 if (s->arglen == 4) { 158 /* FIXME: Check CRC. */ 159 request.cmd = s->cmd; 160 request.arg = ldl_be_p(s->cmdarg); 161 s->arglen = sdbus_do_command(&s->sdbus, &request, 162 longresp, sizeof(longresp)); 163 DPRINTF("CMD%d arg 0x%08x = %d\n", s->cmd, request.arg, s->arglen); 164 assert(s->arglen > 0); 165 memcpy(s->response, longresp, s->arglen); 166 167 /* handle R1b (busy signal) */ 168 if (s->cmd == 28 || s->cmd == 29 || s->cmd == 38) { 169 s->stopping = 1; 170 } 171 s->mode = SSI_SD_PREP_RESP; 172 s->response_pos = 0; 173 } else { 174 s->cmdarg[s->arglen++] = val; 175 } 176 return SSI_DUMMY; 177 case SSI_SD_PREP_RESP: 178 DPRINTF("Prepare card response (Ncr)\n"); 179 s->mode = SSI_SD_RESPONSE; 180 return SSI_DUMMY; 181 case SSI_SD_RESPONSE: 182 if (s->response_pos < s->arglen) { 183 DPRINTF("Response 0x%02x\n", s->response[s->response_pos]); 184 return s->response[s->response_pos++]; 185 } 186 if (s->stopping) { 187 s->stopping = 0; 188 s->mode = SSI_SD_CMD; 189 return SSI_DUMMY; 190 } 191 if (sdbus_data_ready(&s->sdbus)) { 192 DPRINTF("Data read\n"); 193 s->mode = SSI_SD_DATA_START; 194 } else { 195 DPRINTF("End of command\n"); 196 s->mode = SSI_SD_CMD; 197 } 198 return SSI_DUMMY; 199 case SSI_SD_PREP_DATA: 200 DPRINTF("Prepare data block (Nac)\n"); 201 s->mode = SSI_SD_DATA_START; 202 return SSI_DUMMY; 203 case SSI_SD_DATA_START: 204 DPRINTF("Start read block\n"); 205 s->mode = SSI_SD_DATA_READ; 206 s->response_pos = 0; 207 return SSI_TOKEN_SINGLE; 208 case SSI_SD_DATA_READ: 209 val = sdbus_read_byte(&s->sdbus); 210 s->read_bytes++; 211 s->crc16 = crc_ccitt_false(s->crc16, (uint8_t *)&val, 1); 212 if (!sdbus_data_ready(&s->sdbus) || s->read_bytes == 512) { 213 DPRINTF("Data read end\n"); 214 s->mode = SSI_SD_DATA_CRC16; 215 } 216 return val; 217 case SSI_SD_DATA_CRC16: 218 val = (s->crc16 & 0xff00) >> 8; 219 s->crc16 <<= 8; 220 s->response_pos++; 221 if (s->response_pos == 2) { 222 DPRINTF("CRC16 read end\n"); 223 if (s->read_bytes == 512 && s->cmd != 17) { 224 s->mode = SSI_SD_PREP_DATA; 225 } else { 226 s->mode = SSI_SD_CMD; 227 } 228 s->read_bytes = 0; 229 s->response_pos = 0; 230 } 231 return val; 232 case SSI_SD_DATA_WRITE: 233 sdbus_write_byte(&s->sdbus, val); 234 s->write_bytes++; 235 if (!sdbus_receive_ready(&s->sdbus) || s->write_bytes == 512) { 236 DPRINTF("Data write end\n"); 237 s->mode = SSI_SD_SKIP_CRC16; 238 s->response_pos = 0; 239 } 240 return val; 241 case SSI_SD_SKIP_CRC16: 242 /* we don't verify the crc16 */ 243 s->response_pos++; 244 if (s->response_pos == 2) { 245 DPRINTF("CRC16 receive end\n"); 246 s->mode = SSI_SD_RESPONSE; 247 s->write_bytes = 0; 248 s->arglen = 1; 249 s->response[0] = DATA_RESPONSE_ACCEPTED; 250 s->response_pos = 0; 251 } 252 return SSI_DUMMY; 253 } 254 /* Should never happen. */ 255 return SSI_DUMMY; 256 } 257 258 static int ssi_sd_post_load(void *opaque, int version_id) 259 { 260 ssi_sd_state *s = (ssi_sd_state *)opaque; 261 262 if (s->mode > SSI_SD_SKIP_CRC16) { 263 return -EINVAL; 264 } 265 if (s->mode == SSI_SD_CMDARG && 266 (s->arglen >= ARRAY_SIZE(s->cmdarg))) { 267 return -EINVAL; 268 } 269 if (s->mode == SSI_SD_RESPONSE && 270 (s->response_pos < 0 || s->response_pos >= ARRAY_SIZE(s->response) || 271 (!s->stopping && s->arglen > ARRAY_SIZE(s->response)))) { 272 return -EINVAL; 273 } 274 275 return 0; 276 } 277 278 static const VMStateDescription vmstate_ssi_sd = { 279 .name = "ssi_sd", 280 .version_id = 7, 281 .minimum_version_id = 7, 282 .post_load = ssi_sd_post_load, 283 .fields = (const VMStateField []) { 284 VMSTATE_UINT32(mode, ssi_sd_state), 285 VMSTATE_INT32(cmd, ssi_sd_state), 286 VMSTATE_UINT8_ARRAY(cmdarg, ssi_sd_state, 4), 287 VMSTATE_UINT8_ARRAY(response, ssi_sd_state, 5), 288 VMSTATE_UINT16(crc16, ssi_sd_state), 289 VMSTATE_INT32(read_bytes, ssi_sd_state), 290 VMSTATE_INT32(write_bytes, ssi_sd_state), 291 VMSTATE_INT32(arglen, ssi_sd_state), 292 VMSTATE_INT32(response_pos, ssi_sd_state), 293 VMSTATE_INT32(stopping, ssi_sd_state), 294 VMSTATE_SSI_PERIPHERAL(ssidev, ssi_sd_state), 295 VMSTATE_END_OF_LIST() 296 } 297 }; 298 299 static void ssi_sd_realize(SSIPeripheral *d, Error **errp) 300 { 301 ssi_sd_state *s = SSI_SD(d); 302 303 qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, DEVICE(d), "sd-bus"); 304 } 305 306 static void ssi_sd_reset(DeviceState *dev) 307 { 308 ssi_sd_state *s = SSI_SD(dev); 309 310 s->mode = SSI_SD_CMD; 311 s->cmd = 0; 312 memset(s->cmdarg, 0, sizeof(s->cmdarg)); 313 memset(s->response, 0, sizeof(s->response)); 314 s->crc16 = 0; 315 s->read_bytes = 0; 316 s->write_bytes = 0; 317 s->arglen = 0; 318 s->response_pos = 0; 319 s->stopping = 0; 320 } 321 322 static void ssi_sd_class_init(ObjectClass *klass, const void *data) 323 { 324 DeviceClass *dc = DEVICE_CLASS(klass); 325 SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass); 326 327 k->realize = ssi_sd_realize; 328 k->transfer = ssi_sd_transfer; 329 k->cs_polarity = SSI_CS_LOW; 330 dc->vmsd = &vmstate_ssi_sd; 331 device_class_set_legacy_reset(dc, ssi_sd_reset); 332 /* Reason: GPIO chip-select line should be wired up */ 333 dc->user_creatable = false; 334 } 335 336 static const TypeInfo ssi_sd_types[] = { 337 { 338 .name = TYPE_SSI_SD, 339 .parent = TYPE_SSI_PERIPHERAL, 340 .instance_size = sizeof(ssi_sd_state), 341 .class_init = ssi_sd_class_init, 342 }, 343 }; 344 345 DEFINE_TYPES(ssi_sd_types) 346