1 /* 2 * SD Association Host Standard Specification v2.0 controller emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Mitsyanko Igor <i.mitsyanko@samsung.com> 6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 7 * 8 * Based on MMC controller for Samsung S5PC1xx-based board emulation 9 * by Alexey Merkulov and Vladimir Monakhov. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 19 * See the GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "sysemu/block-backend.h" 28 #include "sysemu/blockdev.h" 29 #include "sysemu/dma.h" 30 #include "qemu/timer.h" 31 #include "qemu/bitops.h" 32 #include "sdhci-internal.h" 33 34 /* host controller debug messages */ 35 #ifndef SDHC_DEBUG 36 #define SDHC_DEBUG 0 37 #endif 38 39 #define DPRINT_L1(fmt, args...) \ 40 do { \ 41 if (SDHC_DEBUG) { \ 42 fprintf(stderr, "QEMU SDHC: " fmt, ## args); \ 43 } \ 44 } while (0) 45 #define DPRINT_L2(fmt, args...) \ 46 do { \ 47 if (SDHC_DEBUG > 1) { \ 48 fprintf(stderr, "QEMU SDHC: " fmt, ## args); \ 49 } \ 50 } while (0) 51 #define ERRPRINT(fmt, args...) \ 52 do { \ 53 if (SDHC_DEBUG) { \ 54 fprintf(stderr, "QEMU SDHC ERROR: " fmt, ## args); \ 55 } \ 56 } while (0) 57 58 /* Default SD/MMC host controller features information, which will be 59 * presented in CAPABILITIES register of generic SD host controller at reset. 60 * If not stated otherwise: 61 * 0 - not supported, 1 - supported, other - prohibited. 62 */ 63 #define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */ 64 #define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */ 65 #define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */ 66 #define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */ 67 #define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */ 68 #define SDHC_CAPAB_SDMA 1ul /* SDMA support */ 69 #define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */ 70 #define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */ 71 #define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */ 72 /* Maximum host controller R/W buffers size 73 * Possible values: 512, 1024, 2048 bytes */ 74 #define SDHC_CAPAB_MAXBLOCKLENGTH 512ul 75 /* Maximum clock frequency for SDclock in MHz 76 * value in range 10-63 MHz, 0 - not defined */ 77 #define SDHC_CAPAB_BASECLKFREQ 52ul 78 #define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */ 79 /* Timeout clock frequency 1-63, 0 - not defined */ 80 #define SDHC_CAPAB_TOCLKFREQ 52ul 81 82 /* Now check all parameters and calculate CAPABILITIES REGISTER value */ 83 #if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \ 84 SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \ 85 SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\ 86 SDHC_CAPAB_TOUNIT > 1 87 #error Capabilities features can have value 0 or 1 only! 88 #endif 89 90 #if SDHC_CAPAB_MAXBLOCKLENGTH == 512 91 #define MAX_BLOCK_LENGTH 0ul 92 #elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024 93 #define MAX_BLOCK_LENGTH 1ul 94 #elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048 95 #define MAX_BLOCK_LENGTH 2ul 96 #else 97 #error Max host controller block size can have value 512, 1024 or 2048 only! 98 #endif 99 100 #if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \ 101 SDHC_CAPAB_BASECLKFREQ > 63 102 #error SDclock frequency can have value in range 0, 10-63 only! 103 #endif 104 105 #if SDHC_CAPAB_TOCLKFREQ > 63 106 #error Timeout clock frequency can have value in range 0-63 only! 107 #endif 108 109 #define SDHC_CAPAB_REG_DEFAULT \ 110 ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \ 111 (SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \ 112 (SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \ 113 (SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \ 114 (SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \ 115 (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \ 116 (SDHC_CAPAB_TOCLKFREQ)) 117 118 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) 119 120 static uint8_t sdhci_slotint(SDHCIState *s) 121 { 122 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || 123 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || 124 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); 125 } 126 127 static inline void sdhci_update_irq(SDHCIState *s) 128 { 129 qemu_set_irq(s->irq, sdhci_slotint(s)); 130 } 131 132 static void sdhci_raise_insertion_irq(void *opaque) 133 { 134 SDHCIState *s = (SDHCIState *)opaque; 135 136 if (s->norintsts & SDHC_NIS_REMOVE) { 137 timer_mod(s->insert_timer, 138 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 139 } else { 140 s->prnsts = 0x1ff0000; 141 if (s->norintstsen & SDHC_NISEN_INSERT) { 142 s->norintsts |= SDHC_NIS_INSERT; 143 } 144 sdhci_update_irq(s); 145 } 146 } 147 148 static void sdhci_insert_eject_cb(void *opaque, int irq, int level) 149 { 150 SDHCIState *s = (SDHCIState *)opaque; 151 DPRINT_L1("Card state changed: %s!\n", level ? "insert" : "eject"); 152 153 if ((s->norintsts & SDHC_NIS_REMOVE) && level) { 154 /* Give target some time to notice card ejection */ 155 timer_mod(s->insert_timer, 156 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 157 } else { 158 if (level) { 159 s->prnsts = 0x1ff0000; 160 if (s->norintstsen & SDHC_NISEN_INSERT) { 161 s->norintsts |= SDHC_NIS_INSERT; 162 } 163 } else { 164 s->prnsts = 0x1fa0000; 165 s->pwrcon &= ~SDHC_POWER_ON; 166 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; 167 if (s->norintstsen & SDHC_NISEN_REMOVE) { 168 s->norintsts |= SDHC_NIS_REMOVE; 169 } 170 } 171 sdhci_update_irq(s); 172 } 173 } 174 175 static void sdhci_card_readonly_cb(void *opaque, int irq, int level) 176 { 177 SDHCIState *s = (SDHCIState *)opaque; 178 179 if (level) { 180 s->prnsts &= ~SDHC_WRITE_PROTECT; 181 } else { 182 /* Write enabled */ 183 s->prnsts |= SDHC_WRITE_PROTECT; 184 } 185 } 186 187 static void sdhci_reset(SDHCIState *s) 188 { 189 timer_del(s->insert_timer); 190 timer_del(s->transfer_timer); 191 /* Set all registers to 0. Capabilities registers are not cleared 192 * and assumed to always preserve their value, given to them during 193 * initialization */ 194 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); 195 196 if (!s->noeject_quirk) { 197 sd_set_cb(s->card, s->ro_cb, s->eject_cb); 198 } 199 s->data_count = 0; 200 s->stopped_state = sdhc_not_stopped; 201 } 202 203 static void sdhci_data_transfer(void *opaque); 204 205 static void sdhci_send_command(SDHCIState *s) 206 { 207 SDRequest request; 208 uint8_t response[16]; 209 int rlen; 210 211 s->errintsts = 0; 212 s->acmd12errsts = 0; 213 request.cmd = s->cmdreg >> 8; 214 request.arg = s->argument; 215 DPRINT_L1("sending CMD%u ARG[0x%08x]\n", request.cmd, request.arg); 216 rlen = sd_do_command(s->card, &request, response); 217 218 if (s->cmdreg & SDHC_CMD_RESPONSE) { 219 if (rlen == 4) { 220 s->rspreg[0] = (response[0] << 24) | (response[1] << 16) | 221 (response[2] << 8) | response[3]; 222 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; 223 DPRINT_L1("Response: RSPREG[31..0]=0x%08x\n", s->rspreg[0]); 224 } else if (rlen == 16) { 225 s->rspreg[0] = (response[11] << 24) | (response[12] << 16) | 226 (response[13] << 8) | response[14]; 227 s->rspreg[1] = (response[7] << 24) | (response[8] << 16) | 228 (response[9] << 8) | response[10]; 229 s->rspreg[2] = (response[3] << 24) | (response[4] << 16) | 230 (response[5] << 8) | response[6]; 231 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | 232 response[2]; 233 DPRINT_L1("Response received:\n RSPREG[127..96]=0x%08x, RSPREG[95.." 234 "64]=0x%08x,\n RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x\n", 235 s->rspreg[3], s->rspreg[2], s->rspreg[1], s->rspreg[0]); 236 } else { 237 ERRPRINT("Timeout waiting for command response\n"); 238 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { 239 s->errintsts |= SDHC_EIS_CMDTIMEOUT; 240 s->norintsts |= SDHC_NIS_ERR; 241 } 242 } 243 244 if ((s->norintstsen & SDHC_NISEN_TRSCMP) && 245 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { 246 s->norintsts |= SDHC_NIS_TRSCMP; 247 } 248 } 249 250 if (s->norintstsen & SDHC_NISEN_CMDCMP) { 251 s->norintsts |= SDHC_NIS_CMDCMP; 252 } 253 254 sdhci_update_irq(s); 255 256 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { 257 s->data_count = 0; 258 sdhci_data_transfer(s); 259 } 260 } 261 262 static void sdhci_end_transfer(SDHCIState *s) 263 { 264 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */ 265 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { 266 SDRequest request; 267 uint8_t response[16]; 268 269 request.cmd = 0x0C; 270 request.arg = 0; 271 DPRINT_L1("Automatically issue CMD%d %08x\n", request.cmd, request.arg); 272 sd_do_command(s->card, &request, response); 273 /* Auto CMD12 response goes to the upper Response register */ 274 s->rspreg[3] = (response[0] << 24) | (response[1] << 16) | 275 (response[2] << 8) | response[3]; 276 } 277 278 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | 279 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | 280 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); 281 282 if (s->norintstsen & SDHC_NISEN_TRSCMP) { 283 s->norintsts |= SDHC_NIS_TRSCMP; 284 } 285 286 sdhci_update_irq(s); 287 } 288 289 /* 290 * Programmed i/o data transfer 291 */ 292 293 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ 294 static void sdhci_read_block_from_card(SDHCIState *s) 295 { 296 int index = 0; 297 298 if ((s->trnmod & SDHC_TRNS_MULTI) && 299 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { 300 return; 301 } 302 303 for (index = 0; index < (s->blksize & 0x0fff); index++) { 304 s->fifo_buffer[index] = sd_read_data(s->card); 305 } 306 307 /* New data now available for READ through Buffer Port Register */ 308 s->prnsts |= SDHC_DATA_AVAILABLE; 309 if (s->norintstsen & SDHC_NISEN_RBUFRDY) { 310 s->norintsts |= SDHC_NIS_RBUFRDY; 311 } 312 313 /* Clear DAT line active status if that was the last block */ 314 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 315 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { 316 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 317 } 318 319 /* If stop at block gap request was set and it's not the last block of 320 * data - generate Block Event interrupt */ 321 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && 322 s->blkcnt != 1) { 323 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 324 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 325 s->norintsts |= SDHC_EIS_BLKGAP; 326 } 327 } 328 329 sdhci_update_irq(s); 330 } 331 332 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */ 333 static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) 334 { 335 uint32_t value = 0; 336 int i; 337 338 /* first check that a valid data exists in host controller input buffer */ 339 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { 340 ERRPRINT("Trying to read from empty buffer\n"); 341 return 0; 342 } 343 344 for (i = 0; i < size; i++) { 345 value |= s->fifo_buffer[s->data_count] << i * 8; 346 s->data_count++; 347 /* check if we've read all valid data (blksize bytes) from buffer */ 348 if ((s->data_count) >= (s->blksize & 0x0fff)) { 349 DPRINT_L2("All %u bytes of data have been read from input buffer\n", 350 s->data_count); 351 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ 352 s->data_count = 0; /* next buff read must start at position [0] */ 353 354 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 355 s->blkcnt--; 356 } 357 358 /* if that was the last block of data */ 359 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 360 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || 361 /* stop at gap request */ 362 (s->stopped_state == sdhc_gap_read && 363 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { 364 sdhci_end_transfer(s); 365 } else { /* if there are more data, read next block from card */ 366 sdhci_read_block_from_card(s); 367 } 368 break; 369 } 370 } 371 372 return value; 373 } 374 375 /* Write data from host controller FIFO to card */ 376 static void sdhci_write_block_to_card(SDHCIState *s) 377 { 378 int index = 0; 379 380 if (s->prnsts & SDHC_SPACE_AVAILABLE) { 381 if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 382 s->norintsts |= SDHC_NIS_WBUFRDY; 383 } 384 sdhci_update_irq(s); 385 return; 386 } 387 388 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 389 if (s->blkcnt == 0) { 390 return; 391 } else { 392 s->blkcnt--; 393 } 394 } 395 396 for (index = 0; index < (s->blksize & 0x0fff); index++) { 397 sd_write_data(s->card, s->fifo_buffer[index]); 398 } 399 400 /* Next data can be written through BUFFER DATORT register */ 401 s->prnsts |= SDHC_SPACE_AVAILABLE; 402 403 /* Finish transfer if that was the last block of data */ 404 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 405 ((s->trnmod & SDHC_TRNS_MULTI) && 406 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { 407 sdhci_end_transfer(s); 408 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 409 s->norintsts |= SDHC_NIS_WBUFRDY; 410 } 411 412 /* Generate Block Gap Event if requested and if not the last block */ 413 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && 414 s->blkcnt > 0) { 415 s->prnsts &= ~SDHC_DOING_WRITE; 416 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 417 s->norintsts |= SDHC_EIS_BLKGAP; 418 } 419 sdhci_end_transfer(s); 420 } 421 422 sdhci_update_irq(s); 423 } 424 425 /* Write @size bytes of @value data to host controller @s Buffer Data Port 426 * register */ 427 static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) 428 { 429 unsigned i; 430 431 /* Check that there is free space left in a buffer */ 432 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { 433 ERRPRINT("Can't write to data buffer: buffer full\n"); 434 return; 435 } 436 437 for (i = 0; i < size; i++) { 438 s->fifo_buffer[s->data_count] = value & 0xFF; 439 s->data_count++; 440 value >>= 8; 441 if (s->data_count >= (s->blksize & 0x0fff)) { 442 DPRINT_L2("write buffer filled with %u bytes of data\n", 443 s->data_count); 444 s->data_count = 0; 445 s->prnsts &= ~SDHC_SPACE_AVAILABLE; 446 if (s->prnsts & SDHC_DOING_WRITE) { 447 sdhci_write_block_to_card(s); 448 } 449 } 450 } 451 } 452 453 /* 454 * Single DMA data transfer 455 */ 456 457 /* Multi block SDMA transfer */ 458 static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) 459 { 460 bool page_aligned = false; 461 unsigned int n, begin; 462 const uint16_t block_size = s->blksize & 0x0fff; 463 uint32_t boundary_chk = 1 << (((s->blksize & 0xf000) >> 12) + 12); 464 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); 465 466 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for 467 * possible stop at page boundary if initial address is not page aligned, 468 * allow them to work properly */ 469 if ((s->sdmasysad % boundary_chk) == 0) { 470 page_aligned = true; 471 } 472 473 if (s->trnmod & SDHC_TRNS_READ) { 474 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 475 SDHC_DAT_LINE_ACTIVE; 476 while (s->blkcnt) { 477 if (s->data_count == 0) { 478 for (n = 0; n < block_size; n++) { 479 s->fifo_buffer[n] = sd_read_data(s->card); 480 } 481 } 482 begin = s->data_count; 483 if (((boundary_count + begin) < block_size) && page_aligned) { 484 s->data_count = boundary_count + begin; 485 boundary_count = 0; 486 } else { 487 s->data_count = block_size; 488 boundary_count -= block_size - begin; 489 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 490 s->blkcnt--; 491 } 492 } 493 dma_memory_write(&address_space_memory, s->sdmasysad, 494 &s->fifo_buffer[begin], s->data_count - begin); 495 s->sdmasysad += s->data_count - begin; 496 if (s->data_count == block_size) { 497 s->data_count = 0; 498 } 499 if (page_aligned && boundary_count == 0) { 500 break; 501 } 502 } 503 } else { 504 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT | 505 SDHC_DAT_LINE_ACTIVE; 506 while (s->blkcnt) { 507 begin = s->data_count; 508 if (((boundary_count + begin) < block_size) && page_aligned) { 509 s->data_count = boundary_count + begin; 510 boundary_count = 0; 511 } else { 512 s->data_count = block_size; 513 boundary_count -= block_size - begin; 514 } 515 dma_memory_read(&address_space_memory, s->sdmasysad, 516 &s->fifo_buffer[begin], s->data_count); 517 s->sdmasysad += s->data_count - begin; 518 if (s->data_count == block_size) { 519 for (n = 0; n < block_size; n++) { 520 sd_write_data(s->card, s->fifo_buffer[n]); 521 } 522 s->data_count = 0; 523 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 524 s->blkcnt--; 525 } 526 } 527 if (page_aligned && boundary_count == 0) { 528 break; 529 } 530 } 531 } 532 533 if (s->blkcnt == 0) { 534 sdhci_end_transfer(s); 535 } else { 536 if (s->norintstsen & SDHC_NISEN_DMA) { 537 s->norintsts |= SDHC_NIS_DMA; 538 } 539 sdhci_update_irq(s); 540 } 541 } 542 543 /* single block SDMA transfer */ 544 545 static void sdhci_sdma_transfer_single_block(SDHCIState *s) 546 { 547 int n; 548 uint32_t datacnt = s->blksize & 0x0fff; 549 550 if (s->trnmod & SDHC_TRNS_READ) { 551 for (n = 0; n < datacnt; n++) { 552 s->fifo_buffer[n] = sd_read_data(s->card); 553 } 554 dma_memory_write(&address_space_memory, s->sdmasysad, s->fifo_buffer, 555 datacnt); 556 } else { 557 dma_memory_read(&address_space_memory, s->sdmasysad, s->fifo_buffer, 558 datacnt); 559 for (n = 0; n < datacnt; n++) { 560 sd_write_data(s->card, s->fifo_buffer[n]); 561 } 562 } 563 564 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 565 s->blkcnt--; 566 } 567 568 sdhci_end_transfer(s); 569 } 570 571 typedef struct ADMADescr { 572 hwaddr addr; 573 uint16_t length; 574 uint8_t attr; 575 uint8_t incr; 576 } ADMADescr; 577 578 static void get_adma_description(SDHCIState *s, ADMADescr *dscr) 579 { 580 uint32_t adma1 = 0; 581 uint64_t adma2 = 0; 582 hwaddr entry_addr = (hwaddr)s->admasysaddr; 583 switch (SDHC_DMA_TYPE(s->hostctl)) { 584 case SDHC_CTRL_ADMA2_32: 585 dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma2, 586 sizeof(adma2)); 587 adma2 = le64_to_cpu(adma2); 588 /* The spec does not specify endianness of descriptor table. 589 * We currently assume that it is LE. 590 */ 591 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; 592 dscr->length = (uint16_t)extract64(adma2, 16, 16); 593 dscr->attr = (uint8_t)extract64(adma2, 0, 7); 594 dscr->incr = 8; 595 break; 596 case SDHC_CTRL_ADMA1_32: 597 dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma1, 598 sizeof(adma1)); 599 adma1 = le32_to_cpu(adma1); 600 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); 601 dscr->attr = (uint8_t)extract32(adma1, 0, 7); 602 dscr->incr = 4; 603 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { 604 dscr->length = (uint16_t)extract32(adma1, 12, 16); 605 } else { 606 dscr->length = 4096; 607 } 608 break; 609 case SDHC_CTRL_ADMA2_64: 610 dma_memory_read(&address_space_memory, entry_addr, 611 (uint8_t *)(&dscr->attr), 1); 612 dma_memory_read(&address_space_memory, entry_addr + 2, 613 (uint8_t *)(&dscr->length), 2); 614 dscr->length = le16_to_cpu(dscr->length); 615 dma_memory_read(&address_space_memory, entry_addr + 4, 616 (uint8_t *)(&dscr->addr), 8); 617 dscr->attr = le64_to_cpu(dscr->attr); 618 dscr->attr &= 0xfffffff8; 619 dscr->incr = 12; 620 break; 621 } 622 } 623 624 /* Advanced DMA data transfer */ 625 626 static void sdhci_do_adma(SDHCIState *s) 627 { 628 unsigned int n, begin, length; 629 const uint16_t block_size = s->blksize & 0x0fff; 630 ADMADescr dscr; 631 int i; 632 633 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { 634 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; 635 636 get_adma_description(s, &dscr); 637 DPRINT_L2("ADMA loop: addr=" TARGET_FMT_plx ", len=%d, attr=%x\n", 638 dscr.addr, dscr.length, dscr.attr); 639 640 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { 641 /* Indicate that error occurred in ST_FDS state */ 642 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; 643 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; 644 645 /* Generate ADMA error interrupt */ 646 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 647 s->errintsts |= SDHC_EIS_ADMAERR; 648 s->norintsts |= SDHC_NIS_ERR; 649 } 650 651 sdhci_update_irq(s); 652 return; 653 } 654 655 length = dscr.length ? dscr.length : 65536; 656 657 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { 658 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ 659 660 if (s->trnmod & SDHC_TRNS_READ) { 661 while (length) { 662 if (s->data_count == 0) { 663 for (n = 0; n < block_size; n++) { 664 s->fifo_buffer[n] = sd_read_data(s->card); 665 } 666 } 667 begin = s->data_count; 668 if ((length + begin) < block_size) { 669 s->data_count = length + begin; 670 length = 0; 671 } else { 672 s->data_count = block_size; 673 length -= block_size - begin; 674 } 675 dma_memory_write(&address_space_memory, dscr.addr, 676 &s->fifo_buffer[begin], 677 s->data_count - begin); 678 dscr.addr += s->data_count - begin; 679 if (s->data_count == block_size) { 680 s->data_count = 0; 681 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 682 s->blkcnt--; 683 if (s->blkcnt == 0) { 684 break; 685 } 686 } 687 } 688 } 689 } else { 690 while (length) { 691 begin = s->data_count; 692 if ((length + begin) < block_size) { 693 s->data_count = length + begin; 694 length = 0; 695 } else { 696 s->data_count = block_size; 697 length -= block_size - begin; 698 } 699 dma_memory_read(&address_space_memory, dscr.addr, 700 &s->fifo_buffer[begin], 701 s->data_count - begin); 702 dscr.addr += s->data_count - begin; 703 if (s->data_count == block_size) { 704 for (n = 0; n < block_size; n++) { 705 sd_write_data(s->card, s->fifo_buffer[n]); 706 } 707 s->data_count = 0; 708 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 709 s->blkcnt--; 710 if (s->blkcnt == 0) { 711 break; 712 } 713 } 714 } 715 } 716 } 717 s->admasysaddr += dscr.incr; 718 break; 719 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ 720 s->admasysaddr = dscr.addr; 721 DPRINT_L1("ADMA link: admasysaddr=0x%" PRIx64 "\n", 722 s->admasysaddr); 723 break; 724 default: 725 s->admasysaddr += dscr.incr; 726 break; 727 } 728 729 if (dscr.attr & SDHC_ADMA_ATTR_INT) { 730 DPRINT_L1("ADMA interrupt: admasysaddr=0x%" PRIx64 "\n", 731 s->admasysaddr); 732 if (s->norintstsen & SDHC_NISEN_DMA) { 733 s->norintsts |= SDHC_NIS_DMA; 734 } 735 736 sdhci_update_irq(s); 737 } 738 739 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ 740 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 741 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { 742 DPRINT_L2("ADMA transfer completed\n"); 743 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && 744 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 745 s->blkcnt != 0)) { 746 ERRPRINT("SD/MMC host ADMA length mismatch\n"); 747 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | 748 SDHC_ADMAERR_STATE_ST_TFR; 749 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 750 ERRPRINT("Set ADMA error flag\n"); 751 s->errintsts |= SDHC_EIS_ADMAERR; 752 s->norintsts |= SDHC_NIS_ERR; 753 } 754 755 sdhci_update_irq(s); 756 } 757 sdhci_end_transfer(s); 758 return; 759 } 760 761 } 762 763 /* we have unfinished business - reschedule to continue ADMA */ 764 timer_mod(s->transfer_timer, 765 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY); 766 } 767 768 /* Perform data transfer according to controller configuration */ 769 770 static void sdhci_data_transfer(void *opaque) 771 { 772 SDHCIState *s = (SDHCIState *)opaque; 773 774 if (s->trnmod & SDHC_TRNS_DMA) { 775 switch (SDHC_DMA_TYPE(s->hostctl)) { 776 case SDHC_CTRL_SDMA: 777 if ((s->trnmod & SDHC_TRNS_MULTI) && 778 (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || s->blkcnt == 0)) { 779 break; 780 } 781 782 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { 783 sdhci_sdma_transfer_single_block(s); 784 } else { 785 sdhci_sdma_transfer_multi_blocks(s); 786 } 787 788 break; 789 case SDHC_CTRL_ADMA1_32: 790 if (!(s->capareg & SDHC_CAN_DO_ADMA1)) { 791 ERRPRINT("ADMA1 not supported\n"); 792 break; 793 } 794 795 sdhci_do_adma(s); 796 break; 797 case SDHC_CTRL_ADMA2_32: 798 if (!(s->capareg & SDHC_CAN_DO_ADMA2)) { 799 ERRPRINT("ADMA2 not supported\n"); 800 break; 801 } 802 803 sdhci_do_adma(s); 804 break; 805 case SDHC_CTRL_ADMA2_64: 806 if (!(s->capareg & SDHC_CAN_DO_ADMA2) || 807 !(s->capareg & SDHC_64_BIT_BUS_SUPPORT)) { 808 ERRPRINT("64 bit ADMA not supported\n"); 809 break; 810 } 811 812 sdhci_do_adma(s); 813 break; 814 default: 815 ERRPRINT("Unsupported DMA type\n"); 816 break; 817 } 818 } else { 819 if ((s->trnmod & SDHC_TRNS_READ) && sd_data_ready(s->card)) { 820 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 821 SDHC_DAT_LINE_ACTIVE; 822 sdhci_read_block_from_card(s); 823 } else { 824 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | 825 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; 826 sdhci_write_block_to_card(s); 827 } 828 } 829 } 830 831 static bool sdhci_can_issue_command(SDHCIState *s) 832 { 833 if (!SDHC_CLOCK_IS_ON(s->clkcon) || 834 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && 835 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || 836 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && 837 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { 838 return false; 839 } 840 841 return true; 842 } 843 844 /* The Buffer Data Port register must be accessed in sequential and 845 * continuous manner */ 846 static inline bool 847 sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) 848 { 849 if ((s->data_count & 0x3) != byte_num) { 850 ERRPRINT("Non-sequential access to Buffer Data Port register" 851 "is prohibited\n"); 852 return false; 853 } 854 return true; 855 } 856 857 static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) 858 { 859 SDHCIState *s = (SDHCIState *)opaque; 860 uint32_t ret = 0; 861 862 switch (offset & ~0x3) { 863 case SDHC_SYSAD: 864 ret = s->sdmasysad; 865 break; 866 case SDHC_BLKSIZE: 867 ret = s->blksize | (s->blkcnt << 16); 868 break; 869 case SDHC_ARGUMENT: 870 ret = s->argument; 871 break; 872 case SDHC_TRNMOD: 873 ret = s->trnmod | (s->cmdreg << 16); 874 break; 875 case SDHC_RSPREG0 ... SDHC_RSPREG3: 876 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; 877 break; 878 case SDHC_BDATA: 879 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 880 ret = sdhci_read_dataport(s, size); 881 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset, 882 ret, ret); 883 return ret; 884 } 885 break; 886 case SDHC_PRNSTS: 887 ret = s->prnsts; 888 break; 889 case SDHC_HOSTCTL: 890 ret = s->hostctl | (s->pwrcon << 8) | (s->blkgap << 16) | 891 (s->wakcon << 24); 892 break; 893 case SDHC_CLKCON: 894 ret = s->clkcon | (s->timeoutcon << 16); 895 break; 896 case SDHC_NORINTSTS: 897 ret = s->norintsts | (s->errintsts << 16); 898 break; 899 case SDHC_NORINTSTSEN: 900 ret = s->norintstsen | (s->errintstsen << 16); 901 break; 902 case SDHC_NORINTSIGEN: 903 ret = s->norintsigen | (s->errintsigen << 16); 904 break; 905 case SDHC_ACMD12ERRSTS: 906 ret = s->acmd12errsts; 907 break; 908 case SDHC_CAPAREG: 909 ret = s->capareg; 910 break; 911 case SDHC_MAXCURR: 912 ret = s->maxcurr; 913 break; 914 case SDHC_ADMAERR: 915 ret = s->admaerr; 916 break; 917 case SDHC_ADMASYSADDR: 918 ret = (uint32_t)s->admasysaddr; 919 break; 920 case SDHC_ADMASYSADDR + 4: 921 ret = (uint32_t)(s->admasysaddr >> 32); 922 break; 923 case SDHC_SLOT_INT_STATUS: 924 ret = (SD_HOST_SPECv2_VERS << 16) | sdhci_slotint(s); 925 break; 926 default: 927 ERRPRINT("bad %ub read: addr[0x%04x]\n", size, (int)offset); 928 break; 929 } 930 931 ret >>= (offset & 0x3) * 8; 932 ret &= (1ULL << (size * 8)) - 1; 933 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset, ret, ret); 934 return ret; 935 } 936 937 static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) 938 { 939 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { 940 return; 941 } 942 s->blkgap = value & SDHC_STOP_AT_GAP_REQ; 943 944 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && 945 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { 946 if (s->stopped_state == sdhc_gap_read) { 947 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; 948 sdhci_read_block_from_card(s); 949 } else { 950 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; 951 sdhci_write_block_to_card(s); 952 } 953 s->stopped_state = sdhc_not_stopped; 954 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { 955 if (s->prnsts & SDHC_DOING_READ) { 956 s->stopped_state = sdhc_gap_read; 957 } else if (s->prnsts & SDHC_DOING_WRITE) { 958 s->stopped_state = sdhc_gap_write; 959 } 960 } 961 } 962 963 static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) 964 { 965 switch (value) { 966 case SDHC_RESET_ALL: 967 sdhci_reset(s); 968 break; 969 case SDHC_RESET_CMD: 970 s->prnsts &= ~SDHC_CMD_INHIBIT; 971 s->norintsts &= ~SDHC_NIS_CMDCMP; 972 break; 973 case SDHC_RESET_DATA: 974 s->data_count = 0; 975 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | 976 SDHC_DOING_READ | SDHC_DOING_WRITE | 977 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); 978 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); 979 s->stopped_state = sdhc_not_stopped; 980 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | 981 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); 982 break; 983 } 984 } 985 986 static void 987 sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 988 { 989 SDHCIState *s = (SDHCIState *)opaque; 990 unsigned shift = 8 * (offset & 0x3); 991 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); 992 uint32_t value = val; 993 value <<= shift; 994 995 switch (offset & ~0x3) { 996 case SDHC_SYSAD: 997 s->sdmasysad = (s->sdmasysad & mask) | value; 998 MASKED_WRITE(s->sdmasysad, mask, value); 999 /* Writing to last byte of sdmasysad might trigger transfer */ 1000 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && 1001 s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) { 1002 sdhci_sdma_transfer_multi_blocks(s); 1003 } 1004 break; 1005 case SDHC_BLKSIZE: 1006 if (!TRANSFERRING_DATA(s->prnsts)) { 1007 MASKED_WRITE(s->blksize, mask, value); 1008 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); 1009 } 1010 1011 /* Limit block size to the maximum buffer size */ 1012 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) { 1013 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " \ 1014 "the maximum buffer 0x%x", __func__, s->blksize, 1015 s->buf_maxsz); 1016 1017 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz); 1018 } 1019 1020 break; 1021 case SDHC_ARGUMENT: 1022 MASKED_WRITE(s->argument, mask, value); 1023 break; 1024 case SDHC_TRNMOD: 1025 /* DMA can be enabled only if it is supported as indicated by 1026 * capabilities register */ 1027 if (!(s->capareg & SDHC_CAN_DO_DMA)) { 1028 value &= ~SDHC_TRNS_DMA; 1029 } 1030 MASKED_WRITE(s->trnmod, mask, value); 1031 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); 1032 1033 /* Writing to the upper byte of CMDREG triggers SD command generation */ 1034 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { 1035 break; 1036 } 1037 1038 sdhci_send_command(s); 1039 break; 1040 case SDHC_BDATA: 1041 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1042 sdhci_write_dataport(s, value >> shift, size); 1043 } 1044 break; 1045 case SDHC_HOSTCTL: 1046 if (!(mask & 0xFF0000)) { 1047 sdhci_blkgap_write(s, value >> 16); 1048 } 1049 MASKED_WRITE(s->hostctl, mask, value); 1050 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); 1051 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); 1052 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || 1053 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { 1054 s->pwrcon &= ~SDHC_POWER_ON; 1055 } 1056 break; 1057 case SDHC_CLKCON: 1058 if (!(mask & 0xFF000000)) { 1059 sdhci_reset_write(s, value >> 24); 1060 } 1061 MASKED_WRITE(s->clkcon, mask, value); 1062 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); 1063 if (s->clkcon & SDHC_CLOCK_INT_EN) { 1064 s->clkcon |= SDHC_CLOCK_INT_STABLE; 1065 } else { 1066 s->clkcon &= ~SDHC_CLOCK_INT_STABLE; 1067 } 1068 break; 1069 case SDHC_NORINTSTS: 1070 if (s->norintstsen & SDHC_NISEN_CARDINT) { 1071 value &= ~SDHC_NIS_CARDINT; 1072 } 1073 s->norintsts &= mask | ~value; 1074 s->errintsts &= (mask >> 16) | ~(value >> 16); 1075 if (s->errintsts) { 1076 s->norintsts |= SDHC_NIS_ERR; 1077 } else { 1078 s->norintsts &= ~SDHC_NIS_ERR; 1079 } 1080 sdhci_update_irq(s); 1081 break; 1082 case SDHC_NORINTSTSEN: 1083 MASKED_WRITE(s->norintstsen, mask, value); 1084 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); 1085 s->norintsts &= s->norintstsen; 1086 s->errintsts &= s->errintstsen; 1087 if (s->errintsts) { 1088 s->norintsts |= SDHC_NIS_ERR; 1089 } else { 1090 s->norintsts &= ~SDHC_NIS_ERR; 1091 } 1092 sdhci_update_irq(s); 1093 break; 1094 case SDHC_NORINTSIGEN: 1095 MASKED_WRITE(s->norintsigen, mask, value); 1096 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); 1097 sdhci_update_irq(s); 1098 break; 1099 case SDHC_ADMAERR: 1100 MASKED_WRITE(s->admaerr, mask, value); 1101 break; 1102 case SDHC_ADMASYSADDR: 1103 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | 1104 (uint64_t)mask)) | (uint64_t)value; 1105 break; 1106 case SDHC_ADMASYSADDR + 4: 1107 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | 1108 ((uint64_t)mask << 32))) | ((uint64_t)value << 32); 1109 break; 1110 case SDHC_FEAER: 1111 s->acmd12errsts |= value; 1112 s->errintsts |= (value >> 16) & s->errintstsen; 1113 if (s->acmd12errsts) { 1114 s->errintsts |= SDHC_EIS_CMD12ERR; 1115 } 1116 if (s->errintsts) { 1117 s->norintsts |= SDHC_NIS_ERR; 1118 } 1119 sdhci_update_irq(s); 1120 break; 1121 default: 1122 ERRPRINT("bad %ub write offset: addr[0x%04x] <- %u(0x%x)\n", 1123 size, (int)offset, value >> shift, value >> shift); 1124 break; 1125 } 1126 DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n", 1127 size, (int)offset, value >> shift, value >> shift); 1128 } 1129 1130 static const MemoryRegionOps sdhci_mmio_ops = { 1131 .read = sdhci_read, 1132 .write = sdhci_write, 1133 .valid = { 1134 .min_access_size = 1, 1135 .max_access_size = 4, 1136 .unaligned = false 1137 }, 1138 .endianness = DEVICE_LITTLE_ENDIAN, 1139 }; 1140 1141 static inline unsigned int sdhci_get_fifolen(SDHCIState *s) 1142 { 1143 switch (SDHC_CAPAB_BLOCKSIZE(s->capareg)) { 1144 case 0: 1145 return 512; 1146 case 1: 1147 return 1024; 1148 case 2: 1149 return 2048; 1150 default: 1151 hw_error("SDHC: unsupported value for maximum block size\n"); 1152 return 0; 1153 } 1154 } 1155 1156 static void sdhci_initfn(SDHCIState *s, BlockBackend *blk) 1157 { 1158 s->card = sd_init(blk, false); 1159 if (s->card == NULL) { 1160 exit(1); 1161 } 1162 s->eject_cb = qemu_allocate_irq(sdhci_insert_eject_cb, s, 0); 1163 s->ro_cb = qemu_allocate_irq(sdhci_card_readonly_cb, s, 0); 1164 sd_set_cb(s->card, s->ro_cb, s->eject_cb); 1165 1166 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); 1167 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); 1168 } 1169 1170 static void sdhci_uninitfn(SDHCIState *s) 1171 { 1172 timer_del(s->insert_timer); 1173 timer_free(s->insert_timer); 1174 timer_del(s->transfer_timer); 1175 timer_free(s->transfer_timer); 1176 qemu_free_irq(s->eject_cb); 1177 qemu_free_irq(s->ro_cb); 1178 1179 g_free(s->fifo_buffer); 1180 s->fifo_buffer = NULL; 1181 } 1182 1183 const VMStateDescription sdhci_vmstate = { 1184 .name = "sdhci", 1185 .version_id = 1, 1186 .minimum_version_id = 1, 1187 .fields = (VMStateField[]) { 1188 VMSTATE_UINT32(sdmasysad, SDHCIState), 1189 VMSTATE_UINT16(blksize, SDHCIState), 1190 VMSTATE_UINT16(blkcnt, SDHCIState), 1191 VMSTATE_UINT32(argument, SDHCIState), 1192 VMSTATE_UINT16(trnmod, SDHCIState), 1193 VMSTATE_UINT16(cmdreg, SDHCIState), 1194 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), 1195 VMSTATE_UINT32(prnsts, SDHCIState), 1196 VMSTATE_UINT8(hostctl, SDHCIState), 1197 VMSTATE_UINT8(pwrcon, SDHCIState), 1198 VMSTATE_UINT8(blkgap, SDHCIState), 1199 VMSTATE_UINT8(wakcon, SDHCIState), 1200 VMSTATE_UINT16(clkcon, SDHCIState), 1201 VMSTATE_UINT8(timeoutcon, SDHCIState), 1202 VMSTATE_UINT8(admaerr, SDHCIState), 1203 VMSTATE_UINT16(norintsts, SDHCIState), 1204 VMSTATE_UINT16(errintsts, SDHCIState), 1205 VMSTATE_UINT16(norintstsen, SDHCIState), 1206 VMSTATE_UINT16(errintstsen, SDHCIState), 1207 VMSTATE_UINT16(norintsigen, SDHCIState), 1208 VMSTATE_UINT16(errintsigen, SDHCIState), 1209 VMSTATE_UINT16(acmd12errsts, SDHCIState), 1210 VMSTATE_UINT16(data_count, SDHCIState), 1211 VMSTATE_UINT64(admasysaddr, SDHCIState), 1212 VMSTATE_UINT8(stopped_state, SDHCIState), 1213 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, 0, buf_maxsz), 1214 VMSTATE_TIMER_PTR(insert_timer, SDHCIState), 1215 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState), 1216 VMSTATE_END_OF_LIST() 1217 } 1218 }; 1219 1220 /* Capabilities registers provide information on supported features of this 1221 * specific host controller implementation */ 1222 static Property sdhci_pci_properties[] = { 1223 /* 1224 * We currently fuse controller and card into a single device 1225 * model, but we intend to separate them. For that purpose, the 1226 * properties that belong to the card are marked as experimental. 1227 */ 1228 DEFINE_PROP_DRIVE("x-drive", SDHCIState, blk), 1229 DEFINE_PROP_UINT32("capareg", SDHCIState, capareg, 1230 SDHC_CAPAB_REG_DEFAULT), 1231 DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0), 1232 DEFINE_PROP_END_OF_LIST(), 1233 }; 1234 1235 static void sdhci_pci_realize(PCIDevice *dev, Error **errp) 1236 { 1237 SDHCIState *s = PCI_SDHCI(dev); 1238 dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */ 1239 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ 1240 sdhci_initfn(s, s->blk); 1241 s->buf_maxsz = sdhci_get_fifolen(s); 1242 s->fifo_buffer = g_malloc0(s->buf_maxsz); 1243 s->irq = pci_allocate_irq(dev); 1244 memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci", 1245 SDHC_REGISTERS_MAP_SIZE); 1246 pci_register_bar(dev, 0, 0, &s->iomem); 1247 } 1248 1249 static void sdhci_pci_exit(PCIDevice *dev) 1250 { 1251 SDHCIState *s = PCI_SDHCI(dev); 1252 sdhci_uninitfn(s); 1253 } 1254 1255 static void sdhci_pci_class_init(ObjectClass *klass, void *data) 1256 { 1257 DeviceClass *dc = DEVICE_CLASS(klass); 1258 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1259 1260 k->realize = sdhci_pci_realize; 1261 k->exit = sdhci_pci_exit; 1262 k->vendor_id = PCI_VENDOR_ID_REDHAT; 1263 k->device_id = PCI_DEVICE_ID_REDHAT_SDHCI; 1264 k->class_id = PCI_CLASS_SYSTEM_SDHCI; 1265 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1266 dc->vmsd = &sdhci_vmstate; 1267 dc->props = sdhci_pci_properties; 1268 } 1269 1270 static const TypeInfo sdhci_pci_info = { 1271 .name = TYPE_PCI_SDHCI, 1272 .parent = TYPE_PCI_DEVICE, 1273 .instance_size = sizeof(SDHCIState), 1274 .class_init = sdhci_pci_class_init, 1275 }; 1276 1277 static Property sdhci_sysbus_properties[] = { 1278 DEFINE_PROP_UINT32("capareg", SDHCIState, capareg, 1279 SDHC_CAPAB_REG_DEFAULT), 1280 DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0), 1281 DEFINE_PROP_BOOL("noeject-quirk", SDHCIState, noeject_quirk, false), 1282 DEFINE_PROP_END_OF_LIST(), 1283 }; 1284 1285 static void sdhci_sysbus_init(Object *obj) 1286 { 1287 SDHCIState *s = SYSBUS_SDHCI(obj); 1288 DriveInfo *di; 1289 1290 /* FIXME use a qdev drive property instead of drive_get_next() */ 1291 di = drive_get_next(IF_SD); 1292 sdhci_initfn(s, di ? blk_by_legacy_dinfo(di) : NULL); 1293 } 1294 1295 static void sdhci_sysbus_finalize(Object *obj) 1296 { 1297 SDHCIState *s = SYSBUS_SDHCI(obj); 1298 sdhci_uninitfn(s); 1299 } 1300 1301 static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp) 1302 { 1303 SDHCIState *s = SYSBUS_SDHCI(dev); 1304 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1305 1306 s->buf_maxsz = sdhci_get_fifolen(s); 1307 s->fifo_buffer = g_malloc0(s->buf_maxsz); 1308 sysbus_init_irq(sbd, &s->irq); 1309 memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci", 1310 SDHC_REGISTERS_MAP_SIZE); 1311 sysbus_init_mmio(sbd, &s->iomem); 1312 } 1313 1314 static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) 1315 { 1316 DeviceClass *dc = DEVICE_CLASS(klass); 1317 1318 dc->vmsd = &sdhci_vmstate; 1319 dc->props = sdhci_sysbus_properties; 1320 dc->realize = sdhci_sysbus_realize; 1321 /* Reason: instance_init() method uses drive_get_next() */ 1322 dc->cannot_instantiate_with_device_add_yet = true; 1323 } 1324 1325 static const TypeInfo sdhci_sysbus_info = { 1326 .name = TYPE_SYSBUS_SDHCI, 1327 .parent = TYPE_SYS_BUS_DEVICE, 1328 .instance_size = sizeof(SDHCIState), 1329 .instance_init = sdhci_sysbus_init, 1330 .instance_finalize = sdhci_sysbus_finalize, 1331 .class_init = sdhci_sysbus_class_init, 1332 }; 1333 1334 static void sdhci_register_types(void) 1335 { 1336 type_register_static(&sdhci_pci_info); 1337 type_register_static(&sdhci_sysbus_info); 1338 } 1339 1340 type_init(sdhci_register_types) 1341