1 /* 2 * SD Association Host Standard Specification v2.0 controller emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Mitsyanko Igor <i.mitsyanko@samsung.com> 6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 7 * 8 * Based on MMC controller for Samsung S5PC1xx-based board emulation 9 * by Alexey Merkulov and Vladimir Monakhov. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 19 * See the GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qemu/error-report.h" 28 #include "qapi/error.h" 29 #include "hw/irq.h" 30 #include "hw/qdev-properties.h" 31 #include "sysemu/dma.h" 32 #include "qemu/timer.h" 33 #include "qemu/bitops.h" 34 #include "hw/sd/sdhci.h" 35 #include "migration/vmstate.h" 36 #include "sdhci-internal.h" 37 #include "qemu/log.h" 38 #include "qemu/module.h" 39 #include "trace.h" 40 #include "qom/object.h" 41 42 #define TYPE_SDHCI_BUS "sdhci-bus" 43 /* This is reusing the SDBus typedef from SD_BUS */ 44 DECLARE_INSTANCE_CHECKER(SDBus, SDHCI_BUS, 45 TYPE_SDHCI_BUS) 46 47 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) 48 49 static inline unsigned int sdhci_get_fifolen(SDHCIState *s) 50 { 51 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); 52 } 53 54 /* return true on error */ 55 static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, 56 uint8_t freq, Error **errp) 57 { 58 if (s->sd_spec_version >= 3) { 59 return false; 60 } 61 switch (freq) { 62 case 0: 63 case 10 ... 63: 64 break; 65 default: 66 error_setg(errp, "SD %s clock frequency can have value" 67 "in range 0-63 only", desc); 68 return true; 69 } 70 return false; 71 } 72 73 static void sdhci_check_capareg(SDHCIState *s, Error **errp) 74 { 75 uint64_t msk = s->capareg; 76 uint32_t val; 77 bool y; 78 79 switch (s->sd_spec_version) { 80 case 4: 81 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4); 82 trace_sdhci_capareg("64-bit system bus (v4)", val); 83 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0); 84 85 val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II); 86 trace_sdhci_capareg("UHS-II", val); 87 msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0); 88 89 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3); 90 trace_sdhci_capareg("ADMA3", val); 91 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0); 92 93 /* fallthrough */ 94 case 3: 95 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT); 96 trace_sdhci_capareg("async interrupt", val); 97 msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0); 98 99 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE); 100 if (val) { 101 error_setg(errp, "slot-type not supported"); 102 return; 103 } 104 trace_sdhci_capareg("slot type", val); 105 msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0); 106 107 if (val != 2) { 108 val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT); 109 trace_sdhci_capareg("8-bit bus", val); 110 } 111 msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0); 112 113 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED); 114 trace_sdhci_capareg("bus speed mask", val); 115 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0); 116 117 val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH); 118 trace_sdhci_capareg("driver strength mask", val); 119 msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0); 120 121 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING); 122 trace_sdhci_capareg("timer re-tuning", val); 123 msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0); 124 125 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING); 126 trace_sdhci_capareg("use SDR50 tuning", val); 127 msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0); 128 129 val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE); 130 trace_sdhci_capareg("re-tuning mode", val); 131 msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0); 132 133 val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT); 134 trace_sdhci_capareg("clock multiplier", val); 135 msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0); 136 137 /* fallthrough */ 138 case 2: /* default version */ 139 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2); 140 trace_sdhci_capareg("ADMA2", val); 141 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0); 142 143 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1); 144 trace_sdhci_capareg("ADMA1", val); 145 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0); 146 147 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT); 148 trace_sdhci_capareg("64-bit system bus (v3)", val); 149 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0); 150 151 /* fallthrough */ 152 case 1: 153 y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT); 154 msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0); 155 156 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ); 157 trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val); 158 if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) { 159 return; 160 } 161 msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0); 162 163 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ); 164 trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val); 165 if (sdhci_check_capab_freq_range(s, "base", val, errp)) { 166 return; 167 } 168 msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0); 169 170 val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH); 171 if (val >= 3) { 172 error_setg(errp, "block size can be 512, 1024 or 2048 only"); 173 return; 174 } 175 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s)); 176 msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0); 177 178 val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED); 179 trace_sdhci_capareg("high speed", val); 180 msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0); 181 182 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA); 183 trace_sdhci_capareg("SDMA", val); 184 msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0); 185 186 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME); 187 trace_sdhci_capareg("suspend/resume", val); 188 msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0); 189 190 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33); 191 trace_sdhci_capareg("3.3v", val); 192 msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0); 193 194 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30); 195 trace_sdhci_capareg("3.0v", val); 196 msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0); 197 198 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18); 199 trace_sdhci_capareg("1.8v", val); 200 msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0); 201 break; 202 203 default: 204 error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version); 205 } 206 if (msk) { 207 qemu_log_mask(LOG_UNIMP, 208 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk); 209 } 210 } 211 212 static uint8_t sdhci_slotint(SDHCIState *s) 213 { 214 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || 215 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || 216 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); 217 } 218 219 static inline void sdhci_update_irq(SDHCIState *s) 220 { 221 qemu_set_irq(s->irq, sdhci_slotint(s)); 222 } 223 224 static void sdhci_raise_insertion_irq(void *opaque) 225 { 226 SDHCIState *s = (SDHCIState *)opaque; 227 228 if (s->norintsts & SDHC_NIS_REMOVE) { 229 timer_mod(s->insert_timer, 230 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 231 } else { 232 s->prnsts = 0x1ff0000; 233 if (s->norintstsen & SDHC_NISEN_INSERT) { 234 s->norintsts |= SDHC_NIS_INSERT; 235 } 236 sdhci_update_irq(s); 237 } 238 } 239 240 static void sdhci_set_inserted(DeviceState *dev, bool level) 241 { 242 SDHCIState *s = (SDHCIState *)dev; 243 244 trace_sdhci_set_inserted(level ? "insert" : "eject"); 245 if ((s->norintsts & SDHC_NIS_REMOVE) && level) { 246 /* Give target some time to notice card ejection */ 247 timer_mod(s->insert_timer, 248 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 249 } else { 250 if (level) { 251 s->prnsts = 0x1ff0000; 252 if (s->norintstsen & SDHC_NISEN_INSERT) { 253 s->norintsts |= SDHC_NIS_INSERT; 254 } 255 } else { 256 s->prnsts = 0x1fa0000; 257 s->pwrcon &= ~SDHC_POWER_ON; 258 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; 259 if (s->norintstsen & SDHC_NISEN_REMOVE) { 260 s->norintsts |= SDHC_NIS_REMOVE; 261 } 262 } 263 sdhci_update_irq(s); 264 } 265 } 266 267 static void sdhci_set_readonly(DeviceState *dev, bool level) 268 { 269 SDHCIState *s = (SDHCIState *)dev; 270 271 if (level) { 272 s->prnsts &= ~SDHC_WRITE_PROTECT; 273 } else { 274 /* Write enabled */ 275 s->prnsts |= SDHC_WRITE_PROTECT; 276 } 277 } 278 279 static void sdhci_reset(SDHCIState *s) 280 { 281 DeviceState *dev = DEVICE(s); 282 283 timer_del(s->insert_timer); 284 timer_del(s->transfer_timer); 285 286 /* Set all registers to 0. Capabilities/Version registers are not cleared 287 * and assumed to always preserve their value, given to them during 288 * initialization */ 289 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); 290 291 /* Reset other state based on current card insertion/readonly status */ 292 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus)); 293 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus)); 294 295 s->data_count = 0; 296 s->stopped_state = sdhc_not_stopped; 297 s->pending_insert_state = false; 298 } 299 300 static void sdhci_poweron_reset(DeviceState *dev) 301 { 302 /* QOM (ie power-on) reset. This is identical to reset 303 * commanded via device register apart from handling of the 304 * 'pending insert on powerup' quirk. 305 */ 306 SDHCIState *s = (SDHCIState *)dev; 307 308 sdhci_reset(s); 309 310 if (s->pending_insert_quirk) { 311 s->pending_insert_state = true; 312 } 313 } 314 315 static void sdhci_data_transfer(void *opaque); 316 317 static void sdhci_send_command(SDHCIState *s) 318 { 319 SDRequest request; 320 uint8_t response[16]; 321 int rlen; 322 323 s->errintsts = 0; 324 s->acmd12errsts = 0; 325 request.cmd = s->cmdreg >> 8; 326 request.arg = s->argument; 327 328 trace_sdhci_send_command(request.cmd, request.arg); 329 rlen = sdbus_do_command(&s->sdbus, &request, response); 330 331 if (s->cmdreg & SDHC_CMD_RESPONSE) { 332 if (rlen == 4) { 333 s->rspreg[0] = ldl_be_p(response); 334 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; 335 trace_sdhci_response4(s->rspreg[0]); 336 } else if (rlen == 16) { 337 s->rspreg[0] = ldl_be_p(&response[11]); 338 s->rspreg[1] = ldl_be_p(&response[7]); 339 s->rspreg[2] = ldl_be_p(&response[3]); 340 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | 341 response[2]; 342 trace_sdhci_response16(s->rspreg[3], s->rspreg[2], 343 s->rspreg[1], s->rspreg[0]); 344 } else { 345 trace_sdhci_error("timeout waiting for command response"); 346 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { 347 s->errintsts |= SDHC_EIS_CMDTIMEOUT; 348 s->norintsts |= SDHC_NIS_ERR; 349 } 350 } 351 352 if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && 353 (s->norintstsen & SDHC_NISEN_TRSCMP) && 354 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { 355 s->norintsts |= SDHC_NIS_TRSCMP; 356 } 357 } 358 359 if (s->norintstsen & SDHC_NISEN_CMDCMP) { 360 s->norintsts |= SDHC_NIS_CMDCMP; 361 } 362 363 sdhci_update_irq(s); 364 365 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { 366 s->data_count = 0; 367 sdhci_data_transfer(s); 368 } 369 } 370 371 static void sdhci_end_transfer(SDHCIState *s) 372 { 373 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */ 374 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { 375 SDRequest request; 376 uint8_t response[16]; 377 378 request.cmd = 0x0C; 379 request.arg = 0; 380 trace_sdhci_end_transfer(request.cmd, request.arg); 381 sdbus_do_command(&s->sdbus, &request, response); 382 /* Auto CMD12 response goes to the upper Response register */ 383 s->rspreg[3] = ldl_be_p(response); 384 } 385 386 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | 387 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | 388 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); 389 390 if (s->norintstsen & SDHC_NISEN_TRSCMP) { 391 s->norintsts |= SDHC_NIS_TRSCMP; 392 } 393 394 sdhci_update_irq(s); 395 } 396 397 /* 398 * Programmed i/o data transfer 399 */ 400 #define BLOCK_SIZE_MASK (4 * KiB - 1) 401 402 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ 403 static void sdhci_read_block_from_card(SDHCIState *s) 404 { 405 const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK; 406 407 if ((s->trnmod & SDHC_TRNS_MULTI) && 408 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { 409 return; 410 } 411 412 if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 413 /* Device is not in tuning */ 414 sdbus_read_data(&s->sdbus, s->fifo_buffer, blk_size); 415 } 416 417 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 418 /* Device is in tuning */ 419 s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK; 420 s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK; 421 s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ | 422 SDHC_DATA_INHIBIT); 423 goto read_done; 424 } 425 426 /* New data now available for READ through Buffer Port Register */ 427 s->prnsts |= SDHC_DATA_AVAILABLE; 428 if (s->norintstsen & SDHC_NISEN_RBUFRDY) { 429 s->norintsts |= SDHC_NIS_RBUFRDY; 430 } 431 432 /* Clear DAT line active status if that was the last block */ 433 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 434 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { 435 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 436 } 437 438 /* If stop at block gap request was set and it's not the last block of 439 * data - generate Block Event interrupt */ 440 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && 441 s->blkcnt != 1) { 442 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 443 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 444 s->norintsts |= SDHC_EIS_BLKGAP; 445 } 446 } 447 448 read_done: 449 sdhci_update_irq(s); 450 } 451 452 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */ 453 static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) 454 { 455 uint32_t value = 0; 456 int i; 457 458 /* first check that a valid data exists in host controller input buffer */ 459 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { 460 trace_sdhci_error("read from empty buffer"); 461 return 0; 462 } 463 464 for (i = 0; i < size; i++) { 465 value |= s->fifo_buffer[s->data_count] << i * 8; 466 s->data_count++; 467 /* check if we've read all valid data (blksize bytes) from buffer */ 468 if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) { 469 trace_sdhci_read_dataport(s->data_count); 470 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ 471 s->data_count = 0; /* next buff read must start at position [0] */ 472 473 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 474 s->blkcnt--; 475 } 476 477 /* if that was the last block of data */ 478 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 479 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || 480 /* stop at gap request */ 481 (s->stopped_state == sdhc_gap_read && 482 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { 483 sdhci_end_transfer(s); 484 } else { /* if there are more data, read next block from card */ 485 sdhci_read_block_from_card(s); 486 } 487 break; 488 } 489 } 490 491 return value; 492 } 493 494 /* Write data from host controller FIFO to card */ 495 static void sdhci_write_block_to_card(SDHCIState *s) 496 { 497 if (s->prnsts & SDHC_SPACE_AVAILABLE) { 498 if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 499 s->norintsts |= SDHC_NIS_WBUFRDY; 500 } 501 sdhci_update_irq(s); 502 return; 503 } 504 505 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 506 if (s->blkcnt == 0) { 507 return; 508 } else { 509 s->blkcnt--; 510 } 511 } 512 513 sdbus_write_data(&s->sdbus, s->fifo_buffer, s->blksize & BLOCK_SIZE_MASK); 514 515 /* Next data can be written through BUFFER DATORT register */ 516 s->prnsts |= SDHC_SPACE_AVAILABLE; 517 518 /* Finish transfer if that was the last block of data */ 519 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 520 ((s->trnmod & SDHC_TRNS_MULTI) && 521 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { 522 sdhci_end_transfer(s); 523 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 524 s->norintsts |= SDHC_NIS_WBUFRDY; 525 } 526 527 /* Generate Block Gap Event if requested and if not the last block */ 528 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && 529 s->blkcnt > 0) { 530 s->prnsts &= ~SDHC_DOING_WRITE; 531 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 532 s->norintsts |= SDHC_EIS_BLKGAP; 533 } 534 sdhci_end_transfer(s); 535 } 536 537 sdhci_update_irq(s); 538 } 539 540 /* Write @size bytes of @value data to host controller @s Buffer Data Port 541 * register */ 542 static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) 543 { 544 unsigned i; 545 546 /* Check that there is free space left in a buffer */ 547 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { 548 trace_sdhci_error("Can't write to data buffer: buffer full"); 549 return; 550 } 551 552 for (i = 0; i < size; i++) { 553 s->fifo_buffer[s->data_count] = value & 0xFF; 554 s->data_count++; 555 value >>= 8; 556 if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) { 557 trace_sdhci_write_dataport(s->data_count); 558 s->data_count = 0; 559 s->prnsts &= ~SDHC_SPACE_AVAILABLE; 560 if (s->prnsts & SDHC_DOING_WRITE) { 561 sdhci_write_block_to_card(s); 562 } 563 } 564 } 565 } 566 567 /* 568 * Single DMA data transfer 569 */ 570 571 /* Multi block SDMA transfer */ 572 static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) 573 { 574 bool page_aligned = false; 575 unsigned int begin; 576 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 577 uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12); 578 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); 579 580 if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) { 581 qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n"); 582 return; 583 } 584 585 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for 586 * possible stop at page boundary if initial address is not page aligned, 587 * allow them to work properly */ 588 if ((s->sdmasysad % boundary_chk) == 0) { 589 page_aligned = true; 590 } 591 592 if (s->trnmod & SDHC_TRNS_READ) { 593 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 594 SDHC_DAT_LINE_ACTIVE; 595 while (s->blkcnt) { 596 if (s->data_count == 0) { 597 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size); 598 } 599 begin = s->data_count; 600 if (((boundary_count + begin) < block_size) && page_aligned) { 601 s->data_count = boundary_count + begin; 602 boundary_count = 0; 603 } else { 604 s->data_count = block_size; 605 boundary_count -= block_size - begin; 606 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 607 s->blkcnt--; 608 } 609 } 610 dma_memory_write(s->dma_as, s->sdmasysad, 611 &s->fifo_buffer[begin], s->data_count - begin); 612 s->sdmasysad += s->data_count - begin; 613 if (s->data_count == block_size) { 614 s->data_count = 0; 615 } 616 if (page_aligned && boundary_count == 0) { 617 break; 618 } 619 } 620 } else { 621 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT | 622 SDHC_DAT_LINE_ACTIVE; 623 while (s->blkcnt) { 624 begin = s->data_count; 625 if (((boundary_count + begin) < block_size) && page_aligned) { 626 s->data_count = boundary_count + begin; 627 boundary_count = 0; 628 } else { 629 s->data_count = block_size; 630 boundary_count -= block_size - begin; 631 } 632 dma_memory_read(s->dma_as, s->sdmasysad, 633 &s->fifo_buffer[begin], s->data_count - begin); 634 s->sdmasysad += s->data_count - begin; 635 if (s->data_count == block_size) { 636 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size); 637 s->data_count = 0; 638 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 639 s->blkcnt--; 640 } 641 } 642 if (page_aligned && boundary_count == 0) { 643 break; 644 } 645 } 646 } 647 648 if (s->blkcnt == 0) { 649 sdhci_end_transfer(s); 650 } else { 651 if (s->norintstsen & SDHC_NISEN_DMA) { 652 s->norintsts |= SDHC_NIS_DMA; 653 } 654 sdhci_update_irq(s); 655 } 656 } 657 658 /* single block SDMA transfer */ 659 static void sdhci_sdma_transfer_single_block(SDHCIState *s) 660 { 661 uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK; 662 663 if (s->trnmod & SDHC_TRNS_READ) { 664 sdbus_read_data(&s->sdbus, s->fifo_buffer, datacnt); 665 dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); 666 } else { 667 dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); 668 sdbus_write_data(&s->sdbus, s->fifo_buffer, datacnt); 669 } 670 s->blkcnt--; 671 672 sdhci_end_transfer(s); 673 } 674 675 typedef struct ADMADescr { 676 hwaddr addr; 677 uint16_t length; 678 uint8_t attr; 679 uint8_t incr; 680 } ADMADescr; 681 682 static void get_adma_description(SDHCIState *s, ADMADescr *dscr) 683 { 684 uint32_t adma1 = 0; 685 uint64_t adma2 = 0; 686 hwaddr entry_addr = (hwaddr)s->admasysaddr; 687 switch (SDHC_DMA_TYPE(s->hostctl1)) { 688 case SDHC_CTRL_ADMA2_32: 689 dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2)); 690 adma2 = le64_to_cpu(adma2); 691 /* The spec does not specify endianness of descriptor table. 692 * We currently assume that it is LE. 693 */ 694 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; 695 dscr->length = (uint16_t)extract64(adma2, 16, 16); 696 dscr->attr = (uint8_t)extract64(adma2, 0, 7); 697 dscr->incr = 8; 698 break; 699 case SDHC_CTRL_ADMA1_32: 700 dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(adma1)); 701 adma1 = le32_to_cpu(adma1); 702 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); 703 dscr->attr = (uint8_t)extract32(adma1, 0, 7); 704 dscr->incr = 4; 705 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { 706 dscr->length = (uint16_t)extract32(adma1, 12, 16); 707 } else { 708 dscr->length = 4 * KiB; 709 } 710 break; 711 case SDHC_CTRL_ADMA2_64: 712 dma_memory_read(s->dma_as, entry_addr, &dscr->attr, 1); 713 dma_memory_read(s->dma_as, entry_addr + 2, &dscr->length, 2); 714 dscr->length = le16_to_cpu(dscr->length); 715 dma_memory_read(s->dma_as, entry_addr + 4, &dscr->addr, 8); 716 dscr->addr = le64_to_cpu(dscr->addr); 717 dscr->attr &= (uint8_t) ~0xC0; 718 dscr->incr = 12; 719 break; 720 } 721 } 722 723 /* Advanced DMA data transfer */ 724 725 static void sdhci_do_adma(SDHCIState *s) 726 { 727 unsigned int begin, length; 728 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 729 ADMADescr dscr = {}; 730 int i; 731 732 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { 733 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; 734 735 get_adma_description(s, &dscr); 736 trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr); 737 738 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { 739 /* Indicate that error occurred in ST_FDS state */ 740 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; 741 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; 742 743 /* Generate ADMA error interrupt */ 744 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 745 s->errintsts |= SDHC_EIS_ADMAERR; 746 s->norintsts |= SDHC_NIS_ERR; 747 } 748 749 sdhci_update_irq(s); 750 return; 751 } 752 753 length = dscr.length ? dscr.length : 64 * KiB; 754 755 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { 756 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ 757 758 if (s->trnmod & SDHC_TRNS_READ) { 759 while (length) { 760 if (s->data_count == 0) { 761 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size); 762 } 763 begin = s->data_count; 764 if ((length + begin) < block_size) { 765 s->data_count = length + begin; 766 length = 0; 767 } else { 768 s->data_count = block_size; 769 length -= block_size - begin; 770 } 771 dma_memory_write(s->dma_as, dscr.addr, 772 &s->fifo_buffer[begin], 773 s->data_count - begin); 774 dscr.addr += s->data_count - begin; 775 if (s->data_count == block_size) { 776 s->data_count = 0; 777 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 778 s->blkcnt--; 779 if (s->blkcnt == 0) { 780 break; 781 } 782 } 783 } 784 } 785 } else { 786 while (length) { 787 begin = s->data_count; 788 if ((length + begin) < block_size) { 789 s->data_count = length + begin; 790 length = 0; 791 } else { 792 s->data_count = block_size; 793 length -= block_size - begin; 794 } 795 dma_memory_read(s->dma_as, dscr.addr, 796 &s->fifo_buffer[begin], 797 s->data_count - begin); 798 dscr.addr += s->data_count - begin; 799 if (s->data_count == block_size) { 800 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size); 801 s->data_count = 0; 802 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 803 s->blkcnt--; 804 if (s->blkcnt == 0) { 805 break; 806 } 807 } 808 } 809 } 810 } 811 s->admasysaddr += dscr.incr; 812 break; 813 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ 814 s->admasysaddr = dscr.addr; 815 trace_sdhci_adma("link", s->admasysaddr); 816 break; 817 default: 818 s->admasysaddr += dscr.incr; 819 break; 820 } 821 822 if (dscr.attr & SDHC_ADMA_ATTR_INT) { 823 trace_sdhci_adma("interrupt", s->admasysaddr); 824 if (s->norintstsen & SDHC_NISEN_DMA) { 825 s->norintsts |= SDHC_NIS_DMA; 826 } 827 828 sdhci_update_irq(s); 829 } 830 831 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ 832 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 833 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { 834 trace_sdhci_adma_transfer_completed(); 835 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && 836 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 837 s->blkcnt != 0)) { 838 trace_sdhci_error("SD/MMC host ADMA length mismatch"); 839 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | 840 SDHC_ADMAERR_STATE_ST_TFR; 841 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 842 trace_sdhci_error("Set ADMA error flag"); 843 s->errintsts |= SDHC_EIS_ADMAERR; 844 s->norintsts |= SDHC_NIS_ERR; 845 } 846 847 sdhci_update_irq(s); 848 } 849 sdhci_end_transfer(s); 850 return; 851 } 852 853 } 854 855 /* we have unfinished business - reschedule to continue ADMA */ 856 timer_mod(s->transfer_timer, 857 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY); 858 } 859 860 /* Perform data transfer according to controller configuration */ 861 862 static void sdhci_data_transfer(void *opaque) 863 { 864 SDHCIState *s = (SDHCIState *)opaque; 865 866 if (s->trnmod & SDHC_TRNS_DMA) { 867 switch (SDHC_DMA_TYPE(s->hostctl1)) { 868 case SDHC_CTRL_SDMA: 869 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { 870 sdhci_sdma_transfer_single_block(s); 871 } else { 872 sdhci_sdma_transfer_multi_blocks(s); 873 } 874 875 break; 876 case SDHC_CTRL_ADMA1_32: 877 if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) { 878 trace_sdhci_error("ADMA1 not supported"); 879 break; 880 } 881 882 sdhci_do_adma(s); 883 break; 884 case SDHC_CTRL_ADMA2_32: 885 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) { 886 trace_sdhci_error("ADMA2 not supported"); 887 break; 888 } 889 890 sdhci_do_adma(s); 891 break; 892 case SDHC_CTRL_ADMA2_64: 893 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) || 894 !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) { 895 trace_sdhci_error("64 bit ADMA not supported"); 896 break; 897 } 898 899 sdhci_do_adma(s); 900 break; 901 default: 902 trace_sdhci_error("Unsupported DMA type"); 903 break; 904 } 905 } else { 906 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) { 907 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 908 SDHC_DAT_LINE_ACTIVE; 909 sdhci_read_block_from_card(s); 910 } else { 911 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | 912 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; 913 sdhci_write_block_to_card(s); 914 } 915 } 916 } 917 918 static bool sdhci_can_issue_command(SDHCIState *s) 919 { 920 if (!SDHC_CLOCK_IS_ON(s->clkcon) || 921 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && 922 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || 923 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && 924 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { 925 return false; 926 } 927 928 return true; 929 } 930 931 /* The Buffer Data Port register must be accessed in sequential and 932 * continuous manner */ 933 static inline bool 934 sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) 935 { 936 if ((s->data_count & 0x3) != byte_num) { 937 trace_sdhci_error("Non-sequential access to Buffer Data Port register" 938 "is prohibited\n"); 939 return false; 940 } 941 return true; 942 } 943 944 static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) 945 { 946 SDHCIState *s = (SDHCIState *)opaque; 947 uint32_t ret = 0; 948 949 switch (offset & ~0x3) { 950 case SDHC_SYSAD: 951 ret = s->sdmasysad; 952 break; 953 case SDHC_BLKSIZE: 954 ret = s->blksize | (s->blkcnt << 16); 955 break; 956 case SDHC_ARGUMENT: 957 ret = s->argument; 958 break; 959 case SDHC_TRNMOD: 960 ret = s->trnmod | (s->cmdreg << 16); 961 break; 962 case SDHC_RSPREG0 ... SDHC_RSPREG3: 963 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; 964 break; 965 case SDHC_BDATA: 966 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 967 ret = sdhci_read_dataport(s, size); 968 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 969 return ret; 970 } 971 break; 972 case SDHC_PRNSTS: 973 ret = s->prnsts; 974 ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL, 975 sdbus_get_dat_lines(&s->sdbus)); 976 ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL, 977 sdbus_get_cmd_line(&s->sdbus)); 978 break; 979 case SDHC_HOSTCTL: 980 ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) | 981 (s->wakcon << 24); 982 break; 983 case SDHC_CLKCON: 984 ret = s->clkcon | (s->timeoutcon << 16); 985 break; 986 case SDHC_NORINTSTS: 987 ret = s->norintsts | (s->errintsts << 16); 988 break; 989 case SDHC_NORINTSTSEN: 990 ret = s->norintstsen | (s->errintstsen << 16); 991 break; 992 case SDHC_NORINTSIGEN: 993 ret = s->norintsigen | (s->errintsigen << 16); 994 break; 995 case SDHC_ACMD12ERRSTS: 996 ret = s->acmd12errsts | (s->hostctl2 << 16); 997 break; 998 case SDHC_CAPAB: 999 ret = (uint32_t)s->capareg; 1000 break; 1001 case SDHC_CAPAB + 4: 1002 ret = (uint32_t)(s->capareg >> 32); 1003 break; 1004 case SDHC_MAXCURR: 1005 ret = (uint32_t)s->maxcurr; 1006 break; 1007 case SDHC_MAXCURR + 4: 1008 ret = (uint32_t)(s->maxcurr >> 32); 1009 break; 1010 case SDHC_ADMAERR: 1011 ret = s->admaerr; 1012 break; 1013 case SDHC_ADMASYSADDR: 1014 ret = (uint32_t)s->admasysaddr; 1015 break; 1016 case SDHC_ADMASYSADDR + 4: 1017 ret = (uint32_t)(s->admasysaddr >> 32); 1018 break; 1019 case SDHC_SLOT_INT_STATUS: 1020 ret = (s->version << 16) | sdhci_slotint(s); 1021 break; 1022 default: 1023 qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " " 1024 "not implemented\n", size, offset); 1025 break; 1026 } 1027 1028 ret >>= (offset & 0x3) * 8; 1029 ret &= (1ULL << (size * 8)) - 1; 1030 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 1031 return ret; 1032 } 1033 1034 static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) 1035 { 1036 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { 1037 return; 1038 } 1039 s->blkgap = value & SDHC_STOP_AT_GAP_REQ; 1040 1041 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && 1042 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { 1043 if (s->stopped_state == sdhc_gap_read) { 1044 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; 1045 sdhci_read_block_from_card(s); 1046 } else { 1047 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; 1048 sdhci_write_block_to_card(s); 1049 } 1050 s->stopped_state = sdhc_not_stopped; 1051 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { 1052 if (s->prnsts & SDHC_DOING_READ) { 1053 s->stopped_state = sdhc_gap_read; 1054 } else if (s->prnsts & SDHC_DOING_WRITE) { 1055 s->stopped_state = sdhc_gap_write; 1056 } 1057 } 1058 } 1059 1060 static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) 1061 { 1062 switch (value) { 1063 case SDHC_RESET_ALL: 1064 sdhci_reset(s); 1065 break; 1066 case SDHC_RESET_CMD: 1067 s->prnsts &= ~SDHC_CMD_INHIBIT; 1068 s->norintsts &= ~SDHC_NIS_CMDCMP; 1069 break; 1070 case SDHC_RESET_DATA: 1071 s->data_count = 0; 1072 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | 1073 SDHC_DOING_READ | SDHC_DOING_WRITE | 1074 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); 1075 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); 1076 s->stopped_state = sdhc_not_stopped; 1077 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | 1078 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); 1079 break; 1080 } 1081 } 1082 1083 static void 1084 sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1085 { 1086 SDHCIState *s = (SDHCIState *)opaque; 1087 unsigned shift = 8 * (offset & 0x3); 1088 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); 1089 uint32_t value = val; 1090 value <<= shift; 1091 1092 switch (offset & ~0x3) { 1093 case SDHC_SYSAD: 1094 s->sdmasysad = (s->sdmasysad & mask) | value; 1095 MASKED_WRITE(s->sdmasysad, mask, value); 1096 /* Writing to last byte of sdmasysad might trigger transfer */ 1097 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && 1098 s->blksize && SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) { 1099 if (s->trnmod & SDHC_TRNS_MULTI) { 1100 sdhci_sdma_transfer_multi_blocks(s); 1101 } else { 1102 sdhci_sdma_transfer_single_block(s); 1103 } 1104 } 1105 break; 1106 case SDHC_BLKSIZE: 1107 if (!TRANSFERRING_DATA(s->prnsts)) { 1108 MASKED_WRITE(s->blksize, mask, value); 1109 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); 1110 } 1111 1112 /* Limit block size to the maximum buffer size */ 1113 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) { 1114 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " 1115 "the maximum buffer 0x%x", __func__, s->blksize, 1116 s->buf_maxsz); 1117 1118 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz); 1119 } 1120 1121 break; 1122 case SDHC_ARGUMENT: 1123 MASKED_WRITE(s->argument, mask, value); 1124 break; 1125 case SDHC_TRNMOD: 1126 /* DMA can be enabled only if it is supported as indicated by 1127 * capabilities register */ 1128 if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { 1129 value &= ~SDHC_TRNS_DMA; 1130 } 1131 MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK); 1132 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); 1133 1134 /* Writing to the upper byte of CMDREG triggers SD command generation */ 1135 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { 1136 break; 1137 } 1138 1139 sdhci_send_command(s); 1140 break; 1141 case SDHC_BDATA: 1142 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1143 sdhci_write_dataport(s, value >> shift, size); 1144 } 1145 break; 1146 case SDHC_HOSTCTL: 1147 if (!(mask & 0xFF0000)) { 1148 sdhci_blkgap_write(s, value >> 16); 1149 } 1150 MASKED_WRITE(s->hostctl1, mask, value); 1151 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); 1152 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); 1153 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || 1154 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { 1155 s->pwrcon &= ~SDHC_POWER_ON; 1156 } 1157 break; 1158 case SDHC_CLKCON: 1159 if (!(mask & 0xFF000000)) { 1160 sdhci_reset_write(s, value >> 24); 1161 } 1162 MASKED_WRITE(s->clkcon, mask, value); 1163 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); 1164 if (s->clkcon & SDHC_CLOCK_INT_EN) { 1165 s->clkcon |= SDHC_CLOCK_INT_STABLE; 1166 } else { 1167 s->clkcon &= ~SDHC_CLOCK_INT_STABLE; 1168 } 1169 break; 1170 case SDHC_NORINTSTS: 1171 if (s->norintstsen & SDHC_NISEN_CARDINT) { 1172 value &= ~SDHC_NIS_CARDINT; 1173 } 1174 s->norintsts &= mask | ~value; 1175 s->errintsts &= (mask >> 16) | ~(value >> 16); 1176 if (s->errintsts) { 1177 s->norintsts |= SDHC_NIS_ERR; 1178 } else { 1179 s->norintsts &= ~SDHC_NIS_ERR; 1180 } 1181 sdhci_update_irq(s); 1182 break; 1183 case SDHC_NORINTSTSEN: 1184 MASKED_WRITE(s->norintstsen, mask, value); 1185 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); 1186 s->norintsts &= s->norintstsen; 1187 s->errintsts &= s->errintstsen; 1188 if (s->errintsts) { 1189 s->norintsts |= SDHC_NIS_ERR; 1190 } else { 1191 s->norintsts &= ~SDHC_NIS_ERR; 1192 } 1193 /* Quirk for Raspberry Pi: pending card insert interrupt 1194 * appears when first enabled after power on */ 1195 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { 1196 assert(s->pending_insert_quirk); 1197 s->norintsts |= SDHC_NIS_INSERT; 1198 s->pending_insert_state = false; 1199 } 1200 sdhci_update_irq(s); 1201 break; 1202 case SDHC_NORINTSIGEN: 1203 MASKED_WRITE(s->norintsigen, mask, value); 1204 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); 1205 sdhci_update_irq(s); 1206 break; 1207 case SDHC_ADMAERR: 1208 MASKED_WRITE(s->admaerr, mask, value); 1209 break; 1210 case SDHC_ADMASYSADDR: 1211 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | 1212 (uint64_t)mask)) | (uint64_t)value; 1213 break; 1214 case SDHC_ADMASYSADDR + 4: 1215 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | 1216 ((uint64_t)mask << 32))) | ((uint64_t)value << 32); 1217 break; 1218 case SDHC_FEAER: 1219 s->acmd12errsts |= value; 1220 s->errintsts |= (value >> 16) & s->errintstsen; 1221 if (s->acmd12errsts) { 1222 s->errintsts |= SDHC_EIS_CMD12ERR; 1223 } 1224 if (s->errintsts) { 1225 s->norintsts |= SDHC_NIS_ERR; 1226 } 1227 sdhci_update_irq(s); 1228 break; 1229 case SDHC_ACMD12ERRSTS: 1230 MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX); 1231 if (s->uhs_mode >= UHS_I) { 1232 MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16); 1233 1234 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) { 1235 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V); 1236 } else { 1237 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V); 1238 } 1239 } 1240 break; 1241 1242 case SDHC_CAPAB: 1243 case SDHC_CAPAB + 4: 1244 case SDHC_MAXCURR: 1245 case SDHC_MAXCURR + 4: 1246 qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx 1247 " <- 0x%08x read-only\n", size, offset, value >> shift); 1248 break; 1249 1250 default: 1251 qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x " 1252 "not implemented\n", size, offset, value >> shift); 1253 break; 1254 } 1255 trace_sdhci_access("wr", size << 3, offset, "<-", 1256 value >> shift, value >> shift); 1257 } 1258 1259 static const MemoryRegionOps sdhci_mmio_ops = { 1260 .read = sdhci_read, 1261 .write = sdhci_write, 1262 .valid = { 1263 .min_access_size = 1, 1264 .max_access_size = 4, 1265 .unaligned = false 1266 }, 1267 .endianness = DEVICE_LITTLE_ENDIAN, 1268 }; 1269 1270 static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) 1271 { 1272 ERRP_GUARD(); 1273 1274 switch (s->sd_spec_version) { 1275 case 2 ... 3: 1276 break; 1277 default: 1278 error_setg(errp, "Only Spec v2/v3 are supported"); 1279 return; 1280 } 1281 s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1); 1282 1283 sdhci_check_capareg(s, errp); 1284 if (*errp) { 1285 return; 1286 } 1287 } 1288 1289 /* --- qdev common --- */ 1290 1291 void sdhci_initfn(SDHCIState *s) 1292 { 1293 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), 1294 TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); 1295 1296 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); 1297 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); 1298 1299 s->io_ops = &sdhci_mmio_ops; 1300 } 1301 1302 void sdhci_uninitfn(SDHCIState *s) 1303 { 1304 timer_del(s->insert_timer); 1305 timer_free(s->insert_timer); 1306 timer_del(s->transfer_timer); 1307 timer_free(s->transfer_timer); 1308 1309 g_free(s->fifo_buffer); 1310 s->fifo_buffer = NULL; 1311 } 1312 1313 void sdhci_common_realize(SDHCIState *s, Error **errp) 1314 { 1315 ERRP_GUARD(); 1316 1317 sdhci_init_readonly_registers(s, errp); 1318 if (*errp) { 1319 return; 1320 } 1321 s->buf_maxsz = sdhci_get_fifolen(s); 1322 s->fifo_buffer = g_malloc0(s->buf_maxsz); 1323 1324 memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci", 1325 SDHC_REGISTERS_MAP_SIZE); 1326 } 1327 1328 void sdhci_common_unrealize(SDHCIState *s) 1329 { 1330 /* This function is expected to be called only once for each class: 1331 * - SysBus: via DeviceClass->unrealize(), 1332 * - PCI: via PCIDeviceClass->exit(). 1333 * However to avoid double-free and/or use-after-free we still nullify 1334 * this variable (better safe than sorry!). */ 1335 g_free(s->fifo_buffer); 1336 s->fifo_buffer = NULL; 1337 } 1338 1339 static bool sdhci_pending_insert_vmstate_needed(void *opaque) 1340 { 1341 SDHCIState *s = opaque; 1342 1343 return s->pending_insert_state; 1344 } 1345 1346 static const VMStateDescription sdhci_pending_insert_vmstate = { 1347 .name = "sdhci/pending-insert", 1348 .version_id = 1, 1349 .minimum_version_id = 1, 1350 .needed = sdhci_pending_insert_vmstate_needed, 1351 .fields = (VMStateField[]) { 1352 VMSTATE_BOOL(pending_insert_state, SDHCIState), 1353 VMSTATE_END_OF_LIST() 1354 }, 1355 }; 1356 1357 const VMStateDescription sdhci_vmstate = { 1358 .name = "sdhci", 1359 .version_id = 1, 1360 .minimum_version_id = 1, 1361 .fields = (VMStateField[]) { 1362 VMSTATE_UINT32(sdmasysad, SDHCIState), 1363 VMSTATE_UINT16(blksize, SDHCIState), 1364 VMSTATE_UINT16(blkcnt, SDHCIState), 1365 VMSTATE_UINT32(argument, SDHCIState), 1366 VMSTATE_UINT16(trnmod, SDHCIState), 1367 VMSTATE_UINT16(cmdreg, SDHCIState), 1368 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), 1369 VMSTATE_UINT32(prnsts, SDHCIState), 1370 VMSTATE_UINT8(hostctl1, SDHCIState), 1371 VMSTATE_UINT8(pwrcon, SDHCIState), 1372 VMSTATE_UINT8(blkgap, SDHCIState), 1373 VMSTATE_UINT8(wakcon, SDHCIState), 1374 VMSTATE_UINT16(clkcon, SDHCIState), 1375 VMSTATE_UINT8(timeoutcon, SDHCIState), 1376 VMSTATE_UINT8(admaerr, SDHCIState), 1377 VMSTATE_UINT16(norintsts, SDHCIState), 1378 VMSTATE_UINT16(errintsts, SDHCIState), 1379 VMSTATE_UINT16(norintstsen, SDHCIState), 1380 VMSTATE_UINT16(errintstsen, SDHCIState), 1381 VMSTATE_UINT16(norintsigen, SDHCIState), 1382 VMSTATE_UINT16(errintsigen, SDHCIState), 1383 VMSTATE_UINT16(acmd12errsts, SDHCIState), 1384 VMSTATE_UINT16(data_count, SDHCIState), 1385 VMSTATE_UINT64(admasysaddr, SDHCIState), 1386 VMSTATE_UINT8(stopped_state, SDHCIState), 1387 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz), 1388 VMSTATE_TIMER_PTR(insert_timer, SDHCIState), 1389 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState), 1390 VMSTATE_END_OF_LIST() 1391 }, 1392 .subsections = (const VMStateDescription*[]) { 1393 &sdhci_pending_insert_vmstate, 1394 NULL 1395 }, 1396 }; 1397 1398 void sdhci_common_class_init(ObjectClass *klass, void *data) 1399 { 1400 DeviceClass *dc = DEVICE_CLASS(klass); 1401 1402 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1403 dc->vmsd = &sdhci_vmstate; 1404 dc->reset = sdhci_poweron_reset; 1405 } 1406 1407 /* --- qdev SysBus --- */ 1408 1409 static Property sdhci_sysbus_properties[] = { 1410 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), 1411 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, 1412 false), 1413 DEFINE_PROP_LINK("dma", SDHCIState, 1414 dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), 1415 DEFINE_PROP_END_OF_LIST(), 1416 }; 1417 1418 static void sdhci_sysbus_init(Object *obj) 1419 { 1420 SDHCIState *s = SYSBUS_SDHCI(obj); 1421 1422 sdhci_initfn(s); 1423 } 1424 1425 static void sdhci_sysbus_finalize(Object *obj) 1426 { 1427 SDHCIState *s = SYSBUS_SDHCI(obj); 1428 1429 if (s->dma_mr) { 1430 object_unparent(OBJECT(s->dma_mr)); 1431 } 1432 1433 sdhci_uninitfn(s); 1434 } 1435 1436 static void sdhci_sysbus_realize(DeviceState *dev, Error **errp) 1437 { 1438 ERRP_GUARD(); 1439 SDHCIState *s = SYSBUS_SDHCI(dev); 1440 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1441 1442 sdhci_common_realize(s, errp); 1443 if (*errp) { 1444 return; 1445 } 1446 1447 if (s->dma_mr) { 1448 s->dma_as = &s->sysbus_dma_as; 1449 address_space_init(s->dma_as, s->dma_mr, "sdhci-dma"); 1450 } else { 1451 /* use system_memory() if property "dma" not set */ 1452 s->dma_as = &address_space_memory; 1453 } 1454 1455 sysbus_init_irq(sbd, &s->irq); 1456 1457 sysbus_init_mmio(sbd, &s->iomem); 1458 } 1459 1460 static void sdhci_sysbus_unrealize(DeviceState *dev) 1461 { 1462 SDHCIState *s = SYSBUS_SDHCI(dev); 1463 1464 sdhci_common_unrealize(s); 1465 1466 if (s->dma_mr) { 1467 address_space_destroy(s->dma_as); 1468 } 1469 } 1470 1471 static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) 1472 { 1473 DeviceClass *dc = DEVICE_CLASS(klass); 1474 1475 device_class_set_props(dc, sdhci_sysbus_properties); 1476 dc->realize = sdhci_sysbus_realize; 1477 dc->unrealize = sdhci_sysbus_unrealize; 1478 1479 sdhci_common_class_init(klass, data); 1480 } 1481 1482 static const TypeInfo sdhci_sysbus_info = { 1483 .name = TYPE_SYSBUS_SDHCI, 1484 .parent = TYPE_SYS_BUS_DEVICE, 1485 .instance_size = sizeof(SDHCIState), 1486 .instance_init = sdhci_sysbus_init, 1487 .instance_finalize = sdhci_sysbus_finalize, 1488 .class_init = sdhci_sysbus_class_init, 1489 }; 1490 1491 /* --- qdev bus master --- */ 1492 1493 static void sdhci_bus_class_init(ObjectClass *klass, void *data) 1494 { 1495 SDBusClass *sbc = SD_BUS_CLASS(klass); 1496 1497 sbc->set_inserted = sdhci_set_inserted; 1498 sbc->set_readonly = sdhci_set_readonly; 1499 } 1500 1501 static const TypeInfo sdhci_bus_info = { 1502 .name = TYPE_SDHCI_BUS, 1503 .parent = TYPE_SD_BUS, 1504 .instance_size = sizeof(SDBus), 1505 .class_init = sdhci_bus_class_init, 1506 }; 1507 1508 /* --- qdev i.MX eSDHC --- */ 1509 1510 static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) 1511 { 1512 SDHCIState *s = SYSBUS_SDHCI(opaque); 1513 uint32_t ret; 1514 uint16_t hostctl1; 1515 1516 switch (offset) { 1517 default: 1518 return sdhci_read(opaque, offset, size); 1519 1520 case SDHC_HOSTCTL: 1521 /* 1522 * For a detailed explanation on the following bit 1523 * manipulation code see comments in a similar part of 1524 * usdhc_write() 1525 */ 1526 hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3); 1527 1528 if (s->hostctl1 & SDHC_CTRL_8BITBUS) { 1529 hostctl1 |= ESDHC_CTRL_8BITBUS; 1530 } 1531 1532 if (s->hostctl1 & SDHC_CTRL_4BITBUS) { 1533 hostctl1 |= ESDHC_CTRL_4BITBUS; 1534 } 1535 1536 ret = hostctl1; 1537 ret |= (uint32_t)s->blkgap << 16; 1538 ret |= (uint32_t)s->wakcon << 24; 1539 1540 break; 1541 1542 case SDHC_PRNSTS: 1543 /* Add SDSTB (SD Clock Stable) bit to PRNSTS */ 1544 ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB; 1545 if (s->clkcon & SDHC_CLOCK_INT_STABLE) { 1546 ret |= ESDHC_PRNSTS_SDSTB; 1547 } 1548 break; 1549 1550 case ESDHC_VENDOR_SPEC: 1551 ret = s->vendor_spec; 1552 break; 1553 case ESDHC_DLL_CTRL: 1554 case ESDHC_TUNE_CTRL_STATUS: 1555 case ESDHC_UNDOCUMENTED_REG27: 1556 case ESDHC_TUNING_CTRL: 1557 case ESDHC_MIX_CTRL: 1558 case ESDHC_WTMK_LVL: 1559 ret = 0; 1560 break; 1561 } 1562 1563 return ret; 1564 } 1565 1566 static void 1567 usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1568 { 1569 SDHCIState *s = SYSBUS_SDHCI(opaque); 1570 uint8_t hostctl1; 1571 uint32_t value = (uint32_t)val; 1572 1573 switch (offset) { 1574 case ESDHC_DLL_CTRL: 1575 case ESDHC_TUNE_CTRL_STATUS: 1576 case ESDHC_UNDOCUMENTED_REG27: 1577 case ESDHC_TUNING_CTRL: 1578 case ESDHC_WTMK_LVL: 1579 break; 1580 1581 case ESDHC_VENDOR_SPEC: 1582 s->vendor_spec = value; 1583 switch (s->vendor) { 1584 case SDHCI_VENDOR_IMX: 1585 if (value & ESDHC_IMX_FRC_SDCLK_ON) { 1586 s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF; 1587 } else { 1588 s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF; 1589 } 1590 break; 1591 default: 1592 break; 1593 } 1594 break; 1595 1596 case SDHC_HOSTCTL: 1597 /* 1598 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL) 1599 * 1600 * 7 6 5 4 3 2 1 0 1601 * |-----------+--------+--------+-----------+----------+---------| 1602 * | Card | Card | Endian | DATA3 | Data | Led | 1603 * | Detect | Detect | Mode | as Card | Transfer | Control | 1604 * | Signal | Test | | Detection | Width | | 1605 * | Selection | Level | | Pin | | | 1606 * |-----------+--------+--------+-----------+----------+---------| 1607 * 1608 * and 0x29 1609 * 1610 * 15 10 9 8 1611 * |----------+------| 1612 * | Reserved | DMA | 1613 * | | Sel. | 1614 * | | | 1615 * |----------+------| 1616 * 1617 * and here's what SDCHI spec expects those offsets to be: 1618 * 1619 * 0x28 (Host Control Register) 1620 * 1621 * 7 6 5 4 3 2 1 0 1622 * |--------+--------+----------+------+--------+----------+---------| 1623 * | Card | Card | Extended | DMA | High | Data | LED | 1624 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control | 1625 * | Signal | Test | Transfer | | Enable | Width | | 1626 * | Sel. | Level | Width | | | | | 1627 * |--------+--------+----------+------+--------+----------+---------| 1628 * 1629 * and 0x29 (Power Control Register) 1630 * 1631 * |----------------------------------| 1632 * | Power Control Register | 1633 * | | 1634 * | Description omitted, | 1635 * | since it has no analog in ESDHCI | 1636 * | | 1637 * |----------------------------------| 1638 * 1639 * Since offsets 0x2A and 0x2B should be compatible between 1640 * both IP specs we only need to reconcile least 16-bit of the 1641 * word we've been given. 1642 */ 1643 1644 /* 1645 * First, save bits 7 6 and 0 since they are identical 1646 */ 1647 hostctl1 = value & (SDHC_CTRL_LED | 1648 SDHC_CTRL_CDTEST_INS | 1649 SDHC_CTRL_CDTEST_EN); 1650 /* 1651 * Second, split "Data Transfer Width" from bits 2 and 1 in to 1652 * bits 5 and 1 1653 */ 1654 if (value & ESDHC_CTRL_8BITBUS) { 1655 hostctl1 |= SDHC_CTRL_8BITBUS; 1656 } 1657 1658 if (value & ESDHC_CTRL_4BITBUS) { 1659 hostctl1 |= ESDHC_CTRL_4BITBUS; 1660 } 1661 1662 /* 1663 * Third, move DMA select from bits 9 and 8 to bits 4 and 3 1664 */ 1665 hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3)); 1666 1667 /* 1668 * Now place the corrected value into low 16-bit of the value 1669 * we are going to give standard SDHCI write function 1670 * 1671 * NOTE: This transformation should be the inverse of what can 1672 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux 1673 * kernel 1674 */ 1675 value &= ~UINT16_MAX; 1676 value |= hostctl1; 1677 value |= (uint16_t)s->pwrcon << 8; 1678 1679 sdhci_write(opaque, offset, value, size); 1680 break; 1681 1682 case ESDHC_MIX_CTRL: 1683 /* 1684 * So, when SD/MMC stack in Linux tries to write to "Transfer 1685 * Mode Register", ESDHC i.MX quirk code will translate it 1686 * into a write to ESDHC_MIX_CTRL, so we do the opposite in 1687 * order to get where we started 1688 * 1689 * Note that Auto CMD23 Enable bit is located in a wrong place 1690 * on i.MX, but since it is not used by QEMU we do not care. 1691 * 1692 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...) 1693 * here becuase it will result in a call to 1694 * sdhci_send_command(s) which we don't want. 1695 * 1696 */ 1697 s->trnmod = value & UINT16_MAX; 1698 break; 1699 case SDHC_TRNMOD: 1700 /* 1701 * Similar to above, but this time a write to "Command 1702 * Register" will be translated into a 4-byte write to 1703 * "Transfer Mode register" where lower 16-bit of value would 1704 * be set to zero. So what we do is fill those bits with 1705 * cached value from s->trnmod and let the SDHCI 1706 * infrastructure handle the rest 1707 */ 1708 sdhci_write(opaque, offset, val | s->trnmod, size); 1709 break; 1710 case SDHC_BLKSIZE: 1711 /* 1712 * ESDHCI does not implement "Host SDMA Buffer Boundary", and 1713 * Linux driver will try to zero this field out which will 1714 * break the rest of SDHCI emulation. 1715 * 1716 * Linux defaults to maximum possible setting (512K boundary) 1717 * and it seems to be the only option that i.MX IP implements, 1718 * so we artificially set it to that value. 1719 */ 1720 val |= 0x7 << 12; 1721 /* FALLTHROUGH */ 1722 default: 1723 sdhci_write(opaque, offset, val, size); 1724 break; 1725 } 1726 } 1727 1728 static const MemoryRegionOps usdhc_mmio_ops = { 1729 .read = usdhc_read, 1730 .write = usdhc_write, 1731 .valid = { 1732 .min_access_size = 1, 1733 .max_access_size = 4, 1734 .unaligned = false 1735 }, 1736 .endianness = DEVICE_LITTLE_ENDIAN, 1737 }; 1738 1739 static void imx_usdhc_init(Object *obj) 1740 { 1741 SDHCIState *s = SYSBUS_SDHCI(obj); 1742 1743 s->io_ops = &usdhc_mmio_ops; 1744 s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; 1745 } 1746 1747 static const TypeInfo imx_usdhc_info = { 1748 .name = TYPE_IMX_USDHC, 1749 .parent = TYPE_SYSBUS_SDHCI, 1750 .instance_init = imx_usdhc_init, 1751 }; 1752 1753 /* --- qdev Samsung s3c --- */ 1754 1755 #define S3C_SDHCI_CONTROL2 0x80 1756 #define S3C_SDHCI_CONTROL3 0x84 1757 #define S3C_SDHCI_CONTROL4 0x8c 1758 1759 static uint64_t sdhci_s3c_read(void *opaque, hwaddr offset, unsigned size) 1760 { 1761 uint64_t ret; 1762 1763 switch (offset) { 1764 case S3C_SDHCI_CONTROL2: 1765 case S3C_SDHCI_CONTROL3: 1766 case S3C_SDHCI_CONTROL4: 1767 /* ignore */ 1768 ret = 0; 1769 break; 1770 default: 1771 ret = sdhci_read(opaque, offset, size); 1772 break; 1773 } 1774 1775 return ret; 1776 } 1777 1778 static void sdhci_s3c_write(void *opaque, hwaddr offset, uint64_t val, 1779 unsigned size) 1780 { 1781 switch (offset) { 1782 case S3C_SDHCI_CONTROL2: 1783 case S3C_SDHCI_CONTROL3: 1784 case S3C_SDHCI_CONTROL4: 1785 /* ignore */ 1786 break; 1787 default: 1788 sdhci_write(opaque, offset, val, size); 1789 break; 1790 } 1791 } 1792 1793 static const MemoryRegionOps sdhci_s3c_mmio_ops = { 1794 .read = sdhci_s3c_read, 1795 .write = sdhci_s3c_write, 1796 .valid = { 1797 .min_access_size = 1, 1798 .max_access_size = 4, 1799 .unaligned = false 1800 }, 1801 .endianness = DEVICE_LITTLE_ENDIAN, 1802 }; 1803 1804 static void sdhci_s3c_init(Object *obj) 1805 { 1806 SDHCIState *s = SYSBUS_SDHCI(obj); 1807 1808 s->io_ops = &sdhci_s3c_mmio_ops; 1809 } 1810 1811 static const TypeInfo sdhci_s3c_info = { 1812 .name = TYPE_S3C_SDHCI , 1813 .parent = TYPE_SYSBUS_SDHCI, 1814 .instance_init = sdhci_s3c_init, 1815 }; 1816 1817 static void sdhci_register_types(void) 1818 { 1819 type_register_static(&sdhci_sysbus_info); 1820 type_register_static(&sdhci_bus_info); 1821 type_register_static(&imx_usdhc_info); 1822 type_register_static(&sdhci_s3c_info); 1823 } 1824 1825 type_init(sdhci_register_types) 1826