1 /* 2 * SD Association Host Standard Specification v2.0 controller emulation 3 * 4 * Datasheet: PartA2_SD_Host_Controller_Simplified_Specification_Ver2.00.pdf 5 * 6 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 7 * Mitsyanko Igor <i.mitsyanko@samsung.com> 8 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 9 * 10 * Based on MMC controller for Samsung S5PC1xx-based board emulation 11 * by Alexey Merkulov and Vladimir Monakhov. 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 21 * See the GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, see <http://www.gnu.org/licenses/>. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/units.h" 29 #include "qemu/error-report.h" 30 #include "qapi/error.h" 31 #include "hw/irq.h" 32 #include "hw/qdev-properties.h" 33 #include "sysemu/dma.h" 34 #include "qemu/timer.h" 35 #include "qemu/bitops.h" 36 #include "hw/sd/sdhci.h" 37 #include "migration/vmstate.h" 38 #include "sdhci-internal.h" 39 #include "qemu/log.h" 40 #include "trace.h" 41 #include "qom/object.h" 42 43 #define TYPE_SDHCI_BUS "sdhci-bus" 44 /* This is reusing the SDBus typedef from SD_BUS */ 45 DECLARE_INSTANCE_CHECKER(SDBus, SDHCI_BUS, 46 TYPE_SDHCI_BUS) 47 48 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) 49 50 static inline unsigned int sdhci_get_fifolen(SDHCIState *s) 51 { 52 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); 53 } 54 55 /* return true on error */ 56 static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, 57 uint8_t freq, Error **errp) 58 { 59 if (s->sd_spec_version >= 3) { 60 return false; 61 } 62 switch (freq) { 63 case 0: 64 case 10 ... 63: 65 break; 66 default: 67 error_setg(errp, "SD %s clock frequency can have value" 68 "in range 0-63 only", desc); 69 return true; 70 } 71 return false; 72 } 73 74 static void sdhci_check_capareg(SDHCIState *s, Error **errp) 75 { 76 uint64_t msk = s->capareg; 77 uint32_t val; 78 bool y; 79 80 switch (s->sd_spec_version) { 81 case 4: 82 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4); 83 trace_sdhci_capareg("64-bit system bus (v4)", val); 84 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0); 85 86 val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II); 87 trace_sdhci_capareg("UHS-II", val); 88 msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0); 89 90 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3); 91 trace_sdhci_capareg("ADMA3", val); 92 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0); 93 94 /* fallthrough */ 95 case 3: 96 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT); 97 trace_sdhci_capareg("async interrupt", val); 98 msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0); 99 100 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE); 101 if (val) { 102 error_setg(errp, "slot-type not supported"); 103 return; 104 } 105 trace_sdhci_capareg("slot type", val); 106 msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0); 107 108 if (val != 2) { 109 val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT); 110 trace_sdhci_capareg("8-bit bus", val); 111 } 112 msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0); 113 114 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED); 115 trace_sdhci_capareg("bus speed mask", val); 116 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0); 117 118 val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH); 119 trace_sdhci_capareg("driver strength mask", val); 120 msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0); 121 122 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING); 123 trace_sdhci_capareg("timer re-tuning", val); 124 msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0); 125 126 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING); 127 trace_sdhci_capareg("use SDR50 tuning", val); 128 msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0); 129 130 val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE); 131 trace_sdhci_capareg("re-tuning mode", val); 132 msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0); 133 134 val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT); 135 trace_sdhci_capareg("clock multiplier", val); 136 msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0); 137 138 /* fallthrough */ 139 case 2: /* default version */ 140 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2); 141 trace_sdhci_capareg("ADMA2", val); 142 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0); 143 144 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1); 145 trace_sdhci_capareg("ADMA1", val); 146 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0); 147 148 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT); 149 trace_sdhci_capareg("64-bit system bus (v3)", val); 150 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0); 151 152 /* fallthrough */ 153 case 1: 154 y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT); 155 msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0); 156 157 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ); 158 trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val); 159 if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) { 160 return; 161 } 162 msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0); 163 164 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ); 165 trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val); 166 if (sdhci_check_capab_freq_range(s, "base", val, errp)) { 167 return; 168 } 169 msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0); 170 171 val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH); 172 if (val >= 3) { 173 error_setg(errp, "block size can be 512, 1024 or 2048 only"); 174 return; 175 } 176 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s)); 177 msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0); 178 179 val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED); 180 trace_sdhci_capareg("high speed", val); 181 msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0); 182 183 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA); 184 trace_sdhci_capareg("SDMA", val); 185 msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0); 186 187 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME); 188 trace_sdhci_capareg("suspend/resume", val); 189 msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0); 190 191 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33); 192 trace_sdhci_capareg("3.3v", val); 193 msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0); 194 195 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30); 196 trace_sdhci_capareg("3.0v", val); 197 msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0); 198 199 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18); 200 trace_sdhci_capareg("1.8v", val); 201 msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0); 202 break; 203 204 default: 205 error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version); 206 } 207 if (msk) { 208 qemu_log_mask(LOG_UNIMP, 209 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk); 210 } 211 } 212 213 static uint8_t sdhci_slotint(SDHCIState *s) 214 { 215 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || 216 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || 217 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); 218 } 219 220 /* Return true if IRQ was pending and delivered */ 221 static bool sdhci_update_irq(SDHCIState *s) 222 { 223 bool pending = sdhci_slotint(s); 224 225 qemu_set_irq(s->irq, pending); 226 227 return pending; 228 } 229 230 static void sdhci_raise_insertion_irq(void *opaque) 231 { 232 SDHCIState *s = (SDHCIState *)opaque; 233 234 if (s->norintsts & SDHC_NIS_REMOVE) { 235 timer_mod(s->insert_timer, 236 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 237 } else { 238 s->prnsts = 0x1ff0000; 239 if (s->norintstsen & SDHC_NISEN_INSERT) { 240 s->norintsts |= SDHC_NIS_INSERT; 241 } 242 sdhci_update_irq(s); 243 } 244 } 245 246 static void sdhci_set_inserted(DeviceState *dev, bool level) 247 { 248 SDHCIState *s = (SDHCIState *)dev; 249 250 trace_sdhci_set_inserted(level ? "insert" : "eject"); 251 if ((s->norintsts & SDHC_NIS_REMOVE) && level) { 252 /* Give target some time to notice card ejection */ 253 timer_mod(s->insert_timer, 254 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 255 } else { 256 if (level) { 257 s->prnsts = 0x1ff0000; 258 if (s->norintstsen & SDHC_NISEN_INSERT) { 259 s->norintsts |= SDHC_NIS_INSERT; 260 } 261 } else { 262 s->prnsts = 0x1fa0000; 263 s->pwrcon &= ~SDHC_POWER_ON; 264 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; 265 if (s->norintstsen & SDHC_NISEN_REMOVE) { 266 s->norintsts |= SDHC_NIS_REMOVE; 267 } 268 } 269 sdhci_update_irq(s); 270 } 271 } 272 273 static void sdhci_set_readonly(DeviceState *dev, bool level) 274 { 275 SDHCIState *s = (SDHCIState *)dev; 276 277 if (level) { 278 s->prnsts &= ~SDHC_WRITE_PROTECT; 279 } else { 280 /* Write enabled */ 281 s->prnsts |= SDHC_WRITE_PROTECT; 282 } 283 } 284 285 static void sdhci_reset(SDHCIState *s) 286 { 287 DeviceState *dev = DEVICE(s); 288 289 timer_del(s->insert_timer); 290 timer_del(s->transfer_timer); 291 292 /* 293 * Set all registers to 0. Capabilities/Version registers are not cleared 294 * and assumed to always preserve their value, given to them during 295 * initialization 296 */ 297 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); 298 299 /* Reset other state based on current card insertion/readonly status */ 300 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus)); 301 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus)); 302 303 s->data_count = 0; 304 s->stopped_state = sdhc_not_stopped; 305 s->pending_insert_state = false; 306 } 307 308 static void sdhci_poweron_reset(DeviceState *dev) 309 { 310 /* 311 * QOM (ie power-on) reset. This is identical to reset 312 * commanded via device register apart from handling of the 313 * 'pending insert on powerup' quirk. 314 */ 315 SDHCIState *s = (SDHCIState *)dev; 316 317 sdhci_reset(s); 318 319 if (s->pending_insert_quirk) { 320 s->pending_insert_state = true; 321 } 322 } 323 324 static void sdhci_data_transfer(void *opaque); 325 326 #define BLOCK_SIZE_MASK (4 * KiB - 1) 327 328 static void sdhci_send_command(SDHCIState *s) 329 { 330 SDRequest request; 331 uint8_t response[16]; 332 int rlen; 333 bool timeout = false; 334 335 s->errintsts = 0; 336 s->acmd12errsts = 0; 337 request.cmd = s->cmdreg >> 8; 338 request.arg = s->argument; 339 340 trace_sdhci_send_command(request.cmd, request.arg); 341 rlen = sdbus_do_command(&s->sdbus, &request, response); 342 343 if (s->cmdreg & SDHC_CMD_RESPONSE) { 344 if (rlen == 4) { 345 s->rspreg[0] = ldl_be_p(response); 346 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; 347 trace_sdhci_response4(s->rspreg[0]); 348 } else if (rlen == 16) { 349 s->rspreg[0] = ldl_be_p(&response[11]); 350 s->rspreg[1] = ldl_be_p(&response[7]); 351 s->rspreg[2] = ldl_be_p(&response[3]); 352 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | 353 response[2]; 354 trace_sdhci_response16(s->rspreg[3], s->rspreg[2], 355 s->rspreg[1], s->rspreg[0]); 356 } else { 357 timeout = true; 358 trace_sdhci_error("timeout waiting for command response"); 359 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { 360 s->errintsts |= SDHC_EIS_CMDTIMEOUT; 361 s->norintsts |= SDHC_NIS_ERR; 362 } 363 } 364 365 if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && 366 (s->norintstsen & SDHC_NISEN_TRSCMP) && 367 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { 368 s->norintsts |= SDHC_NIS_TRSCMP; 369 } 370 } 371 372 if (s->norintstsen & SDHC_NISEN_CMDCMP) { 373 s->norintsts |= SDHC_NIS_CMDCMP; 374 } 375 376 sdhci_update_irq(s); 377 378 if (!timeout && (s->blksize & BLOCK_SIZE_MASK) && 379 (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { 380 s->data_count = 0; 381 sdhci_data_transfer(s); 382 } 383 } 384 385 static void sdhci_end_transfer(SDHCIState *s) 386 { 387 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */ 388 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { 389 SDRequest request; 390 uint8_t response[16]; 391 392 request.cmd = 0x0C; 393 request.arg = 0; 394 trace_sdhci_end_transfer(request.cmd, request.arg); 395 sdbus_do_command(&s->sdbus, &request, response); 396 /* Auto CMD12 response goes to the upper Response register */ 397 s->rspreg[3] = ldl_be_p(response); 398 } 399 400 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | 401 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | 402 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); 403 404 if (s->norintstsen & SDHC_NISEN_TRSCMP) { 405 s->norintsts |= SDHC_NIS_TRSCMP; 406 } 407 408 sdhci_update_irq(s); 409 } 410 411 /* 412 * Programmed i/o data transfer 413 */ 414 415 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ 416 static void sdhci_read_block_from_card(SDHCIState *s) 417 { 418 const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK; 419 420 if ((s->trnmod & SDHC_TRNS_MULTI) && 421 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { 422 return; 423 } 424 425 if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 426 /* Device is not in tuning */ 427 sdbus_read_data(&s->sdbus, s->fifo_buffer, blk_size); 428 } 429 430 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 431 /* Device is in tuning */ 432 s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK; 433 s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK; 434 s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ | 435 SDHC_DATA_INHIBIT); 436 goto read_done; 437 } 438 439 /* New data now available for READ through Buffer Port Register */ 440 s->prnsts |= SDHC_DATA_AVAILABLE; 441 if (s->norintstsen & SDHC_NISEN_RBUFRDY) { 442 s->norintsts |= SDHC_NIS_RBUFRDY; 443 } 444 445 /* Clear DAT line active status if that was the last block */ 446 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 447 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { 448 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 449 } 450 451 /* 452 * If stop at block gap request was set and it's not the last block of 453 * data - generate Block Event interrupt 454 */ 455 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && 456 s->blkcnt != 1) { 457 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 458 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 459 s->norintsts |= SDHC_EIS_BLKGAP; 460 } 461 } 462 463 read_done: 464 sdhci_update_irq(s); 465 } 466 467 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */ 468 static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) 469 { 470 uint32_t value = 0; 471 int i; 472 473 /* first check that a valid data exists in host controller input buffer */ 474 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { 475 trace_sdhci_error("read from empty buffer"); 476 return 0; 477 } 478 479 for (i = 0; i < size; i++) { 480 assert(s->data_count < s->buf_maxsz); 481 value |= s->fifo_buffer[s->data_count] << i * 8; 482 s->data_count++; 483 /* check if we've read all valid data (blksize bytes) from buffer */ 484 if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) { 485 trace_sdhci_read_dataport(s->data_count); 486 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ 487 s->data_count = 0; /* next buff read must start at position [0] */ 488 489 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 490 s->blkcnt--; 491 } 492 493 /* if that was the last block of data */ 494 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 495 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || 496 /* stop at gap request */ 497 (s->stopped_state == sdhc_gap_read && 498 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { 499 sdhci_end_transfer(s); 500 } else { /* if there are more data, read next block from card */ 501 sdhci_read_block_from_card(s); 502 } 503 break; 504 } 505 } 506 507 return value; 508 } 509 510 /* Write data from host controller FIFO to card */ 511 static void sdhci_write_block_to_card(SDHCIState *s) 512 { 513 if (s->prnsts & SDHC_SPACE_AVAILABLE) { 514 if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 515 s->norintsts |= SDHC_NIS_WBUFRDY; 516 } 517 sdhci_update_irq(s); 518 return; 519 } 520 521 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 522 if (s->blkcnt == 0) { 523 return; 524 } else { 525 s->blkcnt--; 526 } 527 } 528 529 sdbus_write_data(&s->sdbus, s->fifo_buffer, s->blksize & BLOCK_SIZE_MASK); 530 531 /* Next data can be written through BUFFER DATORT register */ 532 s->prnsts |= SDHC_SPACE_AVAILABLE; 533 534 /* Finish transfer if that was the last block of data */ 535 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 536 ((s->trnmod & SDHC_TRNS_MULTI) && 537 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { 538 sdhci_end_transfer(s); 539 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 540 s->norintsts |= SDHC_NIS_WBUFRDY; 541 } 542 543 /* Generate Block Gap Event if requested and if not the last block */ 544 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && 545 s->blkcnt > 0) { 546 s->prnsts &= ~SDHC_DOING_WRITE; 547 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 548 s->norintsts |= SDHC_EIS_BLKGAP; 549 } 550 sdhci_end_transfer(s); 551 } 552 553 sdhci_update_irq(s); 554 } 555 556 /* 557 * Write @size bytes of @value data to host controller @s Buffer Data Port 558 * register 559 */ 560 static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) 561 { 562 unsigned i; 563 564 /* Check that there is free space left in a buffer */ 565 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { 566 trace_sdhci_error("Can't write to data buffer: buffer full"); 567 return; 568 } 569 570 for (i = 0; i < size; i++) { 571 assert(s->data_count < s->buf_maxsz); 572 s->fifo_buffer[s->data_count] = value & 0xFF; 573 s->data_count++; 574 value >>= 8; 575 if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) { 576 trace_sdhci_write_dataport(s->data_count); 577 s->data_count = 0; 578 s->prnsts &= ~SDHC_SPACE_AVAILABLE; 579 if (s->prnsts & SDHC_DOING_WRITE) { 580 sdhci_write_block_to_card(s); 581 } 582 } 583 } 584 } 585 586 /* 587 * Single DMA data transfer 588 */ 589 590 /* Multi block SDMA transfer */ 591 static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) 592 { 593 bool page_aligned = false; 594 unsigned int begin; 595 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 596 uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12); 597 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); 598 599 if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) { 600 qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n"); 601 return; 602 } 603 604 /* 605 * XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for 606 * possible stop at page boundary if initial address is not page aligned, 607 * allow them to work properly 608 */ 609 if ((s->sdmasysad % boundary_chk) == 0) { 610 page_aligned = true; 611 } 612 613 s->prnsts |= SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE; 614 if (s->trnmod & SDHC_TRNS_READ) { 615 s->prnsts |= SDHC_DOING_READ; 616 while (s->blkcnt) { 617 if (s->data_count == 0) { 618 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size); 619 } 620 begin = s->data_count; 621 if (((boundary_count + begin) < block_size) && page_aligned) { 622 s->data_count = boundary_count + begin; 623 boundary_count = 0; 624 } else { 625 s->data_count = block_size; 626 boundary_count -= block_size - begin; 627 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 628 s->blkcnt--; 629 } 630 } 631 dma_memory_write(s->dma_as, s->sdmasysad, &s->fifo_buffer[begin], 632 s->data_count - begin, MEMTXATTRS_UNSPECIFIED); 633 s->sdmasysad += s->data_count - begin; 634 if (s->data_count == block_size) { 635 s->data_count = 0; 636 } 637 if (page_aligned && boundary_count == 0) { 638 break; 639 } 640 } 641 } else { 642 s->prnsts |= SDHC_DOING_WRITE; 643 while (s->blkcnt) { 644 begin = s->data_count; 645 if (((boundary_count + begin) < block_size) && page_aligned) { 646 s->data_count = boundary_count + begin; 647 boundary_count = 0; 648 } else { 649 s->data_count = block_size; 650 boundary_count -= block_size - begin; 651 } 652 dma_memory_read(s->dma_as, s->sdmasysad, &s->fifo_buffer[begin], 653 s->data_count - begin, MEMTXATTRS_UNSPECIFIED); 654 s->sdmasysad += s->data_count - begin; 655 if (s->data_count == block_size) { 656 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size); 657 s->data_count = 0; 658 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 659 s->blkcnt--; 660 } 661 } 662 if (page_aligned && boundary_count == 0) { 663 break; 664 } 665 } 666 } 667 668 if (s->blkcnt == 0) { 669 sdhci_end_transfer(s); 670 } else { 671 if (s->norintstsen & SDHC_NISEN_DMA) { 672 s->norintsts |= SDHC_NIS_DMA; 673 } 674 sdhci_update_irq(s); 675 } 676 } 677 678 /* single block SDMA transfer */ 679 static void sdhci_sdma_transfer_single_block(SDHCIState *s) 680 { 681 uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK; 682 683 if (s->trnmod & SDHC_TRNS_READ) { 684 sdbus_read_data(&s->sdbus, s->fifo_buffer, datacnt); 685 dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt, 686 MEMTXATTRS_UNSPECIFIED); 687 } else { 688 dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt, 689 MEMTXATTRS_UNSPECIFIED); 690 sdbus_write_data(&s->sdbus, s->fifo_buffer, datacnt); 691 } 692 s->blkcnt--; 693 694 sdhci_end_transfer(s); 695 } 696 697 typedef struct ADMADescr { 698 hwaddr addr; 699 uint16_t length; 700 uint8_t attr; 701 uint8_t incr; 702 } ADMADescr; 703 704 static void get_adma_description(SDHCIState *s, ADMADescr *dscr) 705 { 706 uint32_t adma1 = 0; 707 uint64_t adma2 = 0; 708 hwaddr entry_addr = (hwaddr)s->admasysaddr; 709 switch (SDHC_DMA_TYPE(s->hostctl1)) { 710 case SDHC_CTRL_ADMA2_32: 711 dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2), 712 MEMTXATTRS_UNSPECIFIED); 713 adma2 = le64_to_cpu(adma2); 714 /* 715 * The spec does not specify endianness of descriptor table. 716 * We currently assume that it is LE. 717 */ 718 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; 719 dscr->length = (uint16_t)extract64(adma2, 16, 16); 720 dscr->attr = (uint8_t)extract64(adma2, 0, 7); 721 dscr->incr = 8; 722 break; 723 case SDHC_CTRL_ADMA1_32: 724 dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(adma1), 725 MEMTXATTRS_UNSPECIFIED); 726 adma1 = le32_to_cpu(adma1); 727 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); 728 dscr->attr = (uint8_t)extract32(adma1, 0, 7); 729 dscr->incr = 4; 730 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { 731 dscr->length = (uint16_t)extract32(adma1, 12, 16); 732 } else { 733 dscr->length = 4 * KiB; 734 } 735 break; 736 case SDHC_CTRL_ADMA2_64: 737 dma_memory_read(s->dma_as, entry_addr, &dscr->attr, 1, 738 MEMTXATTRS_UNSPECIFIED); 739 dma_memory_read(s->dma_as, entry_addr + 2, &dscr->length, 2, 740 MEMTXATTRS_UNSPECIFIED); 741 dscr->length = le16_to_cpu(dscr->length); 742 dma_memory_read(s->dma_as, entry_addr + 4, &dscr->addr, 8, 743 MEMTXATTRS_UNSPECIFIED); 744 dscr->addr = le64_to_cpu(dscr->addr); 745 dscr->attr &= (uint8_t) ~0xC0; 746 dscr->incr = 12; 747 break; 748 } 749 } 750 751 /* Advanced DMA data transfer */ 752 753 static void sdhci_do_adma(SDHCIState *s) 754 { 755 unsigned int begin, length; 756 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 757 const MemTxAttrs attrs = { .memory = true }; 758 ADMADescr dscr = {}; 759 MemTxResult res = MEMTX_ERROR; 760 int i; 761 762 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN && !s->blkcnt) { 763 /* Stop Multiple Transfer */ 764 sdhci_end_transfer(s); 765 return; 766 } 767 768 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { 769 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; 770 771 get_adma_description(s, &dscr); 772 trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr); 773 774 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { 775 /* Indicate that error occurred in ST_FDS state */ 776 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; 777 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; 778 779 /* Generate ADMA error interrupt */ 780 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 781 s->errintsts |= SDHC_EIS_ADMAERR; 782 s->norintsts |= SDHC_NIS_ERR; 783 } 784 785 sdhci_update_irq(s); 786 return; 787 } 788 789 length = dscr.length ? dscr.length : 64 * KiB; 790 791 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { 792 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ 793 s->prnsts |= SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE; 794 if (s->trnmod & SDHC_TRNS_READ) { 795 s->prnsts |= SDHC_DOING_READ; 796 while (length) { 797 if (s->data_count == 0) { 798 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size); 799 } 800 begin = s->data_count; 801 if ((length + begin) < block_size) { 802 s->data_count = length + begin; 803 length = 0; 804 } else { 805 s->data_count = block_size; 806 length -= block_size - begin; 807 } 808 res = dma_memory_write(s->dma_as, dscr.addr, 809 &s->fifo_buffer[begin], 810 s->data_count - begin, 811 attrs); 812 if (res != MEMTX_OK) { 813 break; 814 } 815 dscr.addr += s->data_count - begin; 816 if (s->data_count == block_size) { 817 s->data_count = 0; 818 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 819 s->blkcnt--; 820 if (s->blkcnt == 0) { 821 break; 822 } 823 } 824 } 825 } 826 } else { 827 s->prnsts |= SDHC_DOING_WRITE; 828 while (length) { 829 begin = s->data_count; 830 if ((length + begin) < block_size) { 831 s->data_count = length + begin; 832 length = 0; 833 } else { 834 s->data_count = block_size; 835 length -= block_size - begin; 836 } 837 res = dma_memory_read(s->dma_as, dscr.addr, 838 &s->fifo_buffer[begin], 839 s->data_count - begin, 840 attrs); 841 if (res != MEMTX_OK) { 842 break; 843 } 844 dscr.addr += s->data_count - begin; 845 if (s->data_count == block_size) { 846 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size); 847 s->data_count = 0; 848 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 849 s->blkcnt--; 850 if (s->blkcnt == 0) { 851 break; 852 } 853 } 854 } 855 } 856 } 857 if (res != MEMTX_OK) { 858 s->data_count = 0; 859 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 860 trace_sdhci_error("Set ADMA error flag"); 861 s->errintsts |= SDHC_EIS_ADMAERR; 862 s->norintsts |= SDHC_NIS_ERR; 863 } 864 sdhci_update_irq(s); 865 } else { 866 s->admasysaddr += dscr.incr; 867 } 868 break; 869 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ 870 s->admasysaddr = dscr.addr; 871 trace_sdhci_adma("link", s->admasysaddr); 872 break; 873 default: 874 s->admasysaddr += dscr.incr; 875 break; 876 } 877 878 if (dscr.attr & SDHC_ADMA_ATTR_INT) { 879 trace_sdhci_adma("interrupt", s->admasysaddr); 880 if (s->norintstsen & SDHC_NISEN_DMA) { 881 s->norintsts |= SDHC_NIS_DMA; 882 } 883 884 if (sdhci_update_irq(s) && !(dscr.attr & SDHC_ADMA_ATTR_END)) { 885 /* IRQ delivered, reschedule current transfer */ 886 break; 887 } 888 } 889 890 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ 891 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 892 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { 893 trace_sdhci_adma_transfer_completed(); 894 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && 895 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 896 s->blkcnt != 0)) { 897 trace_sdhci_error("SD/MMC host ADMA length mismatch"); 898 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | 899 SDHC_ADMAERR_STATE_ST_TFR; 900 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 901 trace_sdhci_error("Set ADMA error flag"); 902 s->errintsts |= SDHC_EIS_ADMAERR; 903 s->norintsts |= SDHC_NIS_ERR; 904 } 905 906 sdhci_update_irq(s); 907 } 908 sdhci_end_transfer(s); 909 return; 910 } 911 912 } 913 914 /* we have unfinished business - reschedule to continue ADMA */ 915 timer_mod(s->transfer_timer, 916 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY); 917 } 918 919 /* Perform data transfer according to controller configuration */ 920 921 static void sdhci_data_transfer(void *opaque) 922 { 923 SDHCIState *s = (SDHCIState *)opaque; 924 925 if (s->trnmod & SDHC_TRNS_DMA) { 926 switch (SDHC_DMA_TYPE(s->hostctl1)) { 927 case SDHC_CTRL_SDMA: 928 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { 929 sdhci_sdma_transfer_single_block(s); 930 } else { 931 sdhci_sdma_transfer_multi_blocks(s); 932 } 933 934 break; 935 case SDHC_CTRL_ADMA1_32: 936 if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) { 937 trace_sdhci_error("ADMA1 not supported"); 938 break; 939 } 940 941 sdhci_do_adma(s); 942 break; 943 case SDHC_CTRL_ADMA2_32: 944 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) { 945 trace_sdhci_error("ADMA2 not supported"); 946 break; 947 } 948 949 sdhci_do_adma(s); 950 break; 951 case SDHC_CTRL_ADMA2_64: 952 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) || 953 !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) { 954 trace_sdhci_error("64 bit ADMA not supported"); 955 break; 956 } 957 958 sdhci_do_adma(s); 959 break; 960 default: 961 trace_sdhci_error("Unsupported DMA type"); 962 break; 963 } 964 } else { 965 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) { 966 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 967 SDHC_DAT_LINE_ACTIVE; 968 sdhci_read_block_from_card(s); 969 } else { 970 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | 971 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; 972 sdhci_write_block_to_card(s); 973 } 974 } 975 } 976 977 static bool sdhci_can_issue_command(SDHCIState *s) 978 { 979 if (!SDHC_CLOCK_IS_ON(s->clkcon) || 980 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && 981 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || 982 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && 983 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { 984 return false; 985 } 986 987 return true; 988 } 989 990 /* 991 * The Buffer Data Port register must be accessed in sequential and 992 * continuous manner 993 */ 994 static inline bool 995 sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) 996 { 997 if ((s->data_count & 0x3) != byte_num) { 998 qemu_log_mask(LOG_GUEST_ERROR, 999 "SDHCI: Non-sequential access to Buffer Data Port" 1000 " register is prohibited\n"); 1001 return false; 1002 } 1003 return true; 1004 } 1005 1006 static void sdhci_resume_pending_transfer(SDHCIState *s) 1007 { 1008 timer_del(s->transfer_timer); 1009 sdhci_data_transfer(s); 1010 } 1011 1012 static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) 1013 { 1014 SDHCIState *s = (SDHCIState *)opaque; 1015 uint32_t ret = 0; 1016 1017 if (timer_pending(s->transfer_timer)) { 1018 sdhci_resume_pending_transfer(s); 1019 } 1020 1021 switch (offset & ~0x3) { 1022 case SDHC_SYSAD: 1023 ret = s->sdmasysad; 1024 break; 1025 case SDHC_BLKSIZE: 1026 ret = s->blksize | (s->blkcnt << 16); 1027 break; 1028 case SDHC_ARGUMENT: 1029 ret = s->argument; 1030 break; 1031 case SDHC_TRNMOD: 1032 ret = s->trnmod | (s->cmdreg << 16); 1033 break; 1034 case SDHC_RSPREG0 ... SDHC_RSPREG3: 1035 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; 1036 break; 1037 case SDHC_BDATA: 1038 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1039 ret = sdhci_read_dataport(s, size); 1040 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 1041 return ret; 1042 } 1043 break; 1044 case SDHC_PRNSTS: 1045 ret = s->prnsts; 1046 ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL, 1047 sdbus_get_dat_lines(&s->sdbus)); 1048 ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL, 1049 sdbus_get_cmd_line(&s->sdbus)); 1050 break; 1051 case SDHC_HOSTCTL: 1052 ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) | 1053 (s->wakcon << 24); 1054 break; 1055 case SDHC_CLKCON: 1056 ret = s->clkcon | (s->timeoutcon << 16); 1057 break; 1058 case SDHC_NORINTSTS: 1059 ret = s->norintsts | (s->errintsts << 16); 1060 break; 1061 case SDHC_NORINTSTSEN: 1062 ret = s->norintstsen | (s->errintstsen << 16); 1063 break; 1064 case SDHC_NORINTSIGEN: 1065 ret = s->norintsigen | (s->errintsigen << 16); 1066 break; 1067 case SDHC_ACMD12ERRSTS: 1068 ret = s->acmd12errsts | (s->hostctl2 << 16); 1069 break; 1070 case SDHC_CAPAB: 1071 ret = (uint32_t)s->capareg; 1072 break; 1073 case SDHC_CAPAB + 4: 1074 ret = (uint32_t)(s->capareg >> 32); 1075 break; 1076 case SDHC_MAXCURR: 1077 ret = (uint32_t)s->maxcurr; 1078 break; 1079 case SDHC_MAXCURR + 4: 1080 ret = (uint32_t)(s->maxcurr >> 32); 1081 break; 1082 case SDHC_ADMAERR: 1083 ret = s->admaerr; 1084 break; 1085 case SDHC_ADMASYSADDR: 1086 ret = (uint32_t)s->admasysaddr; 1087 break; 1088 case SDHC_ADMASYSADDR + 4: 1089 ret = (uint32_t)(s->admasysaddr >> 32); 1090 break; 1091 case SDHC_SLOT_INT_STATUS: 1092 ret = (s->version << 16) | sdhci_slotint(s); 1093 break; 1094 default: 1095 qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " " 1096 "not implemented\n", size, offset); 1097 break; 1098 } 1099 1100 ret >>= (offset & 0x3) * 8; 1101 ret &= (1ULL << (size * 8)) - 1; 1102 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 1103 return ret; 1104 } 1105 1106 static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) 1107 { 1108 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { 1109 return; 1110 } 1111 s->blkgap = value & SDHC_STOP_AT_GAP_REQ; 1112 1113 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && 1114 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { 1115 if (s->stopped_state == sdhc_gap_read) { 1116 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; 1117 sdhci_read_block_from_card(s); 1118 } else { 1119 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; 1120 sdhci_write_block_to_card(s); 1121 } 1122 s->stopped_state = sdhc_not_stopped; 1123 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { 1124 if (s->prnsts & SDHC_DOING_READ) { 1125 s->stopped_state = sdhc_gap_read; 1126 } else if (s->prnsts & SDHC_DOING_WRITE) { 1127 s->stopped_state = sdhc_gap_write; 1128 } 1129 } 1130 } 1131 1132 static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) 1133 { 1134 switch (value) { 1135 case SDHC_RESET_ALL: 1136 sdhci_reset(s); 1137 break; 1138 case SDHC_RESET_CMD: 1139 s->prnsts &= ~SDHC_CMD_INHIBIT; 1140 s->norintsts &= ~SDHC_NIS_CMDCMP; 1141 break; 1142 case SDHC_RESET_DATA: 1143 s->data_count = 0; 1144 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | 1145 SDHC_DOING_READ | SDHC_DOING_WRITE | 1146 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); 1147 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); 1148 s->stopped_state = sdhc_not_stopped; 1149 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | 1150 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); 1151 break; 1152 } 1153 } 1154 1155 static void 1156 sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1157 { 1158 SDHCIState *s = (SDHCIState *)opaque; 1159 unsigned shift = 8 * (offset & 0x3); 1160 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); 1161 uint32_t value = val; 1162 value <<= shift; 1163 1164 if (timer_pending(s->transfer_timer)) { 1165 sdhci_resume_pending_transfer(s); 1166 } 1167 1168 switch (offset & ~0x3) { 1169 case SDHC_SYSAD: 1170 if (!TRANSFERRING_DATA(s->prnsts)) { 1171 s->sdmasysad = (s->sdmasysad & mask) | value; 1172 MASKED_WRITE(s->sdmasysad, mask, value); 1173 /* Writing to last byte of sdmasysad might trigger transfer */ 1174 if (!(mask & 0xFF000000) && s->blkcnt && 1175 (s->blksize & BLOCK_SIZE_MASK) && 1176 SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) { 1177 if (s->trnmod & SDHC_TRNS_MULTI) { 1178 sdhci_sdma_transfer_multi_blocks(s); 1179 } else { 1180 sdhci_sdma_transfer_single_block(s); 1181 } 1182 } 1183 } 1184 break; 1185 case SDHC_BLKSIZE: 1186 if (!TRANSFERRING_DATA(s->prnsts)) { 1187 uint16_t blksize = s->blksize; 1188 1189 /* 1190 * [14:12] SDMA Buffer Boundary 1191 * [11:00] Transfer Block Size 1192 */ 1193 MASKED_WRITE(s->blksize, mask, extract32(value, 0, 15)); 1194 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); 1195 1196 /* Limit block size to the maximum buffer size */ 1197 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) { 1198 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " 1199 "the maximum buffer 0x%x\n", __func__, s->blksize, 1200 s->buf_maxsz); 1201 1202 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz); 1203 } 1204 1205 /* 1206 * If the block size is programmed to a different value from 1207 * the previous one, reset the data pointer of s->fifo_buffer[] 1208 * so that s->fifo_buffer[] can be filled in using the new block 1209 * size in the next transfer. 1210 */ 1211 if (blksize != s->blksize) { 1212 s->data_count = 0; 1213 } 1214 } 1215 1216 break; 1217 case SDHC_ARGUMENT: 1218 MASKED_WRITE(s->argument, mask, value); 1219 break; 1220 case SDHC_TRNMOD: 1221 /* 1222 * DMA can be enabled only if it is supported as indicated by 1223 * capabilities register 1224 */ 1225 if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { 1226 value &= ~SDHC_TRNS_DMA; 1227 } 1228 1229 /* TRNMOD writes are inhibited while Command Inhibit (DAT) is true */ 1230 if (s->prnsts & SDHC_DATA_INHIBIT) { 1231 mask |= 0xffff; 1232 } 1233 1234 MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK); 1235 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); 1236 1237 /* Writing to the upper byte of CMDREG triggers SD command generation */ 1238 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { 1239 break; 1240 } 1241 1242 sdhci_send_command(s); 1243 break; 1244 case SDHC_BDATA: 1245 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1246 sdhci_write_dataport(s, value >> shift, size); 1247 } 1248 break; 1249 case SDHC_HOSTCTL: 1250 if (!(mask & 0xFF0000)) { 1251 sdhci_blkgap_write(s, value >> 16); 1252 } 1253 MASKED_WRITE(s->hostctl1, mask, value); 1254 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); 1255 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); 1256 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || 1257 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { 1258 s->pwrcon &= ~SDHC_POWER_ON; 1259 } 1260 break; 1261 case SDHC_CLKCON: 1262 if (!(mask & 0xFF000000)) { 1263 sdhci_reset_write(s, value >> 24); 1264 } 1265 MASKED_WRITE(s->clkcon, mask, value); 1266 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); 1267 if (s->clkcon & SDHC_CLOCK_INT_EN) { 1268 s->clkcon |= SDHC_CLOCK_INT_STABLE; 1269 } else { 1270 s->clkcon &= ~SDHC_CLOCK_INT_STABLE; 1271 } 1272 break; 1273 case SDHC_NORINTSTS: 1274 if (s->norintstsen & SDHC_NISEN_CARDINT) { 1275 value &= ~SDHC_NIS_CARDINT; 1276 } 1277 s->norintsts &= mask | ~value; 1278 s->errintsts &= (mask >> 16) | ~(value >> 16); 1279 if (s->errintsts) { 1280 s->norintsts |= SDHC_NIS_ERR; 1281 } else { 1282 s->norintsts &= ~SDHC_NIS_ERR; 1283 } 1284 sdhci_update_irq(s); 1285 break; 1286 case SDHC_NORINTSTSEN: 1287 MASKED_WRITE(s->norintstsen, mask, value); 1288 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); 1289 s->norintsts &= s->norintstsen; 1290 s->errintsts &= s->errintstsen; 1291 if (s->errintsts) { 1292 s->norintsts |= SDHC_NIS_ERR; 1293 } else { 1294 s->norintsts &= ~SDHC_NIS_ERR; 1295 } 1296 /* 1297 * Quirk for Raspberry Pi: pending card insert interrupt 1298 * appears when first enabled after power on 1299 */ 1300 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { 1301 assert(s->pending_insert_quirk); 1302 s->norintsts |= SDHC_NIS_INSERT; 1303 s->pending_insert_state = false; 1304 } 1305 sdhci_update_irq(s); 1306 break; 1307 case SDHC_NORINTSIGEN: 1308 MASKED_WRITE(s->norintsigen, mask, value); 1309 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); 1310 sdhci_update_irq(s); 1311 break; 1312 case SDHC_ADMAERR: 1313 MASKED_WRITE(s->admaerr, mask, value); 1314 break; 1315 case SDHC_ADMASYSADDR: 1316 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | 1317 (uint64_t)mask)) | (uint64_t)value; 1318 break; 1319 case SDHC_ADMASYSADDR + 4: 1320 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | 1321 ((uint64_t)mask << 32))) | ((uint64_t)value << 32); 1322 break; 1323 case SDHC_FEAER: 1324 s->acmd12errsts |= value; 1325 s->errintsts |= (value >> 16) & s->errintstsen; 1326 if (s->acmd12errsts) { 1327 s->errintsts |= SDHC_EIS_CMD12ERR; 1328 } 1329 if (s->errintsts) { 1330 s->norintsts |= SDHC_NIS_ERR; 1331 } 1332 sdhci_update_irq(s); 1333 break; 1334 case SDHC_ACMD12ERRSTS: 1335 MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX); 1336 if (s->uhs_mode >= UHS_I) { 1337 MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16); 1338 1339 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) { 1340 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V); 1341 } else { 1342 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V); 1343 } 1344 } 1345 break; 1346 1347 case SDHC_CAPAB: 1348 case SDHC_CAPAB + 4: 1349 case SDHC_MAXCURR: 1350 case SDHC_MAXCURR + 4: 1351 qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx 1352 " <- 0x%08x read-only\n", size, offset, value >> shift); 1353 break; 1354 1355 default: 1356 qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x " 1357 "not implemented\n", size, offset, value >> shift); 1358 break; 1359 } 1360 trace_sdhci_access("wr", size << 3, offset, "<-", 1361 value >> shift, value >> shift); 1362 } 1363 1364 static const MemoryRegionOps sdhci_mmio_le_ops = { 1365 .read = sdhci_read, 1366 .write = sdhci_write, 1367 .valid = { 1368 .min_access_size = 1, 1369 .max_access_size = 4, 1370 .unaligned = false 1371 }, 1372 .endianness = DEVICE_LITTLE_ENDIAN, 1373 }; 1374 1375 static const MemoryRegionOps sdhci_mmio_be_ops = { 1376 .read = sdhci_read, 1377 .write = sdhci_write, 1378 .impl = { 1379 .min_access_size = 4, 1380 .max_access_size = 4, 1381 }, 1382 .valid = { 1383 .min_access_size = 1, 1384 .max_access_size = 4, 1385 .unaligned = false 1386 }, 1387 .endianness = DEVICE_BIG_ENDIAN, 1388 }; 1389 1390 static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) 1391 { 1392 ERRP_GUARD(); 1393 1394 switch (s->sd_spec_version) { 1395 case 2 ... 3: 1396 break; 1397 default: 1398 error_setg(errp, "Only Spec v2/v3 are supported"); 1399 return; 1400 } 1401 s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1); 1402 1403 sdhci_check_capareg(s, errp); 1404 if (*errp) { 1405 return; 1406 } 1407 } 1408 1409 /* --- qdev common --- */ 1410 1411 void sdhci_initfn(SDHCIState *s) 1412 { 1413 qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); 1414 1415 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1416 sdhci_raise_insertion_irq, s); 1417 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1418 sdhci_data_transfer, s); 1419 1420 s->io_ops = &sdhci_mmio_le_ops; 1421 } 1422 1423 void sdhci_uninitfn(SDHCIState *s) 1424 { 1425 timer_free(s->insert_timer); 1426 timer_free(s->transfer_timer); 1427 1428 g_free(s->fifo_buffer); 1429 s->fifo_buffer = NULL; 1430 } 1431 1432 void sdhci_common_realize(SDHCIState *s, Error **errp) 1433 { 1434 ERRP_GUARD(); 1435 1436 switch (s->endianness) { 1437 case DEVICE_LITTLE_ENDIAN: 1438 /* s->io_ops is little endian by default */ 1439 break; 1440 case DEVICE_BIG_ENDIAN: 1441 if (s->io_ops != &sdhci_mmio_le_ops) { 1442 error_setg(errp, "SD controller doesn't support big endianness"); 1443 return; 1444 } 1445 s->io_ops = &sdhci_mmio_be_ops; 1446 break; 1447 default: 1448 error_setg(errp, "Incorrect endianness"); 1449 return; 1450 } 1451 1452 sdhci_init_readonly_registers(s, errp); 1453 if (*errp) { 1454 return; 1455 } 1456 1457 s->buf_maxsz = sdhci_get_fifolen(s); 1458 s->fifo_buffer = g_malloc0(s->buf_maxsz); 1459 1460 memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci", 1461 SDHC_REGISTERS_MAP_SIZE); 1462 } 1463 1464 void sdhci_common_unrealize(SDHCIState *s) 1465 { 1466 /* 1467 * This function is expected to be called only once for each class: 1468 * - SysBus: via DeviceClass->unrealize(), 1469 * - PCI: via PCIDeviceClass->exit(). 1470 * However to avoid double-free and/or use-after-free we still nullify 1471 * this variable (better safe than sorry!). 1472 */ 1473 g_free(s->fifo_buffer); 1474 s->fifo_buffer = NULL; 1475 } 1476 1477 static bool sdhci_pending_insert_vmstate_needed(void *opaque) 1478 { 1479 SDHCIState *s = opaque; 1480 1481 return s->pending_insert_state; 1482 } 1483 1484 static const VMStateDescription sdhci_pending_insert_vmstate = { 1485 .name = "sdhci/pending-insert", 1486 .version_id = 1, 1487 .minimum_version_id = 1, 1488 .needed = sdhci_pending_insert_vmstate_needed, 1489 .fields = (const VMStateField[]) { 1490 VMSTATE_BOOL(pending_insert_state, SDHCIState), 1491 VMSTATE_END_OF_LIST() 1492 }, 1493 }; 1494 1495 const VMStateDescription sdhci_vmstate = { 1496 .name = "sdhci", 1497 .version_id = 1, 1498 .minimum_version_id = 1, 1499 .fields = (const VMStateField[]) { 1500 VMSTATE_UINT32(sdmasysad, SDHCIState), 1501 VMSTATE_UINT16(blksize, SDHCIState), 1502 VMSTATE_UINT16(blkcnt, SDHCIState), 1503 VMSTATE_UINT32(argument, SDHCIState), 1504 VMSTATE_UINT16(trnmod, SDHCIState), 1505 VMSTATE_UINT16(cmdreg, SDHCIState), 1506 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), 1507 VMSTATE_UINT32(prnsts, SDHCIState), 1508 VMSTATE_UINT8(hostctl1, SDHCIState), 1509 VMSTATE_UINT8(pwrcon, SDHCIState), 1510 VMSTATE_UINT8(blkgap, SDHCIState), 1511 VMSTATE_UINT8(wakcon, SDHCIState), 1512 VMSTATE_UINT16(clkcon, SDHCIState), 1513 VMSTATE_UINT8(timeoutcon, SDHCIState), 1514 VMSTATE_UINT8(admaerr, SDHCIState), 1515 VMSTATE_UINT16(norintsts, SDHCIState), 1516 VMSTATE_UINT16(errintsts, SDHCIState), 1517 VMSTATE_UINT16(norintstsen, SDHCIState), 1518 VMSTATE_UINT16(errintstsen, SDHCIState), 1519 VMSTATE_UINT16(norintsigen, SDHCIState), 1520 VMSTATE_UINT16(errintsigen, SDHCIState), 1521 VMSTATE_UINT16(acmd12errsts, SDHCIState), 1522 VMSTATE_UINT16(data_count, SDHCIState), 1523 VMSTATE_UINT64(admasysaddr, SDHCIState), 1524 VMSTATE_UINT8(stopped_state, SDHCIState), 1525 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz), 1526 VMSTATE_TIMER_PTR(insert_timer, SDHCIState), 1527 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState), 1528 VMSTATE_END_OF_LIST() 1529 }, 1530 .subsections = (const VMStateDescription * const []) { 1531 &sdhci_pending_insert_vmstate, 1532 NULL 1533 }, 1534 }; 1535 1536 void sdhci_common_class_init(ObjectClass *klass, void *data) 1537 { 1538 DeviceClass *dc = DEVICE_CLASS(klass); 1539 1540 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1541 dc->vmsd = &sdhci_vmstate; 1542 device_class_set_legacy_reset(dc, sdhci_poweron_reset); 1543 } 1544 1545 /* --- qdev SysBus --- */ 1546 1547 static Property sdhci_sysbus_properties[] = { 1548 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), 1549 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, 1550 false), 1551 DEFINE_PROP_LINK("dma", SDHCIState, 1552 dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), 1553 DEFINE_PROP_END_OF_LIST(), 1554 }; 1555 1556 static void sdhci_sysbus_init(Object *obj) 1557 { 1558 SDHCIState *s = SYSBUS_SDHCI(obj); 1559 1560 sdhci_initfn(s); 1561 } 1562 1563 static void sdhci_sysbus_finalize(Object *obj) 1564 { 1565 SDHCIState *s = SYSBUS_SDHCI(obj); 1566 1567 if (s->dma_mr) { 1568 object_unparent(OBJECT(s->dma_mr)); 1569 } 1570 1571 sdhci_uninitfn(s); 1572 } 1573 1574 static void sdhci_sysbus_realize(DeviceState *dev, Error **errp) 1575 { 1576 ERRP_GUARD(); 1577 SDHCIState *s = SYSBUS_SDHCI(dev); 1578 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1579 1580 sdhci_common_realize(s, errp); 1581 if (*errp) { 1582 return; 1583 } 1584 1585 if (s->dma_mr) { 1586 s->dma_as = &s->sysbus_dma_as; 1587 address_space_init(s->dma_as, s->dma_mr, "sdhci-dma"); 1588 } else { 1589 /* use system_memory() if property "dma" not set */ 1590 s->dma_as = &address_space_memory; 1591 } 1592 1593 sysbus_init_irq(sbd, &s->irq); 1594 1595 sysbus_init_mmio(sbd, &s->iomem); 1596 } 1597 1598 static void sdhci_sysbus_unrealize(DeviceState *dev) 1599 { 1600 SDHCIState *s = SYSBUS_SDHCI(dev); 1601 1602 sdhci_common_unrealize(s); 1603 1604 if (s->dma_mr) { 1605 address_space_destroy(s->dma_as); 1606 } 1607 } 1608 1609 static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) 1610 { 1611 DeviceClass *dc = DEVICE_CLASS(klass); 1612 1613 device_class_set_props(dc, sdhci_sysbus_properties); 1614 dc->realize = sdhci_sysbus_realize; 1615 dc->unrealize = sdhci_sysbus_unrealize; 1616 1617 sdhci_common_class_init(klass, data); 1618 } 1619 1620 /* --- qdev bus master --- */ 1621 1622 static void sdhci_bus_class_init(ObjectClass *klass, void *data) 1623 { 1624 SDBusClass *sbc = SD_BUS_CLASS(klass); 1625 1626 sbc->set_inserted = sdhci_set_inserted; 1627 sbc->set_readonly = sdhci_set_readonly; 1628 } 1629 1630 /* --- qdev i.MX eSDHC --- */ 1631 1632 #define USDHC_MIX_CTRL 0x48 1633 1634 #define USDHC_VENDOR_SPEC 0xc0 1635 #define USDHC_IMX_FRC_SDCLK_ON (1 << 8) 1636 1637 #define USDHC_DLL_CTRL 0x60 1638 1639 #define USDHC_TUNING_CTRL 0xcc 1640 #define USDHC_TUNE_CTRL_STATUS 0x68 1641 #define USDHC_WTMK_LVL 0x44 1642 1643 /* Undocumented register used by guests working around erratum ERR004536 */ 1644 #define USDHC_UNDOCUMENTED_REG27 0x6c 1645 1646 #define USDHC_CTRL_4BITBUS (0x1 << 1) 1647 #define USDHC_CTRL_8BITBUS (0x2 << 1) 1648 1649 #define USDHC_PRNSTS_SDSTB (1 << 3) 1650 1651 static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) 1652 { 1653 SDHCIState *s = SYSBUS_SDHCI(opaque); 1654 uint32_t ret; 1655 uint16_t hostctl1; 1656 1657 switch (offset) { 1658 default: 1659 return sdhci_read(opaque, offset, size); 1660 1661 case SDHC_HOSTCTL: 1662 /* 1663 * For a detailed explanation on the following bit 1664 * manipulation code see comments in a similar part of 1665 * usdhc_write() 1666 */ 1667 hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3); 1668 1669 if (s->hostctl1 & SDHC_CTRL_8BITBUS) { 1670 hostctl1 |= USDHC_CTRL_8BITBUS; 1671 } 1672 1673 if (s->hostctl1 & SDHC_CTRL_4BITBUS) { 1674 hostctl1 |= USDHC_CTRL_4BITBUS; 1675 } 1676 1677 ret = hostctl1; 1678 ret |= (uint32_t)s->blkgap << 16; 1679 ret |= (uint32_t)s->wakcon << 24; 1680 1681 break; 1682 1683 case SDHC_PRNSTS: 1684 /* Add SDSTB (SD Clock Stable) bit to PRNSTS */ 1685 ret = sdhci_read(opaque, offset, size) & ~USDHC_PRNSTS_SDSTB; 1686 if (s->clkcon & SDHC_CLOCK_INT_STABLE) { 1687 ret |= USDHC_PRNSTS_SDSTB; 1688 } 1689 break; 1690 1691 case USDHC_VENDOR_SPEC: 1692 ret = s->vendor_spec; 1693 break; 1694 case USDHC_DLL_CTRL: 1695 case USDHC_TUNE_CTRL_STATUS: 1696 case USDHC_UNDOCUMENTED_REG27: 1697 case USDHC_TUNING_CTRL: 1698 case USDHC_MIX_CTRL: 1699 case USDHC_WTMK_LVL: 1700 ret = 0; 1701 break; 1702 } 1703 1704 return ret; 1705 } 1706 1707 static void 1708 usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1709 { 1710 SDHCIState *s = SYSBUS_SDHCI(opaque); 1711 uint8_t hostctl1; 1712 uint32_t value = (uint32_t)val; 1713 1714 switch (offset) { 1715 case USDHC_DLL_CTRL: 1716 case USDHC_TUNE_CTRL_STATUS: 1717 case USDHC_UNDOCUMENTED_REG27: 1718 case USDHC_TUNING_CTRL: 1719 case USDHC_WTMK_LVL: 1720 break; 1721 1722 case USDHC_VENDOR_SPEC: 1723 s->vendor_spec = value; 1724 switch (s->vendor) { 1725 case SDHCI_VENDOR_IMX: 1726 if (value & USDHC_IMX_FRC_SDCLK_ON) { 1727 s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF; 1728 } else { 1729 s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF; 1730 } 1731 break; 1732 default: 1733 break; 1734 } 1735 break; 1736 1737 case SDHC_HOSTCTL: 1738 /* 1739 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL) 1740 * 1741 * 7 6 5 4 3 2 1 0 1742 * |-----------+--------+--------+-----------+----------+---------| 1743 * | Card | Card | Endian | DATA3 | Data | Led | 1744 * | Detect | Detect | Mode | as Card | Transfer | Control | 1745 * | Signal | Test | | Detection | Width | | 1746 * | Selection | Level | | Pin | | | 1747 * |-----------+--------+--------+-----------+----------+---------| 1748 * 1749 * and 0x29 1750 * 1751 * 15 10 9 8 1752 * |----------+------| 1753 * | Reserved | DMA | 1754 * | | Sel. | 1755 * | | | 1756 * |----------+------| 1757 * 1758 * and here's what SDCHI spec expects those offsets to be: 1759 * 1760 * 0x28 (Host Control Register) 1761 * 1762 * 7 6 5 4 3 2 1 0 1763 * |--------+--------+----------+------+--------+----------+---------| 1764 * | Card | Card | Extended | DMA | High | Data | LED | 1765 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control | 1766 * | Signal | Test | Transfer | | Enable | Width | | 1767 * | Sel. | Level | Width | | | | | 1768 * |--------+--------+----------+------+--------+----------+---------| 1769 * 1770 * and 0x29 (Power Control Register) 1771 * 1772 * |----------------------------------| 1773 * | Power Control Register | 1774 * | | 1775 * | Description omitted, | 1776 * | since it has no analog in ESDHCI | 1777 * | | 1778 * |----------------------------------| 1779 * 1780 * Since offsets 0x2A and 0x2B should be compatible between 1781 * both IP specs we only need to reconcile least 16-bit of the 1782 * word we've been given. 1783 */ 1784 1785 /* 1786 * First, save bits 7 6 and 0 since they are identical 1787 */ 1788 hostctl1 = value & (SDHC_CTRL_LED | 1789 SDHC_CTRL_CDTEST_INS | 1790 SDHC_CTRL_CDTEST_EN); 1791 /* 1792 * Second, split "Data Transfer Width" from bits 2 and 1 in to 1793 * bits 5 and 1 1794 */ 1795 if (value & USDHC_CTRL_8BITBUS) { 1796 hostctl1 |= SDHC_CTRL_8BITBUS; 1797 } 1798 1799 if (value & USDHC_CTRL_4BITBUS) { 1800 hostctl1 |= USDHC_CTRL_4BITBUS; 1801 } 1802 1803 /* 1804 * Third, move DMA select from bits 9 and 8 to bits 4 and 3 1805 */ 1806 hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3)); 1807 1808 /* 1809 * Now place the corrected value into low 16-bit of the value 1810 * we are going to give standard SDHCI write function 1811 * 1812 * NOTE: This transformation should be the inverse of what can 1813 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux 1814 * kernel 1815 */ 1816 value &= ~UINT16_MAX; 1817 value |= hostctl1; 1818 value |= (uint16_t)s->pwrcon << 8; 1819 1820 sdhci_write(opaque, offset, value, size); 1821 break; 1822 1823 case USDHC_MIX_CTRL: 1824 /* 1825 * So, when SD/MMC stack in Linux tries to write to "Transfer 1826 * Mode Register", ESDHC i.MX quirk code will translate it 1827 * into a write to ESDHC_MIX_CTRL, so we do the opposite in 1828 * order to get where we started 1829 * 1830 * Note that Auto CMD23 Enable bit is located in a wrong place 1831 * on i.MX, but since it is not used by QEMU we do not care. 1832 * 1833 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...) 1834 * here because it will result in a call to 1835 * sdhci_send_command(s) which we don't want. 1836 * 1837 */ 1838 s->trnmod = value & UINT16_MAX; 1839 break; 1840 case SDHC_TRNMOD: 1841 /* 1842 * Similar to above, but this time a write to "Command 1843 * Register" will be translated into a 4-byte write to 1844 * "Transfer Mode register" where lower 16-bit of value would 1845 * be set to zero. So what we do is fill those bits with 1846 * cached value from s->trnmod and let the SDHCI 1847 * infrastructure handle the rest 1848 */ 1849 sdhci_write(opaque, offset, val | s->trnmod, size); 1850 break; 1851 case SDHC_BLKSIZE: 1852 /* 1853 * ESDHCI does not implement "Host SDMA Buffer Boundary", and 1854 * Linux driver will try to zero this field out which will 1855 * break the rest of SDHCI emulation. 1856 * 1857 * Linux defaults to maximum possible setting (512K boundary) 1858 * and it seems to be the only option that i.MX IP implements, 1859 * so we artificially set it to that value. 1860 */ 1861 val |= 0x7 << 12; 1862 /* FALLTHROUGH */ 1863 default: 1864 sdhci_write(opaque, offset, val, size); 1865 break; 1866 } 1867 } 1868 1869 static const MemoryRegionOps usdhc_mmio_ops = { 1870 .read = usdhc_read, 1871 .write = usdhc_write, 1872 .valid = { 1873 .min_access_size = 1, 1874 .max_access_size = 4, 1875 .unaligned = false 1876 }, 1877 .endianness = DEVICE_LITTLE_ENDIAN, 1878 }; 1879 1880 static void imx_usdhc_init(Object *obj) 1881 { 1882 SDHCIState *s = SYSBUS_SDHCI(obj); 1883 1884 s->io_ops = &usdhc_mmio_ops; 1885 s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; 1886 } 1887 1888 /* --- qdev Samsung s3c --- */ 1889 1890 #define S3C_SDHCI_CONTROL2 0x80 1891 #define S3C_SDHCI_CONTROL3 0x84 1892 #define S3C_SDHCI_CONTROL4 0x8c 1893 1894 static uint64_t sdhci_s3c_read(void *opaque, hwaddr offset, unsigned size) 1895 { 1896 uint64_t ret; 1897 1898 switch (offset) { 1899 case S3C_SDHCI_CONTROL2: 1900 case S3C_SDHCI_CONTROL3: 1901 case S3C_SDHCI_CONTROL4: 1902 /* ignore */ 1903 ret = 0; 1904 break; 1905 default: 1906 ret = sdhci_read(opaque, offset, size); 1907 break; 1908 } 1909 1910 return ret; 1911 } 1912 1913 static void sdhci_s3c_write(void *opaque, hwaddr offset, uint64_t val, 1914 unsigned size) 1915 { 1916 switch (offset) { 1917 case S3C_SDHCI_CONTROL2: 1918 case S3C_SDHCI_CONTROL3: 1919 case S3C_SDHCI_CONTROL4: 1920 /* ignore */ 1921 break; 1922 default: 1923 sdhci_write(opaque, offset, val, size); 1924 break; 1925 } 1926 } 1927 1928 static const MemoryRegionOps sdhci_s3c_mmio_ops = { 1929 .read = sdhci_s3c_read, 1930 .write = sdhci_s3c_write, 1931 .valid = { 1932 .min_access_size = 1, 1933 .max_access_size = 4, 1934 .unaligned = false 1935 }, 1936 .endianness = DEVICE_LITTLE_ENDIAN, 1937 }; 1938 1939 static void sdhci_s3c_init(Object *obj) 1940 { 1941 SDHCIState *s = SYSBUS_SDHCI(obj); 1942 1943 s->io_ops = &sdhci_s3c_mmio_ops; 1944 } 1945 1946 static const TypeInfo sdhci_types[] = { 1947 { 1948 .name = TYPE_SDHCI_BUS, 1949 .parent = TYPE_SD_BUS, 1950 .instance_size = sizeof(SDBus), 1951 .class_init = sdhci_bus_class_init, 1952 }, 1953 { 1954 .name = TYPE_SYSBUS_SDHCI, 1955 .parent = TYPE_SYS_BUS_DEVICE, 1956 .instance_size = sizeof(SDHCIState), 1957 .instance_init = sdhci_sysbus_init, 1958 .instance_finalize = sdhci_sysbus_finalize, 1959 .class_init = sdhci_sysbus_class_init, 1960 }, 1961 { 1962 .name = TYPE_IMX_USDHC, 1963 .parent = TYPE_SYSBUS_SDHCI, 1964 .instance_init = imx_usdhc_init, 1965 }, 1966 { 1967 .name = TYPE_S3C_SDHCI, 1968 .parent = TYPE_SYSBUS_SDHCI, 1969 .instance_init = sdhci_s3c_init, 1970 }, 1971 }; 1972 1973 DEFINE_TYPES(sdhci_types) 1974