1 /* 2 * SD Association Host Standard Specification v2.0 controller emulation 3 * 4 * Datasheet: PartA2_SD_Host_Controller_Simplified_Specification_Ver2.00.pdf 5 * 6 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 7 * Mitsyanko Igor <i.mitsyanko@samsung.com> 8 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 9 * 10 * Based on MMC controller for Samsung S5PC1xx-based board emulation 11 * by Alexey Merkulov and Vladimir Monakhov. 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 21 * See the GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, see <http://www.gnu.org/licenses/>. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/units.h" 29 #include "qemu/error-report.h" 30 #include "qapi/error.h" 31 #include "hw/irq.h" 32 #include "hw/qdev-properties.h" 33 #include "sysemu/dma.h" 34 #include "qemu/timer.h" 35 #include "qemu/bitops.h" 36 #include "hw/sd/sdhci.h" 37 #include "migration/vmstate.h" 38 #include "sdhci-internal.h" 39 #include "qemu/log.h" 40 #include "trace.h" 41 #include "qom/object.h" 42 43 #define TYPE_SDHCI_BUS "sdhci-bus" 44 /* This is reusing the SDBus typedef from SD_BUS */ 45 DECLARE_INSTANCE_CHECKER(SDBus, SDHCI_BUS, 46 TYPE_SDHCI_BUS) 47 48 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) 49 50 static inline unsigned int sdhci_get_fifolen(SDHCIState *s) 51 { 52 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); 53 } 54 55 /* return true on error */ 56 static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, 57 uint8_t freq, Error **errp) 58 { 59 if (s->sd_spec_version >= 3) { 60 return false; 61 } 62 switch (freq) { 63 case 0: 64 case 10 ... 63: 65 break; 66 default: 67 error_setg(errp, "SD %s clock frequency can have value" 68 "in range 0-63 only", desc); 69 return true; 70 } 71 return false; 72 } 73 74 static void sdhci_check_capareg(SDHCIState *s, Error **errp) 75 { 76 uint64_t msk = s->capareg; 77 uint32_t val; 78 bool y; 79 80 switch (s->sd_spec_version) { 81 case 4: 82 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4); 83 trace_sdhci_capareg("64-bit system bus (v4)", val); 84 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0); 85 86 val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II); 87 trace_sdhci_capareg("UHS-II", val); 88 msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0); 89 90 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3); 91 trace_sdhci_capareg("ADMA3", val); 92 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0); 93 94 /* fallthrough */ 95 case 3: 96 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT); 97 trace_sdhci_capareg("async interrupt", val); 98 msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0); 99 100 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE); 101 if (val) { 102 error_setg(errp, "slot-type not supported"); 103 return; 104 } 105 trace_sdhci_capareg("slot type", val); 106 msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0); 107 108 if (val != 2) { 109 val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT); 110 trace_sdhci_capareg("8-bit bus", val); 111 } 112 msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0); 113 114 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED); 115 trace_sdhci_capareg("bus speed mask", val); 116 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0); 117 118 val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH); 119 trace_sdhci_capareg("driver strength mask", val); 120 msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0); 121 122 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING); 123 trace_sdhci_capareg("timer re-tuning", val); 124 msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0); 125 126 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING); 127 trace_sdhci_capareg("use SDR50 tuning", val); 128 msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0); 129 130 val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE); 131 trace_sdhci_capareg("re-tuning mode", val); 132 msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0); 133 134 val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT); 135 trace_sdhci_capareg("clock multiplier", val); 136 msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0); 137 138 /* fallthrough */ 139 case 2: /* default version */ 140 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2); 141 trace_sdhci_capareg("ADMA2", val); 142 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0); 143 144 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1); 145 trace_sdhci_capareg("ADMA1", val); 146 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0); 147 148 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT); 149 trace_sdhci_capareg("64-bit system bus (v3)", val); 150 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0); 151 152 /* fallthrough */ 153 case 1: 154 y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT); 155 msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0); 156 157 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ); 158 trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val); 159 if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) { 160 return; 161 } 162 msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0); 163 164 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ); 165 trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val); 166 if (sdhci_check_capab_freq_range(s, "base", val, errp)) { 167 return; 168 } 169 msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0); 170 171 val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH); 172 if (val >= 3) { 173 error_setg(errp, "block size can be 512, 1024 or 2048 only"); 174 return; 175 } 176 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s)); 177 msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0); 178 179 val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED); 180 trace_sdhci_capareg("high speed", val); 181 msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0); 182 183 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA); 184 trace_sdhci_capareg("SDMA", val); 185 msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0); 186 187 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME); 188 trace_sdhci_capareg("suspend/resume", val); 189 msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0); 190 191 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33); 192 trace_sdhci_capareg("3.3v", val); 193 msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0); 194 195 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30); 196 trace_sdhci_capareg("3.0v", val); 197 msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0); 198 199 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18); 200 trace_sdhci_capareg("1.8v", val); 201 msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0); 202 break; 203 204 default: 205 error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version); 206 } 207 if (msk) { 208 qemu_log_mask(LOG_UNIMP, 209 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk); 210 } 211 } 212 213 static uint8_t sdhci_slotint(SDHCIState *s) 214 { 215 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || 216 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || 217 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); 218 } 219 220 /* Return true if IRQ was pending and delivered */ 221 static bool sdhci_update_irq(SDHCIState *s) 222 { 223 bool pending = sdhci_slotint(s); 224 225 qemu_set_irq(s->irq, pending); 226 227 return pending; 228 } 229 230 static void sdhci_raise_insertion_irq(void *opaque) 231 { 232 SDHCIState *s = (SDHCIState *)opaque; 233 234 if (s->norintsts & SDHC_NIS_REMOVE) { 235 timer_mod(s->insert_timer, 236 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 237 } else { 238 s->prnsts = 0x1ff0000; 239 if (s->norintstsen & SDHC_NISEN_INSERT) { 240 s->norintsts |= SDHC_NIS_INSERT; 241 } 242 sdhci_update_irq(s); 243 } 244 } 245 246 static void sdhci_set_inserted(DeviceState *dev, bool level) 247 { 248 SDHCIState *s = (SDHCIState *)dev; 249 250 trace_sdhci_set_inserted(level ? "insert" : "eject"); 251 if ((s->norintsts & SDHC_NIS_REMOVE) && level) { 252 /* Give target some time to notice card ejection */ 253 timer_mod(s->insert_timer, 254 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 255 } else { 256 if (level) { 257 s->prnsts = 0x1ff0000; 258 if (s->norintstsen & SDHC_NISEN_INSERT) { 259 s->norintsts |= SDHC_NIS_INSERT; 260 } 261 } else { 262 s->prnsts = 0x1fa0000; 263 s->pwrcon &= ~SDHC_POWER_ON; 264 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; 265 if (s->norintstsen & SDHC_NISEN_REMOVE) { 266 s->norintsts |= SDHC_NIS_REMOVE; 267 } 268 } 269 sdhci_update_irq(s); 270 } 271 } 272 273 static void sdhci_set_readonly(DeviceState *dev, bool level) 274 { 275 SDHCIState *s = (SDHCIState *)dev; 276 277 if (s->wp_inverted) { 278 level = !level; 279 } 280 281 if (level) { 282 s->prnsts &= ~SDHC_WRITE_PROTECT; 283 } else { 284 /* Write enabled */ 285 s->prnsts |= SDHC_WRITE_PROTECT; 286 } 287 } 288 289 static void sdhci_reset(SDHCIState *s) 290 { 291 DeviceState *dev = DEVICE(s); 292 293 timer_del(s->insert_timer); 294 timer_del(s->transfer_timer); 295 296 /* 297 * Set all registers to 0. Capabilities/Version registers are not cleared 298 * and assumed to always preserve their value, given to them during 299 * initialization 300 */ 301 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); 302 303 /* Reset other state based on current card insertion/readonly status */ 304 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus)); 305 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus)); 306 307 s->data_count = 0; 308 s->stopped_state = sdhc_not_stopped; 309 s->pending_insert_state = false; 310 } 311 312 static void sdhci_poweron_reset(DeviceState *dev) 313 { 314 /* 315 * QOM (ie power-on) reset. This is identical to reset 316 * commanded via device register apart from handling of the 317 * 'pending insert on powerup' quirk. 318 */ 319 SDHCIState *s = (SDHCIState *)dev; 320 321 sdhci_reset(s); 322 323 if (s->pending_insert_quirk) { 324 s->pending_insert_state = true; 325 } 326 } 327 328 static void sdhci_data_transfer(void *opaque); 329 330 #define BLOCK_SIZE_MASK (4 * KiB - 1) 331 332 static void sdhci_send_command(SDHCIState *s) 333 { 334 SDRequest request; 335 uint8_t response[16]; 336 int rlen; 337 bool timeout = false; 338 339 s->errintsts = 0; 340 s->acmd12errsts = 0; 341 request.cmd = s->cmdreg >> 8; 342 request.arg = s->argument; 343 344 trace_sdhci_send_command(request.cmd, request.arg); 345 rlen = sdbus_do_command(&s->sdbus, &request, response); 346 347 if (s->cmdreg & SDHC_CMD_RESPONSE) { 348 if (rlen == 4) { 349 s->rspreg[0] = ldl_be_p(response); 350 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; 351 trace_sdhci_response4(s->rspreg[0]); 352 } else if (rlen == 16) { 353 s->rspreg[0] = ldl_be_p(&response[11]); 354 s->rspreg[1] = ldl_be_p(&response[7]); 355 s->rspreg[2] = ldl_be_p(&response[3]); 356 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | 357 response[2]; 358 trace_sdhci_response16(s->rspreg[3], s->rspreg[2], 359 s->rspreg[1], s->rspreg[0]); 360 } else { 361 timeout = true; 362 trace_sdhci_error("timeout waiting for command response"); 363 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { 364 s->errintsts |= SDHC_EIS_CMDTIMEOUT; 365 s->norintsts |= SDHC_NIS_ERR; 366 } 367 } 368 369 if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && 370 (s->norintstsen & SDHC_NISEN_TRSCMP) && 371 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { 372 s->norintsts |= SDHC_NIS_TRSCMP; 373 } 374 } 375 376 if (s->norintstsen & SDHC_NISEN_CMDCMP) { 377 s->norintsts |= SDHC_NIS_CMDCMP; 378 } 379 380 sdhci_update_irq(s); 381 382 if (!timeout && (s->blksize & BLOCK_SIZE_MASK) && 383 (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { 384 s->data_count = 0; 385 sdhci_data_transfer(s); 386 } 387 } 388 389 static void sdhci_end_transfer(SDHCIState *s) 390 { 391 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */ 392 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { 393 SDRequest request; 394 uint8_t response[16]; 395 396 request.cmd = 0x0C; 397 request.arg = 0; 398 trace_sdhci_end_transfer(request.cmd, request.arg); 399 sdbus_do_command(&s->sdbus, &request, response); 400 /* Auto CMD12 response goes to the upper Response register */ 401 s->rspreg[3] = ldl_be_p(response); 402 } 403 404 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | 405 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | 406 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); 407 408 if (s->norintstsen & SDHC_NISEN_TRSCMP) { 409 s->norintsts |= SDHC_NIS_TRSCMP; 410 } 411 412 sdhci_update_irq(s); 413 } 414 415 /* 416 * Programmed i/o data transfer 417 */ 418 419 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ 420 static void sdhci_read_block_from_card(SDHCIState *s) 421 { 422 const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK; 423 424 if ((s->trnmod & SDHC_TRNS_MULTI) && 425 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { 426 return; 427 } 428 429 if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 430 /* Device is not in tuning */ 431 sdbus_read_data(&s->sdbus, s->fifo_buffer, blk_size); 432 } 433 434 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 435 /* Device is in tuning */ 436 s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK; 437 s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK; 438 s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ | 439 SDHC_DATA_INHIBIT); 440 goto read_done; 441 } 442 443 /* New data now available for READ through Buffer Port Register */ 444 s->prnsts |= SDHC_DATA_AVAILABLE; 445 if (s->norintstsen & SDHC_NISEN_RBUFRDY) { 446 s->norintsts |= SDHC_NIS_RBUFRDY; 447 } 448 449 /* Clear DAT line active status if that was the last block */ 450 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 451 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { 452 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 453 } 454 455 /* 456 * If stop at block gap request was set and it's not the last block of 457 * data - generate Block Event interrupt 458 */ 459 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && 460 s->blkcnt != 1) { 461 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 462 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 463 s->norintsts |= SDHC_EIS_BLKGAP; 464 } 465 } 466 467 read_done: 468 sdhci_update_irq(s); 469 } 470 471 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */ 472 static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) 473 { 474 uint32_t value = 0; 475 int i; 476 477 /* first check that a valid data exists in host controller input buffer */ 478 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { 479 trace_sdhci_error("read from empty buffer"); 480 return 0; 481 } 482 483 for (i = 0; i < size; i++) { 484 assert(s->data_count < s->buf_maxsz); 485 value |= s->fifo_buffer[s->data_count] << i * 8; 486 s->data_count++; 487 /* check if we've read all valid data (blksize bytes) from buffer */ 488 if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) { 489 trace_sdhci_read_dataport(s->data_count); 490 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ 491 s->data_count = 0; /* next buff read must start at position [0] */ 492 493 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 494 s->blkcnt--; 495 } 496 497 /* if that was the last block of data */ 498 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 499 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || 500 /* stop at gap request */ 501 (s->stopped_state == sdhc_gap_read && 502 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { 503 sdhci_end_transfer(s); 504 } else { /* if there are more data, read next block from card */ 505 sdhci_read_block_from_card(s); 506 } 507 break; 508 } 509 } 510 511 return value; 512 } 513 514 /* Write data from host controller FIFO to card */ 515 static void sdhci_write_block_to_card(SDHCIState *s) 516 { 517 if (s->prnsts & SDHC_SPACE_AVAILABLE) { 518 if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 519 s->norintsts |= SDHC_NIS_WBUFRDY; 520 } 521 sdhci_update_irq(s); 522 return; 523 } 524 525 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 526 if (s->blkcnt == 0) { 527 return; 528 } else { 529 s->blkcnt--; 530 } 531 } 532 533 sdbus_write_data(&s->sdbus, s->fifo_buffer, s->blksize & BLOCK_SIZE_MASK); 534 535 /* Next data can be written through BUFFER DATORT register */ 536 s->prnsts |= SDHC_SPACE_AVAILABLE; 537 538 /* Finish transfer if that was the last block of data */ 539 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 540 ((s->trnmod & SDHC_TRNS_MULTI) && 541 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { 542 sdhci_end_transfer(s); 543 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 544 s->norintsts |= SDHC_NIS_WBUFRDY; 545 } 546 547 /* Generate Block Gap Event if requested and if not the last block */ 548 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && 549 s->blkcnt > 0) { 550 s->prnsts &= ~SDHC_DOING_WRITE; 551 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 552 s->norintsts |= SDHC_EIS_BLKGAP; 553 } 554 sdhci_end_transfer(s); 555 } 556 557 sdhci_update_irq(s); 558 } 559 560 /* 561 * Write @size bytes of @value data to host controller @s Buffer Data Port 562 * register 563 */ 564 static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) 565 { 566 unsigned i; 567 568 /* Check that there is free space left in a buffer */ 569 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { 570 trace_sdhci_error("Can't write to data buffer: buffer full"); 571 return; 572 } 573 574 for (i = 0; i < size; i++) { 575 assert(s->data_count < s->buf_maxsz); 576 s->fifo_buffer[s->data_count] = value & 0xFF; 577 s->data_count++; 578 value >>= 8; 579 if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) { 580 trace_sdhci_write_dataport(s->data_count); 581 s->data_count = 0; 582 s->prnsts &= ~SDHC_SPACE_AVAILABLE; 583 if (s->prnsts & SDHC_DOING_WRITE) { 584 sdhci_write_block_to_card(s); 585 } 586 } 587 } 588 } 589 590 /* 591 * Single DMA data transfer 592 */ 593 594 /* Multi block SDMA transfer */ 595 static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) 596 { 597 bool page_aligned = false; 598 unsigned int begin; 599 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 600 uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12); 601 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); 602 603 if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) { 604 qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n"); 605 return; 606 } 607 608 /* 609 * XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for 610 * possible stop at page boundary if initial address is not page aligned, 611 * allow them to work properly 612 */ 613 if ((s->sdmasysad % boundary_chk) == 0) { 614 page_aligned = true; 615 } 616 617 s->prnsts |= SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE; 618 if (s->trnmod & SDHC_TRNS_READ) { 619 s->prnsts |= SDHC_DOING_READ; 620 while (s->blkcnt) { 621 if (s->data_count == 0) { 622 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size); 623 } 624 begin = s->data_count; 625 if (((boundary_count + begin) < block_size) && page_aligned) { 626 s->data_count = boundary_count + begin; 627 boundary_count = 0; 628 } else { 629 s->data_count = block_size; 630 boundary_count -= block_size - begin; 631 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 632 s->blkcnt--; 633 } 634 } 635 dma_memory_write(s->dma_as, s->sdmasysad, &s->fifo_buffer[begin], 636 s->data_count - begin, MEMTXATTRS_UNSPECIFIED); 637 s->sdmasysad += s->data_count - begin; 638 if (s->data_count == block_size) { 639 s->data_count = 0; 640 } 641 if (page_aligned && boundary_count == 0) { 642 break; 643 } 644 } 645 } else { 646 s->prnsts |= SDHC_DOING_WRITE; 647 while (s->blkcnt) { 648 begin = s->data_count; 649 if (((boundary_count + begin) < block_size) && page_aligned) { 650 s->data_count = boundary_count + begin; 651 boundary_count = 0; 652 } else { 653 s->data_count = block_size; 654 boundary_count -= block_size - begin; 655 } 656 dma_memory_read(s->dma_as, s->sdmasysad, &s->fifo_buffer[begin], 657 s->data_count - begin, MEMTXATTRS_UNSPECIFIED); 658 s->sdmasysad += s->data_count - begin; 659 if (s->data_count == block_size) { 660 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size); 661 s->data_count = 0; 662 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 663 s->blkcnt--; 664 } 665 } 666 if (page_aligned && boundary_count == 0) { 667 break; 668 } 669 } 670 } 671 672 if (s->blkcnt == 0) { 673 sdhci_end_transfer(s); 674 } else { 675 if (s->norintstsen & SDHC_NISEN_DMA) { 676 s->norintsts |= SDHC_NIS_DMA; 677 } 678 sdhci_update_irq(s); 679 } 680 } 681 682 /* single block SDMA transfer */ 683 static void sdhci_sdma_transfer_single_block(SDHCIState *s) 684 { 685 uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK; 686 687 if (s->trnmod & SDHC_TRNS_READ) { 688 sdbus_read_data(&s->sdbus, s->fifo_buffer, datacnt); 689 dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt, 690 MEMTXATTRS_UNSPECIFIED); 691 } else { 692 dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt, 693 MEMTXATTRS_UNSPECIFIED); 694 sdbus_write_data(&s->sdbus, s->fifo_buffer, datacnt); 695 } 696 s->blkcnt--; 697 698 sdhci_end_transfer(s); 699 } 700 701 typedef struct ADMADescr { 702 hwaddr addr; 703 uint16_t length; 704 uint8_t attr; 705 uint8_t incr; 706 } ADMADescr; 707 708 static void get_adma_description(SDHCIState *s, ADMADescr *dscr) 709 { 710 uint32_t adma1 = 0; 711 uint64_t adma2 = 0; 712 hwaddr entry_addr = (hwaddr)s->admasysaddr; 713 switch (SDHC_DMA_TYPE(s->hostctl1)) { 714 case SDHC_CTRL_ADMA2_32: 715 dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2), 716 MEMTXATTRS_UNSPECIFIED); 717 adma2 = le64_to_cpu(adma2); 718 /* 719 * The spec does not specify endianness of descriptor table. 720 * We currently assume that it is LE. 721 */ 722 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; 723 dscr->length = (uint16_t)extract64(adma2, 16, 16); 724 dscr->attr = (uint8_t)extract64(adma2, 0, 7); 725 dscr->incr = 8; 726 break; 727 case SDHC_CTRL_ADMA1_32: 728 dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(adma1), 729 MEMTXATTRS_UNSPECIFIED); 730 adma1 = le32_to_cpu(adma1); 731 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); 732 dscr->attr = (uint8_t)extract32(adma1, 0, 7); 733 dscr->incr = 4; 734 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { 735 dscr->length = (uint16_t)extract32(adma1, 12, 16); 736 } else { 737 dscr->length = 4 * KiB; 738 } 739 break; 740 case SDHC_CTRL_ADMA2_64: 741 dma_memory_read(s->dma_as, entry_addr, &dscr->attr, 1, 742 MEMTXATTRS_UNSPECIFIED); 743 dma_memory_read(s->dma_as, entry_addr + 2, &dscr->length, 2, 744 MEMTXATTRS_UNSPECIFIED); 745 dscr->length = le16_to_cpu(dscr->length); 746 dma_memory_read(s->dma_as, entry_addr + 4, &dscr->addr, 8, 747 MEMTXATTRS_UNSPECIFIED); 748 dscr->addr = le64_to_cpu(dscr->addr); 749 dscr->attr &= (uint8_t) ~0xC0; 750 dscr->incr = 12; 751 break; 752 } 753 } 754 755 /* Advanced DMA data transfer */ 756 757 static void sdhci_do_adma(SDHCIState *s) 758 { 759 unsigned int begin, length; 760 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 761 const MemTxAttrs attrs = { .memory = true }; 762 ADMADescr dscr = {}; 763 MemTxResult res = MEMTX_ERROR; 764 int i; 765 766 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN && !s->blkcnt) { 767 /* Stop Multiple Transfer */ 768 sdhci_end_transfer(s); 769 return; 770 } 771 772 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { 773 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; 774 775 get_adma_description(s, &dscr); 776 trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr); 777 778 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { 779 /* Indicate that error occurred in ST_FDS state */ 780 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; 781 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; 782 783 /* Generate ADMA error interrupt */ 784 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 785 s->errintsts |= SDHC_EIS_ADMAERR; 786 s->norintsts |= SDHC_NIS_ERR; 787 } 788 789 sdhci_update_irq(s); 790 return; 791 } 792 793 length = dscr.length ? dscr.length : 64 * KiB; 794 795 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { 796 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ 797 s->prnsts |= SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE; 798 if (s->trnmod & SDHC_TRNS_READ) { 799 s->prnsts |= SDHC_DOING_READ; 800 while (length) { 801 if (s->data_count == 0) { 802 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size); 803 } 804 begin = s->data_count; 805 if ((length + begin) < block_size) { 806 s->data_count = length + begin; 807 length = 0; 808 } else { 809 s->data_count = block_size; 810 length -= block_size - begin; 811 } 812 res = dma_memory_write(s->dma_as, dscr.addr, 813 &s->fifo_buffer[begin], 814 s->data_count - begin, 815 attrs); 816 if (res != MEMTX_OK) { 817 break; 818 } 819 dscr.addr += s->data_count - begin; 820 if (s->data_count == block_size) { 821 s->data_count = 0; 822 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 823 s->blkcnt--; 824 if (s->blkcnt == 0) { 825 break; 826 } 827 } 828 } 829 } 830 } else { 831 s->prnsts |= SDHC_DOING_WRITE; 832 while (length) { 833 begin = s->data_count; 834 if ((length + begin) < block_size) { 835 s->data_count = length + begin; 836 length = 0; 837 } else { 838 s->data_count = block_size; 839 length -= block_size - begin; 840 } 841 res = dma_memory_read(s->dma_as, dscr.addr, 842 &s->fifo_buffer[begin], 843 s->data_count - begin, 844 attrs); 845 if (res != MEMTX_OK) { 846 break; 847 } 848 dscr.addr += s->data_count - begin; 849 if (s->data_count == block_size) { 850 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size); 851 s->data_count = 0; 852 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 853 s->blkcnt--; 854 if (s->blkcnt == 0) { 855 break; 856 } 857 } 858 } 859 } 860 } 861 if (res != MEMTX_OK) { 862 s->data_count = 0; 863 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 864 trace_sdhci_error("Set ADMA error flag"); 865 s->errintsts |= SDHC_EIS_ADMAERR; 866 s->norintsts |= SDHC_NIS_ERR; 867 } 868 sdhci_update_irq(s); 869 } else { 870 s->admasysaddr += dscr.incr; 871 } 872 break; 873 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ 874 s->admasysaddr = dscr.addr; 875 trace_sdhci_adma("link", s->admasysaddr); 876 break; 877 default: 878 s->admasysaddr += dscr.incr; 879 break; 880 } 881 882 if (dscr.attr & SDHC_ADMA_ATTR_INT) { 883 trace_sdhci_adma("interrupt", s->admasysaddr); 884 if (s->norintstsen & SDHC_NISEN_DMA) { 885 s->norintsts |= SDHC_NIS_DMA; 886 } 887 888 if (sdhci_update_irq(s) && !(dscr.attr & SDHC_ADMA_ATTR_END)) { 889 /* IRQ delivered, reschedule current transfer */ 890 break; 891 } 892 } 893 894 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ 895 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 896 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { 897 trace_sdhci_adma_transfer_completed(); 898 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && 899 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 900 s->blkcnt != 0)) { 901 trace_sdhci_error("SD/MMC host ADMA length mismatch"); 902 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | 903 SDHC_ADMAERR_STATE_ST_TFR; 904 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 905 trace_sdhci_error("Set ADMA error flag"); 906 s->errintsts |= SDHC_EIS_ADMAERR; 907 s->norintsts |= SDHC_NIS_ERR; 908 } 909 910 sdhci_update_irq(s); 911 } 912 sdhci_end_transfer(s); 913 return; 914 } 915 916 } 917 918 /* we have unfinished business - reschedule to continue ADMA */ 919 timer_mod(s->transfer_timer, 920 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY); 921 } 922 923 /* Perform data transfer according to controller configuration */ 924 925 static void sdhci_data_transfer(void *opaque) 926 { 927 SDHCIState *s = (SDHCIState *)opaque; 928 929 if (s->trnmod & SDHC_TRNS_DMA) { 930 switch (SDHC_DMA_TYPE(s->hostctl1)) { 931 case SDHC_CTRL_SDMA: 932 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { 933 sdhci_sdma_transfer_single_block(s); 934 } else { 935 sdhci_sdma_transfer_multi_blocks(s); 936 } 937 938 break; 939 case SDHC_CTRL_ADMA1_32: 940 if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) { 941 trace_sdhci_error("ADMA1 not supported"); 942 break; 943 } 944 945 sdhci_do_adma(s); 946 break; 947 case SDHC_CTRL_ADMA2_32: 948 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) { 949 trace_sdhci_error("ADMA2 not supported"); 950 break; 951 } 952 953 sdhci_do_adma(s); 954 break; 955 case SDHC_CTRL_ADMA2_64: 956 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) || 957 !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) { 958 trace_sdhci_error("64 bit ADMA not supported"); 959 break; 960 } 961 962 sdhci_do_adma(s); 963 break; 964 default: 965 trace_sdhci_error("Unsupported DMA type"); 966 break; 967 } 968 } else { 969 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) { 970 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 971 SDHC_DAT_LINE_ACTIVE; 972 sdhci_read_block_from_card(s); 973 } else { 974 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | 975 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; 976 sdhci_write_block_to_card(s); 977 } 978 } 979 } 980 981 static bool sdhci_can_issue_command(SDHCIState *s) 982 { 983 if (!SDHC_CLOCK_IS_ON(s->clkcon) || 984 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && 985 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || 986 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && 987 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { 988 return false; 989 } 990 991 return true; 992 } 993 994 /* 995 * The Buffer Data Port register must be accessed in sequential and 996 * continuous manner 997 */ 998 static inline bool 999 sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) 1000 { 1001 if ((s->data_count & 0x3) != byte_num) { 1002 qemu_log_mask(LOG_GUEST_ERROR, 1003 "SDHCI: Non-sequential access to Buffer Data Port" 1004 " register is prohibited\n"); 1005 return false; 1006 } 1007 return true; 1008 } 1009 1010 static void sdhci_resume_pending_transfer(SDHCIState *s) 1011 { 1012 timer_del(s->transfer_timer); 1013 sdhci_data_transfer(s); 1014 } 1015 1016 static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) 1017 { 1018 SDHCIState *s = (SDHCIState *)opaque; 1019 uint32_t ret = 0; 1020 1021 if (timer_pending(s->transfer_timer)) { 1022 sdhci_resume_pending_transfer(s); 1023 } 1024 1025 switch (offset & ~0x3) { 1026 case SDHC_SYSAD: 1027 ret = s->sdmasysad; 1028 break; 1029 case SDHC_BLKSIZE: 1030 ret = s->blksize | (s->blkcnt << 16); 1031 break; 1032 case SDHC_ARGUMENT: 1033 ret = s->argument; 1034 break; 1035 case SDHC_TRNMOD: 1036 ret = s->trnmod | (s->cmdreg << 16); 1037 break; 1038 case SDHC_RSPREG0 ... SDHC_RSPREG3: 1039 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; 1040 break; 1041 case SDHC_BDATA: 1042 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1043 ret = sdhci_read_dataport(s, size); 1044 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 1045 return ret; 1046 } 1047 break; 1048 case SDHC_PRNSTS: 1049 ret = s->prnsts; 1050 ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL, 1051 sdbus_get_dat_lines(&s->sdbus)); 1052 ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL, 1053 sdbus_get_cmd_line(&s->sdbus)); 1054 break; 1055 case SDHC_HOSTCTL: 1056 ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) | 1057 (s->wakcon << 24); 1058 break; 1059 case SDHC_CLKCON: 1060 ret = s->clkcon | (s->timeoutcon << 16); 1061 break; 1062 case SDHC_NORINTSTS: 1063 ret = s->norintsts | (s->errintsts << 16); 1064 break; 1065 case SDHC_NORINTSTSEN: 1066 ret = s->norintstsen | (s->errintstsen << 16); 1067 break; 1068 case SDHC_NORINTSIGEN: 1069 ret = s->norintsigen | (s->errintsigen << 16); 1070 break; 1071 case SDHC_ACMD12ERRSTS: 1072 ret = s->acmd12errsts | (s->hostctl2 << 16); 1073 break; 1074 case SDHC_CAPAB: 1075 ret = (uint32_t)s->capareg; 1076 break; 1077 case SDHC_CAPAB + 4: 1078 ret = (uint32_t)(s->capareg >> 32); 1079 break; 1080 case SDHC_MAXCURR: 1081 ret = (uint32_t)s->maxcurr; 1082 break; 1083 case SDHC_MAXCURR + 4: 1084 ret = (uint32_t)(s->maxcurr >> 32); 1085 break; 1086 case SDHC_ADMAERR: 1087 ret = s->admaerr; 1088 break; 1089 case SDHC_ADMASYSADDR: 1090 ret = (uint32_t)s->admasysaddr; 1091 break; 1092 case SDHC_ADMASYSADDR + 4: 1093 ret = (uint32_t)(s->admasysaddr >> 32); 1094 break; 1095 case SDHC_SLOT_INT_STATUS: 1096 ret = (s->version << 16) | sdhci_slotint(s); 1097 break; 1098 default: 1099 qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " " 1100 "not implemented\n", size, offset); 1101 break; 1102 } 1103 1104 ret >>= (offset & 0x3) * 8; 1105 ret &= (1ULL << (size * 8)) - 1; 1106 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 1107 return ret; 1108 } 1109 1110 static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) 1111 { 1112 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { 1113 return; 1114 } 1115 s->blkgap = value & SDHC_STOP_AT_GAP_REQ; 1116 1117 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && 1118 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { 1119 if (s->stopped_state == sdhc_gap_read) { 1120 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; 1121 sdhci_read_block_from_card(s); 1122 } else { 1123 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; 1124 sdhci_write_block_to_card(s); 1125 } 1126 s->stopped_state = sdhc_not_stopped; 1127 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { 1128 if (s->prnsts & SDHC_DOING_READ) { 1129 s->stopped_state = sdhc_gap_read; 1130 } else if (s->prnsts & SDHC_DOING_WRITE) { 1131 s->stopped_state = sdhc_gap_write; 1132 } 1133 } 1134 } 1135 1136 static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) 1137 { 1138 switch (value) { 1139 case SDHC_RESET_ALL: 1140 sdhci_reset(s); 1141 break; 1142 case SDHC_RESET_CMD: 1143 s->prnsts &= ~SDHC_CMD_INHIBIT; 1144 s->norintsts &= ~SDHC_NIS_CMDCMP; 1145 break; 1146 case SDHC_RESET_DATA: 1147 s->data_count = 0; 1148 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | 1149 SDHC_DOING_READ | SDHC_DOING_WRITE | 1150 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); 1151 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); 1152 s->stopped_state = sdhc_not_stopped; 1153 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | 1154 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); 1155 break; 1156 } 1157 } 1158 1159 static void 1160 sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1161 { 1162 SDHCIState *s = (SDHCIState *)opaque; 1163 unsigned shift = 8 * (offset & 0x3); 1164 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); 1165 uint32_t value = val; 1166 value <<= shift; 1167 1168 if (timer_pending(s->transfer_timer)) { 1169 sdhci_resume_pending_transfer(s); 1170 } 1171 1172 switch (offset & ~0x3) { 1173 case SDHC_SYSAD: 1174 if (!TRANSFERRING_DATA(s->prnsts)) { 1175 s->sdmasysad = (s->sdmasysad & mask) | value; 1176 MASKED_WRITE(s->sdmasysad, mask, value); 1177 /* Writing to last byte of sdmasysad might trigger transfer */ 1178 if (!(mask & 0xFF000000) && s->blkcnt && 1179 (s->blksize & BLOCK_SIZE_MASK) && 1180 SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) { 1181 if (s->trnmod & SDHC_TRNS_MULTI) { 1182 sdhci_sdma_transfer_multi_blocks(s); 1183 } else { 1184 sdhci_sdma_transfer_single_block(s); 1185 } 1186 } 1187 } 1188 break; 1189 case SDHC_BLKSIZE: 1190 if (!TRANSFERRING_DATA(s->prnsts)) { 1191 uint16_t blksize = s->blksize; 1192 1193 /* 1194 * [14:12] SDMA Buffer Boundary 1195 * [11:00] Transfer Block Size 1196 */ 1197 MASKED_WRITE(s->blksize, mask, extract32(value, 0, 15)); 1198 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); 1199 1200 /* Limit block size to the maximum buffer size */ 1201 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) { 1202 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " 1203 "the maximum buffer 0x%x\n", __func__, s->blksize, 1204 s->buf_maxsz); 1205 1206 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz); 1207 } 1208 1209 /* 1210 * If the block size is programmed to a different value from 1211 * the previous one, reset the data pointer of s->fifo_buffer[] 1212 * so that s->fifo_buffer[] can be filled in using the new block 1213 * size in the next transfer. 1214 */ 1215 if (blksize != s->blksize) { 1216 s->data_count = 0; 1217 } 1218 } 1219 1220 break; 1221 case SDHC_ARGUMENT: 1222 MASKED_WRITE(s->argument, mask, value); 1223 break; 1224 case SDHC_TRNMOD: 1225 /* 1226 * DMA can be enabled only if it is supported as indicated by 1227 * capabilities register 1228 */ 1229 if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { 1230 value &= ~SDHC_TRNS_DMA; 1231 } 1232 1233 /* TRNMOD writes are inhibited while Command Inhibit (DAT) is true */ 1234 if (s->prnsts & SDHC_DATA_INHIBIT) { 1235 mask |= 0xffff; 1236 } 1237 1238 MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK); 1239 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); 1240 1241 /* Writing to the upper byte of CMDREG triggers SD command generation */ 1242 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { 1243 break; 1244 } 1245 1246 sdhci_send_command(s); 1247 break; 1248 case SDHC_BDATA: 1249 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1250 sdhci_write_dataport(s, value >> shift, size); 1251 } 1252 break; 1253 case SDHC_HOSTCTL: 1254 if (!(mask & 0xFF0000)) { 1255 sdhci_blkgap_write(s, value >> 16); 1256 } 1257 MASKED_WRITE(s->hostctl1, mask, value); 1258 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); 1259 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); 1260 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || 1261 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { 1262 s->pwrcon &= ~SDHC_POWER_ON; 1263 } 1264 break; 1265 case SDHC_CLKCON: 1266 if (!(mask & 0xFF000000)) { 1267 sdhci_reset_write(s, value >> 24); 1268 } 1269 MASKED_WRITE(s->clkcon, mask, value); 1270 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); 1271 if (s->clkcon & SDHC_CLOCK_INT_EN) { 1272 s->clkcon |= SDHC_CLOCK_INT_STABLE; 1273 } else { 1274 s->clkcon &= ~SDHC_CLOCK_INT_STABLE; 1275 } 1276 break; 1277 case SDHC_NORINTSTS: 1278 if (s->norintstsen & SDHC_NISEN_CARDINT) { 1279 value &= ~SDHC_NIS_CARDINT; 1280 } 1281 s->norintsts &= mask | ~value; 1282 s->errintsts &= (mask >> 16) | ~(value >> 16); 1283 if (s->errintsts) { 1284 s->norintsts |= SDHC_NIS_ERR; 1285 } else { 1286 s->norintsts &= ~SDHC_NIS_ERR; 1287 } 1288 sdhci_update_irq(s); 1289 break; 1290 case SDHC_NORINTSTSEN: 1291 MASKED_WRITE(s->norintstsen, mask, value); 1292 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); 1293 s->norintsts &= s->norintstsen; 1294 s->errintsts &= s->errintstsen; 1295 if (s->errintsts) { 1296 s->norintsts |= SDHC_NIS_ERR; 1297 } else { 1298 s->norintsts &= ~SDHC_NIS_ERR; 1299 } 1300 /* 1301 * Quirk for Raspberry Pi: pending card insert interrupt 1302 * appears when first enabled after power on 1303 */ 1304 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { 1305 assert(s->pending_insert_quirk); 1306 s->norintsts |= SDHC_NIS_INSERT; 1307 s->pending_insert_state = false; 1308 } 1309 sdhci_update_irq(s); 1310 break; 1311 case SDHC_NORINTSIGEN: 1312 MASKED_WRITE(s->norintsigen, mask, value); 1313 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); 1314 sdhci_update_irq(s); 1315 break; 1316 case SDHC_ADMAERR: 1317 MASKED_WRITE(s->admaerr, mask, value); 1318 break; 1319 case SDHC_ADMASYSADDR: 1320 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | 1321 (uint64_t)mask)) | (uint64_t)value; 1322 break; 1323 case SDHC_ADMASYSADDR + 4: 1324 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | 1325 ((uint64_t)mask << 32))) | ((uint64_t)value << 32); 1326 break; 1327 case SDHC_FEAER: 1328 s->acmd12errsts |= value; 1329 s->errintsts |= (value >> 16) & s->errintstsen; 1330 if (s->acmd12errsts) { 1331 s->errintsts |= SDHC_EIS_CMD12ERR; 1332 } 1333 if (s->errintsts) { 1334 s->norintsts |= SDHC_NIS_ERR; 1335 } 1336 sdhci_update_irq(s); 1337 break; 1338 case SDHC_ACMD12ERRSTS: 1339 MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX); 1340 if (s->uhs_mode >= UHS_I) { 1341 MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16); 1342 1343 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) { 1344 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V); 1345 } else { 1346 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V); 1347 } 1348 } 1349 break; 1350 1351 case SDHC_CAPAB: 1352 case SDHC_CAPAB + 4: 1353 case SDHC_MAXCURR: 1354 case SDHC_MAXCURR + 4: 1355 qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx 1356 " <- 0x%08x read-only\n", size, offset, value >> shift); 1357 break; 1358 1359 default: 1360 qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x " 1361 "not implemented\n", size, offset, value >> shift); 1362 break; 1363 } 1364 trace_sdhci_access("wr", size << 3, offset, "<-", 1365 value >> shift, value >> shift); 1366 } 1367 1368 static const MemoryRegionOps sdhci_mmio_le_ops = { 1369 .read = sdhci_read, 1370 .write = sdhci_write, 1371 .valid = { 1372 .min_access_size = 1, 1373 .max_access_size = 4, 1374 .unaligned = false 1375 }, 1376 .endianness = DEVICE_LITTLE_ENDIAN, 1377 }; 1378 1379 static const MemoryRegionOps sdhci_mmio_be_ops = { 1380 .read = sdhci_read, 1381 .write = sdhci_write, 1382 .impl = { 1383 .min_access_size = 4, 1384 .max_access_size = 4, 1385 }, 1386 .valid = { 1387 .min_access_size = 1, 1388 .max_access_size = 4, 1389 .unaligned = false 1390 }, 1391 .endianness = DEVICE_BIG_ENDIAN, 1392 }; 1393 1394 static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) 1395 { 1396 ERRP_GUARD(); 1397 1398 switch (s->sd_spec_version) { 1399 case 2 ... 3: 1400 break; 1401 default: 1402 error_setg(errp, "Only Spec v2/v3 are supported"); 1403 return; 1404 } 1405 s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1); 1406 1407 sdhci_check_capareg(s, errp); 1408 if (*errp) { 1409 return; 1410 } 1411 } 1412 1413 /* --- qdev common --- */ 1414 1415 void sdhci_initfn(SDHCIState *s) 1416 { 1417 qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); 1418 1419 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1420 sdhci_raise_insertion_irq, s); 1421 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1422 sdhci_data_transfer, s); 1423 1424 s->io_ops = &sdhci_mmio_le_ops; 1425 } 1426 1427 void sdhci_uninitfn(SDHCIState *s) 1428 { 1429 timer_free(s->insert_timer); 1430 timer_free(s->transfer_timer); 1431 1432 g_free(s->fifo_buffer); 1433 s->fifo_buffer = NULL; 1434 } 1435 1436 void sdhci_common_realize(SDHCIState *s, Error **errp) 1437 { 1438 ERRP_GUARD(); 1439 1440 switch (s->endianness) { 1441 case DEVICE_LITTLE_ENDIAN: 1442 /* s->io_ops is little endian by default */ 1443 break; 1444 case DEVICE_BIG_ENDIAN: 1445 if (s->io_ops != &sdhci_mmio_le_ops) { 1446 error_setg(errp, "SD controller doesn't support big endianness"); 1447 return; 1448 } 1449 s->io_ops = &sdhci_mmio_be_ops; 1450 break; 1451 default: 1452 error_setg(errp, "Incorrect endianness"); 1453 return; 1454 } 1455 1456 sdhci_init_readonly_registers(s, errp); 1457 if (*errp) { 1458 return; 1459 } 1460 1461 s->buf_maxsz = sdhci_get_fifolen(s); 1462 s->fifo_buffer = g_malloc0(s->buf_maxsz); 1463 1464 memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci", 1465 SDHC_REGISTERS_MAP_SIZE); 1466 } 1467 1468 void sdhci_common_unrealize(SDHCIState *s) 1469 { 1470 /* 1471 * This function is expected to be called only once for each class: 1472 * - SysBus: via DeviceClass->unrealize(), 1473 * - PCI: via PCIDeviceClass->exit(). 1474 * However to avoid double-free and/or use-after-free we still nullify 1475 * this variable (better safe than sorry!). 1476 */ 1477 g_free(s->fifo_buffer); 1478 s->fifo_buffer = NULL; 1479 } 1480 1481 static bool sdhci_pending_insert_vmstate_needed(void *opaque) 1482 { 1483 SDHCIState *s = opaque; 1484 1485 return s->pending_insert_state; 1486 } 1487 1488 static const VMStateDescription sdhci_pending_insert_vmstate = { 1489 .name = "sdhci/pending-insert", 1490 .version_id = 1, 1491 .minimum_version_id = 1, 1492 .needed = sdhci_pending_insert_vmstate_needed, 1493 .fields = (const VMStateField[]) { 1494 VMSTATE_BOOL(pending_insert_state, SDHCIState), 1495 VMSTATE_END_OF_LIST() 1496 }, 1497 }; 1498 1499 const VMStateDescription sdhci_vmstate = { 1500 .name = "sdhci", 1501 .version_id = 1, 1502 .minimum_version_id = 1, 1503 .fields = (const VMStateField[]) { 1504 VMSTATE_UINT32(sdmasysad, SDHCIState), 1505 VMSTATE_UINT16(blksize, SDHCIState), 1506 VMSTATE_UINT16(blkcnt, SDHCIState), 1507 VMSTATE_UINT32(argument, SDHCIState), 1508 VMSTATE_UINT16(trnmod, SDHCIState), 1509 VMSTATE_UINT16(cmdreg, SDHCIState), 1510 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), 1511 VMSTATE_UINT32(prnsts, SDHCIState), 1512 VMSTATE_UINT8(hostctl1, SDHCIState), 1513 VMSTATE_UINT8(pwrcon, SDHCIState), 1514 VMSTATE_UINT8(blkgap, SDHCIState), 1515 VMSTATE_UINT8(wakcon, SDHCIState), 1516 VMSTATE_UINT16(clkcon, SDHCIState), 1517 VMSTATE_UINT8(timeoutcon, SDHCIState), 1518 VMSTATE_UINT8(admaerr, SDHCIState), 1519 VMSTATE_UINT16(norintsts, SDHCIState), 1520 VMSTATE_UINT16(errintsts, SDHCIState), 1521 VMSTATE_UINT16(norintstsen, SDHCIState), 1522 VMSTATE_UINT16(errintstsen, SDHCIState), 1523 VMSTATE_UINT16(norintsigen, SDHCIState), 1524 VMSTATE_UINT16(errintsigen, SDHCIState), 1525 VMSTATE_UINT16(acmd12errsts, SDHCIState), 1526 VMSTATE_UINT16(data_count, SDHCIState), 1527 VMSTATE_UINT64(admasysaddr, SDHCIState), 1528 VMSTATE_UINT8(stopped_state, SDHCIState), 1529 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz), 1530 VMSTATE_TIMER_PTR(insert_timer, SDHCIState), 1531 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState), 1532 VMSTATE_END_OF_LIST() 1533 }, 1534 .subsections = (const VMStateDescription * const []) { 1535 &sdhci_pending_insert_vmstate, 1536 NULL 1537 }, 1538 }; 1539 1540 void sdhci_common_class_init(ObjectClass *klass, void *data) 1541 { 1542 DeviceClass *dc = DEVICE_CLASS(klass); 1543 1544 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1545 dc->vmsd = &sdhci_vmstate; 1546 device_class_set_legacy_reset(dc, sdhci_poweron_reset); 1547 } 1548 1549 /* --- qdev SysBus --- */ 1550 1551 static Property sdhci_sysbus_properties[] = { 1552 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), 1553 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, 1554 false), 1555 DEFINE_PROP_LINK("dma", SDHCIState, 1556 dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), 1557 DEFINE_PROP_BOOL("wp-inverted", SDHCIState, 1558 wp_inverted, false), 1559 DEFINE_PROP_END_OF_LIST(), 1560 }; 1561 1562 static void sdhci_sysbus_init(Object *obj) 1563 { 1564 SDHCIState *s = SYSBUS_SDHCI(obj); 1565 1566 sdhci_initfn(s); 1567 } 1568 1569 static void sdhci_sysbus_finalize(Object *obj) 1570 { 1571 SDHCIState *s = SYSBUS_SDHCI(obj); 1572 1573 if (s->dma_mr) { 1574 object_unparent(OBJECT(s->dma_mr)); 1575 } 1576 1577 sdhci_uninitfn(s); 1578 } 1579 1580 static void sdhci_sysbus_realize(DeviceState *dev, Error **errp) 1581 { 1582 ERRP_GUARD(); 1583 SDHCIState *s = SYSBUS_SDHCI(dev); 1584 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1585 1586 sdhci_common_realize(s, errp); 1587 if (*errp) { 1588 return; 1589 } 1590 1591 if (s->dma_mr) { 1592 s->dma_as = &s->sysbus_dma_as; 1593 address_space_init(s->dma_as, s->dma_mr, "sdhci-dma"); 1594 } else { 1595 /* use system_memory() if property "dma" not set */ 1596 s->dma_as = &address_space_memory; 1597 } 1598 1599 sysbus_init_irq(sbd, &s->irq); 1600 1601 sysbus_init_mmio(sbd, &s->iomem); 1602 } 1603 1604 static void sdhci_sysbus_unrealize(DeviceState *dev) 1605 { 1606 SDHCIState *s = SYSBUS_SDHCI(dev); 1607 1608 sdhci_common_unrealize(s); 1609 1610 if (s->dma_mr) { 1611 address_space_destroy(s->dma_as); 1612 } 1613 } 1614 1615 static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) 1616 { 1617 DeviceClass *dc = DEVICE_CLASS(klass); 1618 1619 device_class_set_props(dc, sdhci_sysbus_properties); 1620 dc->realize = sdhci_sysbus_realize; 1621 dc->unrealize = sdhci_sysbus_unrealize; 1622 1623 sdhci_common_class_init(klass, data); 1624 } 1625 1626 /* --- qdev bus master --- */ 1627 1628 static void sdhci_bus_class_init(ObjectClass *klass, void *data) 1629 { 1630 SDBusClass *sbc = SD_BUS_CLASS(klass); 1631 1632 sbc->set_inserted = sdhci_set_inserted; 1633 sbc->set_readonly = sdhci_set_readonly; 1634 } 1635 1636 /* --- qdev i.MX eSDHC --- */ 1637 1638 #define USDHC_MIX_CTRL 0x48 1639 1640 #define USDHC_VENDOR_SPEC 0xc0 1641 #define USDHC_IMX_FRC_SDCLK_ON (1 << 8) 1642 1643 #define USDHC_DLL_CTRL 0x60 1644 1645 #define USDHC_TUNING_CTRL 0xcc 1646 #define USDHC_TUNE_CTRL_STATUS 0x68 1647 #define USDHC_WTMK_LVL 0x44 1648 1649 /* Undocumented register used by guests working around erratum ERR004536 */ 1650 #define USDHC_UNDOCUMENTED_REG27 0x6c 1651 1652 #define USDHC_CTRL_4BITBUS (0x1 << 1) 1653 #define USDHC_CTRL_8BITBUS (0x2 << 1) 1654 1655 #define USDHC_PRNSTS_SDSTB (1 << 3) 1656 1657 static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) 1658 { 1659 SDHCIState *s = SYSBUS_SDHCI(opaque); 1660 uint32_t ret; 1661 uint16_t hostctl1; 1662 1663 switch (offset) { 1664 default: 1665 return sdhci_read(opaque, offset, size); 1666 1667 case SDHC_HOSTCTL: 1668 /* 1669 * For a detailed explanation on the following bit 1670 * manipulation code see comments in a similar part of 1671 * usdhc_write() 1672 */ 1673 hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3); 1674 1675 if (s->hostctl1 & SDHC_CTRL_8BITBUS) { 1676 hostctl1 |= USDHC_CTRL_8BITBUS; 1677 } 1678 1679 if (s->hostctl1 & SDHC_CTRL_4BITBUS) { 1680 hostctl1 |= USDHC_CTRL_4BITBUS; 1681 } 1682 1683 ret = hostctl1; 1684 ret |= (uint32_t)s->blkgap << 16; 1685 ret |= (uint32_t)s->wakcon << 24; 1686 1687 break; 1688 1689 case SDHC_PRNSTS: 1690 /* Add SDSTB (SD Clock Stable) bit to PRNSTS */ 1691 ret = sdhci_read(opaque, offset, size) & ~USDHC_PRNSTS_SDSTB; 1692 if (s->clkcon & SDHC_CLOCK_INT_STABLE) { 1693 ret |= USDHC_PRNSTS_SDSTB; 1694 } 1695 break; 1696 1697 case USDHC_VENDOR_SPEC: 1698 ret = s->vendor_spec; 1699 break; 1700 case USDHC_DLL_CTRL: 1701 case USDHC_TUNE_CTRL_STATUS: 1702 case USDHC_UNDOCUMENTED_REG27: 1703 case USDHC_TUNING_CTRL: 1704 case USDHC_MIX_CTRL: 1705 case USDHC_WTMK_LVL: 1706 ret = 0; 1707 break; 1708 } 1709 1710 return ret; 1711 } 1712 1713 static void 1714 usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1715 { 1716 SDHCIState *s = SYSBUS_SDHCI(opaque); 1717 uint8_t hostctl1; 1718 uint32_t value = (uint32_t)val; 1719 1720 switch (offset) { 1721 case USDHC_DLL_CTRL: 1722 case USDHC_TUNE_CTRL_STATUS: 1723 case USDHC_UNDOCUMENTED_REG27: 1724 case USDHC_TUNING_CTRL: 1725 case USDHC_WTMK_LVL: 1726 break; 1727 1728 case USDHC_VENDOR_SPEC: 1729 s->vendor_spec = value; 1730 switch (s->vendor) { 1731 case SDHCI_VENDOR_IMX: 1732 if (value & USDHC_IMX_FRC_SDCLK_ON) { 1733 s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF; 1734 } else { 1735 s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF; 1736 } 1737 break; 1738 default: 1739 break; 1740 } 1741 break; 1742 1743 case SDHC_HOSTCTL: 1744 /* 1745 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL) 1746 * 1747 * 7 6 5 4 3 2 1 0 1748 * |-----------+--------+--------+-----------+----------+---------| 1749 * | Card | Card | Endian | DATA3 | Data | Led | 1750 * | Detect | Detect | Mode | as Card | Transfer | Control | 1751 * | Signal | Test | | Detection | Width | | 1752 * | Selection | Level | | Pin | | | 1753 * |-----------+--------+--------+-----------+----------+---------| 1754 * 1755 * and 0x29 1756 * 1757 * 15 10 9 8 1758 * |----------+------| 1759 * | Reserved | DMA | 1760 * | | Sel. | 1761 * | | | 1762 * |----------+------| 1763 * 1764 * and here's what SDCHI spec expects those offsets to be: 1765 * 1766 * 0x28 (Host Control Register) 1767 * 1768 * 7 6 5 4 3 2 1 0 1769 * |--------+--------+----------+------+--------+----------+---------| 1770 * | Card | Card | Extended | DMA | High | Data | LED | 1771 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control | 1772 * | Signal | Test | Transfer | | Enable | Width | | 1773 * | Sel. | Level | Width | | | | | 1774 * |--------+--------+----------+------+--------+----------+---------| 1775 * 1776 * and 0x29 (Power Control Register) 1777 * 1778 * |----------------------------------| 1779 * | Power Control Register | 1780 * | | 1781 * | Description omitted, | 1782 * | since it has no analog in ESDHCI | 1783 * | | 1784 * |----------------------------------| 1785 * 1786 * Since offsets 0x2A and 0x2B should be compatible between 1787 * both IP specs we only need to reconcile least 16-bit of the 1788 * word we've been given. 1789 */ 1790 1791 /* 1792 * First, save bits 7 6 and 0 since they are identical 1793 */ 1794 hostctl1 = value & (SDHC_CTRL_LED | 1795 SDHC_CTRL_CDTEST_INS | 1796 SDHC_CTRL_CDTEST_EN); 1797 /* 1798 * Second, split "Data Transfer Width" from bits 2 and 1 in to 1799 * bits 5 and 1 1800 */ 1801 if (value & USDHC_CTRL_8BITBUS) { 1802 hostctl1 |= SDHC_CTRL_8BITBUS; 1803 } 1804 1805 if (value & USDHC_CTRL_4BITBUS) { 1806 hostctl1 |= USDHC_CTRL_4BITBUS; 1807 } 1808 1809 /* 1810 * Third, move DMA select from bits 9 and 8 to bits 4 and 3 1811 */ 1812 hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3)); 1813 1814 /* 1815 * Now place the corrected value into low 16-bit of the value 1816 * we are going to give standard SDHCI write function 1817 * 1818 * NOTE: This transformation should be the inverse of what can 1819 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux 1820 * kernel 1821 */ 1822 value &= ~UINT16_MAX; 1823 value |= hostctl1; 1824 value |= (uint16_t)s->pwrcon << 8; 1825 1826 sdhci_write(opaque, offset, value, size); 1827 break; 1828 1829 case USDHC_MIX_CTRL: 1830 /* 1831 * So, when SD/MMC stack in Linux tries to write to "Transfer 1832 * Mode Register", ESDHC i.MX quirk code will translate it 1833 * into a write to ESDHC_MIX_CTRL, so we do the opposite in 1834 * order to get where we started 1835 * 1836 * Note that Auto CMD23 Enable bit is located in a wrong place 1837 * on i.MX, but since it is not used by QEMU we do not care. 1838 * 1839 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...) 1840 * here because it will result in a call to 1841 * sdhci_send_command(s) which we don't want. 1842 * 1843 */ 1844 s->trnmod = value & UINT16_MAX; 1845 break; 1846 case SDHC_TRNMOD: 1847 /* 1848 * Similar to above, but this time a write to "Command 1849 * Register" will be translated into a 4-byte write to 1850 * "Transfer Mode register" where lower 16-bit of value would 1851 * be set to zero. So what we do is fill those bits with 1852 * cached value from s->trnmod and let the SDHCI 1853 * infrastructure handle the rest 1854 */ 1855 sdhci_write(opaque, offset, val | s->trnmod, size); 1856 break; 1857 case SDHC_BLKSIZE: 1858 /* 1859 * ESDHCI does not implement "Host SDMA Buffer Boundary", and 1860 * Linux driver will try to zero this field out which will 1861 * break the rest of SDHCI emulation. 1862 * 1863 * Linux defaults to maximum possible setting (512K boundary) 1864 * and it seems to be the only option that i.MX IP implements, 1865 * so we artificially set it to that value. 1866 */ 1867 val |= 0x7 << 12; 1868 /* FALLTHROUGH */ 1869 default: 1870 sdhci_write(opaque, offset, val, size); 1871 break; 1872 } 1873 } 1874 1875 static const MemoryRegionOps usdhc_mmio_ops = { 1876 .read = usdhc_read, 1877 .write = usdhc_write, 1878 .valid = { 1879 .min_access_size = 1, 1880 .max_access_size = 4, 1881 .unaligned = false 1882 }, 1883 .endianness = DEVICE_LITTLE_ENDIAN, 1884 }; 1885 1886 static void imx_usdhc_init(Object *obj) 1887 { 1888 SDHCIState *s = SYSBUS_SDHCI(obj); 1889 1890 s->io_ops = &usdhc_mmio_ops; 1891 s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; 1892 } 1893 1894 /* --- qdev Samsung s3c --- */ 1895 1896 #define S3C_SDHCI_CONTROL2 0x80 1897 #define S3C_SDHCI_CONTROL3 0x84 1898 #define S3C_SDHCI_CONTROL4 0x8c 1899 1900 static uint64_t sdhci_s3c_read(void *opaque, hwaddr offset, unsigned size) 1901 { 1902 uint64_t ret; 1903 1904 switch (offset) { 1905 case S3C_SDHCI_CONTROL2: 1906 case S3C_SDHCI_CONTROL3: 1907 case S3C_SDHCI_CONTROL4: 1908 /* ignore */ 1909 ret = 0; 1910 break; 1911 default: 1912 ret = sdhci_read(opaque, offset, size); 1913 break; 1914 } 1915 1916 return ret; 1917 } 1918 1919 static void sdhci_s3c_write(void *opaque, hwaddr offset, uint64_t val, 1920 unsigned size) 1921 { 1922 switch (offset) { 1923 case S3C_SDHCI_CONTROL2: 1924 case S3C_SDHCI_CONTROL3: 1925 case S3C_SDHCI_CONTROL4: 1926 /* ignore */ 1927 break; 1928 default: 1929 sdhci_write(opaque, offset, val, size); 1930 break; 1931 } 1932 } 1933 1934 static const MemoryRegionOps sdhci_s3c_mmio_ops = { 1935 .read = sdhci_s3c_read, 1936 .write = sdhci_s3c_write, 1937 .valid = { 1938 .min_access_size = 1, 1939 .max_access_size = 4, 1940 .unaligned = false 1941 }, 1942 .endianness = DEVICE_LITTLE_ENDIAN, 1943 }; 1944 1945 static void sdhci_s3c_init(Object *obj) 1946 { 1947 SDHCIState *s = SYSBUS_SDHCI(obj); 1948 1949 s->io_ops = &sdhci_s3c_mmio_ops; 1950 } 1951 1952 static const TypeInfo sdhci_types[] = { 1953 { 1954 .name = TYPE_SDHCI_BUS, 1955 .parent = TYPE_SD_BUS, 1956 .instance_size = sizeof(SDBus), 1957 .class_init = sdhci_bus_class_init, 1958 }, 1959 { 1960 .name = TYPE_SYSBUS_SDHCI, 1961 .parent = TYPE_SYS_BUS_DEVICE, 1962 .instance_size = sizeof(SDHCIState), 1963 .instance_init = sdhci_sysbus_init, 1964 .instance_finalize = sdhci_sysbus_finalize, 1965 .class_init = sdhci_sysbus_class_init, 1966 }, 1967 { 1968 .name = TYPE_IMX_USDHC, 1969 .parent = TYPE_SYSBUS_SDHCI, 1970 .instance_init = imx_usdhc_init, 1971 }, 1972 { 1973 .name = TYPE_S3C_SDHCI, 1974 .parent = TYPE_SYSBUS_SDHCI, 1975 .instance_init = sdhci_s3c_init, 1976 }, 1977 }; 1978 1979 DEFINE_TYPES(sdhci_types) 1980