1 /* 2 * SD Association Host Standard Specification v2.0 controller emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Mitsyanko Igor <i.mitsyanko@samsung.com> 6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 7 * 8 * Based on MMC controller for Samsung S5PC1xx-based board emulation 9 * by Alexey Merkulov and Vladimir Monakhov. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 19 * See the GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "sysemu/block-backend.h" 28 #include "sysemu/blockdev.h" 29 #include "sysemu/dma.h" 30 #include "qemu/timer.h" 31 #include "qemu/bitops.h" 32 #include "sdhci-internal.h" 33 34 /* host controller debug messages */ 35 #ifndef SDHC_DEBUG 36 #define SDHC_DEBUG 0 37 #endif 38 39 #define DPRINT_L1(fmt, args...) \ 40 do { \ 41 if (SDHC_DEBUG) { \ 42 fprintf(stderr, "QEMU SDHC: " fmt, ## args); \ 43 } \ 44 } while (0) 45 #define DPRINT_L2(fmt, args...) \ 46 do { \ 47 if (SDHC_DEBUG > 1) { \ 48 fprintf(stderr, "QEMU SDHC: " fmt, ## args); \ 49 } \ 50 } while (0) 51 #define ERRPRINT(fmt, args...) \ 52 do { \ 53 if (SDHC_DEBUG) { \ 54 fprintf(stderr, "QEMU SDHC ERROR: " fmt, ## args); \ 55 } \ 56 } while (0) 57 58 #define TYPE_SDHCI_BUS "sdhci-bus" 59 #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS) 60 61 /* Default SD/MMC host controller features information, which will be 62 * presented in CAPABILITIES register of generic SD host controller at reset. 63 * If not stated otherwise: 64 * 0 - not supported, 1 - supported, other - prohibited. 65 */ 66 #define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */ 67 #define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */ 68 #define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */ 69 #define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */ 70 #define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */ 71 #define SDHC_CAPAB_SDMA 1ul /* SDMA support */ 72 #define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */ 73 #define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */ 74 #define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */ 75 /* Maximum host controller R/W buffers size 76 * Possible values: 512, 1024, 2048 bytes */ 77 #define SDHC_CAPAB_MAXBLOCKLENGTH 512ul 78 /* Maximum clock frequency for SDclock in MHz 79 * value in range 10-63 MHz, 0 - not defined */ 80 #define SDHC_CAPAB_BASECLKFREQ 52ul 81 #define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */ 82 /* Timeout clock frequency 1-63, 0 - not defined */ 83 #define SDHC_CAPAB_TOCLKFREQ 52ul 84 85 /* Now check all parameters and calculate CAPABILITIES REGISTER value */ 86 #if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \ 87 SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \ 88 SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\ 89 SDHC_CAPAB_TOUNIT > 1 90 #error Capabilities features can have value 0 or 1 only! 91 #endif 92 93 #if SDHC_CAPAB_MAXBLOCKLENGTH == 512 94 #define MAX_BLOCK_LENGTH 0ul 95 #elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024 96 #define MAX_BLOCK_LENGTH 1ul 97 #elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048 98 #define MAX_BLOCK_LENGTH 2ul 99 #else 100 #error Max host controller block size can have value 512, 1024 or 2048 only! 101 #endif 102 103 #if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \ 104 SDHC_CAPAB_BASECLKFREQ > 63 105 #error SDclock frequency can have value in range 0, 10-63 only! 106 #endif 107 108 #if SDHC_CAPAB_TOCLKFREQ > 63 109 #error Timeout clock frequency can have value in range 0-63 only! 110 #endif 111 112 #define SDHC_CAPAB_REG_DEFAULT \ 113 ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \ 114 (SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \ 115 (SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \ 116 (SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \ 117 (SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \ 118 (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \ 119 (SDHC_CAPAB_TOCLKFREQ)) 120 121 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) 122 123 static uint8_t sdhci_slotint(SDHCIState *s) 124 { 125 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || 126 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || 127 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); 128 } 129 130 static inline void sdhci_update_irq(SDHCIState *s) 131 { 132 qemu_set_irq(s->irq, sdhci_slotint(s)); 133 } 134 135 static void sdhci_raise_insertion_irq(void *opaque) 136 { 137 SDHCIState *s = (SDHCIState *)opaque; 138 139 if (s->norintsts & SDHC_NIS_REMOVE) { 140 timer_mod(s->insert_timer, 141 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 142 } else { 143 s->prnsts = 0x1ff0000; 144 if (s->norintstsen & SDHC_NISEN_INSERT) { 145 s->norintsts |= SDHC_NIS_INSERT; 146 } 147 sdhci_update_irq(s); 148 } 149 } 150 151 static void sdhci_set_inserted(DeviceState *dev, bool level) 152 { 153 SDHCIState *s = (SDHCIState *)dev; 154 DPRINT_L1("Card state changed: %s!\n", level ? "insert" : "eject"); 155 156 if ((s->norintsts & SDHC_NIS_REMOVE) && level) { 157 /* Give target some time to notice card ejection */ 158 timer_mod(s->insert_timer, 159 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 160 } else { 161 if (level) { 162 s->prnsts = 0x1ff0000; 163 if (s->norintstsen & SDHC_NISEN_INSERT) { 164 s->norintsts |= SDHC_NIS_INSERT; 165 } 166 } else { 167 s->prnsts = 0x1fa0000; 168 s->pwrcon &= ~SDHC_POWER_ON; 169 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; 170 if (s->norintstsen & SDHC_NISEN_REMOVE) { 171 s->norintsts |= SDHC_NIS_REMOVE; 172 } 173 } 174 sdhci_update_irq(s); 175 } 176 } 177 178 static void sdhci_set_readonly(DeviceState *dev, bool level) 179 { 180 SDHCIState *s = (SDHCIState *)dev; 181 182 if (level) { 183 s->prnsts &= ~SDHC_WRITE_PROTECT; 184 } else { 185 /* Write enabled */ 186 s->prnsts |= SDHC_WRITE_PROTECT; 187 } 188 } 189 190 static void sdhci_reset(SDHCIState *s) 191 { 192 DeviceState *dev = DEVICE(s); 193 194 timer_del(s->insert_timer); 195 timer_del(s->transfer_timer); 196 /* Set all registers to 0. Capabilities registers are not cleared 197 * and assumed to always preserve their value, given to them during 198 * initialization */ 199 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); 200 201 /* Reset other state based on current card insertion/readonly status */ 202 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus)); 203 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus)); 204 205 s->data_count = 0; 206 s->stopped_state = sdhc_not_stopped; 207 s->pending_insert_state = false; 208 } 209 210 static void sdhci_data_transfer(void *opaque); 211 212 static void sdhci_send_command(SDHCIState *s) 213 { 214 SDRequest request; 215 uint8_t response[16]; 216 int rlen; 217 218 s->errintsts = 0; 219 s->acmd12errsts = 0; 220 request.cmd = s->cmdreg >> 8; 221 request.arg = s->argument; 222 DPRINT_L1("sending CMD%u ARG[0x%08x]\n", request.cmd, request.arg); 223 rlen = sdbus_do_command(&s->sdbus, &request, response); 224 225 if (s->cmdreg & SDHC_CMD_RESPONSE) { 226 if (rlen == 4) { 227 s->rspreg[0] = (response[0] << 24) | (response[1] << 16) | 228 (response[2] << 8) | response[3]; 229 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; 230 DPRINT_L1("Response: RSPREG[31..0]=0x%08x\n", s->rspreg[0]); 231 } else if (rlen == 16) { 232 s->rspreg[0] = (response[11] << 24) | (response[12] << 16) | 233 (response[13] << 8) | response[14]; 234 s->rspreg[1] = (response[7] << 24) | (response[8] << 16) | 235 (response[9] << 8) | response[10]; 236 s->rspreg[2] = (response[3] << 24) | (response[4] << 16) | 237 (response[5] << 8) | response[6]; 238 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | 239 response[2]; 240 DPRINT_L1("Response received:\n RSPREG[127..96]=0x%08x, RSPREG[95.." 241 "64]=0x%08x,\n RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x\n", 242 s->rspreg[3], s->rspreg[2], s->rspreg[1], s->rspreg[0]); 243 } else { 244 ERRPRINT("Timeout waiting for command response\n"); 245 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { 246 s->errintsts |= SDHC_EIS_CMDTIMEOUT; 247 s->norintsts |= SDHC_NIS_ERR; 248 } 249 } 250 251 if ((s->norintstsen & SDHC_NISEN_TRSCMP) && 252 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { 253 s->norintsts |= SDHC_NIS_TRSCMP; 254 } 255 } 256 257 if (s->norintstsen & SDHC_NISEN_CMDCMP) { 258 s->norintsts |= SDHC_NIS_CMDCMP; 259 } 260 261 sdhci_update_irq(s); 262 263 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { 264 s->data_count = 0; 265 sdhci_data_transfer(s); 266 } 267 } 268 269 static void sdhci_end_transfer(SDHCIState *s) 270 { 271 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */ 272 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { 273 SDRequest request; 274 uint8_t response[16]; 275 276 request.cmd = 0x0C; 277 request.arg = 0; 278 DPRINT_L1("Automatically issue CMD%d %08x\n", request.cmd, request.arg); 279 sdbus_do_command(&s->sdbus, &request, response); 280 /* Auto CMD12 response goes to the upper Response register */ 281 s->rspreg[3] = (response[0] << 24) | (response[1] << 16) | 282 (response[2] << 8) | response[3]; 283 } 284 285 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | 286 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | 287 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); 288 289 if (s->norintstsen & SDHC_NISEN_TRSCMP) { 290 s->norintsts |= SDHC_NIS_TRSCMP; 291 } 292 293 sdhci_update_irq(s); 294 } 295 296 /* 297 * Programmed i/o data transfer 298 */ 299 300 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ 301 static void sdhci_read_block_from_card(SDHCIState *s) 302 { 303 int index = 0; 304 305 if ((s->trnmod & SDHC_TRNS_MULTI) && 306 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { 307 return; 308 } 309 310 for (index = 0; index < (s->blksize & 0x0fff); index++) { 311 s->fifo_buffer[index] = sdbus_read_data(&s->sdbus); 312 } 313 314 /* New data now available for READ through Buffer Port Register */ 315 s->prnsts |= SDHC_DATA_AVAILABLE; 316 if (s->norintstsen & SDHC_NISEN_RBUFRDY) { 317 s->norintsts |= SDHC_NIS_RBUFRDY; 318 } 319 320 /* Clear DAT line active status if that was the last block */ 321 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 322 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { 323 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 324 } 325 326 /* If stop at block gap request was set and it's not the last block of 327 * data - generate Block Event interrupt */ 328 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && 329 s->blkcnt != 1) { 330 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 331 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 332 s->norintsts |= SDHC_EIS_BLKGAP; 333 } 334 } 335 336 sdhci_update_irq(s); 337 } 338 339 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */ 340 static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) 341 { 342 uint32_t value = 0; 343 int i; 344 345 /* first check that a valid data exists in host controller input buffer */ 346 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { 347 ERRPRINT("Trying to read from empty buffer\n"); 348 return 0; 349 } 350 351 for (i = 0; i < size; i++) { 352 value |= s->fifo_buffer[s->data_count] << i * 8; 353 s->data_count++; 354 /* check if we've read all valid data (blksize bytes) from buffer */ 355 if ((s->data_count) >= (s->blksize & 0x0fff)) { 356 DPRINT_L2("All %u bytes of data have been read from input buffer\n", 357 s->data_count); 358 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ 359 s->data_count = 0; /* next buff read must start at position [0] */ 360 361 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 362 s->blkcnt--; 363 } 364 365 /* if that was the last block of data */ 366 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 367 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || 368 /* stop at gap request */ 369 (s->stopped_state == sdhc_gap_read && 370 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { 371 sdhci_end_transfer(s); 372 } else { /* if there are more data, read next block from card */ 373 sdhci_read_block_from_card(s); 374 } 375 break; 376 } 377 } 378 379 return value; 380 } 381 382 /* Write data from host controller FIFO to card */ 383 static void sdhci_write_block_to_card(SDHCIState *s) 384 { 385 int index = 0; 386 387 if (s->prnsts & SDHC_SPACE_AVAILABLE) { 388 if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 389 s->norintsts |= SDHC_NIS_WBUFRDY; 390 } 391 sdhci_update_irq(s); 392 return; 393 } 394 395 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 396 if (s->blkcnt == 0) { 397 return; 398 } else { 399 s->blkcnt--; 400 } 401 } 402 403 for (index = 0; index < (s->blksize & 0x0fff); index++) { 404 sdbus_write_data(&s->sdbus, s->fifo_buffer[index]); 405 } 406 407 /* Next data can be written through BUFFER DATORT register */ 408 s->prnsts |= SDHC_SPACE_AVAILABLE; 409 410 /* Finish transfer if that was the last block of data */ 411 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 412 ((s->trnmod & SDHC_TRNS_MULTI) && 413 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { 414 sdhci_end_transfer(s); 415 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 416 s->norintsts |= SDHC_NIS_WBUFRDY; 417 } 418 419 /* Generate Block Gap Event if requested and if not the last block */ 420 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && 421 s->blkcnt > 0) { 422 s->prnsts &= ~SDHC_DOING_WRITE; 423 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 424 s->norintsts |= SDHC_EIS_BLKGAP; 425 } 426 sdhci_end_transfer(s); 427 } 428 429 sdhci_update_irq(s); 430 } 431 432 /* Write @size bytes of @value data to host controller @s Buffer Data Port 433 * register */ 434 static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) 435 { 436 unsigned i; 437 438 /* Check that there is free space left in a buffer */ 439 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { 440 ERRPRINT("Can't write to data buffer: buffer full\n"); 441 return; 442 } 443 444 for (i = 0; i < size; i++) { 445 s->fifo_buffer[s->data_count] = value & 0xFF; 446 s->data_count++; 447 value >>= 8; 448 if (s->data_count >= (s->blksize & 0x0fff)) { 449 DPRINT_L2("write buffer filled with %u bytes of data\n", 450 s->data_count); 451 s->data_count = 0; 452 s->prnsts &= ~SDHC_SPACE_AVAILABLE; 453 if (s->prnsts & SDHC_DOING_WRITE) { 454 sdhci_write_block_to_card(s); 455 } 456 } 457 } 458 } 459 460 /* 461 * Single DMA data transfer 462 */ 463 464 /* Multi block SDMA transfer */ 465 static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) 466 { 467 bool page_aligned = false; 468 unsigned int n, begin; 469 const uint16_t block_size = s->blksize & 0x0fff; 470 uint32_t boundary_chk = 1 << (((s->blksize & 0xf000) >> 12) + 12); 471 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); 472 473 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for 474 * possible stop at page boundary if initial address is not page aligned, 475 * allow them to work properly */ 476 if ((s->sdmasysad % boundary_chk) == 0) { 477 page_aligned = true; 478 } 479 480 if (s->trnmod & SDHC_TRNS_READ) { 481 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 482 SDHC_DAT_LINE_ACTIVE; 483 while (s->blkcnt) { 484 if (s->data_count == 0) { 485 for (n = 0; n < block_size; n++) { 486 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 487 } 488 } 489 begin = s->data_count; 490 if (((boundary_count + begin) < block_size) && page_aligned) { 491 s->data_count = boundary_count + begin; 492 boundary_count = 0; 493 } else { 494 s->data_count = block_size; 495 boundary_count -= block_size - begin; 496 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 497 s->blkcnt--; 498 } 499 } 500 dma_memory_write(&address_space_memory, s->sdmasysad, 501 &s->fifo_buffer[begin], s->data_count - begin); 502 s->sdmasysad += s->data_count - begin; 503 if (s->data_count == block_size) { 504 s->data_count = 0; 505 } 506 if (page_aligned && boundary_count == 0) { 507 break; 508 } 509 } 510 } else { 511 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT | 512 SDHC_DAT_LINE_ACTIVE; 513 while (s->blkcnt) { 514 begin = s->data_count; 515 if (((boundary_count + begin) < block_size) && page_aligned) { 516 s->data_count = boundary_count + begin; 517 boundary_count = 0; 518 } else { 519 s->data_count = block_size; 520 boundary_count -= block_size - begin; 521 } 522 dma_memory_read(&address_space_memory, s->sdmasysad, 523 &s->fifo_buffer[begin], s->data_count); 524 s->sdmasysad += s->data_count - begin; 525 if (s->data_count == block_size) { 526 for (n = 0; n < block_size; n++) { 527 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 528 } 529 s->data_count = 0; 530 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 531 s->blkcnt--; 532 } 533 } 534 if (page_aligned && boundary_count == 0) { 535 break; 536 } 537 } 538 } 539 540 if (s->blkcnt == 0) { 541 sdhci_end_transfer(s); 542 } else { 543 if (s->norintstsen & SDHC_NISEN_DMA) { 544 s->norintsts |= SDHC_NIS_DMA; 545 } 546 sdhci_update_irq(s); 547 } 548 } 549 550 /* single block SDMA transfer */ 551 552 static void sdhci_sdma_transfer_single_block(SDHCIState *s) 553 { 554 int n; 555 uint32_t datacnt = s->blksize & 0x0fff; 556 557 if (s->trnmod & SDHC_TRNS_READ) { 558 for (n = 0; n < datacnt; n++) { 559 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 560 } 561 dma_memory_write(&address_space_memory, s->sdmasysad, s->fifo_buffer, 562 datacnt); 563 } else { 564 dma_memory_read(&address_space_memory, s->sdmasysad, s->fifo_buffer, 565 datacnt); 566 for (n = 0; n < datacnt; n++) { 567 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 568 } 569 } 570 571 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 572 s->blkcnt--; 573 } 574 575 sdhci_end_transfer(s); 576 } 577 578 typedef struct ADMADescr { 579 hwaddr addr; 580 uint16_t length; 581 uint8_t attr; 582 uint8_t incr; 583 } ADMADescr; 584 585 static void get_adma_description(SDHCIState *s, ADMADescr *dscr) 586 { 587 uint32_t adma1 = 0; 588 uint64_t adma2 = 0; 589 hwaddr entry_addr = (hwaddr)s->admasysaddr; 590 switch (SDHC_DMA_TYPE(s->hostctl)) { 591 case SDHC_CTRL_ADMA2_32: 592 dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma2, 593 sizeof(adma2)); 594 adma2 = le64_to_cpu(adma2); 595 /* The spec does not specify endianness of descriptor table. 596 * We currently assume that it is LE. 597 */ 598 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; 599 dscr->length = (uint16_t)extract64(adma2, 16, 16); 600 dscr->attr = (uint8_t)extract64(adma2, 0, 7); 601 dscr->incr = 8; 602 break; 603 case SDHC_CTRL_ADMA1_32: 604 dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma1, 605 sizeof(adma1)); 606 adma1 = le32_to_cpu(adma1); 607 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); 608 dscr->attr = (uint8_t)extract32(adma1, 0, 7); 609 dscr->incr = 4; 610 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { 611 dscr->length = (uint16_t)extract32(adma1, 12, 16); 612 } else { 613 dscr->length = 4096; 614 } 615 break; 616 case SDHC_CTRL_ADMA2_64: 617 dma_memory_read(&address_space_memory, entry_addr, 618 (uint8_t *)(&dscr->attr), 1); 619 dma_memory_read(&address_space_memory, entry_addr + 2, 620 (uint8_t *)(&dscr->length), 2); 621 dscr->length = le16_to_cpu(dscr->length); 622 dma_memory_read(&address_space_memory, entry_addr + 4, 623 (uint8_t *)(&dscr->addr), 8); 624 dscr->attr = le64_to_cpu(dscr->attr); 625 dscr->attr &= 0xfffffff8; 626 dscr->incr = 12; 627 break; 628 } 629 } 630 631 /* Advanced DMA data transfer */ 632 633 static void sdhci_do_adma(SDHCIState *s) 634 { 635 unsigned int n, begin, length; 636 const uint16_t block_size = s->blksize & 0x0fff; 637 ADMADescr dscr; 638 int i; 639 640 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { 641 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; 642 643 get_adma_description(s, &dscr); 644 DPRINT_L2("ADMA loop: addr=" TARGET_FMT_plx ", len=%d, attr=%x\n", 645 dscr.addr, dscr.length, dscr.attr); 646 647 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { 648 /* Indicate that error occurred in ST_FDS state */ 649 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; 650 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; 651 652 /* Generate ADMA error interrupt */ 653 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 654 s->errintsts |= SDHC_EIS_ADMAERR; 655 s->norintsts |= SDHC_NIS_ERR; 656 } 657 658 sdhci_update_irq(s); 659 return; 660 } 661 662 length = dscr.length ? dscr.length : 65536; 663 664 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { 665 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ 666 667 if (s->trnmod & SDHC_TRNS_READ) { 668 while (length) { 669 if (s->data_count == 0) { 670 for (n = 0; n < block_size; n++) { 671 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 672 } 673 } 674 begin = s->data_count; 675 if ((length + begin) < block_size) { 676 s->data_count = length + begin; 677 length = 0; 678 } else { 679 s->data_count = block_size; 680 length -= block_size - begin; 681 } 682 dma_memory_write(&address_space_memory, dscr.addr, 683 &s->fifo_buffer[begin], 684 s->data_count - begin); 685 dscr.addr += s->data_count - begin; 686 if (s->data_count == block_size) { 687 s->data_count = 0; 688 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 689 s->blkcnt--; 690 if (s->blkcnt == 0) { 691 break; 692 } 693 } 694 } 695 } 696 } else { 697 while (length) { 698 begin = s->data_count; 699 if ((length + begin) < block_size) { 700 s->data_count = length + begin; 701 length = 0; 702 } else { 703 s->data_count = block_size; 704 length -= block_size - begin; 705 } 706 dma_memory_read(&address_space_memory, dscr.addr, 707 &s->fifo_buffer[begin], 708 s->data_count - begin); 709 dscr.addr += s->data_count - begin; 710 if (s->data_count == block_size) { 711 for (n = 0; n < block_size; n++) { 712 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 713 } 714 s->data_count = 0; 715 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 716 s->blkcnt--; 717 if (s->blkcnt == 0) { 718 break; 719 } 720 } 721 } 722 } 723 } 724 s->admasysaddr += dscr.incr; 725 break; 726 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ 727 s->admasysaddr = dscr.addr; 728 DPRINT_L1("ADMA link: admasysaddr=0x%" PRIx64 "\n", 729 s->admasysaddr); 730 break; 731 default: 732 s->admasysaddr += dscr.incr; 733 break; 734 } 735 736 if (dscr.attr & SDHC_ADMA_ATTR_INT) { 737 DPRINT_L1("ADMA interrupt: admasysaddr=0x%" PRIx64 "\n", 738 s->admasysaddr); 739 if (s->norintstsen & SDHC_NISEN_DMA) { 740 s->norintsts |= SDHC_NIS_DMA; 741 } 742 743 sdhci_update_irq(s); 744 } 745 746 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ 747 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 748 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { 749 DPRINT_L2("ADMA transfer completed\n"); 750 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && 751 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 752 s->blkcnt != 0)) { 753 ERRPRINT("SD/MMC host ADMA length mismatch\n"); 754 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | 755 SDHC_ADMAERR_STATE_ST_TFR; 756 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 757 ERRPRINT("Set ADMA error flag\n"); 758 s->errintsts |= SDHC_EIS_ADMAERR; 759 s->norintsts |= SDHC_NIS_ERR; 760 } 761 762 sdhci_update_irq(s); 763 } 764 sdhci_end_transfer(s); 765 return; 766 } 767 768 } 769 770 /* we have unfinished business - reschedule to continue ADMA */ 771 timer_mod(s->transfer_timer, 772 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY); 773 } 774 775 /* Perform data transfer according to controller configuration */ 776 777 static void sdhci_data_transfer(void *opaque) 778 { 779 SDHCIState *s = (SDHCIState *)opaque; 780 781 if (s->trnmod & SDHC_TRNS_DMA) { 782 switch (SDHC_DMA_TYPE(s->hostctl)) { 783 case SDHC_CTRL_SDMA: 784 if ((s->trnmod & SDHC_TRNS_MULTI) && 785 (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || s->blkcnt == 0)) { 786 break; 787 } 788 789 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { 790 sdhci_sdma_transfer_single_block(s); 791 } else { 792 sdhci_sdma_transfer_multi_blocks(s); 793 } 794 795 break; 796 case SDHC_CTRL_ADMA1_32: 797 if (!(s->capareg & SDHC_CAN_DO_ADMA1)) { 798 ERRPRINT("ADMA1 not supported\n"); 799 break; 800 } 801 802 sdhci_do_adma(s); 803 break; 804 case SDHC_CTRL_ADMA2_32: 805 if (!(s->capareg & SDHC_CAN_DO_ADMA2)) { 806 ERRPRINT("ADMA2 not supported\n"); 807 break; 808 } 809 810 sdhci_do_adma(s); 811 break; 812 case SDHC_CTRL_ADMA2_64: 813 if (!(s->capareg & SDHC_CAN_DO_ADMA2) || 814 !(s->capareg & SDHC_64_BIT_BUS_SUPPORT)) { 815 ERRPRINT("64 bit ADMA not supported\n"); 816 break; 817 } 818 819 sdhci_do_adma(s); 820 break; 821 default: 822 ERRPRINT("Unsupported DMA type\n"); 823 break; 824 } 825 } else { 826 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) { 827 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 828 SDHC_DAT_LINE_ACTIVE; 829 sdhci_read_block_from_card(s); 830 } else { 831 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | 832 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; 833 sdhci_write_block_to_card(s); 834 } 835 } 836 } 837 838 static bool sdhci_can_issue_command(SDHCIState *s) 839 { 840 if (!SDHC_CLOCK_IS_ON(s->clkcon) || 841 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && 842 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || 843 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && 844 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { 845 return false; 846 } 847 848 return true; 849 } 850 851 /* The Buffer Data Port register must be accessed in sequential and 852 * continuous manner */ 853 static inline bool 854 sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) 855 { 856 if ((s->data_count & 0x3) != byte_num) { 857 ERRPRINT("Non-sequential access to Buffer Data Port register" 858 "is prohibited\n"); 859 return false; 860 } 861 return true; 862 } 863 864 static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) 865 { 866 SDHCIState *s = (SDHCIState *)opaque; 867 uint32_t ret = 0; 868 869 switch (offset & ~0x3) { 870 case SDHC_SYSAD: 871 ret = s->sdmasysad; 872 break; 873 case SDHC_BLKSIZE: 874 ret = s->blksize | (s->blkcnt << 16); 875 break; 876 case SDHC_ARGUMENT: 877 ret = s->argument; 878 break; 879 case SDHC_TRNMOD: 880 ret = s->trnmod | (s->cmdreg << 16); 881 break; 882 case SDHC_RSPREG0 ... SDHC_RSPREG3: 883 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; 884 break; 885 case SDHC_BDATA: 886 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 887 ret = sdhci_read_dataport(s, size); 888 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset, 889 ret, ret); 890 return ret; 891 } 892 break; 893 case SDHC_PRNSTS: 894 ret = s->prnsts; 895 break; 896 case SDHC_HOSTCTL: 897 ret = s->hostctl | (s->pwrcon << 8) | (s->blkgap << 16) | 898 (s->wakcon << 24); 899 break; 900 case SDHC_CLKCON: 901 ret = s->clkcon | (s->timeoutcon << 16); 902 break; 903 case SDHC_NORINTSTS: 904 ret = s->norintsts | (s->errintsts << 16); 905 break; 906 case SDHC_NORINTSTSEN: 907 ret = s->norintstsen | (s->errintstsen << 16); 908 break; 909 case SDHC_NORINTSIGEN: 910 ret = s->norintsigen | (s->errintsigen << 16); 911 break; 912 case SDHC_ACMD12ERRSTS: 913 ret = s->acmd12errsts; 914 break; 915 case SDHC_CAPAREG: 916 ret = s->capareg; 917 break; 918 case SDHC_MAXCURR: 919 ret = s->maxcurr; 920 break; 921 case SDHC_ADMAERR: 922 ret = s->admaerr; 923 break; 924 case SDHC_ADMASYSADDR: 925 ret = (uint32_t)s->admasysaddr; 926 break; 927 case SDHC_ADMASYSADDR + 4: 928 ret = (uint32_t)(s->admasysaddr >> 32); 929 break; 930 case SDHC_SLOT_INT_STATUS: 931 ret = (SD_HOST_SPECv2_VERS << 16) | sdhci_slotint(s); 932 break; 933 default: 934 ERRPRINT("bad %ub read: addr[0x%04x]\n", size, (int)offset); 935 break; 936 } 937 938 ret >>= (offset & 0x3) * 8; 939 ret &= (1ULL << (size * 8)) - 1; 940 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset, ret, ret); 941 return ret; 942 } 943 944 static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) 945 { 946 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { 947 return; 948 } 949 s->blkgap = value & SDHC_STOP_AT_GAP_REQ; 950 951 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && 952 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { 953 if (s->stopped_state == sdhc_gap_read) { 954 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; 955 sdhci_read_block_from_card(s); 956 } else { 957 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; 958 sdhci_write_block_to_card(s); 959 } 960 s->stopped_state = sdhc_not_stopped; 961 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { 962 if (s->prnsts & SDHC_DOING_READ) { 963 s->stopped_state = sdhc_gap_read; 964 } else if (s->prnsts & SDHC_DOING_WRITE) { 965 s->stopped_state = sdhc_gap_write; 966 } 967 } 968 } 969 970 static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) 971 { 972 switch (value) { 973 case SDHC_RESET_ALL: 974 sdhci_reset(s); 975 break; 976 case SDHC_RESET_CMD: 977 s->prnsts &= ~SDHC_CMD_INHIBIT; 978 s->norintsts &= ~SDHC_NIS_CMDCMP; 979 break; 980 case SDHC_RESET_DATA: 981 s->data_count = 0; 982 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | 983 SDHC_DOING_READ | SDHC_DOING_WRITE | 984 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); 985 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); 986 s->stopped_state = sdhc_not_stopped; 987 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | 988 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); 989 break; 990 } 991 } 992 993 static void 994 sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 995 { 996 SDHCIState *s = (SDHCIState *)opaque; 997 unsigned shift = 8 * (offset & 0x3); 998 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); 999 uint32_t value = val; 1000 value <<= shift; 1001 1002 switch (offset & ~0x3) { 1003 case SDHC_SYSAD: 1004 s->sdmasysad = (s->sdmasysad & mask) | value; 1005 MASKED_WRITE(s->sdmasysad, mask, value); 1006 /* Writing to last byte of sdmasysad might trigger transfer */ 1007 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && 1008 s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) { 1009 sdhci_sdma_transfer_multi_blocks(s); 1010 } 1011 break; 1012 case SDHC_BLKSIZE: 1013 if (!TRANSFERRING_DATA(s->prnsts)) { 1014 MASKED_WRITE(s->blksize, mask, value); 1015 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); 1016 } 1017 1018 /* Limit block size to the maximum buffer size */ 1019 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) { 1020 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " \ 1021 "the maximum buffer 0x%x", __func__, s->blksize, 1022 s->buf_maxsz); 1023 1024 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz); 1025 } 1026 1027 break; 1028 case SDHC_ARGUMENT: 1029 MASKED_WRITE(s->argument, mask, value); 1030 break; 1031 case SDHC_TRNMOD: 1032 /* DMA can be enabled only if it is supported as indicated by 1033 * capabilities register */ 1034 if (!(s->capareg & SDHC_CAN_DO_DMA)) { 1035 value &= ~SDHC_TRNS_DMA; 1036 } 1037 MASKED_WRITE(s->trnmod, mask, value); 1038 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); 1039 1040 /* Writing to the upper byte of CMDREG triggers SD command generation */ 1041 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { 1042 break; 1043 } 1044 1045 sdhci_send_command(s); 1046 break; 1047 case SDHC_BDATA: 1048 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1049 sdhci_write_dataport(s, value >> shift, size); 1050 } 1051 break; 1052 case SDHC_HOSTCTL: 1053 if (!(mask & 0xFF0000)) { 1054 sdhci_blkgap_write(s, value >> 16); 1055 } 1056 MASKED_WRITE(s->hostctl, mask, value); 1057 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); 1058 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); 1059 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || 1060 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { 1061 s->pwrcon &= ~SDHC_POWER_ON; 1062 } 1063 break; 1064 case SDHC_CLKCON: 1065 if (!(mask & 0xFF000000)) { 1066 sdhci_reset_write(s, value >> 24); 1067 } 1068 MASKED_WRITE(s->clkcon, mask, value); 1069 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); 1070 if (s->clkcon & SDHC_CLOCK_INT_EN) { 1071 s->clkcon |= SDHC_CLOCK_INT_STABLE; 1072 } else { 1073 s->clkcon &= ~SDHC_CLOCK_INT_STABLE; 1074 } 1075 break; 1076 case SDHC_NORINTSTS: 1077 if (s->norintstsen & SDHC_NISEN_CARDINT) { 1078 value &= ~SDHC_NIS_CARDINT; 1079 } 1080 s->norintsts &= mask | ~value; 1081 s->errintsts &= (mask >> 16) | ~(value >> 16); 1082 if (s->errintsts) { 1083 s->norintsts |= SDHC_NIS_ERR; 1084 } else { 1085 s->norintsts &= ~SDHC_NIS_ERR; 1086 } 1087 sdhci_update_irq(s); 1088 break; 1089 case SDHC_NORINTSTSEN: 1090 MASKED_WRITE(s->norintstsen, mask, value); 1091 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); 1092 s->norintsts &= s->norintstsen; 1093 s->errintsts &= s->errintstsen; 1094 if (s->errintsts) { 1095 s->norintsts |= SDHC_NIS_ERR; 1096 } else { 1097 s->norintsts &= ~SDHC_NIS_ERR; 1098 } 1099 /* Quirk for Raspberry Pi: pending card insert interrupt 1100 * appears when first enabled after power on */ 1101 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { 1102 assert(s->pending_insert_quirk); 1103 s->norintsts |= SDHC_NIS_INSERT; 1104 s->pending_insert_state = false; 1105 } 1106 sdhci_update_irq(s); 1107 break; 1108 case SDHC_NORINTSIGEN: 1109 MASKED_WRITE(s->norintsigen, mask, value); 1110 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); 1111 sdhci_update_irq(s); 1112 break; 1113 case SDHC_ADMAERR: 1114 MASKED_WRITE(s->admaerr, mask, value); 1115 break; 1116 case SDHC_ADMASYSADDR: 1117 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | 1118 (uint64_t)mask)) | (uint64_t)value; 1119 break; 1120 case SDHC_ADMASYSADDR + 4: 1121 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | 1122 ((uint64_t)mask << 32))) | ((uint64_t)value << 32); 1123 break; 1124 case SDHC_FEAER: 1125 s->acmd12errsts |= value; 1126 s->errintsts |= (value >> 16) & s->errintstsen; 1127 if (s->acmd12errsts) { 1128 s->errintsts |= SDHC_EIS_CMD12ERR; 1129 } 1130 if (s->errintsts) { 1131 s->norintsts |= SDHC_NIS_ERR; 1132 } 1133 sdhci_update_irq(s); 1134 break; 1135 default: 1136 ERRPRINT("bad %ub write offset: addr[0x%04x] <- %u(0x%x)\n", 1137 size, (int)offset, value >> shift, value >> shift); 1138 break; 1139 } 1140 DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n", 1141 size, (int)offset, value >> shift, value >> shift); 1142 } 1143 1144 static const MemoryRegionOps sdhci_mmio_ops = { 1145 .read = sdhci_read, 1146 .write = sdhci_write, 1147 .valid = { 1148 .min_access_size = 1, 1149 .max_access_size = 4, 1150 .unaligned = false 1151 }, 1152 .endianness = DEVICE_LITTLE_ENDIAN, 1153 }; 1154 1155 static inline unsigned int sdhci_get_fifolen(SDHCIState *s) 1156 { 1157 switch (SDHC_CAPAB_BLOCKSIZE(s->capareg)) { 1158 case 0: 1159 return 512; 1160 case 1: 1161 return 1024; 1162 case 2: 1163 return 2048; 1164 default: 1165 hw_error("SDHC: unsupported value for maximum block size\n"); 1166 return 0; 1167 } 1168 } 1169 1170 static void sdhci_initfn(SDHCIState *s) 1171 { 1172 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), 1173 TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); 1174 1175 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); 1176 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); 1177 } 1178 1179 static void sdhci_uninitfn(SDHCIState *s) 1180 { 1181 timer_del(s->insert_timer); 1182 timer_free(s->insert_timer); 1183 timer_del(s->transfer_timer); 1184 timer_free(s->transfer_timer); 1185 qemu_free_irq(s->eject_cb); 1186 qemu_free_irq(s->ro_cb); 1187 1188 g_free(s->fifo_buffer); 1189 s->fifo_buffer = NULL; 1190 } 1191 1192 static bool sdhci_pending_insert_vmstate_needed(void *opaque) 1193 { 1194 SDHCIState *s = opaque; 1195 1196 return s->pending_insert_state; 1197 } 1198 1199 static const VMStateDescription sdhci_pending_insert_vmstate = { 1200 .name = "sdhci/pending-insert", 1201 .version_id = 1, 1202 .minimum_version_id = 1, 1203 .needed = sdhci_pending_insert_vmstate_needed, 1204 .fields = (VMStateField[]) { 1205 VMSTATE_BOOL(pending_insert_state, SDHCIState), 1206 VMSTATE_END_OF_LIST() 1207 }, 1208 }; 1209 1210 const VMStateDescription sdhci_vmstate = { 1211 .name = "sdhci", 1212 .version_id = 1, 1213 .minimum_version_id = 1, 1214 .fields = (VMStateField[]) { 1215 VMSTATE_UINT32(sdmasysad, SDHCIState), 1216 VMSTATE_UINT16(blksize, SDHCIState), 1217 VMSTATE_UINT16(blkcnt, SDHCIState), 1218 VMSTATE_UINT32(argument, SDHCIState), 1219 VMSTATE_UINT16(trnmod, SDHCIState), 1220 VMSTATE_UINT16(cmdreg, SDHCIState), 1221 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), 1222 VMSTATE_UINT32(prnsts, SDHCIState), 1223 VMSTATE_UINT8(hostctl, SDHCIState), 1224 VMSTATE_UINT8(pwrcon, SDHCIState), 1225 VMSTATE_UINT8(blkgap, SDHCIState), 1226 VMSTATE_UINT8(wakcon, SDHCIState), 1227 VMSTATE_UINT16(clkcon, SDHCIState), 1228 VMSTATE_UINT8(timeoutcon, SDHCIState), 1229 VMSTATE_UINT8(admaerr, SDHCIState), 1230 VMSTATE_UINT16(norintsts, SDHCIState), 1231 VMSTATE_UINT16(errintsts, SDHCIState), 1232 VMSTATE_UINT16(norintstsen, SDHCIState), 1233 VMSTATE_UINT16(errintstsen, SDHCIState), 1234 VMSTATE_UINT16(norintsigen, SDHCIState), 1235 VMSTATE_UINT16(errintsigen, SDHCIState), 1236 VMSTATE_UINT16(acmd12errsts, SDHCIState), 1237 VMSTATE_UINT16(data_count, SDHCIState), 1238 VMSTATE_UINT64(admasysaddr, SDHCIState), 1239 VMSTATE_UINT8(stopped_state, SDHCIState), 1240 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, 0, buf_maxsz), 1241 VMSTATE_TIMER_PTR(insert_timer, SDHCIState), 1242 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState), 1243 VMSTATE_END_OF_LIST() 1244 }, 1245 .subsections = (const VMStateDescription*[]) { 1246 &sdhci_pending_insert_vmstate, 1247 NULL 1248 }, 1249 }; 1250 1251 /* Capabilities registers provide information on supported features of this 1252 * specific host controller implementation */ 1253 static Property sdhci_pci_properties[] = { 1254 DEFINE_PROP_UINT32("capareg", SDHCIState, capareg, 1255 SDHC_CAPAB_REG_DEFAULT), 1256 DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0), 1257 DEFINE_PROP_END_OF_LIST(), 1258 }; 1259 1260 static void sdhci_pci_realize(PCIDevice *dev, Error **errp) 1261 { 1262 SDHCIState *s = PCI_SDHCI(dev); 1263 dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */ 1264 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ 1265 sdhci_initfn(s); 1266 s->buf_maxsz = sdhci_get_fifolen(s); 1267 s->fifo_buffer = g_malloc0(s->buf_maxsz); 1268 s->irq = pci_allocate_irq(dev); 1269 memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci", 1270 SDHC_REGISTERS_MAP_SIZE); 1271 pci_register_bar(dev, 0, 0, &s->iomem); 1272 } 1273 1274 static void sdhci_pci_exit(PCIDevice *dev) 1275 { 1276 SDHCIState *s = PCI_SDHCI(dev); 1277 sdhci_uninitfn(s); 1278 } 1279 1280 static void sdhci_pci_class_init(ObjectClass *klass, void *data) 1281 { 1282 DeviceClass *dc = DEVICE_CLASS(klass); 1283 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1284 1285 k->realize = sdhci_pci_realize; 1286 k->exit = sdhci_pci_exit; 1287 k->vendor_id = PCI_VENDOR_ID_REDHAT; 1288 k->device_id = PCI_DEVICE_ID_REDHAT_SDHCI; 1289 k->class_id = PCI_CLASS_SYSTEM_SDHCI; 1290 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1291 dc->vmsd = &sdhci_vmstate; 1292 dc->props = sdhci_pci_properties; 1293 } 1294 1295 static const TypeInfo sdhci_pci_info = { 1296 .name = TYPE_PCI_SDHCI, 1297 .parent = TYPE_PCI_DEVICE, 1298 .instance_size = sizeof(SDHCIState), 1299 .class_init = sdhci_pci_class_init, 1300 }; 1301 1302 static Property sdhci_sysbus_properties[] = { 1303 DEFINE_PROP_UINT32("capareg", SDHCIState, capareg, 1304 SDHC_CAPAB_REG_DEFAULT), 1305 DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0), 1306 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, 1307 false), 1308 DEFINE_PROP_END_OF_LIST(), 1309 }; 1310 1311 static void sdhci_sysbus_init(Object *obj) 1312 { 1313 SDHCIState *s = SYSBUS_SDHCI(obj); 1314 1315 sdhci_initfn(s); 1316 } 1317 1318 static void sdhci_sysbus_finalize(Object *obj) 1319 { 1320 SDHCIState *s = SYSBUS_SDHCI(obj); 1321 sdhci_uninitfn(s); 1322 } 1323 1324 static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp) 1325 { 1326 SDHCIState *s = SYSBUS_SDHCI(dev); 1327 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1328 1329 s->buf_maxsz = sdhci_get_fifolen(s); 1330 s->fifo_buffer = g_malloc0(s->buf_maxsz); 1331 sysbus_init_irq(sbd, &s->irq); 1332 memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci", 1333 SDHC_REGISTERS_MAP_SIZE); 1334 sysbus_init_mmio(sbd, &s->iomem); 1335 1336 if (s->pending_insert_quirk) { 1337 s->pending_insert_state = true; 1338 } 1339 } 1340 1341 static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) 1342 { 1343 DeviceClass *dc = DEVICE_CLASS(klass); 1344 1345 dc->vmsd = &sdhci_vmstate; 1346 dc->props = sdhci_sysbus_properties; 1347 dc->realize = sdhci_sysbus_realize; 1348 } 1349 1350 static const TypeInfo sdhci_sysbus_info = { 1351 .name = TYPE_SYSBUS_SDHCI, 1352 .parent = TYPE_SYS_BUS_DEVICE, 1353 .instance_size = sizeof(SDHCIState), 1354 .instance_init = sdhci_sysbus_init, 1355 .instance_finalize = sdhci_sysbus_finalize, 1356 .class_init = sdhci_sysbus_class_init, 1357 }; 1358 1359 static void sdhci_bus_class_init(ObjectClass *klass, void *data) 1360 { 1361 SDBusClass *sbc = SD_BUS_CLASS(klass); 1362 1363 sbc->set_inserted = sdhci_set_inserted; 1364 sbc->set_readonly = sdhci_set_readonly; 1365 } 1366 1367 static const TypeInfo sdhci_bus_info = { 1368 .name = TYPE_SDHCI_BUS, 1369 .parent = TYPE_SD_BUS, 1370 .instance_size = sizeof(SDBus), 1371 .class_init = sdhci_bus_class_init, 1372 }; 1373 1374 static void sdhci_register_types(void) 1375 { 1376 type_register_static(&sdhci_pci_info); 1377 type_register_static(&sdhci_sysbus_info); 1378 type_register_static(&sdhci_bus_info); 1379 } 1380 1381 type_init(sdhci_register_types) 1382