1 /* 2 * SD Association Host Standard Specification v2.0 controller emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Mitsyanko Igor <i.mitsyanko@samsung.com> 6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 7 * 8 * Based on MMC controller for Samsung S5PC1xx-based board emulation 9 * by Alexey Merkulov and Vladimir Monakhov. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 19 * See the GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qemu/error-report.h" 28 #include "qapi/error.h" 29 #include "hw/hw.h" 30 #include "sysemu/dma.h" 31 #include "qemu/timer.h" 32 #include "qemu/bitops.h" 33 #include "hw/sd/sdhci.h" 34 #include "sdhci-internal.h" 35 #include "qemu/log.h" 36 #include "qemu/module.h" 37 #include "trace.h" 38 39 #define TYPE_SDHCI_BUS "sdhci-bus" 40 #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS) 41 42 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) 43 44 static inline unsigned int sdhci_get_fifolen(SDHCIState *s) 45 { 46 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); 47 } 48 49 /* return true on error */ 50 static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, 51 uint8_t freq, Error **errp) 52 { 53 if (s->sd_spec_version >= 3) { 54 return false; 55 } 56 switch (freq) { 57 case 0: 58 case 10 ... 63: 59 break; 60 default: 61 error_setg(errp, "SD %s clock frequency can have value" 62 "in range 0-63 only", desc); 63 return true; 64 } 65 return false; 66 } 67 68 static void sdhci_check_capareg(SDHCIState *s, Error **errp) 69 { 70 uint64_t msk = s->capareg; 71 uint32_t val; 72 bool y; 73 74 switch (s->sd_spec_version) { 75 case 4: 76 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4); 77 trace_sdhci_capareg("64-bit system bus (v4)", val); 78 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0); 79 80 val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II); 81 trace_sdhci_capareg("UHS-II", val); 82 msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0); 83 84 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3); 85 trace_sdhci_capareg("ADMA3", val); 86 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0); 87 88 /* fallthrough */ 89 case 3: 90 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT); 91 trace_sdhci_capareg("async interrupt", val); 92 msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0); 93 94 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE); 95 if (val) { 96 error_setg(errp, "slot-type not supported"); 97 return; 98 } 99 trace_sdhci_capareg("slot type", val); 100 msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0); 101 102 if (val != 2) { 103 val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT); 104 trace_sdhci_capareg("8-bit bus", val); 105 } 106 msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0); 107 108 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED); 109 trace_sdhci_capareg("bus speed mask", val); 110 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0); 111 112 val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH); 113 trace_sdhci_capareg("driver strength mask", val); 114 msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0); 115 116 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING); 117 trace_sdhci_capareg("timer re-tuning", val); 118 msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0); 119 120 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING); 121 trace_sdhci_capareg("use SDR50 tuning", val); 122 msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0); 123 124 val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE); 125 trace_sdhci_capareg("re-tuning mode", val); 126 msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0); 127 128 val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT); 129 trace_sdhci_capareg("clock multiplier", val); 130 msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0); 131 132 /* fallthrough */ 133 case 2: /* default version */ 134 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2); 135 trace_sdhci_capareg("ADMA2", val); 136 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0); 137 138 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1); 139 trace_sdhci_capareg("ADMA1", val); 140 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0); 141 142 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT); 143 trace_sdhci_capareg("64-bit system bus (v3)", val); 144 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0); 145 146 /* fallthrough */ 147 case 1: 148 y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT); 149 msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0); 150 151 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ); 152 trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val); 153 if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) { 154 return; 155 } 156 msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0); 157 158 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ); 159 trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val); 160 if (sdhci_check_capab_freq_range(s, "base", val, errp)) { 161 return; 162 } 163 msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0); 164 165 val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH); 166 if (val >= 3) { 167 error_setg(errp, "block size can be 512, 1024 or 2048 only"); 168 return; 169 } 170 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s)); 171 msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0); 172 173 val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED); 174 trace_sdhci_capareg("high speed", val); 175 msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0); 176 177 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA); 178 trace_sdhci_capareg("SDMA", val); 179 msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0); 180 181 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME); 182 trace_sdhci_capareg("suspend/resume", val); 183 msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0); 184 185 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33); 186 trace_sdhci_capareg("3.3v", val); 187 msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0); 188 189 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30); 190 trace_sdhci_capareg("3.0v", val); 191 msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0); 192 193 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18); 194 trace_sdhci_capareg("1.8v", val); 195 msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0); 196 break; 197 198 default: 199 error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version); 200 } 201 if (msk) { 202 qemu_log_mask(LOG_UNIMP, 203 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk); 204 } 205 } 206 207 static uint8_t sdhci_slotint(SDHCIState *s) 208 { 209 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || 210 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || 211 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); 212 } 213 214 static inline void sdhci_update_irq(SDHCIState *s) 215 { 216 qemu_set_irq(s->irq, sdhci_slotint(s)); 217 } 218 219 static void sdhci_raise_insertion_irq(void *opaque) 220 { 221 SDHCIState *s = (SDHCIState *)opaque; 222 223 if (s->norintsts & SDHC_NIS_REMOVE) { 224 timer_mod(s->insert_timer, 225 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 226 } else { 227 s->prnsts = 0x1ff0000; 228 if (s->norintstsen & SDHC_NISEN_INSERT) { 229 s->norintsts |= SDHC_NIS_INSERT; 230 } 231 sdhci_update_irq(s); 232 } 233 } 234 235 static void sdhci_set_inserted(DeviceState *dev, bool level) 236 { 237 SDHCIState *s = (SDHCIState *)dev; 238 239 trace_sdhci_set_inserted(level ? "insert" : "eject"); 240 if ((s->norintsts & SDHC_NIS_REMOVE) && level) { 241 /* Give target some time to notice card ejection */ 242 timer_mod(s->insert_timer, 243 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 244 } else { 245 if (level) { 246 s->prnsts = 0x1ff0000; 247 if (s->norintstsen & SDHC_NISEN_INSERT) { 248 s->norintsts |= SDHC_NIS_INSERT; 249 } 250 } else { 251 s->prnsts = 0x1fa0000; 252 s->pwrcon &= ~SDHC_POWER_ON; 253 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; 254 if (s->norintstsen & SDHC_NISEN_REMOVE) { 255 s->norintsts |= SDHC_NIS_REMOVE; 256 } 257 } 258 sdhci_update_irq(s); 259 } 260 } 261 262 static void sdhci_set_readonly(DeviceState *dev, bool level) 263 { 264 SDHCIState *s = (SDHCIState *)dev; 265 266 if (level) { 267 s->prnsts &= ~SDHC_WRITE_PROTECT; 268 } else { 269 /* Write enabled */ 270 s->prnsts |= SDHC_WRITE_PROTECT; 271 } 272 } 273 274 static void sdhci_reset(SDHCIState *s) 275 { 276 DeviceState *dev = DEVICE(s); 277 278 timer_del(s->insert_timer); 279 timer_del(s->transfer_timer); 280 281 /* Set all registers to 0. Capabilities/Version registers are not cleared 282 * and assumed to always preserve their value, given to them during 283 * initialization */ 284 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); 285 286 /* Reset other state based on current card insertion/readonly status */ 287 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus)); 288 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus)); 289 290 s->data_count = 0; 291 s->stopped_state = sdhc_not_stopped; 292 s->pending_insert_state = false; 293 } 294 295 static void sdhci_poweron_reset(DeviceState *dev) 296 { 297 /* QOM (ie power-on) reset. This is identical to reset 298 * commanded via device register apart from handling of the 299 * 'pending insert on powerup' quirk. 300 */ 301 SDHCIState *s = (SDHCIState *)dev; 302 303 sdhci_reset(s); 304 305 if (s->pending_insert_quirk) { 306 s->pending_insert_state = true; 307 } 308 } 309 310 static void sdhci_data_transfer(void *opaque); 311 312 static void sdhci_send_command(SDHCIState *s) 313 { 314 SDRequest request; 315 uint8_t response[16]; 316 int rlen; 317 318 s->errintsts = 0; 319 s->acmd12errsts = 0; 320 request.cmd = s->cmdreg >> 8; 321 request.arg = s->argument; 322 323 trace_sdhci_send_command(request.cmd, request.arg); 324 rlen = sdbus_do_command(&s->sdbus, &request, response); 325 326 if (s->cmdreg & SDHC_CMD_RESPONSE) { 327 if (rlen == 4) { 328 s->rspreg[0] = ldl_be_p(response); 329 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; 330 trace_sdhci_response4(s->rspreg[0]); 331 } else if (rlen == 16) { 332 s->rspreg[0] = ldl_be_p(&response[11]); 333 s->rspreg[1] = ldl_be_p(&response[7]); 334 s->rspreg[2] = ldl_be_p(&response[3]); 335 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | 336 response[2]; 337 trace_sdhci_response16(s->rspreg[3], s->rspreg[2], 338 s->rspreg[1], s->rspreg[0]); 339 } else { 340 trace_sdhci_error("timeout waiting for command response"); 341 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { 342 s->errintsts |= SDHC_EIS_CMDTIMEOUT; 343 s->norintsts |= SDHC_NIS_ERR; 344 } 345 } 346 347 if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && 348 (s->norintstsen & SDHC_NISEN_TRSCMP) && 349 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { 350 s->norintsts |= SDHC_NIS_TRSCMP; 351 } 352 } 353 354 if (s->norintstsen & SDHC_NISEN_CMDCMP) { 355 s->norintsts |= SDHC_NIS_CMDCMP; 356 } 357 358 sdhci_update_irq(s); 359 360 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { 361 s->data_count = 0; 362 sdhci_data_transfer(s); 363 } 364 } 365 366 static void sdhci_end_transfer(SDHCIState *s) 367 { 368 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */ 369 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { 370 SDRequest request; 371 uint8_t response[16]; 372 373 request.cmd = 0x0C; 374 request.arg = 0; 375 trace_sdhci_end_transfer(request.cmd, request.arg); 376 sdbus_do_command(&s->sdbus, &request, response); 377 /* Auto CMD12 response goes to the upper Response register */ 378 s->rspreg[3] = ldl_be_p(response); 379 } 380 381 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | 382 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | 383 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); 384 385 if (s->norintstsen & SDHC_NISEN_TRSCMP) { 386 s->norintsts |= SDHC_NIS_TRSCMP; 387 } 388 389 sdhci_update_irq(s); 390 } 391 392 /* 393 * Programmed i/o data transfer 394 */ 395 #define BLOCK_SIZE_MASK (4 * KiB - 1) 396 397 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ 398 static void sdhci_read_block_from_card(SDHCIState *s) 399 { 400 int index = 0; 401 uint8_t data; 402 const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK; 403 404 if ((s->trnmod & SDHC_TRNS_MULTI) && 405 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { 406 return; 407 } 408 409 for (index = 0; index < blk_size; index++) { 410 data = sdbus_read_data(&s->sdbus); 411 if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 412 /* Device is not in tuning */ 413 s->fifo_buffer[index] = data; 414 } 415 } 416 417 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 418 /* Device is in tuning */ 419 s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK; 420 s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK; 421 s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ | 422 SDHC_DATA_INHIBIT); 423 goto read_done; 424 } 425 426 /* New data now available for READ through Buffer Port Register */ 427 s->prnsts |= SDHC_DATA_AVAILABLE; 428 if (s->norintstsen & SDHC_NISEN_RBUFRDY) { 429 s->norintsts |= SDHC_NIS_RBUFRDY; 430 } 431 432 /* Clear DAT line active status if that was the last block */ 433 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 434 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { 435 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 436 } 437 438 /* If stop at block gap request was set and it's not the last block of 439 * data - generate Block Event interrupt */ 440 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && 441 s->blkcnt != 1) { 442 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 443 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 444 s->norintsts |= SDHC_EIS_BLKGAP; 445 } 446 } 447 448 read_done: 449 sdhci_update_irq(s); 450 } 451 452 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */ 453 static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) 454 { 455 uint32_t value = 0; 456 int i; 457 458 /* first check that a valid data exists in host controller input buffer */ 459 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { 460 trace_sdhci_error("read from empty buffer"); 461 return 0; 462 } 463 464 for (i = 0; i < size; i++) { 465 value |= s->fifo_buffer[s->data_count] << i * 8; 466 s->data_count++; 467 /* check if we've read all valid data (blksize bytes) from buffer */ 468 if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) { 469 trace_sdhci_read_dataport(s->data_count); 470 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ 471 s->data_count = 0; /* next buff read must start at position [0] */ 472 473 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 474 s->blkcnt--; 475 } 476 477 /* if that was the last block of data */ 478 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 479 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || 480 /* stop at gap request */ 481 (s->stopped_state == sdhc_gap_read && 482 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { 483 sdhci_end_transfer(s); 484 } else { /* if there are more data, read next block from card */ 485 sdhci_read_block_from_card(s); 486 } 487 break; 488 } 489 } 490 491 return value; 492 } 493 494 /* Write data from host controller FIFO to card */ 495 static void sdhci_write_block_to_card(SDHCIState *s) 496 { 497 int index = 0; 498 499 if (s->prnsts & SDHC_SPACE_AVAILABLE) { 500 if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 501 s->norintsts |= SDHC_NIS_WBUFRDY; 502 } 503 sdhci_update_irq(s); 504 return; 505 } 506 507 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 508 if (s->blkcnt == 0) { 509 return; 510 } else { 511 s->blkcnt--; 512 } 513 } 514 515 for (index = 0; index < (s->blksize & BLOCK_SIZE_MASK); index++) { 516 sdbus_write_data(&s->sdbus, s->fifo_buffer[index]); 517 } 518 519 /* Next data can be written through BUFFER DATORT register */ 520 s->prnsts |= SDHC_SPACE_AVAILABLE; 521 522 /* Finish transfer if that was the last block of data */ 523 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 524 ((s->trnmod & SDHC_TRNS_MULTI) && 525 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { 526 sdhci_end_transfer(s); 527 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 528 s->norintsts |= SDHC_NIS_WBUFRDY; 529 } 530 531 /* Generate Block Gap Event if requested and if not the last block */ 532 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && 533 s->blkcnt > 0) { 534 s->prnsts &= ~SDHC_DOING_WRITE; 535 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 536 s->norintsts |= SDHC_EIS_BLKGAP; 537 } 538 sdhci_end_transfer(s); 539 } 540 541 sdhci_update_irq(s); 542 } 543 544 /* Write @size bytes of @value data to host controller @s Buffer Data Port 545 * register */ 546 static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) 547 { 548 unsigned i; 549 550 /* Check that there is free space left in a buffer */ 551 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { 552 trace_sdhci_error("Can't write to data buffer: buffer full"); 553 return; 554 } 555 556 for (i = 0; i < size; i++) { 557 s->fifo_buffer[s->data_count] = value & 0xFF; 558 s->data_count++; 559 value >>= 8; 560 if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) { 561 trace_sdhci_write_dataport(s->data_count); 562 s->data_count = 0; 563 s->prnsts &= ~SDHC_SPACE_AVAILABLE; 564 if (s->prnsts & SDHC_DOING_WRITE) { 565 sdhci_write_block_to_card(s); 566 } 567 } 568 } 569 } 570 571 /* 572 * Single DMA data transfer 573 */ 574 575 /* Multi block SDMA transfer */ 576 static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) 577 { 578 bool page_aligned = false; 579 unsigned int n, begin; 580 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 581 uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12); 582 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); 583 584 if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) { 585 qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n"); 586 return; 587 } 588 589 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for 590 * possible stop at page boundary if initial address is not page aligned, 591 * allow them to work properly */ 592 if ((s->sdmasysad % boundary_chk) == 0) { 593 page_aligned = true; 594 } 595 596 if (s->trnmod & SDHC_TRNS_READ) { 597 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 598 SDHC_DAT_LINE_ACTIVE; 599 while (s->blkcnt) { 600 if (s->data_count == 0) { 601 for (n = 0; n < block_size; n++) { 602 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 603 } 604 } 605 begin = s->data_count; 606 if (((boundary_count + begin) < block_size) && page_aligned) { 607 s->data_count = boundary_count + begin; 608 boundary_count = 0; 609 } else { 610 s->data_count = block_size; 611 boundary_count -= block_size - begin; 612 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 613 s->blkcnt--; 614 } 615 } 616 dma_memory_write(s->dma_as, s->sdmasysad, 617 &s->fifo_buffer[begin], s->data_count - begin); 618 s->sdmasysad += s->data_count - begin; 619 if (s->data_count == block_size) { 620 s->data_count = 0; 621 } 622 if (page_aligned && boundary_count == 0) { 623 break; 624 } 625 } 626 } else { 627 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT | 628 SDHC_DAT_LINE_ACTIVE; 629 while (s->blkcnt) { 630 begin = s->data_count; 631 if (((boundary_count + begin) < block_size) && page_aligned) { 632 s->data_count = boundary_count + begin; 633 boundary_count = 0; 634 } else { 635 s->data_count = block_size; 636 boundary_count -= block_size - begin; 637 } 638 dma_memory_read(s->dma_as, s->sdmasysad, 639 &s->fifo_buffer[begin], s->data_count - begin); 640 s->sdmasysad += s->data_count - begin; 641 if (s->data_count == block_size) { 642 for (n = 0; n < block_size; n++) { 643 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 644 } 645 s->data_count = 0; 646 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 647 s->blkcnt--; 648 } 649 } 650 if (page_aligned && boundary_count == 0) { 651 break; 652 } 653 } 654 } 655 656 if (s->blkcnt == 0) { 657 sdhci_end_transfer(s); 658 } else { 659 if (s->norintstsen & SDHC_NISEN_DMA) { 660 s->norintsts |= SDHC_NIS_DMA; 661 } 662 sdhci_update_irq(s); 663 } 664 } 665 666 /* single block SDMA transfer */ 667 static void sdhci_sdma_transfer_single_block(SDHCIState *s) 668 { 669 int n; 670 uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK; 671 672 if (s->trnmod & SDHC_TRNS_READ) { 673 for (n = 0; n < datacnt; n++) { 674 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 675 } 676 dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); 677 } else { 678 dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); 679 for (n = 0; n < datacnt; n++) { 680 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 681 } 682 } 683 s->blkcnt--; 684 685 sdhci_end_transfer(s); 686 } 687 688 typedef struct ADMADescr { 689 hwaddr addr; 690 uint16_t length; 691 uint8_t attr; 692 uint8_t incr; 693 } ADMADescr; 694 695 static void get_adma_description(SDHCIState *s, ADMADescr *dscr) 696 { 697 uint32_t adma1 = 0; 698 uint64_t adma2 = 0; 699 hwaddr entry_addr = (hwaddr)s->admasysaddr; 700 switch (SDHC_DMA_TYPE(s->hostctl1)) { 701 case SDHC_CTRL_ADMA2_32: 702 dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma2, 703 sizeof(adma2)); 704 adma2 = le64_to_cpu(adma2); 705 /* The spec does not specify endianness of descriptor table. 706 * We currently assume that it is LE. 707 */ 708 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; 709 dscr->length = (uint16_t)extract64(adma2, 16, 16); 710 dscr->attr = (uint8_t)extract64(adma2, 0, 7); 711 dscr->incr = 8; 712 break; 713 case SDHC_CTRL_ADMA1_32: 714 dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma1, 715 sizeof(adma1)); 716 adma1 = le32_to_cpu(adma1); 717 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); 718 dscr->attr = (uint8_t)extract32(adma1, 0, 7); 719 dscr->incr = 4; 720 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { 721 dscr->length = (uint16_t)extract32(adma1, 12, 16); 722 } else { 723 dscr->length = 4 * KiB; 724 } 725 break; 726 case SDHC_CTRL_ADMA2_64: 727 dma_memory_read(s->dma_as, entry_addr, 728 (uint8_t *)(&dscr->attr), 1); 729 dma_memory_read(s->dma_as, entry_addr + 2, 730 (uint8_t *)(&dscr->length), 2); 731 dscr->length = le16_to_cpu(dscr->length); 732 dma_memory_read(s->dma_as, entry_addr + 4, 733 (uint8_t *)(&dscr->addr), 8); 734 dscr->addr = le64_to_cpu(dscr->addr); 735 dscr->attr &= (uint8_t) ~0xC0; 736 dscr->incr = 12; 737 break; 738 } 739 } 740 741 /* Advanced DMA data transfer */ 742 743 static void sdhci_do_adma(SDHCIState *s) 744 { 745 unsigned int n, begin, length; 746 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 747 ADMADescr dscr = {}; 748 int i; 749 750 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { 751 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; 752 753 get_adma_description(s, &dscr); 754 trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr); 755 756 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { 757 /* Indicate that error occurred in ST_FDS state */ 758 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; 759 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; 760 761 /* Generate ADMA error interrupt */ 762 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 763 s->errintsts |= SDHC_EIS_ADMAERR; 764 s->norintsts |= SDHC_NIS_ERR; 765 } 766 767 sdhci_update_irq(s); 768 return; 769 } 770 771 length = dscr.length ? dscr.length : 64 * KiB; 772 773 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { 774 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ 775 776 if (s->trnmod & SDHC_TRNS_READ) { 777 while (length) { 778 if (s->data_count == 0) { 779 for (n = 0; n < block_size; n++) { 780 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 781 } 782 } 783 begin = s->data_count; 784 if ((length + begin) < block_size) { 785 s->data_count = length + begin; 786 length = 0; 787 } else { 788 s->data_count = block_size; 789 length -= block_size - begin; 790 } 791 dma_memory_write(s->dma_as, dscr.addr, 792 &s->fifo_buffer[begin], 793 s->data_count - begin); 794 dscr.addr += s->data_count - begin; 795 if (s->data_count == block_size) { 796 s->data_count = 0; 797 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 798 s->blkcnt--; 799 if (s->blkcnt == 0) { 800 break; 801 } 802 } 803 } 804 } 805 } else { 806 while (length) { 807 begin = s->data_count; 808 if ((length + begin) < block_size) { 809 s->data_count = length + begin; 810 length = 0; 811 } else { 812 s->data_count = block_size; 813 length -= block_size - begin; 814 } 815 dma_memory_read(s->dma_as, dscr.addr, 816 &s->fifo_buffer[begin], 817 s->data_count - begin); 818 dscr.addr += s->data_count - begin; 819 if (s->data_count == block_size) { 820 for (n = 0; n < block_size; n++) { 821 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 822 } 823 s->data_count = 0; 824 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 825 s->blkcnt--; 826 if (s->blkcnt == 0) { 827 break; 828 } 829 } 830 } 831 } 832 } 833 s->admasysaddr += dscr.incr; 834 break; 835 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ 836 s->admasysaddr = dscr.addr; 837 trace_sdhci_adma("link", s->admasysaddr); 838 break; 839 default: 840 s->admasysaddr += dscr.incr; 841 break; 842 } 843 844 if (dscr.attr & SDHC_ADMA_ATTR_INT) { 845 trace_sdhci_adma("interrupt", s->admasysaddr); 846 if (s->norintstsen & SDHC_NISEN_DMA) { 847 s->norintsts |= SDHC_NIS_DMA; 848 } 849 850 sdhci_update_irq(s); 851 } 852 853 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ 854 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 855 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { 856 trace_sdhci_adma_transfer_completed(); 857 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && 858 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 859 s->blkcnt != 0)) { 860 trace_sdhci_error("SD/MMC host ADMA length mismatch"); 861 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | 862 SDHC_ADMAERR_STATE_ST_TFR; 863 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 864 trace_sdhci_error("Set ADMA error flag"); 865 s->errintsts |= SDHC_EIS_ADMAERR; 866 s->norintsts |= SDHC_NIS_ERR; 867 } 868 869 sdhci_update_irq(s); 870 } 871 sdhci_end_transfer(s); 872 return; 873 } 874 875 } 876 877 /* we have unfinished business - reschedule to continue ADMA */ 878 timer_mod(s->transfer_timer, 879 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY); 880 } 881 882 /* Perform data transfer according to controller configuration */ 883 884 static void sdhci_data_transfer(void *opaque) 885 { 886 SDHCIState *s = (SDHCIState *)opaque; 887 888 if (s->trnmod & SDHC_TRNS_DMA) { 889 switch (SDHC_DMA_TYPE(s->hostctl1)) { 890 case SDHC_CTRL_SDMA: 891 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { 892 sdhci_sdma_transfer_single_block(s); 893 } else { 894 sdhci_sdma_transfer_multi_blocks(s); 895 } 896 897 break; 898 case SDHC_CTRL_ADMA1_32: 899 if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) { 900 trace_sdhci_error("ADMA1 not supported"); 901 break; 902 } 903 904 sdhci_do_adma(s); 905 break; 906 case SDHC_CTRL_ADMA2_32: 907 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) { 908 trace_sdhci_error("ADMA2 not supported"); 909 break; 910 } 911 912 sdhci_do_adma(s); 913 break; 914 case SDHC_CTRL_ADMA2_64: 915 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) || 916 !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) { 917 trace_sdhci_error("64 bit ADMA not supported"); 918 break; 919 } 920 921 sdhci_do_adma(s); 922 break; 923 default: 924 trace_sdhci_error("Unsupported DMA type"); 925 break; 926 } 927 } else { 928 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) { 929 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 930 SDHC_DAT_LINE_ACTIVE; 931 sdhci_read_block_from_card(s); 932 } else { 933 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | 934 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; 935 sdhci_write_block_to_card(s); 936 } 937 } 938 } 939 940 static bool sdhci_can_issue_command(SDHCIState *s) 941 { 942 if (!SDHC_CLOCK_IS_ON(s->clkcon) || 943 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && 944 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || 945 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && 946 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { 947 return false; 948 } 949 950 return true; 951 } 952 953 /* The Buffer Data Port register must be accessed in sequential and 954 * continuous manner */ 955 static inline bool 956 sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) 957 { 958 if ((s->data_count & 0x3) != byte_num) { 959 trace_sdhci_error("Non-sequential access to Buffer Data Port register" 960 "is prohibited\n"); 961 return false; 962 } 963 return true; 964 } 965 966 static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) 967 { 968 SDHCIState *s = (SDHCIState *)opaque; 969 uint32_t ret = 0; 970 971 switch (offset & ~0x3) { 972 case SDHC_SYSAD: 973 ret = s->sdmasysad; 974 break; 975 case SDHC_BLKSIZE: 976 ret = s->blksize | (s->blkcnt << 16); 977 break; 978 case SDHC_ARGUMENT: 979 ret = s->argument; 980 break; 981 case SDHC_TRNMOD: 982 ret = s->trnmod | (s->cmdreg << 16); 983 break; 984 case SDHC_RSPREG0 ... SDHC_RSPREG3: 985 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; 986 break; 987 case SDHC_BDATA: 988 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 989 ret = sdhci_read_dataport(s, size); 990 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 991 return ret; 992 } 993 break; 994 case SDHC_PRNSTS: 995 ret = s->prnsts; 996 ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL, 997 sdbus_get_dat_lines(&s->sdbus)); 998 ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL, 999 sdbus_get_cmd_line(&s->sdbus)); 1000 break; 1001 case SDHC_HOSTCTL: 1002 ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) | 1003 (s->wakcon << 24); 1004 break; 1005 case SDHC_CLKCON: 1006 ret = s->clkcon | (s->timeoutcon << 16); 1007 break; 1008 case SDHC_NORINTSTS: 1009 ret = s->norintsts | (s->errintsts << 16); 1010 break; 1011 case SDHC_NORINTSTSEN: 1012 ret = s->norintstsen | (s->errintstsen << 16); 1013 break; 1014 case SDHC_NORINTSIGEN: 1015 ret = s->norintsigen | (s->errintsigen << 16); 1016 break; 1017 case SDHC_ACMD12ERRSTS: 1018 ret = s->acmd12errsts | (s->hostctl2 << 16); 1019 break; 1020 case SDHC_CAPAB: 1021 ret = (uint32_t)s->capareg; 1022 break; 1023 case SDHC_CAPAB + 4: 1024 ret = (uint32_t)(s->capareg >> 32); 1025 break; 1026 case SDHC_MAXCURR: 1027 ret = (uint32_t)s->maxcurr; 1028 break; 1029 case SDHC_MAXCURR + 4: 1030 ret = (uint32_t)(s->maxcurr >> 32); 1031 break; 1032 case SDHC_ADMAERR: 1033 ret = s->admaerr; 1034 break; 1035 case SDHC_ADMASYSADDR: 1036 ret = (uint32_t)s->admasysaddr; 1037 break; 1038 case SDHC_ADMASYSADDR + 4: 1039 ret = (uint32_t)(s->admasysaddr >> 32); 1040 break; 1041 case SDHC_SLOT_INT_STATUS: 1042 ret = (s->version << 16) | sdhci_slotint(s); 1043 break; 1044 default: 1045 qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " " 1046 "not implemented\n", size, offset); 1047 break; 1048 } 1049 1050 ret >>= (offset & 0x3) * 8; 1051 ret &= (1ULL << (size * 8)) - 1; 1052 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 1053 return ret; 1054 } 1055 1056 static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) 1057 { 1058 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { 1059 return; 1060 } 1061 s->blkgap = value & SDHC_STOP_AT_GAP_REQ; 1062 1063 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && 1064 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { 1065 if (s->stopped_state == sdhc_gap_read) { 1066 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; 1067 sdhci_read_block_from_card(s); 1068 } else { 1069 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; 1070 sdhci_write_block_to_card(s); 1071 } 1072 s->stopped_state = sdhc_not_stopped; 1073 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { 1074 if (s->prnsts & SDHC_DOING_READ) { 1075 s->stopped_state = sdhc_gap_read; 1076 } else if (s->prnsts & SDHC_DOING_WRITE) { 1077 s->stopped_state = sdhc_gap_write; 1078 } 1079 } 1080 } 1081 1082 static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) 1083 { 1084 switch (value) { 1085 case SDHC_RESET_ALL: 1086 sdhci_reset(s); 1087 break; 1088 case SDHC_RESET_CMD: 1089 s->prnsts &= ~SDHC_CMD_INHIBIT; 1090 s->norintsts &= ~SDHC_NIS_CMDCMP; 1091 break; 1092 case SDHC_RESET_DATA: 1093 s->data_count = 0; 1094 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | 1095 SDHC_DOING_READ | SDHC_DOING_WRITE | 1096 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); 1097 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); 1098 s->stopped_state = sdhc_not_stopped; 1099 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | 1100 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); 1101 break; 1102 } 1103 } 1104 1105 static void 1106 sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1107 { 1108 SDHCIState *s = (SDHCIState *)opaque; 1109 unsigned shift = 8 * (offset & 0x3); 1110 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); 1111 uint32_t value = val; 1112 value <<= shift; 1113 1114 switch (offset & ~0x3) { 1115 case SDHC_SYSAD: 1116 s->sdmasysad = (s->sdmasysad & mask) | value; 1117 MASKED_WRITE(s->sdmasysad, mask, value); 1118 /* Writing to last byte of sdmasysad might trigger transfer */ 1119 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && 1120 s->blksize && SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) { 1121 if (s->trnmod & SDHC_TRNS_MULTI) { 1122 sdhci_sdma_transfer_multi_blocks(s); 1123 } else { 1124 sdhci_sdma_transfer_single_block(s); 1125 } 1126 } 1127 break; 1128 case SDHC_BLKSIZE: 1129 if (!TRANSFERRING_DATA(s->prnsts)) { 1130 MASKED_WRITE(s->blksize, mask, value); 1131 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); 1132 } 1133 1134 /* Limit block size to the maximum buffer size */ 1135 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) { 1136 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " \ 1137 "the maximum buffer 0x%x", __func__, s->blksize, 1138 s->buf_maxsz); 1139 1140 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz); 1141 } 1142 1143 break; 1144 case SDHC_ARGUMENT: 1145 MASKED_WRITE(s->argument, mask, value); 1146 break; 1147 case SDHC_TRNMOD: 1148 /* DMA can be enabled only if it is supported as indicated by 1149 * capabilities register */ 1150 if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { 1151 value &= ~SDHC_TRNS_DMA; 1152 } 1153 MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK); 1154 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); 1155 1156 /* Writing to the upper byte of CMDREG triggers SD command generation */ 1157 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { 1158 break; 1159 } 1160 1161 sdhci_send_command(s); 1162 break; 1163 case SDHC_BDATA: 1164 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1165 sdhci_write_dataport(s, value >> shift, size); 1166 } 1167 break; 1168 case SDHC_HOSTCTL: 1169 if (!(mask & 0xFF0000)) { 1170 sdhci_blkgap_write(s, value >> 16); 1171 } 1172 MASKED_WRITE(s->hostctl1, mask, value); 1173 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); 1174 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); 1175 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || 1176 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { 1177 s->pwrcon &= ~SDHC_POWER_ON; 1178 } 1179 break; 1180 case SDHC_CLKCON: 1181 if (!(mask & 0xFF000000)) { 1182 sdhci_reset_write(s, value >> 24); 1183 } 1184 MASKED_WRITE(s->clkcon, mask, value); 1185 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); 1186 if (s->clkcon & SDHC_CLOCK_INT_EN) { 1187 s->clkcon |= SDHC_CLOCK_INT_STABLE; 1188 } else { 1189 s->clkcon &= ~SDHC_CLOCK_INT_STABLE; 1190 } 1191 break; 1192 case SDHC_NORINTSTS: 1193 if (s->norintstsen & SDHC_NISEN_CARDINT) { 1194 value &= ~SDHC_NIS_CARDINT; 1195 } 1196 s->norintsts &= mask | ~value; 1197 s->errintsts &= (mask >> 16) | ~(value >> 16); 1198 if (s->errintsts) { 1199 s->norintsts |= SDHC_NIS_ERR; 1200 } else { 1201 s->norintsts &= ~SDHC_NIS_ERR; 1202 } 1203 sdhci_update_irq(s); 1204 break; 1205 case SDHC_NORINTSTSEN: 1206 MASKED_WRITE(s->norintstsen, mask, value); 1207 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); 1208 s->norintsts &= s->norintstsen; 1209 s->errintsts &= s->errintstsen; 1210 if (s->errintsts) { 1211 s->norintsts |= SDHC_NIS_ERR; 1212 } else { 1213 s->norintsts &= ~SDHC_NIS_ERR; 1214 } 1215 /* Quirk for Raspberry Pi: pending card insert interrupt 1216 * appears when first enabled after power on */ 1217 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { 1218 assert(s->pending_insert_quirk); 1219 s->norintsts |= SDHC_NIS_INSERT; 1220 s->pending_insert_state = false; 1221 } 1222 sdhci_update_irq(s); 1223 break; 1224 case SDHC_NORINTSIGEN: 1225 MASKED_WRITE(s->norintsigen, mask, value); 1226 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); 1227 sdhci_update_irq(s); 1228 break; 1229 case SDHC_ADMAERR: 1230 MASKED_WRITE(s->admaerr, mask, value); 1231 break; 1232 case SDHC_ADMASYSADDR: 1233 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | 1234 (uint64_t)mask)) | (uint64_t)value; 1235 break; 1236 case SDHC_ADMASYSADDR + 4: 1237 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | 1238 ((uint64_t)mask << 32))) | ((uint64_t)value << 32); 1239 break; 1240 case SDHC_FEAER: 1241 s->acmd12errsts |= value; 1242 s->errintsts |= (value >> 16) & s->errintstsen; 1243 if (s->acmd12errsts) { 1244 s->errintsts |= SDHC_EIS_CMD12ERR; 1245 } 1246 if (s->errintsts) { 1247 s->norintsts |= SDHC_NIS_ERR; 1248 } 1249 sdhci_update_irq(s); 1250 break; 1251 case SDHC_ACMD12ERRSTS: 1252 MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX); 1253 if (s->uhs_mode >= UHS_I) { 1254 MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16); 1255 1256 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) { 1257 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V); 1258 } else { 1259 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V); 1260 } 1261 } 1262 break; 1263 1264 case SDHC_CAPAB: 1265 case SDHC_CAPAB + 4: 1266 case SDHC_MAXCURR: 1267 case SDHC_MAXCURR + 4: 1268 qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx 1269 " <- 0x%08x read-only\n", size, offset, value >> shift); 1270 break; 1271 1272 default: 1273 qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x " 1274 "not implemented\n", size, offset, value >> shift); 1275 break; 1276 } 1277 trace_sdhci_access("wr", size << 3, offset, "<-", 1278 value >> shift, value >> shift); 1279 } 1280 1281 static const MemoryRegionOps sdhci_mmio_ops = { 1282 .read = sdhci_read, 1283 .write = sdhci_write, 1284 .valid = { 1285 .min_access_size = 1, 1286 .max_access_size = 4, 1287 .unaligned = false 1288 }, 1289 .endianness = DEVICE_LITTLE_ENDIAN, 1290 }; 1291 1292 static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) 1293 { 1294 Error *local_err = NULL; 1295 1296 switch (s->sd_spec_version) { 1297 case 2 ... 3: 1298 break; 1299 default: 1300 error_setg(errp, "Only Spec v2/v3 are supported"); 1301 return; 1302 } 1303 s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1); 1304 1305 sdhci_check_capareg(s, &local_err); 1306 if (local_err) { 1307 error_propagate(errp, local_err); 1308 return; 1309 } 1310 } 1311 1312 /* --- qdev common --- */ 1313 1314 void sdhci_initfn(SDHCIState *s) 1315 { 1316 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), 1317 TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); 1318 1319 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); 1320 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); 1321 1322 s->io_ops = &sdhci_mmio_ops; 1323 } 1324 1325 void sdhci_uninitfn(SDHCIState *s) 1326 { 1327 timer_del(s->insert_timer); 1328 timer_free(s->insert_timer); 1329 timer_del(s->transfer_timer); 1330 timer_free(s->transfer_timer); 1331 1332 g_free(s->fifo_buffer); 1333 s->fifo_buffer = NULL; 1334 } 1335 1336 void sdhci_common_realize(SDHCIState *s, Error **errp) 1337 { 1338 Error *local_err = NULL; 1339 1340 sdhci_init_readonly_registers(s, &local_err); 1341 if (local_err) { 1342 error_propagate(errp, local_err); 1343 return; 1344 } 1345 s->buf_maxsz = sdhci_get_fifolen(s); 1346 s->fifo_buffer = g_malloc0(s->buf_maxsz); 1347 1348 memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci", 1349 SDHC_REGISTERS_MAP_SIZE); 1350 } 1351 1352 void sdhci_common_unrealize(SDHCIState *s, Error **errp) 1353 { 1354 /* This function is expected to be called only once for each class: 1355 * - SysBus: via DeviceClass->unrealize(), 1356 * - PCI: via PCIDeviceClass->exit(). 1357 * However to avoid double-free and/or use-after-free we still nullify 1358 * this variable (better safe than sorry!). */ 1359 g_free(s->fifo_buffer); 1360 s->fifo_buffer = NULL; 1361 } 1362 1363 static bool sdhci_pending_insert_vmstate_needed(void *opaque) 1364 { 1365 SDHCIState *s = opaque; 1366 1367 return s->pending_insert_state; 1368 } 1369 1370 static const VMStateDescription sdhci_pending_insert_vmstate = { 1371 .name = "sdhci/pending-insert", 1372 .version_id = 1, 1373 .minimum_version_id = 1, 1374 .needed = sdhci_pending_insert_vmstate_needed, 1375 .fields = (VMStateField[]) { 1376 VMSTATE_BOOL(pending_insert_state, SDHCIState), 1377 VMSTATE_END_OF_LIST() 1378 }, 1379 }; 1380 1381 const VMStateDescription sdhci_vmstate = { 1382 .name = "sdhci", 1383 .version_id = 1, 1384 .minimum_version_id = 1, 1385 .fields = (VMStateField[]) { 1386 VMSTATE_UINT32(sdmasysad, SDHCIState), 1387 VMSTATE_UINT16(blksize, SDHCIState), 1388 VMSTATE_UINT16(blkcnt, SDHCIState), 1389 VMSTATE_UINT32(argument, SDHCIState), 1390 VMSTATE_UINT16(trnmod, SDHCIState), 1391 VMSTATE_UINT16(cmdreg, SDHCIState), 1392 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), 1393 VMSTATE_UINT32(prnsts, SDHCIState), 1394 VMSTATE_UINT8(hostctl1, SDHCIState), 1395 VMSTATE_UINT8(pwrcon, SDHCIState), 1396 VMSTATE_UINT8(blkgap, SDHCIState), 1397 VMSTATE_UINT8(wakcon, SDHCIState), 1398 VMSTATE_UINT16(clkcon, SDHCIState), 1399 VMSTATE_UINT8(timeoutcon, SDHCIState), 1400 VMSTATE_UINT8(admaerr, SDHCIState), 1401 VMSTATE_UINT16(norintsts, SDHCIState), 1402 VMSTATE_UINT16(errintsts, SDHCIState), 1403 VMSTATE_UINT16(norintstsen, SDHCIState), 1404 VMSTATE_UINT16(errintstsen, SDHCIState), 1405 VMSTATE_UINT16(norintsigen, SDHCIState), 1406 VMSTATE_UINT16(errintsigen, SDHCIState), 1407 VMSTATE_UINT16(acmd12errsts, SDHCIState), 1408 VMSTATE_UINT16(data_count, SDHCIState), 1409 VMSTATE_UINT64(admasysaddr, SDHCIState), 1410 VMSTATE_UINT8(stopped_state, SDHCIState), 1411 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz), 1412 VMSTATE_TIMER_PTR(insert_timer, SDHCIState), 1413 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState), 1414 VMSTATE_END_OF_LIST() 1415 }, 1416 .subsections = (const VMStateDescription*[]) { 1417 &sdhci_pending_insert_vmstate, 1418 NULL 1419 }, 1420 }; 1421 1422 void sdhci_common_class_init(ObjectClass *klass, void *data) 1423 { 1424 DeviceClass *dc = DEVICE_CLASS(klass); 1425 1426 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1427 dc->vmsd = &sdhci_vmstate; 1428 dc->reset = sdhci_poweron_reset; 1429 } 1430 1431 /* --- qdev SysBus --- */ 1432 1433 static Property sdhci_sysbus_properties[] = { 1434 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), 1435 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, 1436 false), 1437 DEFINE_PROP_LINK("dma", SDHCIState, 1438 dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), 1439 DEFINE_PROP_END_OF_LIST(), 1440 }; 1441 1442 static void sdhci_sysbus_init(Object *obj) 1443 { 1444 SDHCIState *s = SYSBUS_SDHCI(obj); 1445 1446 sdhci_initfn(s); 1447 } 1448 1449 static void sdhci_sysbus_finalize(Object *obj) 1450 { 1451 SDHCIState *s = SYSBUS_SDHCI(obj); 1452 1453 if (s->dma_mr) { 1454 object_unparent(OBJECT(s->dma_mr)); 1455 } 1456 1457 sdhci_uninitfn(s); 1458 } 1459 1460 static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp) 1461 { 1462 SDHCIState *s = SYSBUS_SDHCI(dev); 1463 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1464 Error *local_err = NULL; 1465 1466 sdhci_common_realize(s, &local_err); 1467 if (local_err) { 1468 error_propagate(errp, local_err); 1469 return; 1470 } 1471 1472 if (s->dma_mr) { 1473 s->dma_as = &s->sysbus_dma_as; 1474 address_space_init(s->dma_as, s->dma_mr, "sdhci-dma"); 1475 } else { 1476 /* use system_memory() if property "dma" not set */ 1477 s->dma_as = &address_space_memory; 1478 } 1479 1480 sysbus_init_irq(sbd, &s->irq); 1481 1482 sysbus_init_mmio(sbd, &s->iomem); 1483 } 1484 1485 static void sdhci_sysbus_unrealize(DeviceState *dev, Error **errp) 1486 { 1487 SDHCIState *s = SYSBUS_SDHCI(dev); 1488 1489 sdhci_common_unrealize(s, &error_abort); 1490 1491 if (s->dma_mr) { 1492 address_space_destroy(s->dma_as); 1493 } 1494 } 1495 1496 static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) 1497 { 1498 DeviceClass *dc = DEVICE_CLASS(klass); 1499 1500 dc->props = sdhci_sysbus_properties; 1501 dc->realize = sdhci_sysbus_realize; 1502 dc->unrealize = sdhci_sysbus_unrealize; 1503 1504 sdhci_common_class_init(klass, data); 1505 } 1506 1507 static const TypeInfo sdhci_sysbus_info = { 1508 .name = TYPE_SYSBUS_SDHCI, 1509 .parent = TYPE_SYS_BUS_DEVICE, 1510 .instance_size = sizeof(SDHCIState), 1511 .instance_init = sdhci_sysbus_init, 1512 .instance_finalize = sdhci_sysbus_finalize, 1513 .class_init = sdhci_sysbus_class_init, 1514 }; 1515 1516 /* --- qdev bus master --- */ 1517 1518 static void sdhci_bus_class_init(ObjectClass *klass, void *data) 1519 { 1520 SDBusClass *sbc = SD_BUS_CLASS(klass); 1521 1522 sbc->set_inserted = sdhci_set_inserted; 1523 sbc->set_readonly = sdhci_set_readonly; 1524 } 1525 1526 static const TypeInfo sdhci_bus_info = { 1527 .name = TYPE_SDHCI_BUS, 1528 .parent = TYPE_SD_BUS, 1529 .instance_size = sizeof(SDBus), 1530 .class_init = sdhci_bus_class_init, 1531 }; 1532 1533 static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) 1534 { 1535 SDHCIState *s = SYSBUS_SDHCI(opaque); 1536 uint32_t ret; 1537 uint16_t hostctl1; 1538 1539 switch (offset) { 1540 default: 1541 return sdhci_read(opaque, offset, size); 1542 1543 case SDHC_HOSTCTL: 1544 /* 1545 * For a detailed explanation on the following bit 1546 * manipulation code see comments in a similar part of 1547 * usdhc_write() 1548 */ 1549 hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3); 1550 1551 if (s->hostctl1 & SDHC_CTRL_8BITBUS) { 1552 hostctl1 |= ESDHC_CTRL_8BITBUS; 1553 } 1554 1555 if (s->hostctl1 & SDHC_CTRL_4BITBUS) { 1556 hostctl1 |= ESDHC_CTRL_4BITBUS; 1557 } 1558 1559 ret = hostctl1; 1560 ret |= (uint32_t)s->blkgap << 16; 1561 ret |= (uint32_t)s->wakcon << 24; 1562 1563 break; 1564 1565 case SDHC_PRNSTS: 1566 /* Add SDSTB (SD Clock Stable) bit to PRNSTS */ 1567 ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB; 1568 if (s->clkcon & SDHC_CLOCK_INT_STABLE) { 1569 ret |= ESDHC_PRNSTS_SDSTB; 1570 } 1571 break; 1572 1573 case ESDHC_DLL_CTRL: 1574 case ESDHC_TUNE_CTRL_STATUS: 1575 case ESDHC_UNDOCUMENTED_REG27: 1576 case ESDHC_TUNING_CTRL: 1577 case ESDHC_VENDOR_SPEC: 1578 case ESDHC_MIX_CTRL: 1579 case ESDHC_WTMK_LVL: 1580 ret = 0; 1581 break; 1582 } 1583 1584 return ret; 1585 } 1586 1587 static void 1588 usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1589 { 1590 SDHCIState *s = SYSBUS_SDHCI(opaque); 1591 uint8_t hostctl1; 1592 uint32_t value = (uint32_t)val; 1593 1594 switch (offset) { 1595 case ESDHC_DLL_CTRL: 1596 case ESDHC_TUNE_CTRL_STATUS: 1597 case ESDHC_UNDOCUMENTED_REG27: 1598 case ESDHC_TUNING_CTRL: 1599 case ESDHC_WTMK_LVL: 1600 case ESDHC_VENDOR_SPEC: 1601 break; 1602 1603 case SDHC_HOSTCTL: 1604 /* 1605 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL) 1606 * 1607 * 7 6 5 4 3 2 1 0 1608 * |-----------+--------+--------+-----------+----------+---------| 1609 * | Card | Card | Endian | DATA3 | Data | Led | 1610 * | Detect | Detect | Mode | as Card | Transfer | Control | 1611 * | Signal | Test | | Detection | Width | | 1612 * | Selection | Level | | Pin | | | 1613 * |-----------+--------+--------+-----------+----------+---------| 1614 * 1615 * and 0x29 1616 * 1617 * 15 10 9 8 1618 * |----------+------| 1619 * | Reserved | DMA | 1620 * | | Sel. | 1621 * | | | 1622 * |----------+------| 1623 * 1624 * and here's what SDCHI spec expects those offsets to be: 1625 * 1626 * 0x28 (Host Control Register) 1627 * 1628 * 7 6 5 4 3 2 1 0 1629 * |--------+--------+----------+------+--------+----------+---------| 1630 * | Card | Card | Extended | DMA | High | Data | LED | 1631 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control | 1632 * | Signal | Test | Transfer | | Enable | Width | | 1633 * | Sel. | Level | Width | | | | | 1634 * |--------+--------+----------+------+--------+----------+---------| 1635 * 1636 * and 0x29 (Power Control Register) 1637 * 1638 * |----------------------------------| 1639 * | Power Control Register | 1640 * | | 1641 * | Description omitted, | 1642 * | since it has no analog in ESDHCI | 1643 * | | 1644 * |----------------------------------| 1645 * 1646 * Since offsets 0x2A and 0x2B should be compatible between 1647 * both IP specs we only need to reconcile least 16-bit of the 1648 * word we've been given. 1649 */ 1650 1651 /* 1652 * First, save bits 7 6 and 0 since they are identical 1653 */ 1654 hostctl1 = value & (SDHC_CTRL_LED | 1655 SDHC_CTRL_CDTEST_INS | 1656 SDHC_CTRL_CDTEST_EN); 1657 /* 1658 * Second, split "Data Transfer Width" from bits 2 and 1 in to 1659 * bits 5 and 1 1660 */ 1661 if (value & ESDHC_CTRL_8BITBUS) { 1662 hostctl1 |= SDHC_CTRL_8BITBUS; 1663 } 1664 1665 if (value & ESDHC_CTRL_4BITBUS) { 1666 hostctl1 |= ESDHC_CTRL_4BITBUS; 1667 } 1668 1669 /* 1670 * Third, move DMA select from bits 9 and 8 to bits 4 and 3 1671 */ 1672 hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3)); 1673 1674 /* 1675 * Now place the corrected value into low 16-bit of the value 1676 * we are going to give standard SDHCI write function 1677 * 1678 * NOTE: This transformation should be the inverse of what can 1679 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux 1680 * kernel 1681 */ 1682 value &= ~UINT16_MAX; 1683 value |= hostctl1; 1684 value |= (uint16_t)s->pwrcon << 8; 1685 1686 sdhci_write(opaque, offset, value, size); 1687 break; 1688 1689 case ESDHC_MIX_CTRL: 1690 /* 1691 * So, when SD/MMC stack in Linux tries to write to "Transfer 1692 * Mode Register", ESDHC i.MX quirk code will translate it 1693 * into a write to ESDHC_MIX_CTRL, so we do the opposite in 1694 * order to get where we started 1695 * 1696 * Note that Auto CMD23 Enable bit is located in a wrong place 1697 * on i.MX, but since it is not used by QEMU we do not care. 1698 * 1699 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...) 1700 * here becuase it will result in a call to 1701 * sdhci_send_command(s) which we don't want. 1702 * 1703 */ 1704 s->trnmod = value & UINT16_MAX; 1705 break; 1706 case SDHC_TRNMOD: 1707 /* 1708 * Similar to above, but this time a write to "Command 1709 * Register" will be translated into a 4-byte write to 1710 * "Transfer Mode register" where lower 16-bit of value would 1711 * be set to zero. So what we do is fill those bits with 1712 * cached value from s->trnmod and let the SDHCI 1713 * infrastructure handle the rest 1714 */ 1715 sdhci_write(opaque, offset, val | s->trnmod, size); 1716 break; 1717 case SDHC_BLKSIZE: 1718 /* 1719 * ESDHCI does not implement "Host SDMA Buffer Boundary", and 1720 * Linux driver will try to zero this field out which will 1721 * break the rest of SDHCI emulation. 1722 * 1723 * Linux defaults to maximum possible setting (512K boundary) 1724 * and it seems to be the only option that i.MX IP implements, 1725 * so we artificially set it to that value. 1726 */ 1727 val |= 0x7 << 12; 1728 /* FALLTHROUGH */ 1729 default: 1730 sdhci_write(opaque, offset, val, size); 1731 break; 1732 } 1733 } 1734 1735 1736 static const MemoryRegionOps usdhc_mmio_ops = { 1737 .read = usdhc_read, 1738 .write = usdhc_write, 1739 .valid = { 1740 .min_access_size = 1, 1741 .max_access_size = 4, 1742 .unaligned = false 1743 }, 1744 .endianness = DEVICE_LITTLE_ENDIAN, 1745 }; 1746 1747 static void imx_usdhc_init(Object *obj) 1748 { 1749 SDHCIState *s = SYSBUS_SDHCI(obj); 1750 1751 s->io_ops = &usdhc_mmio_ops; 1752 s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; 1753 } 1754 1755 static const TypeInfo imx_usdhc_info = { 1756 .name = TYPE_IMX_USDHC, 1757 .parent = TYPE_SYSBUS_SDHCI, 1758 .instance_init = imx_usdhc_init, 1759 }; 1760 1761 static void sdhci_register_types(void) 1762 { 1763 type_register_static(&sdhci_sysbus_info); 1764 type_register_static(&sdhci_bus_info); 1765 type_register_static(&imx_usdhc_info); 1766 } 1767 1768 type_init(sdhci_register_types) 1769