1 /* 2 * SD Association Host Standard Specification v2.0 controller emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Mitsyanko Igor <i.mitsyanko@samsung.com> 6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 7 * 8 * Based on MMC controller for Samsung S5PC1xx-based board emulation 9 * by Alexey Merkulov and Vladimir Monakhov. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 19 * See the GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/error-report.h" 27 #include "qapi/error.h" 28 #include "hw/hw.h" 29 #include "sysemu/blockdev.h" 30 #include "sysemu/dma.h" 31 #include "qemu/timer.h" 32 #include "qemu/bitops.h" 33 #include "hw/sd/sdhci.h" 34 #include "sdhci-internal.h" 35 #include "qemu/log.h" 36 #include "qemu/cutils.h" 37 #include "trace.h" 38 39 #define TYPE_SDHCI_BUS "sdhci-bus" 40 #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS) 41 42 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) 43 44 /* Default SD/MMC host controller features information, which will be 45 * presented in CAPABILITIES register of generic SD host controller at reset. 46 * 47 * support: 48 * - 3.3v and 1.8v voltages 49 * - SDMA/ADMA1/ADMA2 50 * - high-speed 51 * max host controller R/W buffers size: 512B 52 * max clock frequency for SDclock: 52 MHz 53 * timeout clock frequency: 52 MHz 54 * 55 * does not support: 56 * - 3.0v voltage 57 * - 64-bit system bus 58 * - suspend/resume 59 */ 60 #define SDHC_CAPAB_REG_DEFAULT 0x057834b4 61 62 static inline unsigned int sdhci_get_fifolen(SDHCIState *s) 63 { 64 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); 65 } 66 67 /* return true on error */ 68 static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, 69 uint8_t freq, Error **errp) 70 { 71 if (s->sd_spec_version >= 3) { 72 return false; 73 } 74 switch (freq) { 75 case 0: 76 case 10 ... 63: 77 break; 78 default: 79 error_setg(errp, "SD %s clock frequency can have value" 80 "in range 0-63 only", desc); 81 return true; 82 } 83 return false; 84 } 85 86 static void sdhci_check_capareg(SDHCIState *s, Error **errp) 87 { 88 uint64_t msk = s->capareg; 89 uint32_t val; 90 bool y; 91 92 switch (s->sd_spec_version) { 93 case 4: 94 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4); 95 trace_sdhci_capareg("64-bit system bus (v4)", val); 96 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0); 97 98 val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II); 99 trace_sdhci_capareg("UHS-II", val); 100 msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0); 101 102 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3); 103 trace_sdhci_capareg("ADMA3", val); 104 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0); 105 106 /* fallthrough */ 107 case 3: 108 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT); 109 trace_sdhci_capareg("async interrupt", val); 110 msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0); 111 112 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE); 113 if (val) { 114 error_setg(errp, "slot-type not supported"); 115 return; 116 } 117 trace_sdhci_capareg("slot type", val); 118 msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0); 119 120 if (val != 2) { 121 val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT); 122 trace_sdhci_capareg("8-bit bus", val); 123 } 124 msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0); 125 126 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED); 127 trace_sdhci_capareg("bus speed mask", val); 128 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0); 129 130 val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH); 131 trace_sdhci_capareg("driver strength mask", val); 132 msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0); 133 134 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING); 135 trace_sdhci_capareg("timer re-tuning", val); 136 msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0); 137 138 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING); 139 trace_sdhci_capareg("use SDR50 tuning", val); 140 msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0); 141 142 val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE); 143 trace_sdhci_capareg("re-tuning mode", val); 144 msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0); 145 146 val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT); 147 trace_sdhci_capareg("clock multiplier", val); 148 msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0); 149 150 /* fallthrough */ 151 case 2: /* default version */ 152 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2); 153 trace_sdhci_capareg("ADMA2", val); 154 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0); 155 156 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1); 157 trace_sdhci_capareg("ADMA1", val); 158 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0); 159 160 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT); 161 trace_sdhci_capareg("64-bit system bus (v3)", val); 162 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0); 163 164 /* fallthrough */ 165 case 1: 166 y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT); 167 msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0); 168 169 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ); 170 trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val); 171 if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) { 172 return; 173 } 174 msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0); 175 176 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ); 177 trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val); 178 if (sdhci_check_capab_freq_range(s, "base", val, errp)) { 179 return; 180 } 181 msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0); 182 183 val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH); 184 if (val >= 3) { 185 error_setg(errp, "block size can be 512, 1024 or 2048 only"); 186 return; 187 } 188 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s)); 189 msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0); 190 191 val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED); 192 trace_sdhci_capareg("high speed", val); 193 msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0); 194 195 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA); 196 trace_sdhci_capareg("SDMA", val); 197 msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0); 198 199 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME); 200 trace_sdhci_capareg("suspend/resume", val); 201 msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0); 202 203 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33); 204 trace_sdhci_capareg("3.3v", val); 205 msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0); 206 207 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30); 208 trace_sdhci_capareg("3.0v", val); 209 msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0); 210 211 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18); 212 trace_sdhci_capareg("1.8v", val); 213 msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0); 214 break; 215 216 default: 217 error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version); 218 } 219 if (msk) { 220 qemu_log_mask(LOG_UNIMP, 221 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk); 222 } 223 } 224 225 static uint8_t sdhci_slotint(SDHCIState *s) 226 { 227 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || 228 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || 229 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); 230 } 231 232 static inline void sdhci_update_irq(SDHCIState *s) 233 { 234 qemu_set_irq(s->irq, sdhci_slotint(s)); 235 } 236 237 static void sdhci_raise_insertion_irq(void *opaque) 238 { 239 SDHCIState *s = (SDHCIState *)opaque; 240 241 if (s->norintsts & SDHC_NIS_REMOVE) { 242 timer_mod(s->insert_timer, 243 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 244 } else { 245 s->prnsts = 0x1ff0000; 246 if (s->norintstsen & SDHC_NISEN_INSERT) { 247 s->norintsts |= SDHC_NIS_INSERT; 248 } 249 sdhci_update_irq(s); 250 } 251 } 252 253 static void sdhci_set_inserted(DeviceState *dev, bool level) 254 { 255 SDHCIState *s = (SDHCIState *)dev; 256 257 trace_sdhci_set_inserted(level ? "insert" : "eject"); 258 if ((s->norintsts & SDHC_NIS_REMOVE) && level) { 259 /* Give target some time to notice card ejection */ 260 timer_mod(s->insert_timer, 261 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 262 } else { 263 if (level) { 264 s->prnsts = 0x1ff0000; 265 if (s->norintstsen & SDHC_NISEN_INSERT) { 266 s->norintsts |= SDHC_NIS_INSERT; 267 } 268 } else { 269 s->prnsts = 0x1fa0000; 270 s->pwrcon &= ~SDHC_POWER_ON; 271 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; 272 if (s->norintstsen & SDHC_NISEN_REMOVE) { 273 s->norintsts |= SDHC_NIS_REMOVE; 274 } 275 } 276 sdhci_update_irq(s); 277 } 278 } 279 280 static void sdhci_set_readonly(DeviceState *dev, bool level) 281 { 282 SDHCIState *s = (SDHCIState *)dev; 283 284 if (level) { 285 s->prnsts &= ~SDHC_WRITE_PROTECT; 286 } else { 287 /* Write enabled */ 288 s->prnsts |= SDHC_WRITE_PROTECT; 289 } 290 } 291 292 static void sdhci_reset(SDHCIState *s) 293 { 294 DeviceState *dev = DEVICE(s); 295 296 timer_del(s->insert_timer); 297 timer_del(s->transfer_timer); 298 299 /* Set all registers to 0. Capabilities/Version registers are not cleared 300 * and assumed to always preserve their value, given to them during 301 * initialization */ 302 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); 303 304 /* Reset other state based on current card insertion/readonly status */ 305 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus)); 306 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus)); 307 308 s->data_count = 0; 309 s->stopped_state = sdhc_not_stopped; 310 s->pending_insert_state = false; 311 } 312 313 static void sdhci_poweron_reset(DeviceState *dev) 314 { 315 /* QOM (ie power-on) reset. This is identical to reset 316 * commanded via device register apart from handling of the 317 * 'pending insert on powerup' quirk. 318 */ 319 SDHCIState *s = (SDHCIState *)dev; 320 321 sdhci_reset(s); 322 323 if (s->pending_insert_quirk) { 324 s->pending_insert_state = true; 325 } 326 } 327 328 static void sdhci_data_transfer(void *opaque); 329 330 static void sdhci_send_command(SDHCIState *s) 331 { 332 SDRequest request; 333 uint8_t response[16]; 334 int rlen; 335 336 s->errintsts = 0; 337 s->acmd12errsts = 0; 338 request.cmd = s->cmdreg >> 8; 339 request.arg = s->argument; 340 341 trace_sdhci_send_command(request.cmd, request.arg); 342 rlen = sdbus_do_command(&s->sdbus, &request, response); 343 344 if (s->cmdreg & SDHC_CMD_RESPONSE) { 345 if (rlen == 4) { 346 s->rspreg[0] = (response[0] << 24) | (response[1] << 16) | 347 (response[2] << 8) | response[3]; 348 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; 349 trace_sdhci_response4(s->rspreg[0]); 350 } else if (rlen == 16) { 351 s->rspreg[0] = (response[11] << 24) | (response[12] << 16) | 352 (response[13] << 8) | response[14]; 353 s->rspreg[1] = (response[7] << 24) | (response[8] << 16) | 354 (response[9] << 8) | response[10]; 355 s->rspreg[2] = (response[3] << 24) | (response[4] << 16) | 356 (response[5] << 8) | response[6]; 357 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | 358 response[2]; 359 trace_sdhci_response16(s->rspreg[3], s->rspreg[2], 360 s->rspreg[1], s->rspreg[0]); 361 } else { 362 trace_sdhci_error("timeout waiting for command response"); 363 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { 364 s->errintsts |= SDHC_EIS_CMDTIMEOUT; 365 s->norintsts |= SDHC_NIS_ERR; 366 } 367 } 368 369 if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && 370 (s->norintstsen & SDHC_NISEN_TRSCMP) && 371 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { 372 s->norintsts |= SDHC_NIS_TRSCMP; 373 } 374 } 375 376 if (s->norintstsen & SDHC_NISEN_CMDCMP) { 377 s->norintsts |= SDHC_NIS_CMDCMP; 378 } 379 380 sdhci_update_irq(s); 381 382 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { 383 s->data_count = 0; 384 sdhci_data_transfer(s); 385 } 386 } 387 388 static void sdhci_end_transfer(SDHCIState *s) 389 { 390 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */ 391 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { 392 SDRequest request; 393 uint8_t response[16]; 394 395 request.cmd = 0x0C; 396 request.arg = 0; 397 trace_sdhci_end_transfer(request.cmd, request.arg); 398 sdbus_do_command(&s->sdbus, &request, response); 399 /* Auto CMD12 response goes to the upper Response register */ 400 s->rspreg[3] = (response[0] << 24) | (response[1] << 16) | 401 (response[2] << 8) | response[3]; 402 } 403 404 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | 405 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | 406 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); 407 408 if (s->norintstsen & SDHC_NISEN_TRSCMP) { 409 s->norintsts |= SDHC_NIS_TRSCMP; 410 } 411 412 sdhci_update_irq(s); 413 } 414 415 /* 416 * Programmed i/o data transfer 417 */ 418 #define BLOCK_SIZE_MASK (4 * K_BYTE - 1) 419 420 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ 421 static void sdhci_read_block_from_card(SDHCIState *s) 422 { 423 int index = 0; 424 uint8_t data; 425 const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK; 426 427 if ((s->trnmod & SDHC_TRNS_MULTI) && 428 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { 429 return; 430 } 431 432 for (index = 0; index < blk_size; index++) { 433 data = sdbus_read_data(&s->sdbus); 434 if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 435 /* Device is not in tuning */ 436 s->fifo_buffer[index] = data; 437 } 438 } 439 440 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 441 /* Device is in tuning */ 442 s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK; 443 s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK; 444 s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ | 445 SDHC_DATA_INHIBIT); 446 goto read_done; 447 } 448 449 /* New data now available for READ through Buffer Port Register */ 450 s->prnsts |= SDHC_DATA_AVAILABLE; 451 if (s->norintstsen & SDHC_NISEN_RBUFRDY) { 452 s->norintsts |= SDHC_NIS_RBUFRDY; 453 } 454 455 /* Clear DAT line active status if that was the last block */ 456 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 457 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { 458 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 459 } 460 461 /* If stop at block gap request was set and it's not the last block of 462 * data - generate Block Event interrupt */ 463 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && 464 s->blkcnt != 1) { 465 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 466 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 467 s->norintsts |= SDHC_EIS_BLKGAP; 468 } 469 } 470 471 read_done: 472 sdhci_update_irq(s); 473 } 474 475 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */ 476 static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) 477 { 478 uint32_t value = 0; 479 int i; 480 481 /* first check that a valid data exists in host controller input buffer */ 482 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { 483 trace_sdhci_error("read from empty buffer"); 484 return 0; 485 } 486 487 for (i = 0; i < size; i++) { 488 value |= s->fifo_buffer[s->data_count] << i * 8; 489 s->data_count++; 490 /* check if we've read all valid data (blksize bytes) from buffer */ 491 if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) { 492 trace_sdhci_read_dataport(s->data_count); 493 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ 494 s->data_count = 0; /* next buff read must start at position [0] */ 495 496 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 497 s->blkcnt--; 498 } 499 500 /* if that was the last block of data */ 501 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 502 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || 503 /* stop at gap request */ 504 (s->stopped_state == sdhc_gap_read && 505 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { 506 sdhci_end_transfer(s); 507 } else { /* if there are more data, read next block from card */ 508 sdhci_read_block_from_card(s); 509 } 510 break; 511 } 512 } 513 514 return value; 515 } 516 517 /* Write data from host controller FIFO to card */ 518 static void sdhci_write_block_to_card(SDHCIState *s) 519 { 520 int index = 0; 521 522 if (s->prnsts & SDHC_SPACE_AVAILABLE) { 523 if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 524 s->norintsts |= SDHC_NIS_WBUFRDY; 525 } 526 sdhci_update_irq(s); 527 return; 528 } 529 530 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 531 if (s->blkcnt == 0) { 532 return; 533 } else { 534 s->blkcnt--; 535 } 536 } 537 538 for (index = 0; index < (s->blksize & BLOCK_SIZE_MASK); index++) { 539 sdbus_write_data(&s->sdbus, s->fifo_buffer[index]); 540 } 541 542 /* Next data can be written through BUFFER DATORT register */ 543 s->prnsts |= SDHC_SPACE_AVAILABLE; 544 545 /* Finish transfer if that was the last block of data */ 546 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 547 ((s->trnmod & SDHC_TRNS_MULTI) && 548 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { 549 sdhci_end_transfer(s); 550 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 551 s->norintsts |= SDHC_NIS_WBUFRDY; 552 } 553 554 /* Generate Block Gap Event if requested and if not the last block */ 555 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && 556 s->blkcnt > 0) { 557 s->prnsts &= ~SDHC_DOING_WRITE; 558 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 559 s->norintsts |= SDHC_EIS_BLKGAP; 560 } 561 sdhci_end_transfer(s); 562 } 563 564 sdhci_update_irq(s); 565 } 566 567 /* Write @size bytes of @value data to host controller @s Buffer Data Port 568 * register */ 569 static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) 570 { 571 unsigned i; 572 573 /* Check that there is free space left in a buffer */ 574 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { 575 trace_sdhci_error("Can't write to data buffer: buffer full"); 576 return; 577 } 578 579 for (i = 0; i < size; i++) { 580 s->fifo_buffer[s->data_count] = value & 0xFF; 581 s->data_count++; 582 value >>= 8; 583 if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) { 584 trace_sdhci_write_dataport(s->data_count); 585 s->data_count = 0; 586 s->prnsts &= ~SDHC_SPACE_AVAILABLE; 587 if (s->prnsts & SDHC_DOING_WRITE) { 588 sdhci_write_block_to_card(s); 589 } 590 } 591 } 592 } 593 594 /* 595 * Single DMA data transfer 596 */ 597 598 /* Multi block SDMA transfer */ 599 static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) 600 { 601 bool page_aligned = false; 602 unsigned int n, begin; 603 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 604 uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12); 605 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); 606 607 if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) { 608 qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n"); 609 return; 610 } 611 612 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for 613 * possible stop at page boundary if initial address is not page aligned, 614 * allow them to work properly */ 615 if ((s->sdmasysad % boundary_chk) == 0) { 616 page_aligned = true; 617 } 618 619 if (s->trnmod & SDHC_TRNS_READ) { 620 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 621 SDHC_DAT_LINE_ACTIVE; 622 while (s->blkcnt) { 623 if (s->data_count == 0) { 624 for (n = 0; n < block_size; n++) { 625 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 626 } 627 } 628 begin = s->data_count; 629 if (((boundary_count + begin) < block_size) && page_aligned) { 630 s->data_count = boundary_count + begin; 631 boundary_count = 0; 632 } else { 633 s->data_count = block_size; 634 boundary_count -= block_size - begin; 635 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 636 s->blkcnt--; 637 } 638 } 639 dma_memory_write(s->dma_as, s->sdmasysad, 640 &s->fifo_buffer[begin], s->data_count - begin); 641 s->sdmasysad += s->data_count - begin; 642 if (s->data_count == block_size) { 643 s->data_count = 0; 644 } 645 if (page_aligned && boundary_count == 0) { 646 break; 647 } 648 } 649 } else { 650 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT | 651 SDHC_DAT_LINE_ACTIVE; 652 while (s->blkcnt) { 653 begin = s->data_count; 654 if (((boundary_count + begin) < block_size) && page_aligned) { 655 s->data_count = boundary_count + begin; 656 boundary_count = 0; 657 } else { 658 s->data_count = block_size; 659 boundary_count -= block_size - begin; 660 } 661 dma_memory_read(s->dma_as, s->sdmasysad, 662 &s->fifo_buffer[begin], s->data_count - begin); 663 s->sdmasysad += s->data_count - begin; 664 if (s->data_count == block_size) { 665 for (n = 0; n < block_size; n++) { 666 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 667 } 668 s->data_count = 0; 669 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 670 s->blkcnt--; 671 } 672 } 673 if (page_aligned && boundary_count == 0) { 674 break; 675 } 676 } 677 } 678 679 if (s->blkcnt == 0) { 680 sdhci_end_transfer(s); 681 } else { 682 if (s->norintstsen & SDHC_NISEN_DMA) { 683 s->norintsts |= SDHC_NIS_DMA; 684 } 685 sdhci_update_irq(s); 686 } 687 } 688 689 /* single block SDMA transfer */ 690 static void sdhci_sdma_transfer_single_block(SDHCIState *s) 691 { 692 int n; 693 uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK; 694 695 if (s->trnmod & SDHC_TRNS_READ) { 696 for (n = 0; n < datacnt; n++) { 697 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 698 } 699 dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); 700 } else { 701 dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); 702 for (n = 0; n < datacnt; n++) { 703 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 704 } 705 } 706 s->blkcnt--; 707 708 sdhci_end_transfer(s); 709 } 710 711 typedef struct ADMADescr { 712 hwaddr addr; 713 uint16_t length; 714 uint8_t attr; 715 uint8_t incr; 716 } ADMADescr; 717 718 static void get_adma_description(SDHCIState *s, ADMADescr *dscr) 719 { 720 uint32_t adma1 = 0; 721 uint64_t adma2 = 0; 722 hwaddr entry_addr = (hwaddr)s->admasysaddr; 723 switch (SDHC_DMA_TYPE(s->hostctl1)) { 724 case SDHC_CTRL_ADMA2_32: 725 dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma2, 726 sizeof(adma2)); 727 adma2 = le64_to_cpu(adma2); 728 /* The spec does not specify endianness of descriptor table. 729 * We currently assume that it is LE. 730 */ 731 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; 732 dscr->length = (uint16_t)extract64(adma2, 16, 16); 733 dscr->attr = (uint8_t)extract64(adma2, 0, 7); 734 dscr->incr = 8; 735 break; 736 case SDHC_CTRL_ADMA1_32: 737 dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma1, 738 sizeof(adma1)); 739 adma1 = le32_to_cpu(adma1); 740 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); 741 dscr->attr = (uint8_t)extract32(adma1, 0, 7); 742 dscr->incr = 4; 743 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { 744 dscr->length = (uint16_t)extract32(adma1, 12, 16); 745 } else { 746 dscr->length = 4096; 747 } 748 break; 749 case SDHC_CTRL_ADMA2_64: 750 dma_memory_read(s->dma_as, entry_addr, 751 (uint8_t *)(&dscr->attr), 1); 752 dma_memory_read(s->dma_as, entry_addr + 2, 753 (uint8_t *)(&dscr->length), 2); 754 dscr->length = le16_to_cpu(dscr->length); 755 dma_memory_read(s->dma_as, entry_addr + 4, 756 (uint8_t *)(&dscr->addr), 8); 757 dscr->addr = le64_to_cpu(dscr->addr); 758 dscr->attr &= (uint8_t) ~0xC0; 759 dscr->incr = 12; 760 break; 761 } 762 } 763 764 /* Advanced DMA data transfer */ 765 766 static void sdhci_do_adma(SDHCIState *s) 767 { 768 unsigned int n, begin, length; 769 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 770 ADMADescr dscr = {}; 771 int i; 772 773 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { 774 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; 775 776 get_adma_description(s, &dscr); 777 trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr); 778 779 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { 780 /* Indicate that error occurred in ST_FDS state */ 781 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; 782 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; 783 784 /* Generate ADMA error interrupt */ 785 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 786 s->errintsts |= SDHC_EIS_ADMAERR; 787 s->norintsts |= SDHC_NIS_ERR; 788 } 789 790 sdhci_update_irq(s); 791 return; 792 } 793 794 length = dscr.length ? dscr.length : 65536; 795 796 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { 797 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ 798 799 if (s->trnmod & SDHC_TRNS_READ) { 800 while (length) { 801 if (s->data_count == 0) { 802 for (n = 0; n < block_size; n++) { 803 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 804 } 805 } 806 begin = s->data_count; 807 if ((length + begin) < block_size) { 808 s->data_count = length + begin; 809 length = 0; 810 } else { 811 s->data_count = block_size; 812 length -= block_size - begin; 813 } 814 dma_memory_write(s->dma_as, dscr.addr, 815 &s->fifo_buffer[begin], 816 s->data_count - begin); 817 dscr.addr += s->data_count - begin; 818 if (s->data_count == block_size) { 819 s->data_count = 0; 820 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 821 s->blkcnt--; 822 if (s->blkcnt == 0) { 823 break; 824 } 825 } 826 } 827 } 828 } else { 829 while (length) { 830 begin = s->data_count; 831 if ((length + begin) < block_size) { 832 s->data_count = length + begin; 833 length = 0; 834 } else { 835 s->data_count = block_size; 836 length -= block_size - begin; 837 } 838 dma_memory_read(s->dma_as, dscr.addr, 839 &s->fifo_buffer[begin], 840 s->data_count - begin); 841 dscr.addr += s->data_count - begin; 842 if (s->data_count == block_size) { 843 for (n = 0; n < block_size; n++) { 844 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 845 } 846 s->data_count = 0; 847 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 848 s->blkcnt--; 849 if (s->blkcnt == 0) { 850 break; 851 } 852 } 853 } 854 } 855 } 856 s->admasysaddr += dscr.incr; 857 break; 858 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ 859 s->admasysaddr = dscr.addr; 860 trace_sdhci_adma("link", s->admasysaddr); 861 break; 862 default: 863 s->admasysaddr += dscr.incr; 864 break; 865 } 866 867 if (dscr.attr & SDHC_ADMA_ATTR_INT) { 868 trace_sdhci_adma("interrupt", s->admasysaddr); 869 if (s->norintstsen & SDHC_NISEN_DMA) { 870 s->norintsts |= SDHC_NIS_DMA; 871 } 872 873 sdhci_update_irq(s); 874 } 875 876 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ 877 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 878 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { 879 trace_sdhci_adma_transfer_completed(); 880 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && 881 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 882 s->blkcnt != 0)) { 883 trace_sdhci_error("SD/MMC host ADMA length mismatch"); 884 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | 885 SDHC_ADMAERR_STATE_ST_TFR; 886 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 887 trace_sdhci_error("Set ADMA error flag"); 888 s->errintsts |= SDHC_EIS_ADMAERR; 889 s->norintsts |= SDHC_NIS_ERR; 890 } 891 892 sdhci_update_irq(s); 893 } 894 sdhci_end_transfer(s); 895 return; 896 } 897 898 } 899 900 /* we have unfinished business - reschedule to continue ADMA */ 901 timer_mod(s->transfer_timer, 902 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY); 903 } 904 905 /* Perform data transfer according to controller configuration */ 906 907 static void sdhci_data_transfer(void *opaque) 908 { 909 SDHCIState *s = (SDHCIState *)opaque; 910 911 if (s->trnmod & SDHC_TRNS_DMA) { 912 switch (SDHC_DMA_TYPE(s->hostctl1)) { 913 case SDHC_CTRL_SDMA: 914 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { 915 sdhci_sdma_transfer_single_block(s); 916 } else { 917 sdhci_sdma_transfer_multi_blocks(s); 918 } 919 920 break; 921 case SDHC_CTRL_ADMA1_32: 922 if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) { 923 trace_sdhci_error("ADMA1 not supported"); 924 break; 925 } 926 927 sdhci_do_adma(s); 928 break; 929 case SDHC_CTRL_ADMA2_32: 930 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) { 931 trace_sdhci_error("ADMA2 not supported"); 932 break; 933 } 934 935 sdhci_do_adma(s); 936 break; 937 case SDHC_CTRL_ADMA2_64: 938 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) || 939 !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) { 940 trace_sdhci_error("64 bit ADMA not supported"); 941 break; 942 } 943 944 sdhci_do_adma(s); 945 break; 946 default: 947 trace_sdhci_error("Unsupported DMA type"); 948 break; 949 } 950 } else { 951 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) { 952 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 953 SDHC_DAT_LINE_ACTIVE; 954 sdhci_read_block_from_card(s); 955 } else { 956 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | 957 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; 958 sdhci_write_block_to_card(s); 959 } 960 } 961 } 962 963 static bool sdhci_can_issue_command(SDHCIState *s) 964 { 965 if (!SDHC_CLOCK_IS_ON(s->clkcon) || 966 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && 967 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || 968 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && 969 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { 970 return false; 971 } 972 973 return true; 974 } 975 976 /* The Buffer Data Port register must be accessed in sequential and 977 * continuous manner */ 978 static inline bool 979 sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) 980 { 981 if ((s->data_count & 0x3) != byte_num) { 982 trace_sdhci_error("Non-sequential access to Buffer Data Port register" 983 "is prohibited\n"); 984 return false; 985 } 986 return true; 987 } 988 989 static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) 990 { 991 SDHCIState *s = (SDHCIState *)opaque; 992 uint32_t ret = 0; 993 994 switch (offset & ~0x3) { 995 case SDHC_SYSAD: 996 ret = s->sdmasysad; 997 break; 998 case SDHC_BLKSIZE: 999 ret = s->blksize | (s->blkcnt << 16); 1000 break; 1001 case SDHC_ARGUMENT: 1002 ret = s->argument; 1003 break; 1004 case SDHC_TRNMOD: 1005 ret = s->trnmod | (s->cmdreg << 16); 1006 break; 1007 case SDHC_RSPREG0 ... SDHC_RSPREG3: 1008 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; 1009 break; 1010 case SDHC_BDATA: 1011 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1012 ret = sdhci_read_dataport(s, size); 1013 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 1014 return ret; 1015 } 1016 break; 1017 case SDHC_PRNSTS: 1018 ret = s->prnsts; 1019 ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL, 1020 sdbus_get_dat_lines(&s->sdbus)); 1021 ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL, 1022 sdbus_get_cmd_line(&s->sdbus)); 1023 break; 1024 case SDHC_HOSTCTL: 1025 ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) | 1026 (s->wakcon << 24); 1027 break; 1028 case SDHC_CLKCON: 1029 ret = s->clkcon | (s->timeoutcon << 16); 1030 break; 1031 case SDHC_NORINTSTS: 1032 ret = s->norintsts | (s->errintsts << 16); 1033 break; 1034 case SDHC_NORINTSTSEN: 1035 ret = s->norintstsen | (s->errintstsen << 16); 1036 break; 1037 case SDHC_NORINTSIGEN: 1038 ret = s->norintsigen | (s->errintsigen << 16); 1039 break; 1040 case SDHC_ACMD12ERRSTS: 1041 ret = s->acmd12errsts | (s->hostctl2 << 16); 1042 break; 1043 case SDHC_CAPAB: 1044 ret = (uint32_t)s->capareg; 1045 break; 1046 case SDHC_CAPAB + 4: 1047 ret = (uint32_t)(s->capareg >> 32); 1048 break; 1049 case SDHC_MAXCURR: 1050 ret = (uint32_t)s->maxcurr; 1051 break; 1052 case SDHC_MAXCURR + 4: 1053 ret = (uint32_t)(s->maxcurr >> 32); 1054 break; 1055 case SDHC_ADMAERR: 1056 ret = s->admaerr; 1057 break; 1058 case SDHC_ADMASYSADDR: 1059 ret = (uint32_t)s->admasysaddr; 1060 break; 1061 case SDHC_ADMASYSADDR + 4: 1062 ret = (uint32_t)(s->admasysaddr >> 32); 1063 break; 1064 case SDHC_SLOT_INT_STATUS: 1065 ret = (s->version << 16) | sdhci_slotint(s); 1066 break; 1067 default: 1068 qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " " 1069 "not implemented\n", size, offset); 1070 break; 1071 } 1072 1073 ret >>= (offset & 0x3) * 8; 1074 ret &= (1ULL << (size * 8)) - 1; 1075 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 1076 return ret; 1077 } 1078 1079 static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) 1080 { 1081 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { 1082 return; 1083 } 1084 s->blkgap = value & SDHC_STOP_AT_GAP_REQ; 1085 1086 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && 1087 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { 1088 if (s->stopped_state == sdhc_gap_read) { 1089 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; 1090 sdhci_read_block_from_card(s); 1091 } else { 1092 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; 1093 sdhci_write_block_to_card(s); 1094 } 1095 s->stopped_state = sdhc_not_stopped; 1096 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { 1097 if (s->prnsts & SDHC_DOING_READ) { 1098 s->stopped_state = sdhc_gap_read; 1099 } else if (s->prnsts & SDHC_DOING_WRITE) { 1100 s->stopped_state = sdhc_gap_write; 1101 } 1102 } 1103 } 1104 1105 static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) 1106 { 1107 switch (value) { 1108 case SDHC_RESET_ALL: 1109 sdhci_reset(s); 1110 break; 1111 case SDHC_RESET_CMD: 1112 s->prnsts &= ~SDHC_CMD_INHIBIT; 1113 s->norintsts &= ~SDHC_NIS_CMDCMP; 1114 break; 1115 case SDHC_RESET_DATA: 1116 s->data_count = 0; 1117 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | 1118 SDHC_DOING_READ | SDHC_DOING_WRITE | 1119 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); 1120 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); 1121 s->stopped_state = sdhc_not_stopped; 1122 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | 1123 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); 1124 break; 1125 } 1126 } 1127 1128 static void 1129 sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1130 { 1131 SDHCIState *s = (SDHCIState *)opaque; 1132 unsigned shift = 8 * (offset & 0x3); 1133 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); 1134 uint32_t value = val; 1135 value <<= shift; 1136 1137 switch (offset & ~0x3) { 1138 case SDHC_SYSAD: 1139 s->sdmasysad = (s->sdmasysad & mask) | value; 1140 MASKED_WRITE(s->sdmasysad, mask, value); 1141 /* Writing to last byte of sdmasysad might trigger transfer */ 1142 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && 1143 s->blksize && SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) { 1144 if (s->trnmod & SDHC_TRNS_MULTI) { 1145 sdhci_sdma_transfer_multi_blocks(s); 1146 } else { 1147 sdhci_sdma_transfer_single_block(s); 1148 } 1149 } 1150 break; 1151 case SDHC_BLKSIZE: 1152 if (!TRANSFERRING_DATA(s->prnsts)) { 1153 MASKED_WRITE(s->blksize, mask, value); 1154 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); 1155 } 1156 1157 /* Limit block size to the maximum buffer size */ 1158 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) { 1159 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " \ 1160 "the maximum buffer 0x%x", __func__, s->blksize, 1161 s->buf_maxsz); 1162 1163 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz); 1164 } 1165 1166 break; 1167 case SDHC_ARGUMENT: 1168 MASKED_WRITE(s->argument, mask, value); 1169 break; 1170 case SDHC_TRNMOD: 1171 /* DMA can be enabled only if it is supported as indicated by 1172 * capabilities register */ 1173 if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { 1174 value &= ~SDHC_TRNS_DMA; 1175 } 1176 MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK); 1177 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); 1178 1179 /* Writing to the upper byte of CMDREG triggers SD command generation */ 1180 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { 1181 break; 1182 } 1183 1184 sdhci_send_command(s); 1185 break; 1186 case SDHC_BDATA: 1187 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1188 sdhci_write_dataport(s, value >> shift, size); 1189 } 1190 break; 1191 case SDHC_HOSTCTL: 1192 if (!(mask & 0xFF0000)) { 1193 sdhci_blkgap_write(s, value >> 16); 1194 } 1195 MASKED_WRITE(s->hostctl1, mask, value); 1196 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); 1197 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); 1198 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || 1199 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { 1200 s->pwrcon &= ~SDHC_POWER_ON; 1201 } 1202 break; 1203 case SDHC_CLKCON: 1204 if (!(mask & 0xFF000000)) { 1205 sdhci_reset_write(s, value >> 24); 1206 } 1207 MASKED_WRITE(s->clkcon, mask, value); 1208 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); 1209 if (s->clkcon & SDHC_CLOCK_INT_EN) { 1210 s->clkcon |= SDHC_CLOCK_INT_STABLE; 1211 } else { 1212 s->clkcon &= ~SDHC_CLOCK_INT_STABLE; 1213 } 1214 break; 1215 case SDHC_NORINTSTS: 1216 if (s->norintstsen & SDHC_NISEN_CARDINT) { 1217 value &= ~SDHC_NIS_CARDINT; 1218 } 1219 s->norintsts &= mask | ~value; 1220 s->errintsts &= (mask >> 16) | ~(value >> 16); 1221 if (s->errintsts) { 1222 s->norintsts |= SDHC_NIS_ERR; 1223 } else { 1224 s->norintsts &= ~SDHC_NIS_ERR; 1225 } 1226 sdhci_update_irq(s); 1227 break; 1228 case SDHC_NORINTSTSEN: 1229 MASKED_WRITE(s->norintstsen, mask, value); 1230 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); 1231 s->norintsts &= s->norintstsen; 1232 s->errintsts &= s->errintstsen; 1233 if (s->errintsts) { 1234 s->norintsts |= SDHC_NIS_ERR; 1235 } else { 1236 s->norintsts &= ~SDHC_NIS_ERR; 1237 } 1238 /* Quirk for Raspberry Pi: pending card insert interrupt 1239 * appears when first enabled after power on */ 1240 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { 1241 assert(s->pending_insert_quirk); 1242 s->norintsts |= SDHC_NIS_INSERT; 1243 s->pending_insert_state = false; 1244 } 1245 sdhci_update_irq(s); 1246 break; 1247 case SDHC_NORINTSIGEN: 1248 MASKED_WRITE(s->norintsigen, mask, value); 1249 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); 1250 sdhci_update_irq(s); 1251 break; 1252 case SDHC_ADMAERR: 1253 MASKED_WRITE(s->admaerr, mask, value); 1254 break; 1255 case SDHC_ADMASYSADDR: 1256 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | 1257 (uint64_t)mask)) | (uint64_t)value; 1258 break; 1259 case SDHC_ADMASYSADDR + 4: 1260 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | 1261 ((uint64_t)mask << 32))) | ((uint64_t)value << 32); 1262 break; 1263 case SDHC_FEAER: 1264 s->acmd12errsts |= value; 1265 s->errintsts |= (value >> 16) & s->errintstsen; 1266 if (s->acmd12errsts) { 1267 s->errintsts |= SDHC_EIS_CMD12ERR; 1268 } 1269 if (s->errintsts) { 1270 s->norintsts |= SDHC_NIS_ERR; 1271 } 1272 sdhci_update_irq(s); 1273 break; 1274 case SDHC_ACMD12ERRSTS: 1275 MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX); 1276 if (s->uhs_mode >= UHS_I) { 1277 MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16); 1278 1279 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) { 1280 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V); 1281 } else { 1282 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V); 1283 } 1284 } 1285 break; 1286 1287 case SDHC_CAPAB: 1288 case SDHC_CAPAB + 4: 1289 case SDHC_MAXCURR: 1290 case SDHC_MAXCURR + 4: 1291 qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx 1292 " <- 0x%08x read-only\n", size, offset, value >> shift); 1293 break; 1294 1295 default: 1296 qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x " 1297 "not implemented\n", size, offset, value >> shift); 1298 break; 1299 } 1300 trace_sdhci_access("wr", size << 3, offset, "<-", 1301 value >> shift, value >> shift); 1302 } 1303 1304 static const MemoryRegionOps sdhci_mmio_ops = { 1305 .read = sdhci_read, 1306 .write = sdhci_write, 1307 .valid = { 1308 .min_access_size = 1, 1309 .max_access_size = 4, 1310 .unaligned = false 1311 }, 1312 .endianness = DEVICE_LITTLE_ENDIAN, 1313 }; 1314 1315 static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) 1316 { 1317 Error *local_err = NULL; 1318 1319 switch (s->sd_spec_version) { 1320 case 2 ... 3: 1321 break; 1322 default: 1323 error_setg(errp, "Only Spec v2/v3 are supported"); 1324 return; 1325 } 1326 s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1); 1327 1328 sdhci_check_capareg(s, &local_err); 1329 if (local_err) { 1330 error_propagate(errp, local_err); 1331 return; 1332 } 1333 } 1334 1335 /* --- qdev common --- */ 1336 1337 #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \ 1338 DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \ 1339 DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \ 1340 \ 1341 /* Capabilities registers provide information on supported 1342 * features of this specific host controller implementation */ \ 1343 DEFINE_PROP_UINT64("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \ 1344 DEFINE_PROP_UINT64("maxcurr", _state, maxcurr, 0) 1345 1346 static void sdhci_initfn(SDHCIState *s) 1347 { 1348 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), 1349 TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); 1350 1351 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); 1352 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); 1353 1354 s->io_ops = &sdhci_mmio_ops; 1355 } 1356 1357 static void sdhci_uninitfn(SDHCIState *s) 1358 { 1359 timer_del(s->insert_timer); 1360 timer_free(s->insert_timer); 1361 timer_del(s->transfer_timer); 1362 timer_free(s->transfer_timer); 1363 1364 g_free(s->fifo_buffer); 1365 s->fifo_buffer = NULL; 1366 } 1367 1368 static void sdhci_common_realize(SDHCIState *s, Error **errp) 1369 { 1370 Error *local_err = NULL; 1371 1372 sdhci_init_readonly_registers(s, &local_err); 1373 if (local_err) { 1374 error_propagate(errp, local_err); 1375 return; 1376 } 1377 s->buf_maxsz = sdhci_get_fifolen(s); 1378 s->fifo_buffer = g_malloc0(s->buf_maxsz); 1379 1380 memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci", 1381 SDHC_REGISTERS_MAP_SIZE); 1382 } 1383 1384 static void sdhci_common_unrealize(SDHCIState *s, Error **errp) 1385 { 1386 /* This function is expected to be called only once for each class: 1387 * - SysBus: via DeviceClass->unrealize(), 1388 * - PCI: via PCIDeviceClass->exit(). 1389 * However to avoid double-free and/or use-after-free we still nullify 1390 * this variable (better safe than sorry!). */ 1391 g_free(s->fifo_buffer); 1392 s->fifo_buffer = NULL; 1393 } 1394 1395 static bool sdhci_pending_insert_vmstate_needed(void *opaque) 1396 { 1397 SDHCIState *s = opaque; 1398 1399 return s->pending_insert_state; 1400 } 1401 1402 static const VMStateDescription sdhci_pending_insert_vmstate = { 1403 .name = "sdhci/pending-insert", 1404 .version_id = 1, 1405 .minimum_version_id = 1, 1406 .needed = sdhci_pending_insert_vmstate_needed, 1407 .fields = (VMStateField[]) { 1408 VMSTATE_BOOL(pending_insert_state, SDHCIState), 1409 VMSTATE_END_OF_LIST() 1410 }, 1411 }; 1412 1413 const VMStateDescription sdhci_vmstate = { 1414 .name = "sdhci", 1415 .version_id = 1, 1416 .minimum_version_id = 1, 1417 .fields = (VMStateField[]) { 1418 VMSTATE_UINT32(sdmasysad, SDHCIState), 1419 VMSTATE_UINT16(blksize, SDHCIState), 1420 VMSTATE_UINT16(blkcnt, SDHCIState), 1421 VMSTATE_UINT32(argument, SDHCIState), 1422 VMSTATE_UINT16(trnmod, SDHCIState), 1423 VMSTATE_UINT16(cmdreg, SDHCIState), 1424 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), 1425 VMSTATE_UINT32(prnsts, SDHCIState), 1426 VMSTATE_UINT8(hostctl1, SDHCIState), 1427 VMSTATE_UINT8(pwrcon, SDHCIState), 1428 VMSTATE_UINT8(blkgap, SDHCIState), 1429 VMSTATE_UINT8(wakcon, SDHCIState), 1430 VMSTATE_UINT16(clkcon, SDHCIState), 1431 VMSTATE_UINT8(timeoutcon, SDHCIState), 1432 VMSTATE_UINT8(admaerr, SDHCIState), 1433 VMSTATE_UINT16(norintsts, SDHCIState), 1434 VMSTATE_UINT16(errintsts, SDHCIState), 1435 VMSTATE_UINT16(norintstsen, SDHCIState), 1436 VMSTATE_UINT16(errintstsen, SDHCIState), 1437 VMSTATE_UINT16(norintsigen, SDHCIState), 1438 VMSTATE_UINT16(errintsigen, SDHCIState), 1439 VMSTATE_UINT16(acmd12errsts, SDHCIState), 1440 VMSTATE_UINT16(data_count, SDHCIState), 1441 VMSTATE_UINT64(admasysaddr, SDHCIState), 1442 VMSTATE_UINT8(stopped_state, SDHCIState), 1443 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz), 1444 VMSTATE_TIMER_PTR(insert_timer, SDHCIState), 1445 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState), 1446 VMSTATE_END_OF_LIST() 1447 }, 1448 .subsections = (const VMStateDescription*[]) { 1449 &sdhci_pending_insert_vmstate, 1450 NULL 1451 }, 1452 }; 1453 1454 static void sdhci_common_class_init(ObjectClass *klass, void *data) 1455 { 1456 DeviceClass *dc = DEVICE_CLASS(klass); 1457 1458 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1459 dc->vmsd = &sdhci_vmstate; 1460 dc->reset = sdhci_poweron_reset; 1461 } 1462 1463 /* --- qdev PCI --- */ 1464 1465 static Property sdhci_pci_properties[] = { 1466 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), 1467 DEFINE_PROP_END_OF_LIST(), 1468 }; 1469 1470 static void sdhci_pci_realize(PCIDevice *dev, Error **errp) 1471 { 1472 SDHCIState *s = PCI_SDHCI(dev); 1473 Error *local_err = NULL; 1474 1475 sdhci_initfn(s); 1476 sdhci_common_realize(s, &local_err); 1477 if (local_err) { 1478 error_propagate(errp, local_err); 1479 return; 1480 } 1481 1482 dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */ 1483 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ 1484 s->irq = pci_allocate_irq(dev); 1485 s->dma_as = pci_get_address_space(dev); 1486 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->iomem); 1487 } 1488 1489 static void sdhci_pci_exit(PCIDevice *dev) 1490 { 1491 SDHCIState *s = PCI_SDHCI(dev); 1492 1493 sdhci_common_unrealize(s, &error_abort); 1494 sdhci_uninitfn(s); 1495 } 1496 1497 static void sdhci_pci_class_init(ObjectClass *klass, void *data) 1498 { 1499 DeviceClass *dc = DEVICE_CLASS(klass); 1500 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1501 1502 k->realize = sdhci_pci_realize; 1503 k->exit = sdhci_pci_exit; 1504 k->vendor_id = PCI_VENDOR_ID_REDHAT; 1505 k->device_id = PCI_DEVICE_ID_REDHAT_SDHCI; 1506 k->class_id = PCI_CLASS_SYSTEM_SDHCI; 1507 dc->props = sdhci_pci_properties; 1508 1509 sdhci_common_class_init(klass, data); 1510 } 1511 1512 static const TypeInfo sdhci_pci_info = { 1513 .name = TYPE_PCI_SDHCI, 1514 .parent = TYPE_PCI_DEVICE, 1515 .instance_size = sizeof(SDHCIState), 1516 .class_init = sdhci_pci_class_init, 1517 .interfaces = (InterfaceInfo[]) { 1518 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1519 { }, 1520 }, 1521 }; 1522 1523 /* --- qdev SysBus --- */ 1524 1525 static Property sdhci_sysbus_properties[] = { 1526 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), 1527 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, 1528 false), 1529 DEFINE_PROP_LINK("dma", SDHCIState, 1530 dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), 1531 DEFINE_PROP_END_OF_LIST(), 1532 }; 1533 1534 static void sdhci_sysbus_init(Object *obj) 1535 { 1536 SDHCIState *s = SYSBUS_SDHCI(obj); 1537 1538 sdhci_initfn(s); 1539 } 1540 1541 static void sdhci_sysbus_finalize(Object *obj) 1542 { 1543 SDHCIState *s = SYSBUS_SDHCI(obj); 1544 1545 if (s->dma_mr) { 1546 object_unparent(OBJECT(s->dma_mr)); 1547 } 1548 1549 sdhci_uninitfn(s); 1550 } 1551 1552 static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp) 1553 { 1554 SDHCIState *s = SYSBUS_SDHCI(dev); 1555 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1556 Error *local_err = NULL; 1557 1558 sdhci_common_realize(s, &local_err); 1559 if (local_err) { 1560 error_propagate(errp, local_err); 1561 return; 1562 } 1563 1564 if (s->dma_mr) { 1565 s->dma_as = &s->sysbus_dma_as; 1566 address_space_init(s->dma_as, s->dma_mr, "sdhci-dma"); 1567 } else { 1568 /* use system_memory() if property "dma" not set */ 1569 s->dma_as = &address_space_memory; 1570 } 1571 1572 sysbus_init_irq(sbd, &s->irq); 1573 1574 memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci", 1575 SDHC_REGISTERS_MAP_SIZE); 1576 1577 sysbus_init_mmio(sbd, &s->iomem); 1578 } 1579 1580 static void sdhci_sysbus_unrealize(DeviceState *dev, Error **errp) 1581 { 1582 SDHCIState *s = SYSBUS_SDHCI(dev); 1583 1584 sdhci_common_unrealize(s, &error_abort); 1585 1586 if (s->dma_mr) { 1587 address_space_destroy(s->dma_as); 1588 } 1589 } 1590 1591 static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) 1592 { 1593 DeviceClass *dc = DEVICE_CLASS(klass); 1594 1595 dc->props = sdhci_sysbus_properties; 1596 dc->realize = sdhci_sysbus_realize; 1597 dc->unrealize = sdhci_sysbus_unrealize; 1598 1599 sdhci_common_class_init(klass, data); 1600 } 1601 1602 static const TypeInfo sdhci_sysbus_info = { 1603 .name = TYPE_SYSBUS_SDHCI, 1604 .parent = TYPE_SYS_BUS_DEVICE, 1605 .instance_size = sizeof(SDHCIState), 1606 .instance_init = sdhci_sysbus_init, 1607 .instance_finalize = sdhci_sysbus_finalize, 1608 .class_init = sdhci_sysbus_class_init, 1609 }; 1610 1611 /* --- qdev bus master --- */ 1612 1613 static void sdhci_bus_class_init(ObjectClass *klass, void *data) 1614 { 1615 SDBusClass *sbc = SD_BUS_CLASS(klass); 1616 1617 sbc->set_inserted = sdhci_set_inserted; 1618 sbc->set_readonly = sdhci_set_readonly; 1619 } 1620 1621 static const TypeInfo sdhci_bus_info = { 1622 .name = TYPE_SDHCI_BUS, 1623 .parent = TYPE_SD_BUS, 1624 .instance_size = sizeof(SDBus), 1625 .class_init = sdhci_bus_class_init, 1626 }; 1627 1628 static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) 1629 { 1630 SDHCIState *s = SYSBUS_SDHCI(opaque); 1631 uint32_t ret; 1632 uint16_t hostctl1; 1633 1634 switch (offset) { 1635 default: 1636 return sdhci_read(opaque, offset, size); 1637 1638 case SDHC_HOSTCTL: 1639 /* 1640 * For a detailed explanation on the following bit 1641 * manipulation code see comments in a similar part of 1642 * usdhc_write() 1643 */ 1644 hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3); 1645 1646 if (s->hostctl1 & SDHC_CTRL_8BITBUS) { 1647 hostctl1 |= ESDHC_CTRL_8BITBUS; 1648 } 1649 1650 if (s->hostctl1 & SDHC_CTRL_4BITBUS) { 1651 hostctl1 |= ESDHC_CTRL_4BITBUS; 1652 } 1653 1654 ret = hostctl1; 1655 ret |= (uint32_t)s->blkgap << 16; 1656 ret |= (uint32_t)s->wakcon << 24; 1657 1658 break; 1659 1660 case ESDHC_DLL_CTRL: 1661 case ESDHC_TUNE_CTRL_STATUS: 1662 case ESDHC_UNDOCUMENTED_REG27: 1663 case ESDHC_TUNING_CTRL: 1664 case ESDHC_VENDOR_SPEC: 1665 case ESDHC_MIX_CTRL: 1666 case ESDHC_WTMK_LVL: 1667 ret = 0; 1668 break; 1669 } 1670 1671 return ret; 1672 } 1673 1674 static void 1675 usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1676 { 1677 SDHCIState *s = SYSBUS_SDHCI(opaque); 1678 uint8_t hostctl1; 1679 uint32_t value = (uint32_t)val; 1680 1681 switch (offset) { 1682 case ESDHC_DLL_CTRL: 1683 case ESDHC_TUNE_CTRL_STATUS: 1684 case ESDHC_UNDOCUMENTED_REG27: 1685 case ESDHC_TUNING_CTRL: 1686 case ESDHC_WTMK_LVL: 1687 case ESDHC_VENDOR_SPEC: 1688 break; 1689 1690 case SDHC_HOSTCTL: 1691 /* 1692 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL) 1693 * 1694 * 7 6 5 4 3 2 1 0 1695 * |-----------+--------+--------+-----------+----------+---------| 1696 * | Card | Card | Endian | DATA3 | Data | Led | 1697 * | Detect | Detect | Mode | as Card | Transfer | Control | 1698 * | Signal | Test | | Detection | Width | | 1699 * | Selection | Level | | Pin | | | 1700 * |-----------+--------+--------+-----------+----------+---------| 1701 * 1702 * and 0x29 1703 * 1704 * 15 10 9 8 1705 * |----------+------| 1706 * | Reserved | DMA | 1707 * | | Sel. | 1708 * | | | 1709 * |----------+------| 1710 * 1711 * and here's what SDCHI spec expects those offsets to be: 1712 * 1713 * 0x28 (Host Control Register) 1714 * 1715 * 7 6 5 4 3 2 1 0 1716 * |--------+--------+----------+------+--------+----------+---------| 1717 * | Card | Card | Extended | DMA | High | Data | LED | 1718 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control | 1719 * | Signal | Test | Transfer | | Enable | Width | | 1720 * | Sel. | Level | Width | | | | | 1721 * |--------+--------+----------+------+--------+----------+---------| 1722 * 1723 * and 0x29 (Power Control Register) 1724 * 1725 * |----------------------------------| 1726 * | Power Control Register | 1727 * | | 1728 * | Description omitted, | 1729 * | since it has no analog in ESDHCI | 1730 * | | 1731 * |----------------------------------| 1732 * 1733 * Since offsets 0x2A and 0x2B should be compatible between 1734 * both IP specs we only need to reconcile least 16-bit of the 1735 * word we've been given. 1736 */ 1737 1738 /* 1739 * First, save bits 7 6 and 0 since they are identical 1740 */ 1741 hostctl1 = value & (SDHC_CTRL_LED | 1742 SDHC_CTRL_CDTEST_INS | 1743 SDHC_CTRL_CDTEST_EN); 1744 /* 1745 * Second, split "Data Transfer Width" from bits 2 and 1 in to 1746 * bits 5 and 1 1747 */ 1748 if (value & ESDHC_CTRL_8BITBUS) { 1749 hostctl1 |= SDHC_CTRL_8BITBUS; 1750 } 1751 1752 if (value & ESDHC_CTRL_4BITBUS) { 1753 hostctl1 |= ESDHC_CTRL_4BITBUS; 1754 } 1755 1756 /* 1757 * Third, move DMA select from bits 9 and 8 to bits 4 and 3 1758 */ 1759 hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3)); 1760 1761 /* 1762 * Now place the corrected value into low 16-bit of the value 1763 * we are going to give standard SDHCI write function 1764 * 1765 * NOTE: This transformation should be the inverse of what can 1766 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux 1767 * kernel 1768 */ 1769 value &= ~UINT16_MAX; 1770 value |= hostctl1; 1771 value |= (uint16_t)s->pwrcon << 8; 1772 1773 sdhci_write(opaque, offset, value, size); 1774 break; 1775 1776 case ESDHC_MIX_CTRL: 1777 /* 1778 * So, when SD/MMC stack in Linux tries to write to "Transfer 1779 * Mode Register", ESDHC i.MX quirk code will translate it 1780 * into a write to ESDHC_MIX_CTRL, so we do the opposite in 1781 * order to get where we started 1782 * 1783 * Note that Auto CMD23 Enable bit is located in a wrong place 1784 * on i.MX, but since it is not used by QEMU we do not care. 1785 * 1786 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...) 1787 * here becuase it will result in a call to 1788 * sdhci_send_command(s) which we don't want. 1789 * 1790 */ 1791 s->trnmod = value & UINT16_MAX; 1792 break; 1793 case SDHC_TRNMOD: 1794 /* 1795 * Similar to above, but this time a write to "Command 1796 * Register" will be translated into a 4-byte write to 1797 * "Transfer Mode register" where lower 16-bit of value would 1798 * be set to zero. So what we do is fill those bits with 1799 * cached value from s->trnmod and let the SDHCI 1800 * infrastructure handle the rest 1801 */ 1802 sdhci_write(opaque, offset, val | s->trnmod, size); 1803 break; 1804 case SDHC_BLKSIZE: 1805 /* 1806 * ESDHCI does not implement "Host SDMA Buffer Boundary", and 1807 * Linux driver will try to zero this field out which will 1808 * break the rest of SDHCI emulation. 1809 * 1810 * Linux defaults to maximum possible setting (512K boundary) 1811 * and it seems to be the only option that i.MX IP implements, 1812 * so we artificially set it to that value. 1813 */ 1814 val |= 0x7 << 12; 1815 /* FALLTHROUGH */ 1816 default: 1817 sdhci_write(opaque, offset, val, size); 1818 break; 1819 } 1820 } 1821 1822 1823 static const MemoryRegionOps usdhc_mmio_ops = { 1824 .read = usdhc_read, 1825 .write = usdhc_write, 1826 .valid = { 1827 .min_access_size = 1, 1828 .max_access_size = 4, 1829 .unaligned = false 1830 }, 1831 .endianness = DEVICE_LITTLE_ENDIAN, 1832 }; 1833 1834 static void imx_usdhc_init(Object *obj) 1835 { 1836 SDHCIState *s = SYSBUS_SDHCI(obj); 1837 1838 s->io_ops = &usdhc_mmio_ops; 1839 s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; 1840 } 1841 1842 static const TypeInfo imx_usdhc_info = { 1843 .name = TYPE_IMX_USDHC, 1844 .parent = TYPE_SYSBUS_SDHCI, 1845 .instance_init = imx_usdhc_init, 1846 }; 1847 1848 static void sdhci_register_types(void) 1849 { 1850 type_register_static(&sdhci_pci_info); 1851 type_register_static(&sdhci_sysbus_info); 1852 type_register_static(&sdhci_bus_info); 1853 type_register_static(&imx_usdhc_info); 1854 } 1855 1856 type_init(sdhci_register_types) 1857