1 /* 2 * SD Association Host Standard Specification v2.0 controller emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Mitsyanko Igor <i.mitsyanko@samsung.com> 6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 7 * 8 * Based on MMC controller for Samsung S5PC1xx-based board emulation 9 * by Alexey Merkulov and Vladimir Monakhov. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 19 * See the GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qemu/error-report.h" 28 #include "qapi/error.h" 29 #include "hw/hw.h" 30 #include "sysemu/dma.h" 31 #include "qemu/timer.h" 32 #include "qemu/bitops.h" 33 #include "hw/sd/sdhci.h" 34 #include "sdhci-internal.h" 35 #include "qemu/log.h" 36 #include "trace.h" 37 38 #define TYPE_SDHCI_BUS "sdhci-bus" 39 #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS) 40 41 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) 42 43 /* Default SD/MMC host controller features information, which will be 44 * presented in CAPABILITIES register of generic SD host controller at reset. 45 * 46 * support: 47 * - 3.3v and 1.8v voltages 48 * - SDMA/ADMA1/ADMA2 49 * - high-speed 50 * max host controller R/W buffers size: 512B 51 * max clock frequency for SDclock: 52 MHz 52 * timeout clock frequency: 52 MHz 53 * 54 * does not support: 55 * - 3.0v voltage 56 * - 64-bit system bus 57 * - suspend/resume 58 */ 59 #define SDHC_CAPAB_REG_DEFAULT 0x057834b4 60 61 static inline unsigned int sdhci_get_fifolen(SDHCIState *s) 62 { 63 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); 64 } 65 66 /* return true on error */ 67 static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, 68 uint8_t freq, Error **errp) 69 { 70 if (s->sd_spec_version >= 3) { 71 return false; 72 } 73 switch (freq) { 74 case 0: 75 case 10 ... 63: 76 break; 77 default: 78 error_setg(errp, "SD %s clock frequency can have value" 79 "in range 0-63 only", desc); 80 return true; 81 } 82 return false; 83 } 84 85 static void sdhci_check_capareg(SDHCIState *s, Error **errp) 86 { 87 uint64_t msk = s->capareg; 88 uint32_t val; 89 bool y; 90 91 switch (s->sd_spec_version) { 92 case 4: 93 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4); 94 trace_sdhci_capareg("64-bit system bus (v4)", val); 95 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0); 96 97 val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II); 98 trace_sdhci_capareg("UHS-II", val); 99 msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0); 100 101 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3); 102 trace_sdhci_capareg("ADMA3", val); 103 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0); 104 105 /* fallthrough */ 106 case 3: 107 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT); 108 trace_sdhci_capareg("async interrupt", val); 109 msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0); 110 111 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE); 112 if (val) { 113 error_setg(errp, "slot-type not supported"); 114 return; 115 } 116 trace_sdhci_capareg("slot type", val); 117 msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0); 118 119 if (val != 2) { 120 val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT); 121 trace_sdhci_capareg("8-bit bus", val); 122 } 123 msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0); 124 125 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED); 126 trace_sdhci_capareg("bus speed mask", val); 127 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0); 128 129 val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH); 130 trace_sdhci_capareg("driver strength mask", val); 131 msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0); 132 133 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING); 134 trace_sdhci_capareg("timer re-tuning", val); 135 msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0); 136 137 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING); 138 trace_sdhci_capareg("use SDR50 tuning", val); 139 msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0); 140 141 val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE); 142 trace_sdhci_capareg("re-tuning mode", val); 143 msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0); 144 145 val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT); 146 trace_sdhci_capareg("clock multiplier", val); 147 msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0); 148 149 /* fallthrough */ 150 case 2: /* default version */ 151 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2); 152 trace_sdhci_capareg("ADMA2", val); 153 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0); 154 155 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1); 156 trace_sdhci_capareg("ADMA1", val); 157 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0); 158 159 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT); 160 trace_sdhci_capareg("64-bit system bus (v3)", val); 161 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0); 162 163 /* fallthrough */ 164 case 1: 165 y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT); 166 msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0); 167 168 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ); 169 trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val); 170 if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) { 171 return; 172 } 173 msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0); 174 175 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ); 176 trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val); 177 if (sdhci_check_capab_freq_range(s, "base", val, errp)) { 178 return; 179 } 180 msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0); 181 182 val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH); 183 if (val >= 3) { 184 error_setg(errp, "block size can be 512, 1024 or 2048 only"); 185 return; 186 } 187 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s)); 188 msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0); 189 190 val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED); 191 trace_sdhci_capareg("high speed", val); 192 msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0); 193 194 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA); 195 trace_sdhci_capareg("SDMA", val); 196 msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0); 197 198 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME); 199 trace_sdhci_capareg("suspend/resume", val); 200 msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0); 201 202 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33); 203 trace_sdhci_capareg("3.3v", val); 204 msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0); 205 206 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30); 207 trace_sdhci_capareg("3.0v", val); 208 msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0); 209 210 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18); 211 trace_sdhci_capareg("1.8v", val); 212 msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0); 213 break; 214 215 default: 216 error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version); 217 } 218 if (msk) { 219 qemu_log_mask(LOG_UNIMP, 220 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk); 221 } 222 } 223 224 static uint8_t sdhci_slotint(SDHCIState *s) 225 { 226 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || 227 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || 228 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); 229 } 230 231 static inline void sdhci_update_irq(SDHCIState *s) 232 { 233 qemu_set_irq(s->irq, sdhci_slotint(s)); 234 } 235 236 static void sdhci_raise_insertion_irq(void *opaque) 237 { 238 SDHCIState *s = (SDHCIState *)opaque; 239 240 if (s->norintsts & SDHC_NIS_REMOVE) { 241 timer_mod(s->insert_timer, 242 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 243 } else { 244 s->prnsts = 0x1ff0000; 245 if (s->norintstsen & SDHC_NISEN_INSERT) { 246 s->norintsts |= SDHC_NIS_INSERT; 247 } 248 sdhci_update_irq(s); 249 } 250 } 251 252 static void sdhci_set_inserted(DeviceState *dev, bool level) 253 { 254 SDHCIState *s = (SDHCIState *)dev; 255 256 trace_sdhci_set_inserted(level ? "insert" : "eject"); 257 if ((s->norintsts & SDHC_NIS_REMOVE) && level) { 258 /* Give target some time to notice card ejection */ 259 timer_mod(s->insert_timer, 260 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 261 } else { 262 if (level) { 263 s->prnsts = 0x1ff0000; 264 if (s->norintstsen & SDHC_NISEN_INSERT) { 265 s->norintsts |= SDHC_NIS_INSERT; 266 } 267 } else { 268 s->prnsts = 0x1fa0000; 269 s->pwrcon &= ~SDHC_POWER_ON; 270 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; 271 if (s->norintstsen & SDHC_NISEN_REMOVE) { 272 s->norintsts |= SDHC_NIS_REMOVE; 273 } 274 } 275 sdhci_update_irq(s); 276 } 277 } 278 279 static void sdhci_set_readonly(DeviceState *dev, bool level) 280 { 281 SDHCIState *s = (SDHCIState *)dev; 282 283 if (level) { 284 s->prnsts &= ~SDHC_WRITE_PROTECT; 285 } else { 286 /* Write enabled */ 287 s->prnsts |= SDHC_WRITE_PROTECT; 288 } 289 } 290 291 static void sdhci_reset(SDHCIState *s) 292 { 293 DeviceState *dev = DEVICE(s); 294 295 timer_del(s->insert_timer); 296 timer_del(s->transfer_timer); 297 298 /* Set all registers to 0. Capabilities/Version registers are not cleared 299 * and assumed to always preserve their value, given to them during 300 * initialization */ 301 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); 302 303 /* Reset other state based on current card insertion/readonly status */ 304 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus)); 305 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus)); 306 307 s->data_count = 0; 308 s->stopped_state = sdhc_not_stopped; 309 s->pending_insert_state = false; 310 } 311 312 static void sdhci_poweron_reset(DeviceState *dev) 313 { 314 /* QOM (ie power-on) reset. This is identical to reset 315 * commanded via device register apart from handling of the 316 * 'pending insert on powerup' quirk. 317 */ 318 SDHCIState *s = (SDHCIState *)dev; 319 320 sdhci_reset(s); 321 322 if (s->pending_insert_quirk) { 323 s->pending_insert_state = true; 324 } 325 } 326 327 static void sdhci_data_transfer(void *opaque); 328 329 static void sdhci_send_command(SDHCIState *s) 330 { 331 SDRequest request; 332 uint8_t response[16]; 333 int rlen; 334 335 s->errintsts = 0; 336 s->acmd12errsts = 0; 337 request.cmd = s->cmdreg >> 8; 338 request.arg = s->argument; 339 340 trace_sdhci_send_command(request.cmd, request.arg); 341 rlen = sdbus_do_command(&s->sdbus, &request, response); 342 343 if (s->cmdreg & SDHC_CMD_RESPONSE) { 344 if (rlen == 4) { 345 s->rspreg[0] = ldl_be_p(response); 346 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; 347 trace_sdhci_response4(s->rspreg[0]); 348 } else if (rlen == 16) { 349 s->rspreg[0] = ldl_be_p(&response[11]); 350 s->rspreg[1] = ldl_be_p(&response[7]); 351 s->rspreg[2] = ldl_be_p(&response[3]); 352 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | 353 response[2]; 354 trace_sdhci_response16(s->rspreg[3], s->rspreg[2], 355 s->rspreg[1], s->rspreg[0]); 356 } else { 357 trace_sdhci_error("timeout waiting for command response"); 358 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { 359 s->errintsts |= SDHC_EIS_CMDTIMEOUT; 360 s->norintsts |= SDHC_NIS_ERR; 361 } 362 } 363 364 if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && 365 (s->norintstsen & SDHC_NISEN_TRSCMP) && 366 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { 367 s->norintsts |= SDHC_NIS_TRSCMP; 368 } 369 } 370 371 if (s->norintstsen & SDHC_NISEN_CMDCMP) { 372 s->norintsts |= SDHC_NIS_CMDCMP; 373 } 374 375 sdhci_update_irq(s); 376 377 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { 378 s->data_count = 0; 379 sdhci_data_transfer(s); 380 } 381 } 382 383 static void sdhci_end_transfer(SDHCIState *s) 384 { 385 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */ 386 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { 387 SDRequest request; 388 uint8_t response[16]; 389 390 request.cmd = 0x0C; 391 request.arg = 0; 392 trace_sdhci_end_transfer(request.cmd, request.arg); 393 sdbus_do_command(&s->sdbus, &request, response); 394 /* Auto CMD12 response goes to the upper Response register */ 395 s->rspreg[3] = ldl_be_p(response); 396 } 397 398 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | 399 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | 400 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); 401 402 if (s->norintstsen & SDHC_NISEN_TRSCMP) { 403 s->norintsts |= SDHC_NIS_TRSCMP; 404 } 405 406 sdhci_update_irq(s); 407 } 408 409 /* 410 * Programmed i/o data transfer 411 */ 412 #define BLOCK_SIZE_MASK (4 * KiB - 1) 413 414 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ 415 static void sdhci_read_block_from_card(SDHCIState *s) 416 { 417 int index = 0; 418 uint8_t data; 419 const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK; 420 421 if ((s->trnmod & SDHC_TRNS_MULTI) && 422 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { 423 return; 424 } 425 426 for (index = 0; index < blk_size; index++) { 427 data = sdbus_read_data(&s->sdbus); 428 if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 429 /* Device is not in tuning */ 430 s->fifo_buffer[index] = data; 431 } 432 } 433 434 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 435 /* Device is in tuning */ 436 s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK; 437 s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK; 438 s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ | 439 SDHC_DATA_INHIBIT); 440 goto read_done; 441 } 442 443 /* New data now available for READ through Buffer Port Register */ 444 s->prnsts |= SDHC_DATA_AVAILABLE; 445 if (s->norintstsen & SDHC_NISEN_RBUFRDY) { 446 s->norintsts |= SDHC_NIS_RBUFRDY; 447 } 448 449 /* Clear DAT line active status if that was the last block */ 450 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 451 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { 452 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 453 } 454 455 /* If stop at block gap request was set and it's not the last block of 456 * data - generate Block Event interrupt */ 457 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && 458 s->blkcnt != 1) { 459 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 460 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 461 s->norintsts |= SDHC_EIS_BLKGAP; 462 } 463 } 464 465 read_done: 466 sdhci_update_irq(s); 467 } 468 469 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */ 470 static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) 471 { 472 uint32_t value = 0; 473 int i; 474 475 /* first check that a valid data exists in host controller input buffer */ 476 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { 477 trace_sdhci_error("read from empty buffer"); 478 return 0; 479 } 480 481 for (i = 0; i < size; i++) { 482 value |= s->fifo_buffer[s->data_count] << i * 8; 483 s->data_count++; 484 /* check if we've read all valid data (blksize bytes) from buffer */ 485 if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) { 486 trace_sdhci_read_dataport(s->data_count); 487 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ 488 s->data_count = 0; /* next buff read must start at position [0] */ 489 490 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 491 s->blkcnt--; 492 } 493 494 /* if that was the last block of data */ 495 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 496 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || 497 /* stop at gap request */ 498 (s->stopped_state == sdhc_gap_read && 499 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { 500 sdhci_end_transfer(s); 501 } else { /* if there are more data, read next block from card */ 502 sdhci_read_block_from_card(s); 503 } 504 break; 505 } 506 } 507 508 return value; 509 } 510 511 /* Write data from host controller FIFO to card */ 512 static void sdhci_write_block_to_card(SDHCIState *s) 513 { 514 int index = 0; 515 516 if (s->prnsts & SDHC_SPACE_AVAILABLE) { 517 if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 518 s->norintsts |= SDHC_NIS_WBUFRDY; 519 } 520 sdhci_update_irq(s); 521 return; 522 } 523 524 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 525 if (s->blkcnt == 0) { 526 return; 527 } else { 528 s->blkcnt--; 529 } 530 } 531 532 for (index = 0; index < (s->blksize & BLOCK_SIZE_MASK); index++) { 533 sdbus_write_data(&s->sdbus, s->fifo_buffer[index]); 534 } 535 536 /* Next data can be written through BUFFER DATORT register */ 537 s->prnsts |= SDHC_SPACE_AVAILABLE; 538 539 /* Finish transfer if that was the last block of data */ 540 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 541 ((s->trnmod & SDHC_TRNS_MULTI) && 542 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { 543 sdhci_end_transfer(s); 544 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 545 s->norintsts |= SDHC_NIS_WBUFRDY; 546 } 547 548 /* Generate Block Gap Event if requested and if not the last block */ 549 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && 550 s->blkcnt > 0) { 551 s->prnsts &= ~SDHC_DOING_WRITE; 552 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 553 s->norintsts |= SDHC_EIS_BLKGAP; 554 } 555 sdhci_end_transfer(s); 556 } 557 558 sdhci_update_irq(s); 559 } 560 561 /* Write @size bytes of @value data to host controller @s Buffer Data Port 562 * register */ 563 static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) 564 { 565 unsigned i; 566 567 /* Check that there is free space left in a buffer */ 568 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { 569 trace_sdhci_error("Can't write to data buffer: buffer full"); 570 return; 571 } 572 573 for (i = 0; i < size; i++) { 574 s->fifo_buffer[s->data_count] = value & 0xFF; 575 s->data_count++; 576 value >>= 8; 577 if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) { 578 trace_sdhci_write_dataport(s->data_count); 579 s->data_count = 0; 580 s->prnsts &= ~SDHC_SPACE_AVAILABLE; 581 if (s->prnsts & SDHC_DOING_WRITE) { 582 sdhci_write_block_to_card(s); 583 } 584 } 585 } 586 } 587 588 /* 589 * Single DMA data transfer 590 */ 591 592 /* Multi block SDMA transfer */ 593 static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) 594 { 595 bool page_aligned = false; 596 unsigned int n, begin; 597 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 598 uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12); 599 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); 600 601 if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) { 602 qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n"); 603 return; 604 } 605 606 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for 607 * possible stop at page boundary if initial address is not page aligned, 608 * allow them to work properly */ 609 if ((s->sdmasysad % boundary_chk) == 0) { 610 page_aligned = true; 611 } 612 613 if (s->trnmod & SDHC_TRNS_READ) { 614 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 615 SDHC_DAT_LINE_ACTIVE; 616 while (s->blkcnt) { 617 if (s->data_count == 0) { 618 for (n = 0; n < block_size; n++) { 619 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 620 } 621 } 622 begin = s->data_count; 623 if (((boundary_count + begin) < block_size) && page_aligned) { 624 s->data_count = boundary_count + begin; 625 boundary_count = 0; 626 } else { 627 s->data_count = block_size; 628 boundary_count -= block_size - begin; 629 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 630 s->blkcnt--; 631 } 632 } 633 dma_memory_write(s->dma_as, s->sdmasysad, 634 &s->fifo_buffer[begin], s->data_count - begin); 635 s->sdmasysad += s->data_count - begin; 636 if (s->data_count == block_size) { 637 s->data_count = 0; 638 } 639 if (page_aligned && boundary_count == 0) { 640 break; 641 } 642 } 643 } else { 644 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT | 645 SDHC_DAT_LINE_ACTIVE; 646 while (s->blkcnt) { 647 begin = s->data_count; 648 if (((boundary_count + begin) < block_size) && page_aligned) { 649 s->data_count = boundary_count + begin; 650 boundary_count = 0; 651 } else { 652 s->data_count = block_size; 653 boundary_count -= block_size - begin; 654 } 655 dma_memory_read(s->dma_as, s->sdmasysad, 656 &s->fifo_buffer[begin], s->data_count - begin); 657 s->sdmasysad += s->data_count - begin; 658 if (s->data_count == block_size) { 659 for (n = 0; n < block_size; n++) { 660 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 661 } 662 s->data_count = 0; 663 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 664 s->blkcnt--; 665 } 666 } 667 if (page_aligned && boundary_count == 0) { 668 break; 669 } 670 } 671 } 672 673 if (s->blkcnt == 0) { 674 sdhci_end_transfer(s); 675 } else { 676 if (s->norintstsen & SDHC_NISEN_DMA) { 677 s->norintsts |= SDHC_NIS_DMA; 678 } 679 sdhci_update_irq(s); 680 } 681 } 682 683 /* single block SDMA transfer */ 684 static void sdhci_sdma_transfer_single_block(SDHCIState *s) 685 { 686 int n; 687 uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK; 688 689 if (s->trnmod & SDHC_TRNS_READ) { 690 for (n = 0; n < datacnt; n++) { 691 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 692 } 693 dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); 694 } else { 695 dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); 696 for (n = 0; n < datacnt; n++) { 697 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 698 } 699 } 700 s->blkcnt--; 701 702 sdhci_end_transfer(s); 703 } 704 705 typedef struct ADMADescr { 706 hwaddr addr; 707 uint16_t length; 708 uint8_t attr; 709 uint8_t incr; 710 } ADMADescr; 711 712 static void get_adma_description(SDHCIState *s, ADMADescr *dscr) 713 { 714 uint32_t adma1 = 0; 715 uint64_t adma2 = 0; 716 hwaddr entry_addr = (hwaddr)s->admasysaddr; 717 switch (SDHC_DMA_TYPE(s->hostctl1)) { 718 case SDHC_CTRL_ADMA2_32: 719 dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma2, 720 sizeof(adma2)); 721 adma2 = le64_to_cpu(adma2); 722 /* The spec does not specify endianness of descriptor table. 723 * We currently assume that it is LE. 724 */ 725 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; 726 dscr->length = (uint16_t)extract64(adma2, 16, 16); 727 dscr->attr = (uint8_t)extract64(adma2, 0, 7); 728 dscr->incr = 8; 729 break; 730 case SDHC_CTRL_ADMA1_32: 731 dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma1, 732 sizeof(adma1)); 733 adma1 = le32_to_cpu(adma1); 734 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); 735 dscr->attr = (uint8_t)extract32(adma1, 0, 7); 736 dscr->incr = 4; 737 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { 738 dscr->length = (uint16_t)extract32(adma1, 12, 16); 739 } else { 740 dscr->length = 4 * KiB; 741 } 742 break; 743 case SDHC_CTRL_ADMA2_64: 744 dma_memory_read(s->dma_as, entry_addr, 745 (uint8_t *)(&dscr->attr), 1); 746 dma_memory_read(s->dma_as, entry_addr + 2, 747 (uint8_t *)(&dscr->length), 2); 748 dscr->length = le16_to_cpu(dscr->length); 749 dma_memory_read(s->dma_as, entry_addr + 4, 750 (uint8_t *)(&dscr->addr), 8); 751 dscr->addr = le64_to_cpu(dscr->addr); 752 dscr->attr &= (uint8_t) ~0xC0; 753 dscr->incr = 12; 754 break; 755 } 756 } 757 758 /* Advanced DMA data transfer */ 759 760 static void sdhci_do_adma(SDHCIState *s) 761 { 762 unsigned int n, begin, length; 763 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 764 ADMADescr dscr = {}; 765 int i; 766 767 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { 768 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; 769 770 get_adma_description(s, &dscr); 771 trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr); 772 773 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { 774 /* Indicate that error occurred in ST_FDS state */ 775 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; 776 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; 777 778 /* Generate ADMA error interrupt */ 779 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 780 s->errintsts |= SDHC_EIS_ADMAERR; 781 s->norintsts |= SDHC_NIS_ERR; 782 } 783 784 sdhci_update_irq(s); 785 return; 786 } 787 788 length = dscr.length ? dscr.length : 64 * KiB; 789 790 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { 791 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ 792 793 if (s->trnmod & SDHC_TRNS_READ) { 794 while (length) { 795 if (s->data_count == 0) { 796 for (n = 0; n < block_size; n++) { 797 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 798 } 799 } 800 begin = s->data_count; 801 if ((length + begin) < block_size) { 802 s->data_count = length + begin; 803 length = 0; 804 } else { 805 s->data_count = block_size; 806 length -= block_size - begin; 807 } 808 dma_memory_write(s->dma_as, dscr.addr, 809 &s->fifo_buffer[begin], 810 s->data_count - begin); 811 dscr.addr += s->data_count - begin; 812 if (s->data_count == block_size) { 813 s->data_count = 0; 814 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 815 s->blkcnt--; 816 if (s->blkcnt == 0) { 817 break; 818 } 819 } 820 } 821 } 822 } else { 823 while (length) { 824 begin = s->data_count; 825 if ((length + begin) < block_size) { 826 s->data_count = length + begin; 827 length = 0; 828 } else { 829 s->data_count = block_size; 830 length -= block_size - begin; 831 } 832 dma_memory_read(s->dma_as, dscr.addr, 833 &s->fifo_buffer[begin], 834 s->data_count - begin); 835 dscr.addr += s->data_count - begin; 836 if (s->data_count == block_size) { 837 for (n = 0; n < block_size; n++) { 838 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 839 } 840 s->data_count = 0; 841 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 842 s->blkcnt--; 843 if (s->blkcnt == 0) { 844 break; 845 } 846 } 847 } 848 } 849 } 850 s->admasysaddr += dscr.incr; 851 break; 852 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ 853 s->admasysaddr = dscr.addr; 854 trace_sdhci_adma("link", s->admasysaddr); 855 break; 856 default: 857 s->admasysaddr += dscr.incr; 858 break; 859 } 860 861 if (dscr.attr & SDHC_ADMA_ATTR_INT) { 862 trace_sdhci_adma("interrupt", s->admasysaddr); 863 if (s->norintstsen & SDHC_NISEN_DMA) { 864 s->norintsts |= SDHC_NIS_DMA; 865 } 866 867 sdhci_update_irq(s); 868 } 869 870 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ 871 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 872 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { 873 trace_sdhci_adma_transfer_completed(); 874 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && 875 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 876 s->blkcnt != 0)) { 877 trace_sdhci_error("SD/MMC host ADMA length mismatch"); 878 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | 879 SDHC_ADMAERR_STATE_ST_TFR; 880 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 881 trace_sdhci_error("Set ADMA error flag"); 882 s->errintsts |= SDHC_EIS_ADMAERR; 883 s->norintsts |= SDHC_NIS_ERR; 884 } 885 886 sdhci_update_irq(s); 887 } 888 sdhci_end_transfer(s); 889 return; 890 } 891 892 } 893 894 /* we have unfinished business - reschedule to continue ADMA */ 895 timer_mod(s->transfer_timer, 896 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY); 897 } 898 899 /* Perform data transfer according to controller configuration */ 900 901 static void sdhci_data_transfer(void *opaque) 902 { 903 SDHCIState *s = (SDHCIState *)opaque; 904 905 if (s->trnmod & SDHC_TRNS_DMA) { 906 switch (SDHC_DMA_TYPE(s->hostctl1)) { 907 case SDHC_CTRL_SDMA: 908 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { 909 sdhci_sdma_transfer_single_block(s); 910 } else { 911 sdhci_sdma_transfer_multi_blocks(s); 912 } 913 914 break; 915 case SDHC_CTRL_ADMA1_32: 916 if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) { 917 trace_sdhci_error("ADMA1 not supported"); 918 break; 919 } 920 921 sdhci_do_adma(s); 922 break; 923 case SDHC_CTRL_ADMA2_32: 924 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) { 925 trace_sdhci_error("ADMA2 not supported"); 926 break; 927 } 928 929 sdhci_do_adma(s); 930 break; 931 case SDHC_CTRL_ADMA2_64: 932 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) || 933 !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) { 934 trace_sdhci_error("64 bit ADMA not supported"); 935 break; 936 } 937 938 sdhci_do_adma(s); 939 break; 940 default: 941 trace_sdhci_error("Unsupported DMA type"); 942 break; 943 } 944 } else { 945 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) { 946 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 947 SDHC_DAT_LINE_ACTIVE; 948 sdhci_read_block_from_card(s); 949 } else { 950 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | 951 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; 952 sdhci_write_block_to_card(s); 953 } 954 } 955 } 956 957 static bool sdhci_can_issue_command(SDHCIState *s) 958 { 959 if (!SDHC_CLOCK_IS_ON(s->clkcon) || 960 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && 961 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || 962 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && 963 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { 964 return false; 965 } 966 967 return true; 968 } 969 970 /* The Buffer Data Port register must be accessed in sequential and 971 * continuous manner */ 972 static inline bool 973 sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) 974 { 975 if ((s->data_count & 0x3) != byte_num) { 976 trace_sdhci_error("Non-sequential access to Buffer Data Port register" 977 "is prohibited\n"); 978 return false; 979 } 980 return true; 981 } 982 983 static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) 984 { 985 SDHCIState *s = (SDHCIState *)opaque; 986 uint32_t ret = 0; 987 988 switch (offset & ~0x3) { 989 case SDHC_SYSAD: 990 ret = s->sdmasysad; 991 break; 992 case SDHC_BLKSIZE: 993 ret = s->blksize | (s->blkcnt << 16); 994 break; 995 case SDHC_ARGUMENT: 996 ret = s->argument; 997 break; 998 case SDHC_TRNMOD: 999 ret = s->trnmod | (s->cmdreg << 16); 1000 break; 1001 case SDHC_RSPREG0 ... SDHC_RSPREG3: 1002 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; 1003 break; 1004 case SDHC_BDATA: 1005 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1006 ret = sdhci_read_dataport(s, size); 1007 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 1008 return ret; 1009 } 1010 break; 1011 case SDHC_PRNSTS: 1012 ret = s->prnsts; 1013 ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL, 1014 sdbus_get_dat_lines(&s->sdbus)); 1015 ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL, 1016 sdbus_get_cmd_line(&s->sdbus)); 1017 break; 1018 case SDHC_HOSTCTL: 1019 ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) | 1020 (s->wakcon << 24); 1021 break; 1022 case SDHC_CLKCON: 1023 ret = s->clkcon | (s->timeoutcon << 16); 1024 break; 1025 case SDHC_NORINTSTS: 1026 ret = s->norintsts | (s->errintsts << 16); 1027 break; 1028 case SDHC_NORINTSTSEN: 1029 ret = s->norintstsen | (s->errintstsen << 16); 1030 break; 1031 case SDHC_NORINTSIGEN: 1032 ret = s->norintsigen | (s->errintsigen << 16); 1033 break; 1034 case SDHC_ACMD12ERRSTS: 1035 ret = s->acmd12errsts | (s->hostctl2 << 16); 1036 break; 1037 case SDHC_CAPAB: 1038 ret = (uint32_t)s->capareg; 1039 break; 1040 case SDHC_CAPAB + 4: 1041 ret = (uint32_t)(s->capareg >> 32); 1042 break; 1043 case SDHC_MAXCURR: 1044 ret = (uint32_t)s->maxcurr; 1045 break; 1046 case SDHC_MAXCURR + 4: 1047 ret = (uint32_t)(s->maxcurr >> 32); 1048 break; 1049 case SDHC_ADMAERR: 1050 ret = s->admaerr; 1051 break; 1052 case SDHC_ADMASYSADDR: 1053 ret = (uint32_t)s->admasysaddr; 1054 break; 1055 case SDHC_ADMASYSADDR + 4: 1056 ret = (uint32_t)(s->admasysaddr >> 32); 1057 break; 1058 case SDHC_SLOT_INT_STATUS: 1059 ret = (s->version << 16) | sdhci_slotint(s); 1060 break; 1061 default: 1062 qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " " 1063 "not implemented\n", size, offset); 1064 break; 1065 } 1066 1067 ret >>= (offset & 0x3) * 8; 1068 ret &= (1ULL << (size * 8)) - 1; 1069 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 1070 return ret; 1071 } 1072 1073 static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) 1074 { 1075 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { 1076 return; 1077 } 1078 s->blkgap = value & SDHC_STOP_AT_GAP_REQ; 1079 1080 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && 1081 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { 1082 if (s->stopped_state == sdhc_gap_read) { 1083 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; 1084 sdhci_read_block_from_card(s); 1085 } else { 1086 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; 1087 sdhci_write_block_to_card(s); 1088 } 1089 s->stopped_state = sdhc_not_stopped; 1090 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { 1091 if (s->prnsts & SDHC_DOING_READ) { 1092 s->stopped_state = sdhc_gap_read; 1093 } else if (s->prnsts & SDHC_DOING_WRITE) { 1094 s->stopped_state = sdhc_gap_write; 1095 } 1096 } 1097 } 1098 1099 static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) 1100 { 1101 switch (value) { 1102 case SDHC_RESET_ALL: 1103 sdhci_reset(s); 1104 break; 1105 case SDHC_RESET_CMD: 1106 s->prnsts &= ~SDHC_CMD_INHIBIT; 1107 s->norintsts &= ~SDHC_NIS_CMDCMP; 1108 break; 1109 case SDHC_RESET_DATA: 1110 s->data_count = 0; 1111 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | 1112 SDHC_DOING_READ | SDHC_DOING_WRITE | 1113 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); 1114 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); 1115 s->stopped_state = sdhc_not_stopped; 1116 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | 1117 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); 1118 break; 1119 } 1120 } 1121 1122 static void 1123 sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1124 { 1125 SDHCIState *s = (SDHCIState *)opaque; 1126 unsigned shift = 8 * (offset & 0x3); 1127 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); 1128 uint32_t value = val; 1129 value <<= shift; 1130 1131 switch (offset & ~0x3) { 1132 case SDHC_SYSAD: 1133 s->sdmasysad = (s->sdmasysad & mask) | value; 1134 MASKED_WRITE(s->sdmasysad, mask, value); 1135 /* Writing to last byte of sdmasysad might trigger transfer */ 1136 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && 1137 s->blksize && SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) { 1138 if (s->trnmod & SDHC_TRNS_MULTI) { 1139 sdhci_sdma_transfer_multi_blocks(s); 1140 } else { 1141 sdhci_sdma_transfer_single_block(s); 1142 } 1143 } 1144 break; 1145 case SDHC_BLKSIZE: 1146 if (!TRANSFERRING_DATA(s->prnsts)) { 1147 MASKED_WRITE(s->blksize, mask, value); 1148 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); 1149 } 1150 1151 /* Limit block size to the maximum buffer size */ 1152 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) { 1153 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " \ 1154 "the maximum buffer 0x%x", __func__, s->blksize, 1155 s->buf_maxsz); 1156 1157 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz); 1158 } 1159 1160 break; 1161 case SDHC_ARGUMENT: 1162 MASKED_WRITE(s->argument, mask, value); 1163 break; 1164 case SDHC_TRNMOD: 1165 /* DMA can be enabled only if it is supported as indicated by 1166 * capabilities register */ 1167 if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { 1168 value &= ~SDHC_TRNS_DMA; 1169 } 1170 MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK); 1171 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); 1172 1173 /* Writing to the upper byte of CMDREG triggers SD command generation */ 1174 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { 1175 break; 1176 } 1177 1178 sdhci_send_command(s); 1179 break; 1180 case SDHC_BDATA: 1181 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1182 sdhci_write_dataport(s, value >> shift, size); 1183 } 1184 break; 1185 case SDHC_HOSTCTL: 1186 if (!(mask & 0xFF0000)) { 1187 sdhci_blkgap_write(s, value >> 16); 1188 } 1189 MASKED_WRITE(s->hostctl1, mask, value); 1190 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); 1191 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); 1192 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || 1193 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { 1194 s->pwrcon &= ~SDHC_POWER_ON; 1195 } 1196 break; 1197 case SDHC_CLKCON: 1198 if (!(mask & 0xFF000000)) { 1199 sdhci_reset_write(s, value >> 24); 1200 } 1201 MASKED_WRITE(s->clkcon, mask, value); 1202 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); 1203 if (s->clkcon & SDHC_CLOCK_INT_EN) { 1204 s->clkcon |= SDHC_CLOCK_INT_STABLE; 1205 } else { 1206 s->clkcon &= ~SDHC_CLOCK_INT_STABLE; 1207 } 1208 break; 1209 case SDHC_NORINTSTS: 1210 if (s->norintstsen & SDHC_NISEN_CARDINT) { 1211 value &= ~SDHC_NIS_CARDINT; 1212 } 1213 s->norintsts &= mask | ~value; 1214 s->errintsts &= (mask >> 16) | ~(value >> 16); 1215 if (s->errintsts) { 1216 s->norintsts |= SDHC_NIS_ERR; 1217 } else { 1218 s->norintsts &= ~SDHC_NIS_ERR; 1219 } 1220 sdhci_update_irq(s); 1221 break; 1222 case SDHC_NORINTSTSEN: 1223 MASKED_WRITE(s->norintstsen, mask, value); 1224 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); 1225 s->norintsts &= s->norintstsen; 1226 s->errintsts &= s->errintstsen; 1227 if (s->errintsts) { 1228 s->norintsts |= SDHC_NIS_ERR; 1229 } else { 1230 s->norintsts &= ~SDHC_NIS_ERR; 1231 } 1232 /* Quirk for Raspberry Pi: pending card insert interrupt 1233 * appears when first enabled after power on */ 1234 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { 1235 assert(s->pending_insert_quirk); 1236 s->norintsts |= SDHC_NIS_INSERT; 1237 s->pending_insert_state = false; 1238 } 1239 sdhci_update_irq(s); 1240 break; 1241 case SDHC_NORINTSIGEN: 1242 MASKED_WRITE(s->norintsigen, mask, value); 1243 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); 1244 sdhci_update_irq(s); 1245 break; 1246 case SDHC_ADMAERR: 1247 MASKED_WRITE(s->admaerr, mask, value); 1248 break; 1249 case SDHC_ADMASYSADDR: 1250 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | 1251 (uint64_t)mask)) | (uint64_t)value; 1252 break; 1253 case SDHC_ADMASYSADDR + 4: 1254 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | 1255 ((uint64_t)mask << 32))) | ((uint64_t)value << 32); 1256 break; 1257 case SDHC_FEAER: 1258 s->acmd12errsts |= value; 1259 s->errintsts |= (value >> 16) & s->errintstsen; 1260 if (s->acmd12errsts) { 1261 s->errintsts |= SDHC_EIS_CMD12ERR; 1262 } 1263 if (s->errintsts) { 1264 s->norintsts |= SDHC_NIS_ERR; 1265 } 1266 sdhci_update_irq(s); 1267 break; 1268 case SDHC_ACMD12ERRSTS: 1269 MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX); 1270 if (s->uhs_mode >= UHS_I) { 1271 MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16); 1272 1273 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) { 1274 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V); 1275 } else { 1276 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V); 1277 } 1278 } 1279 break; 1280 1281 case SDHC_CAPAB: 1282 case SDHC_CAPAB + 4: 1283 case SDHC_MAXCURR: 1284 case SDHC_MAXCURR + 4: 1285 qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx 1286 " <- 0x%08x read-only\n", size, offset, value >> shift); 1287 break; 1288 1289 default: 1290 qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x " 1291 "not implemented\n", size, offset, value >> shift); 1292 break; 1293 } 1294 trace_sdhci_access("wr", size << 3, offset, "<-", 1295 value >> shift, value >> shift); 1296 } 1297 1298 static const MemoryRegionOps sdhci_mmio_ops = { 1299 .read = sdhci_read, 1300 .write = sdhci_write, 1301 .valid = { 1302 .min_access_size = 1, 1303 .max_access_size = 4, 1304 .unaligned = false 1305 }, 1306 .endianness = DEVICE_LITTLE_ENDIAN, 1307 }; 1308 1309 static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) 1310 { 1311 Error *local_err = NULL; 1312 1313 switch (s->sd_spec_version) { 1314 case 2 ... 3: 1315 break; 1316 default: 1317 error_setg(errp, "Only Spec v2/v3 are supported"); 1318 return; 1319 } 1320 s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1); 1321 1322 sdhci_check_capareg(s, &local_err); 1323 if (local_err) { 1324 error_propagate(errp, local_err); 1325 return; 1326 } 1327 } 1328 1329 /* --- qdev common --- */ 1330 1331 #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \ 1332 DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \ 1333 DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \ 1334 \ 1335 /* Capabilities registers provide information on supported 1336 * features of this specific host controller implementation */ \ 1337 DEFINE_PROP_UINT64("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \ 1338 DEFINE_PROP_UINT64("maxcurr", _state, maxcurr, 0) 1339 1340 static void sdhci_initfn(SDHCIState *s) 1341 { 1342 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), 1343 TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); 1344 1345 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); 1346 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); 1347 1348 s->io_ops = &sdhci_mmio_ops; 1349 } 1350 1351 static void sdhci_uninitfn(SDHCIState *s) 1352 { 1353 timer_del(s->insert_timer); 1354 timer_free(s->insert_timer); 1355 timer_del(s->transfer_timer); 1356 timer_free(s->transfer_timer); 1357 1358 g_free(s->fifo_buffer); 1359 s->fifo_buffer = NULL; 1360 } 1361 1362 static void sdhci_common_realize(SDHCIState *s, Error **errp) 1363 { 1364 Error *local_err = NULL; 1365 1366 sdhci_init_readonly_registers(s, &local_err); 1367 if (local_err) { 1368 error_propagate(errp, local_err); 1369 return; 1370 } 1371 s->buf_maxsz = sdhci_get_fifolen(s); 1372 s->fifo_buffer = g_malloc0(s->buf_maxsz); 1373 1374 memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci", 1375 SDHC_REGISTERS_MAP_SIZE); 1376 } 1377 1378 static void sdhci_common_unrealize(SDHCIState *s, Error **errp) 1379 { 1380 /* This function is expected to be called only once for each class: 1381 * - SysBus: via DeviceClass->unrealize(), 1382 * - PCI: via PCIDeviceClass->exit(). 1383 * However to avoid double-free and/or use-after-free we still nullify 1384 * this variable (better safe than sorry!). */ 1385 g_free(s->fifo_buffer); 1386 s->fifo_buffer = NULL; 1387 } 1388 1389 static bool sdhci_pending_insert_vmstate_needed(void *opaque) 1390 { 1391 SDHCIState *s = opaque; 1392 1393 return s->pending_insert_state; 1394 } 1395 1396 static const VMStateDescription sdhci_pending_insert_vmstate = { 1397 .name = "sdhci/pending-insert", 1398 .version_id = 1, 1399 .minimum_version_id = 1, 1400 .needed = sdhci_pending_insert_vmstate_needed, 1401 .fields = (VMStateField[]) { 1402 VMSTATE_BOOL(pending_insert_state, SDHCIState), 1403 VMSTATE_END_OF_LIST() 1404 }, 1405 }; 1406 1407 const VMStateDescription sdhci_vmstate = { 1408 .name = "sdhci", 1409 .version_id = 1, 1410 .minimum_version_id = 1, 1411 .fields = (VMStateField[]) { 1412 VMSTATE_UINT32(sdmasysad, SDHCIState), 1413 VMSTATE_UINT16(blksize, SDHCIState), 1414 VMSTATE_UINT16(blkcnt, SDHCIState), 1415 VMSTATE_UINT32(argument, SDHCIState), 1416 VMSTATE_UINT16(trnmod, SDHCIState), 1417 VMSTATE_UINT16(cmdreg, SDHCIState), 1418 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), 1419 VMSTATE_UINT32(prnsts, SDHCIState), 1420 VMSTATE_UINT8(hostctl1, SDHCIState), 1421 VMSTATE_UINT8(pwrcon, SDHCIState), 1422 VMSTATE_UINT8(blkgap, SDHCIState), 1423 VMSTATE_UINT8(wakcon, SDHCIState), 1424 VMSTATE_UINT16(clkcon, SDHCIState), 1425 VMSTATE_UINT8(timeoutcon, SDHCIState), 1426 VMSTATE_UINT8(admaerr, SDHCIState), 1427 VMSTATE_UINT16(norintsts, SDHCIState), 1428 VMSTATE_UINT16(errintsts, SDHCIState), 1429 VMSTATE_UINT16(norintstsen, SDHCIState), 1430 VMSTATE_UINT16(errintstsen, SDHCIState), 1431 VMSTATE_UINT16(norintsigen, SDHCIState), 1432 VMSTATE_UINT16(errintsigen, SDHCIState), 1433 VMSTATE_UINT16(acmd12errsts, SDHCIState), 1434 VMSTATE_UINT16(data_count, SDHCIState), 1435 VMSTATE_UINT64(admasysaddr, SDHCIState), 1436 VMSTATE_UINT8(stopped_state, SDHCIState), 1437 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz), 1438 VMSTATE_TIMER_PTR(insert_timer, SDHCIState), 1439 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState), 1440 VMSTATE_END_OF_LIST() 1441 }, 1442 .subsections = (const VMStateDescription*[]) { 1443 &sdhci_pending_insert_vmstate, 1444 NULL 1445 }, 1446 }; 1447 1448 static void sdhci_common_class_init(ObjectClass *klass, void *data) 1449 { 1450 DeviceClass *dc = DEVICE_CLASS(klass); 1451 1452 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1453 dc->vmsd = &sdhci_vmstate; 1454 dc->reset = sdhci_poweron_reset; 1455 } 1456 1457 /* --- qdev PCI --- */ 1458 1459 static Property sdhci_pci_properties[] = { 1460 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), 1461 DEFINE_PROP_END_OF_LIST(), 1462 }; 1463 1464 static void sdhci_pci_realize(PCIDevice *dev, Error **errp) 1465 { 1466 SDHCIState *s = PCI_SDHCI(dev); 1467 Error *local_err = NULL; 1468 1469 sdhci_initfn(s); 1470 sdhci_common_realize(s, &local_err); 1471 if (local_err) { 1472 error_propagate(errp, local_err); 1473 return; 1474 } 1475 1476 dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */ 1477 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ 1478 s->irq = pci_allocate_irq(dev); 1479 s->dma_as = pci_get_address_space(dev); 1480 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->iomem); 1481 } 1482 1483 static void sdhci_pci_exit(PCIDevice *dev) 1484 { 1485 SDHCIState *s = PCI_SDHCI(dev); 1486 1487 sdhci_common_unrealize(s, &error_abort); 1488 sdhci_uninitfn(s); 1489 } 1490 1491 static void sdhci_pci_class_init(ObjectClass *klass, void *data) 1492 { 1493 DeviceClass *dc = DEVICE_CLASS(klass); 1494 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1495 1496 k->realize = sdhci_pci_realize; 1497 k->exit = sdhci_pci_exit; 1498 k->vendor_id = PCI_VENDOR_ID_REDHAT; 1499 k->device_id = PCI_DEVICE_ID_REDHAT_SDHCI; 1500 k->class_id = PCI_CLASS_SYSTEM_SDHCI; 1501 dc->props = sdhci_pci_properties; 1502 1503 sdhci_common_class_init(klass, data); 1504 } 1505 1506 static const TypeInfo sdhci_pci_info = { 1507 .name = TYPE_PCI_SDHCI, 1508 .parent = TYPE_PCI_DEVICE, 1509 .instance_size = sizeof(SDHCIState), 1510 .class_init = sdhci_pci_class_init, 1511 .interfaces = (InterfaceInfo[]) { 1512 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1513 { }, 1514 }, 1515 }; 1516 1517 /* --- qdev SysBus --- */ 1518 1519 static Property sdhci_sysbus_properties[] = { 1520 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), 1521 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, 1522 false), 1523 DEFINE_PROP_LINK("dma", SDHCIState, 1524 dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), 1525 DEFINE_PROP_END_OF_LIST(), 1526 }; 1527 1528 static void sdhci_sysbus_init(Object *obj) 1529 { 1530 SDHCIState *s = SYSBUS_SDHCI(obj); 1531 1532 sdhci_initfn(s); 1533 } 1534 1535 static void sdhci_sysbus_finalize(Object *obj) 1536 { 1537 SDHCIState *s = SYSBUS_SDHCI(obj); 1538 1539 if (s->dma_mr) { 1540 object_unparent(OBJECT(s->dma_mr)); 1541 } 1542 1543 sdhci_uninitfn(s); 1544 } 1545 1546 static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp) 1547 { 1548 SDHCIState *s = SYSBUS_SDHCI(dev); 1549 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1550 Error *local_err = NULL; 1551 1552 sdhci_common_realize(s, &local_err); 1553 if (local_err) { 1554 error_propagate(errp, local_err); 1555 return; 1556 } 1557 1558 if (s->dma_mr) { 1559 s->dma_as = &s->sysbus_dma_as; 1560 address_space_init(s->dma_as, s->dma_mr, "sdhci-dma"); 1561 } else { 1562 /* use system_memory() if property "dma" not set */ 1563 s->dma_as = &address_space_memory; 1564 } 1565 1566 sysbus_init_irq(sbd, &s->irq); 1567 1568 memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci", 1569 SDHC_REGISTERS_MAP_SIZE); 1570 1571 sysbus_init_mmio(sbd, &s->iomem); 1572 } 1573 1574 static void sdhci_sysbus_unrealize(DeviceState *dev, Error **errp) 1575 { 1576 SDHCIState *s = SYSBUS_SDHCI(dev); 1577 1578 sdhci_common_unrealize(s, &error_abort); 1579 1580 if (s->dma_mr) { 1581 address_space_destroy(s->dma_as); 1582 } 1583 } 1584 1585 static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) 1586 { 1587 DeviceClass *dc = DEVICE_CLASS(klass); 1588 1589 dc->props = sdhci_sysbus_properties; 1590 dc->realize = sdhci_sysbus_realize; 1591 dc->unrealize = sdhci_sysbus_unrealize; 1592 1593 sdhci_common_class_init(klass, data); 1594 } 1595 1596 static const TypeInfo sdhci_sysbus_info = { 1597 .name = TYPE_SYSBUS_SDHCI, 1598 .parent = TYPE_SYS_BUS_DEVICE, 1599 .instance_size = sizeof(SDHCIState), 1600 .instance_init = sdhci_sysbus_init, 1601 .instance_finalize = sdhci_sysbus_finalize, 1602 .class_init = sdhci_sysbus_class_init, 1603 }; 1604 1605 /* --- qdev bus master --- */ 1606 1607 static void sdhci_bus_class_init(ObjectClass *klass, void *data) 1608 { 1609 SDBusClass *sbc = SD_BUS_CLASS(klass); 1610 1611 sbc->set_inserted = sdhci_set_inserted; 1612 sbc->set_readonly = sdhci_set_readonly; 1613 } 1614 1615 static const TypeInfo sdhci_bus_info = { 1616 .name = TYPE_SDHCI_BUS, 1617 .parent = TYPE_SD_BUS, 1618 .instance_size = sizeof(SDBus), 1619 .class_init = sdhci_bus_class_init, 1620 }; 1621 1622 static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) 1623 { 1624 SDHCIState *s = SYSBUS_SDHCI(opaque); 1625 uint32_t ret; 1626 uint16_t hostctl1; 1627 1628 switch (offset) { 1629 default: 1630 return sdhci_read(opaque, offset, size); 1631 1632 case SDHC_HOSTCTL: 1633 /* 1634 * For a detailed explanation on the following bit 1635 * manipulation code see comments in a similar part of 1636 * usdhc_write() 1637 */ 1638 hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3); 1639 1640 if (s->hostctl1 & SDHC_CTRL_8BITBUS) { 1641 hostctl1 |= ESDHC_CTRL_8BITBUS; 1642 } 1643 1644 if (s->hostctl1 & SDHC_CTRL_4BITBUS) { 1645 hostctl1 |= ESDHC_CTRL_4BITBUS; 1646 } 1647 1648 ret = hostctl1; 1649 ret |= (uint32_t)s->blkgap << 16; 1650 ret |= (uint32_t)s->wakcon << 24; 1651 1652 break; 1653 1654 case ESDHC_DLL_CTRL: 1655 case ESDHC_TUNE_CTRL_STATUS: 1656 case ESDHC_UNDOCUMENTED_REG27: 1657 case ESDHC_TUNING_CTRL: 1658 case ESDHC_VENDOR_SPEC: 1659 case ESDHC_MIX_CTRL: 1660 case ESDHC_WTMK_LVL: 1661 ret = 0; 1662 break; 1663 } 1664 1665 return ret; 1666 } 1667 1668 static void 1669 usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1670 { 1671 SDHCIState *s = SYSBUS_SDHCI(opaque); 1672 uint8_t hostctl1; 1673 uint32_t value = (uint32_t)val; 1674 1675 switch (offset) { 1676 case ESDHC_DLL_CTRL: 1677 case ESDHC_TUNE_CTRL_STATUS: 1678 case ESDHC_UNDOCUMENTED_REG27: 1679 case ESDHC_TUNING_CTRL: 1680 case ESDHC_WTMK_LVL: 1681 case ESDHC_VENDOR_SPEC: 1682 break; 1683 1684 case SDHC_HOSTCTL: 1685 /* 1686 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL) 1687 * 1688 * 7 6 5 4 3 2 1 0 1689 * |-----------+--------+--------+-----------+----------+---------| 1690 * | Card | Card | Endian | DATA3 | Data | Led | 1691 * | Detect | Detect | Mode | as Card | Transfer | Control | 1692 * | Signal | Test | | Detection | Width | | 1693 * | Selection | Level | | Pin | | | 1694 * |-----------+--------+--------+-----------+----------+---------| 1695 * 1696 * and 0x29 1697 * 1698 * 15 10 9 8 1699 * |----------+------| 1700 * | Reserved | DMA | 1701 * | | Sel. | 1702 * | | | 1703 * |----------+------| 1704 * 1705 * and here's what SDCHI spec expects those offsets to be: 1706 * 1707 * 0x28 (Host Control Register) 1708 * 1709 * 7 6 5 4 3 2 1 0 1710 * |--------+--------+----------+------+--------+----------+---------| 1711 * | Card | Card | Extended | DMA | High | Data | LED | 1712 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control | 1713 * | Signal | Test | Transfer | | Enable | Width | | 1714 * | Sel. | Level | Width | | | | | 1715 * |--------+--------+----------+------+--------+----------+---------| 1716 * 1717 * and 0x29 (Power Control Register) 1718 * 1719 * |----------------------------------| 1720 * | Power Control Register | 1721 * | | 1722 * | Description omitted, | 1723 * | since it has no analog in ESDHCI | 1724 * | | 1725 * |----------------------------------| 1726 * 1727 * Since offsets 0x2A and 0x2B should be compatible between 1728 * both IP specs we only need to reconcile least 16-bit of the 1729 * word we've been given. 1730 */ 1731 1732 /* 1733 * First, save bits 7 6 and 0 since they are identical 1734 */ 1735 hostctl1 = value & (SDHC_CTRL_LED | 1736 SDHC_CTRL_CDTEST_INS | 1737 SDHC_CTRL_CDTEST_EN); 1738 /* 1739 * Second, split "Data Transfer Width" from bits 2 and 1 in to 1740 * bits 5 and 1 1741 */ 1742 if (value & ESDHC_CTRL_8BITBUS) { 1743 hostctl1 |= SDHC_CTRL_8BITBUS; 1744 } 1745 1746 if (value & ESDHC_CTRL_4BITBUS) { 1747 hostctl1 |= ESDHC_CTRL_4BITBUS; 1748 } 1749 1750 /* 1751 * Third, move DMA select from bits 9 and 8 to bits 4 and 3 1752 */ 1753 hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3)); 1754 1755 /* 1756 * Now place the corrected value into low 16-bit of the value 1757 * we are going to give standard SDHCI write function 1758 * 1759 * NOTE: This transformation should be the inverse of what can 1760 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux 1761 * kernel 1762 */ 1763 value &= ~UINT16_MAX; 1764 value |= hostctl1; 1765 value |= (uint16_t)s->pwrcon << 8; 1766 1767 sdhci_write(opaque, offset, value, size); 1768 break; 1769 1770 case ESDHC_MIX_CTRL: 1771 /* 1772 * So, when SD/MMC stack in Linux tries to write to "Transfer 1773 * Mode Register", ESDHC i.MX quirk code will translate it 1774 * into a write to ESDHC_MIX_CTRL, so we do the opposite in 1775 * order to get where we started 1776 * 1777 * Note that Auto CMD23 Enable bit is located in a wrong place 1778 * on i.MX, but since it is not used by QEMU we do not care. 1779 * 1780 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...) 1781 * here becuase it will result in a call to 1782 * sdhci_send_command(s) which we don't want. 1783 * 1784 */ 1785 s->trnmod = value & UINT16_MAX; 1786 break; 1787 case SDHC_TRNMOD: 1788 /* 1789 * Similar to above, but this time a write to "Command 1790 * Register" will be translated into a 4-byte write to 1791 * "Transfer Mode register" where lower 16-bit of value would 1792 * be set to zero. So what we do is fill those bits with 1793 * cached value from s->trnmod and let the SDHCI 1794 * infrastructure handle the rest 1795 */ 1796 sdhci_write(opaque, offset, val | s->trnmod, size); 1797 break; 1798 case SDHC_BLKSIZE: 1799 /* 1800 * ESDHCI does not implement "Host SDMA Buffer Boundary", and 1801 * Linux driver will try to zero this field out which will 1802 * break the rest of SDHCI emulation. 1803 * 1804 * Linux defaults to maximum possible setting (512K boundary) 1805 * and it seems to be the only option that i.MX IP implements, 1806 * so we artificially set it to that value. 1807 */ 1808 val |= 0x7 << 12; 1809 /* FALLTHROUGH */ 1810 default: 1811 sdhci_write(opaque, offset, val, size); 1812 break; 1813 } 1814 } 1815 1816 1817 static const MemoryRegionOps usdhc_mmio_ops = { 1818 .read = usdhc_read, 1819 .write = usdhc_write, 1820 .valid = { 1821 .min_access_size = 1, 1822 .max_access_size = 4, 1823 .unaligned = false 1824 }, 1825 .endianness = DEVICE_LITTLE_ENDIAN, 1826 }; 1827 1828 static void imx_usdhc_init(Object *obj) 1829 { 1830 SDHCIState *s = SYSBUS_SDHCI(obj); 1831 1832 s->io_ops = &usdhc_mmio_ops; 1833 s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; 1834 } 1835 1836 static const TypeInfo imx_usdhc_info = { 1837 .name = TYPE_IMX_USDHC, 1838 .parent = TYPE_SYSBUS_SDHCI, 1839 .instance_init = imx_usdhc_init, 1840 }; 1841 1842 static void sdhci_register_types(void) 1843 { 1844 type_register_static(&sdhci_pci_info); 1845 type_register_static(&sdhci_sysbus_info); 1846 type_register_static(&sdhci_bus_info); 1847 type_register_static(&imx_usdhc_info); 1848 } 1849 1850 type_init(sdhci_register_types) 1851