1 /* 2 * SD Association Host Standard Specification v2.0 controller emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Mitsyanko Igor <i.mitsyanko@samsung.com> 6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 7 * 8 * Based on MMC controller for Samsung S5PC1xx-based board emulation 9 * by Alexey Merkulov and Vladimir Monakhov. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 19 * See the GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 #ifndef SDHCI_INTERNAL_H 25 #define SDHCI_INTERNAL_H 26 27 /* R/W SDMA System Address register 0x0 */ 28 #define SDHC_SYSAD 0x00 29 30 /* R/W Host DMA Buffer Boundary and Transfer Block Size Register 0x0 */ 31 #define SDHC_BLKSIZE 0x04 32 33 /* R/W Blocks count for current transfer 0x0 */ 34 #define SDHC_BLKCNT 0x06 35 36 /* R/W Command Argument Register 0x0 */ 37 #define SDHC_ARGUMENT 0x08 38 39 /* R/W Transfer Mode Setting Register 0x0 */ 40 #define SDHC_TRNMOD 0x0C 41 #define SDHC_TRNS_DMA 0x0001 42 #define SDHC_TRNS_BLK_CNT_EN 0x0002 43 #define SDHC_TRNS_ACMD12 0x0004 44 #define SDHC_TRNS_READ 0x0010 45 #define SDHC_TRNS_MULTI 0x0020 46 #define SDHC_TRNMOD_MASK 0x0037 47 48 /* R/W Command Register 0x0 */ 49 #define SDHC_CMDREG 0x0E 50 #define SDHC_CMD_RSP_WITH_BUSY (3 << 0) 51 #define SDHC_CMD_DATA_PRESENT (1 << 5) 52 #define SDHC_CMD_SUSPEND (1 << 6) 53 #define SDHC_CMD_RESUME (1 << 7) 54 #define SDHC_CMD_ABORT ((1 << 6)|(1 << 7)) 55 #define SDHC_CMD_TYPE_MASK ((1 << 6)|(1 << 7)) 56 #define SDHC_COMMAND_TYPE(x) ((x) & SDHC_CMD_TYPE_MASK) 57 58 /* ROC Response Register 0 0x0 */ 59 #define SDHC_RSPREG0 0x10 60 /* ROC Response Register 1 0x0 */ 61 #define SDHC_RSPREG1 0x14 62 /* ROC Response Register 2 0x0 */ 63 #define SDHC_RSPREG2 0x18 64 /* ROC Response Register 3 0x0 */ 65 #define SDHC_RSPREG3 0x1C 66 67 /* R/W Buffer Data Register 0x0 */ 68 #define SDHC_BDATA 0x20 69 70 /* R/ROC Present State Register 0x000A0000 */ 71 #define SDHC_PRNSTS 0x24 72 #define SDHC_CMD_INHIBIT 0x00000001 73 #define SDHC_DATA_INHIBIT 0x00000002 74 #define SDHC_DAT_LINE_ACTIVE 0x00000004 75 #define SDHC_DOING_WRITE 0x00000100 76 #define SDHC_DOING_READ 0x00000200 77 #define SDHC_SPACE_AVAILABLE 0x00000400 78 #define SDHC_DATA_AVAILABLE 0x00000800 79 #define SDHC_CARD_PRESENT 0x00010000 80 #define SDHC_CARD_DETECT 0x00040000 81 #define SDHC_WRITE_PROTECT 0x00080000 82 #define TRANSFERRING_DATA(x) \ 83 ((x) & (SDHC_DOING_READ | SDHC_DOING_WRITE)) 84 85 /* R/W Host control Register 0x0 */ 86 #define SDHC_HOSTCTL 0x28 87 #define SDHC_CTRL_DMA_CHECK_MASK 0x18 88 #define SDHC_CTRL_SDMA 0x00 89 #define SDHC_CTRL_ADMA1_32 0x08 90 #define SDHC_CTRL_ADMA2_32 0x10 91 #define SDHC_CTRL_ADMA2_64 0x18 92 #define SDHC_DMA_TYPE(x) ((x) & SDHC_CTRL_DMA_CHECK_MASK) 93 94 /* R/W Power Control Register 0x0 */ 95 #define SDHC_PWRCON 0x29 96 #define SDHC_POWER_ON (1 << 0) 97 98 /* R/W Block Gap Control Register 0x0 */ 99 #define SDHC_BLKGAP 0x2A 100 #define SDHC_STOP_AT_GAP_REQ 0x01 101 #define SDHC_CONTINUE_REQ 0x02 102 103 /* R/W WakeUp Control Register 0x0 */ 104 #define SDHC_WAKCON 0x2B 105 #define SDHC_WKUP_ON_INS (1 << 1) 106 #define SDHC_WKUP_ON_RMV (1 << 2) 107 108 /* CLKCON */ 109 #define SDHC_CLKCON 0x2C 110 #define SDHC_CLOCK_INT_STABLE 0x0002 111 #define SDHC_CLOCK_INT_EN 0x0001 112 #define SDHC_CLOCK_SDCLK_EN (1 << 2) 113 #define SDHC_CLOCK_CHK_MASK 0x0007 114 #define SDHC_CLOCK_IS_ON(x) \ 115 (((x) & SDHC_CLOCK_CHK_MASK) == SDHC_CLOCK_CHK_MASK) 116 117 /* R/W Timeout Control Register 0x0 */ 118 #define SDHC_TIMEOUTCON 0x2E 119 120 /* R/W Software Reset Register 0x0 */ 121 #define SDHC_SWRST 0x2F 122 #define SDHC_RESET_ALL 0x01 123 #define SDHC_RESET_CMD 0x02 124 #define SDHC_RESET_DATA 0x04 125 126 /* ROC/RW1C Normal Interrupt Status Register 0x0 */ 127 #define SDHC_NORINTSTS 0x30 128 #define SDHC_NIS_ERR 0x8000 129 #define SDHC_NIS_CMDCMP 0x0001 130 #define SDHC_NIS_TRSCMP 0x0002 131 #define SDHC_NIS_BLKGAP 0x0004 132 #define SDHC_NIS_DMA 0x0008 133 #define SDHC_NIS_WBUFRDY 0x0010 134 #define SDHC_NIS_RBUFRDY 0x0020 135 #define SDHC_NIS_INSERT 0x0040 136 #define SDHC_NIS_REMOVE 0x0080 137 #define SDHC_NIS_CARDINT 0x0100 138 139 /* ROC/RW1C Error Interrupt Status Register 0x0 */ 140 #define SDHC_ERRINTSTS 0x32 141 #define SDHC_EIS_CMDTIMEOUT 0x0001 142 #define SDHC_EIS_BLKGAP 0x0004 143 #define SDHC_EIS_CMDIDX 0x0008 144 #define SDHC_EIS_CMD12ERR 0x0100 145 #define SDHC_EIS_ADMAERR 0x0200 146 147 /* R/W Normal Interrupt Status Enable Register 0x0 */ 148 #define SDHC_NORINTSTSEN 0x34 149 #define SDHC_NISEN_CMDCMP 0x0001 150 #define SDHC_NISEN_TRSCMP 0x0002 151 #define SDHC_NISEN_DMA 0x0008 152 #define SDHC_NISEN_WBUFRDY 0x0010 153 #define SDHC_NISEN_RBUFRDY 0x0020 154 #define SDHC_NISEN_INSERT 0x0040 155 #define SDHC_NISEN_REMOVE 0x0080 156 #define SDHC_NISEN_CARDINT 0x0100 157 158 /* R/W Error Interrupt Status Enable Register 0x0 */ 159 #define SDHC_ERRINTSTSEN 0x36 160 #define SDHC_EISEN_CMDTIMEOUT 0x0001 161 #define SDHC_EISEN_BLKGAP 0x0004 162 #define SDHC_EISEN_CMDIDX 0x0008 163 #define SDHC_EISEN_ADMAERR 0x0200 164 165 /* R/W Normal Interrupt Signal Enable Register 0x0 */ 166 #define SDHC_NORINTSIGEN 0x38 167 #define SDHC_NORINTSIG_INSERT (1 << 6) 168 #define SDHC_NORINTSIG_REMOVE (1 << 7) 169 170 /* R/W Error Interrupt Signal Enable Register 0x0 */ 171 #define SDHC_ERRINTSIGEN 0x3A 172 173 /* ROC Auto CMD12 error status register 0x0 */ 174 #define SDHC_ACMD12ERRSTS 0x3C 175 176 /* HWInit Capabilities Register 0x05E80080 */ 177 #define SDHC_CAPAB 0x40 178 #define SDHC_CAN_DO_DMA 0x00400000 179 #define SDHC_CAN_DO_ADMA2 0x00080000 180 #define SDHC_CAN_DO_ADMA1 0x00100000 181 #define SDHC_64_BIT_BUS_SUPPORT (1 << 28) 182 #define SDHC_CAPAB_BLOCKSIZE(x) (((x) >> 16) & 0x3) 183 184 /* HWInit Maximum Current Capabilities Register 0x0 */ 185 #define SDHC_MAXCURR 0x48 186 187 /* W Force Event Auto CMD12 Error Interrupt Register 0x0000 */ 188 #define SDHC_FEAER 0x50 189 /* W Force Event Error Interrupt Register Error Interrupt 0x0000 */ 190 #define SDHC_FEERR 0x52 191 192 /* R/W ADMA Error Status Register 0x00 */ 193 #define SDHC_ADMAERR 0x54 194 #define SDHC_ADMAERR_LENGTH_MISMATCH (1 << 2) 195 #define SDHC_ADMAERR_STATE_ST_STOP (0 << 0) 196 #define SDHC_ADMAERR_STATE_ST_FDS (1 << 0) 197 #define SDHC_ADMAERR_STATE_ST_TFR (3 << 0) 198 #define SDHC_ADMAERR_STATE_MASK (3 << 0) 199 200 /* R/W ADMA System Address Register 0x00 */ 201 #define SDHC_ADMASYSADDR 0x58 202 #define SDHC_ADMA_ATTR_SET_LEN (1 << 4) 203 #define SDHC_ADMA_ATTR_ACT_TRAN (1 << 5) 204 #define SDHC_ADMA_ATTR_ACT_LINK (3 << 4) 205 #define SDHC_ADMA_ATTR_INT (1 << 2) 206 #define SDHC_ADMA_ATTR_END (1 << 1) 207 #define SDHC_ADMA_ATTR_VALID (1 << 0) 208 #define SDHC_ADMA_ATTR_ACT_MASK ((1 << 4)|(1 << 5)) 209 210 /* Slot interrupt status */ 211 #define SDHC_SLOT_INT_STATUS 0xFC 212 213 /* HWInit Host Controller Version Register 0x0401 */ 214 #define SDHC_HCVER 0xFE 215 #define SD_HOST_SPECv2_VERS 0x2401 216 217 #define SDHC_REGISTERS_MAP_SIZE 0x100 218 #define SDHC_INSERTION_DELAY (NANOSECONDS_PER_SECOND) 219 #define SDHC_TRANSFER_DELAY 100 220 #define SDHC_ADMA_DESCS_PER_DELAY 5 221 #define SDHC_CMD_RESPONSE (3 << 0) 222 223 enum { 224 sdhc_not_stopped = 0, /* normal SDHC state */ 225 sdhc_gap_read = 1, /* SDHC stopped at block gap during read operation */ 226 sdhc_gap_write = 2 /* SDHC stopped at block gap during write operation */ 227 }; 228 229 #endif 230