1 /* 2 * OMAP on-chip MMC/SD host emulation. 3 * 4 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "hw/hw.h" 20 #include "hw/arm/omap.h" 21 #include "hw/sd.h" 22 23 struct omap_mmc_s { 24 qemu_irq irq; 25 qemu_irq *dma; 26 qemu_irq coverswitch; 27 MemoryRegion iomem; 28 omap_clk clk; 29 SDState *card; 30 uint16_t last_cmd; 31 uint16_t sdio; 32 uint16_t rsp[8]; 33 uint32_t arg; 34 int lines; 35 int dw; 36 int mode; 37 int enable; 38 int be; 39 int rev; 40 uint16_t status; 41 uint16_t mask; 42 uint8_t cto; 43 uint16_t dto; 44 int clkdiv; 45 uint16_t fifo[32]; 46 int fifo_start; 47 int fifo_len; 48 uint16_t blen; 49 uint16_t blen_counter; 50 uint16_t nblk; 51 uint16_t nblk_counter; 52 int tx_dma; 53 int rx_dma; 54 int af_level; 55 int ae_level; 56 57 int ddir; 58 int transfer; 59 60 int cdet_wakeup; 61 int cdet_enable; 62 int cdet_state; 63 qemu_irq cdet; 64 }; 65 66 static void omap_mmc_interrupts_update(struct omap_mmc_s *s) 67 { 68 qemu_set_irq(s->irq, !!(s->status & s->mask)); 69 } 70 71 static void omap_mmc_fifolevel_update(struct omap_mmc_s *host) 72 { 73 if (!host->transfer && !host->fifo_len) { 74 host->status &= 0xf3ff; 75 return; 76 } 77 78 if (host->fifo_len > host->af_level && host->ddir) { 79 if (host->rx_dma) { 80 host->status &= 0xfbff; 81 qemu_irq_raise(host->dma[1]); 82 } else 83 host->status |= 0x0400; 84 } else { 85 host->status &= 0xfbff; 86 qemu_irq_lower(host->dma[1]); 87 } 88 89 if (host->fifo_len < host->ae_level && !host->ddir) { 90 if (host->tx_dma) { 91 host->status &= 0xf7ff; 92 qemu_irq_raise(host->dma[0]); 93 } else 94 host->status |= 0x0800; 95 } else { 96 qemu_irq_lower(host->dma[0]); 97 host->status &= 0xf7ff; 98 } 99 } 100 101 typedef enum { 102 sd_nore = 0, /* no response */ 103 sd_r1, /* normal response command */ 104 sd_r2, /* CID, CSD registers */ 105 sd_r3, /* OCR register */ 106 sd_r6 = 6, /* Published RCA response */ 107 sd_r1b = -1, 108 } sd_rsp_type_t; 109 110 static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir, 111 sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init) 112 { 113 uint32_t rspstatus, mask; 114 int rsplen, timeout; 115 SDRequest request; 116 uint8_t response[16]; 117 118 if (init && cmd == 0) { 119 host->status |= 0x0001; 120 return; 121 } 122 123 if (resptype == sd_r1 && busy) 124 resptype = sd_r1b; 125 126 if (type == sd_adtc) { 127 host->fifo_start = 0; 128 host->fifo_len = 0; 129 host->transfer = 1; 130 host->ddir = dir; 131 } else 132 host->transfer = 0; 133 timeout = 0; 134 mask = 0; 135 rspstatus = 0; 136 137 request.cmd = cmd; 138 request.arg = host->arg; 139 request.crc = 0; /* FIXME */ 140 141 rsplen = sd_do_command(host->card, &request, response); 142 143 /* TODO: validate CRCs */ 144 switch (resptype) { 145 case sd_nore: 146 rsplen = 0; 147 break; 148 149 case sd_r1: 150 case sd_r1b: 151 if (rsplen < 4) { 152 timeout = 1; 153 break; 154 } 155 rsplen = 4; 156 157 mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR | 158 ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION | 159 LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND | 160 CARD_ECC_FAILED | CC_ERROR | SD_ERROR | 161 CID_CSD_OVERWRITE; 162 if (host->sdio & (1 << 13)) 163 mask |= AKE_SEQ_ERROR; 164 rspstatus = (response[0] << 24) | (response[1] << 16) | 165 (response[2] << 8) | (response[3] << 0); 166 break; 167 168 case sd_r2: 169 if (rsplen < 16) { 170 timeout = 1; 171 break; 172 } 173 rsplen = 16; 174 break; 175 176 case sd_r3: 177 if (rsplen < 4) { 178 timeout = 1; 179 break; 180 } 181 rsplen = 4; 182 183 rspstatus = (response[0] << 24) | (response[1] << 16) | 184 (response[2] << 8) | (response[3] << 0); 185 if (rspstatus & 0x80000000) 186 host->status &= 0xe000; 187 else 188 host->status |= 0x1000; 189 break; 190 191 case sd_r6: 192 if (rsplen < 4) { 193 timeout = 1; 194 break; 195 } 196 rsplen = 4; 197 198 mask = 0xe000 | AKE_SEQ_ERROR; 199 rspstatus = (response[2] << 8) | (response[3] << 0); 200 } 201 202 if (rspstatus & mask) 203 host->status |= 0x4000; 204 else 205 host->status &= 0xb000; 206 207 if (rsplen) 208 for (rsplen = 0; rsplen < 8; rsplen ++) 209 host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] | 210 (response[(rsplen << 1) | 0] << 8); 211 212 if (timeout) 213 host->status |= 0x0080; 214 else if (cmd == 12) 215 host->status |= 0x0005; /* Makes it more real */ 216 else 217 host->status |= 0x0001; 218 } 219 220 static void omap_mmc_transfer(struct omap_mmc_s *host) 221 { 222 uint8_t value; 223 224 if (!host->transfer) 225 return; 226 227 while (1) { 228 if (host->ddir) { 229 if (host->fifo_len > host->af_level) 230 break; 231 232 value = sd_read_data(host->card); 233 host->fifo[(host->fifo_start + host->fifo_len) & 31] = value; 234 if (-- host->blen_counter) { 235 value = sd_read_data(host->card); 236 host->fifo[(host->fifo_start + host->fifo_len) & 31] |= 237 value << 8; 238 host->blen_counter --; 239 } 240 241 host->fifo_len ++; 242 } else { 243 if (!host->fifo_len) 244 break; 245 246 value = host->fifo[host->fifo_start] & 0xff; 247 sd_write_data(host->card, value); 248 if (-- host->blen_counter) { 249 value = host->fifo[host->fifo_start] >> 8; 250 sd_write_data(host->card, value); 251 host->blen_counter --; 252 } 253 254 host->fifo_start ++; 255 host->fifo_len --; 256 host->fifo_start &= 31; 257 } 258 259 if (host->blen_counter == 0) { 260 host->nblk_counter --; 261 host->blen_counter = host->blen; 262 263 if (host->nblk_counter == 0) { 264 host->nblk_counter = host->nblk; 265 host->transfer = 0; 266 host->status |= 0x0008; 267 break; 268 } 269 } 270 } 271 } 272 273 static void omap_mmc_update(void *opaque) 274 { 275 struct omap_mmc_s *s = opaque; 276 omap_mmc_transfer(s); 277 omap_mmc_fifolevel_update(s); 278 omap_mmc_interrupts_update(s); 279 } 280 281 void omap_mmc_reset(struct omap_mmc_s *host) 282 { 283 host->last_cmd = 0; 284 memset(host->rsp, 0, sizeof(host->rsp)); 285 host->arg = 0; 286 host->dw = 0; 287 host->mode = 0; 288 host->enable = 0; 289 host->status = 0; 290 host->mask = 0; 291 host->cto = 0; 292 host->dto = 0; 293 host->fifo_len = 0; 294 host->blen = 0; 295 host->blen_counter = 0; 296 host->nblk = 0; 297 host->nblk_counter = 0; 298 host->tx_dma = 0; 299 host->rx_dma = 0; 300 host->ae_level = 0x00; 301 host->af_level = 0x1f; 302 host->transfer = 0; 303 host->cdet_wakeup = 0; 304 host->cdet_enable = 0; 305 qemu_set_irq(host->coverswitch, host->cdet_state); 306 host->clkdiv = 0; 307 } 308 309 static uint64_t omap_mmc_read(void *opaque, hwaddr offset, 310 unsigned size) 311 { 312 uint16_t i; 313 struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; 314 315 if (size != 2) { 316 return omap_badwidth_read16(opaque, offset); 317 } 318 319 switch (offset) { 320 case 0x00: /* MMC_CMD */ 321 return s->last_cmd; 322 323 case 0x04: /* MMC_ARGL */ 324 return s->arg & 0x0000ffff; 325 326 case 0x08: /* MMC_ARGH */ 327 return s->arg >> 16; 328 329 case 0x0c: /* MMC_CON */ 330 return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) | 331 (s->be << 10) | s->clkdiv; 332 333 case 0x10: /* MMC_STAT */ 334 return s->status; 335 336 case 0x14: /* MMC_IE */ 337 return s->mask; 338 339 case 0x18: /* MMC_CTO */ 340 return s->cto; 341 342 case 0x1c: /* MMC_DTO */ 343 return s->dto; 344 345 case 0x20: /* MMC_DATA */ 346 /* TODO: support 8-bit access */ 347 i = s->fifo[s->fifo_start]; 348 if (s->fifo_len == 0) { 349 printf("MMC: FIFO underrun\n"); 350 return i; 351 } 352 s->fifo_start ++; 353 s->fifo_len --; 354 s->fifo_start &= 31; 355 omap_mmc_transfer(s); 356 omap_mmc_fifolevel_update(s); 357 omap_mmc_interrupts_update(s); 358 return i; 359 360 case 0x24: /* MMC_BLEN */ 361 return s->blen_counter; 362 363 case 0x28: /* MMC_NBLK */ 364 return s->nblk_counter; 365 366 case 0x2c: /* MMC_BUF */ 367 return (s->rx_dma << 15) | (s->af_level << 8) | 368 (s->tx_dma << 7) | s->ae_level; 369 370 case 0x30: /* MMC_SPI */ 371 return 0x0000; 372 case 0x34: /* MMC_SDIO */ 373 return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio; 374 case 0x38: /* MMC_SYST */ 375 return 0x0000; 376 377 case 0x3c: /* MMC_REV */ 378 return s->rev; 379 380 case 0x40: /* MMC_RSP0 */ 381 case 0x44: /* MMC_RSP1 */ 382 case 0x48: /* MMC_RSP2 */ 383 case 0x4c: /* MMC_RSP3 */ 384 case 0x50: /* MMC_RSP4 */ 385 case 0x54: /* MMC_RSP5 */ 386 case 0x58: /* MMC_RSP6 */ 387 case 0x5c: /* MMC_RSP7 */ 388 return s->rsp[(offset - 0x40) >> 2]; 389 390 /* OMAP2-specific */ 391 case 0x60: /* MMC_IOSR */ 392 case 0x64: /* MMC_SYSC */ 393 return 0; 394 case 0x68: /* MMC_SYSS */ 395 return 1; /* RSTD */ 396 } 397 398 OMAP_BAD_REG(offset); 399 return 0; 400 } 401 402 static void omap_mmc_write(void *opaque, hwaddr offset, 403 uint64_t value, unsigned size) 404 { 405 int i; 406 struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; 407 408 if (size != 2) { 409 omap_badwidth_write16(opaque, offset, value); 410 return; 411 } 412 413 switch (offset) { 414 case 0x00: /* MMC_CMD */ 415 if (!s->enable) 416 break; 417 418 s->last_cmd = value; 419 for (i = 0; i < 8; i ++) 420 s->rsp[i] = 0x0000; 421 omap_mmc_command(s, value & 63, (value >> 15) & 1, 422 (sd_cmd_type_t) ((value >> 12) & 3), 423 (value >> 11) & 1, 424 (sd_rsp_type_t) ((value >> 8) & 7), 425 (value >> 7) & 1); 426 omap_mmc_update(s); 427 break; 428 429 case 0x04: /* MMC_ARGL */ 430 s->arg &= 0xffff0000; 431 s->arg |= 0x0000ffff & value; 432 break; 433 434 case 0x08: /* MMC_ARGH */ 435 s->arg &= 0x0000ffff; 436 s->arg |= value << 16; 437 break; 438 439 case 0x0c: /* MMC_CON */ 440 s->dw = (value >> 15) & 1; 441 s->mode = (value >> 12) & 3; 442 s->enable = (value >> 11) & 1; 443 s->be = (value >> 10) & 1; 444 s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff); 445 if (s->mode != 0) 446 printf("SD mode %i unimplemented!\n", s->mode); 447 if (s->be != 0) 448 printf("SD FIFO byte sex unimplemented!\n"); 449 if (s->dw != 0 && s->lines < 4) 450 printf("4-bit SD bus enabled\n"); 451 if (!s->enable) 452 omap_mmc_reset(s); 453 break; 454 455 case 0x10: /* MMC_STAT */ 456 s->status &= ~value; 457 omap_mmc_interrupts_update(s); 458 break; 459 460 case 0x14: /* MMC_IE */ 461 s->mask = value & 0x7fff; 462 omap_mmc_interrupts_update(s); 463 break; 464 465 case 0x18: /* MMC_CTO */ 466 s->cto = value & 0xff; 467 if (s->cto > 0xfd && s->rev <= 1) 468 printf("MMC: CTO of 0xff and 0xfe cannot be used!\n"); 469 break; 470 471 case 0x1c: /* MMC_DTO */ 472 s->dto = value & 0xffff; 473 break; 474 475 case 0x20: /* MMC_DATA */ 476 /* TODO: support 8-bit access */ 477 if (s->fifo_len == 32) 478 break; 479 s->fifo[(s->fifo_start + s->fifo_len) & 31] = value; 480 s->fifo_len ++; 481 omap_mmc_transfer(s); 482 omap_mmc_fifolevel_update(s); 483 omap_mmc_interrupts_update(s); 484 break; 485 486 case 0x24: /* MMC_BLEN */ 487 s->blen = (value & 0x07ff) + 1; 488 s->blen_counter = s->blen; 489 break; 490 491 case 0x28: /* MMC_NBLK */ 492 s->nblk = (value & 0x07ff) + 1; 493 s->nblk_counter = s->nblk; 494 s->blen_counter = s->blen; 495 break; 496 497 case 0x2c: /* MMC_BUF */ 498 s->rx_dma = (value >> 15) & 1; 499 s->af_level = (value >> 8) & 0x1f; 500 s->tx_dma = (value >> 7) & 1; 501 s->ae_level = value & 0x1f; 502 503 if (s->rx_dma) 504 s->status &= 0xfbff; 505 if (s->tx_dma) 506 s->status &= 0xf7ff; 507 omap_mmc_fifolevel_update(s); 508 omap_mmc_interrupts_update(s); 509 break; 510 511 /* SPI, SDIO and TEST modes unimplemented */ 512 case 0x30: /* MMC_SPI (OMAP1 only) */ 513 break; 514 case 0x34: /* MMC_SDIO */ 515 s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020); 516 s->cdet_wakeup = (value >> 9) & 1; 517 s->cdet_enable = (value >> 2) & 1; 518 break; 519 case 0x38: /* MMC_SYST */ 520 break; 521 522 case 0x3c: /* MMC_REV */ 523 case 0x40: /* MMC_RSP0 */ 524 case 0x44: /* MMC_RSP1 */ 525 case 0x48: /* MMC_RSP2 */ 526 case 0x4c: /* MMC_RSP3 */ 527 case 0x50: /* MMC_RSP4 */ 528 case 0x54: /* MMC_RSP5 */ 529 case 0x58: /* MMC_RSP6 */ 530 case 0x5c: /* MMC_RSP7 */ 531 OMAP_RO_REG(offset); 532 break; 533 534 /* OMAP2-specific */ 535 case 0x60: /* MMC_IOSR */ 536 if (value & 0xf) 537 printf("MMC: SDIO bits used!\n"); 538 break; 539 case 0x64: /* MMC_SYSC */ 540 if (value & (1 << 2)) /* SRTS */ 541 omap_mmc_reset(s); 542 break; 543 case 0x68: /* MMC_SYSS */ 544 OMAP_RO_REG(offset); 545 break; 546 547 default: 548 OMAP_BAD_REG(offset); 549 } 550 } 551 552 static const MemoryRegionOps omap_mmc_ops = { 553 .read = omap_mmc_read, 554 .write = omap_mmc_write, 555 .endianness = DEVICE_NATIVE_ENDIAN, 556 }; 557 558 static void omap_mmc_cover_cb(void *opaque, int line, int level) 559 { 560 struct omap_mmc_s *host = (struct omap_mmc_s *) opaque; 561 562 if (!host->cdet_state && level) { 563 host->status |= 0x0002; 564 omap_mmc_interrupts_update(host); 565 if (host->cdet_wakeup) { 566 /* TODO: Assert wake-up */ 567 } 568 } 569 570 if (host->cdet_state != level) { 571 qemu_set_irq(host->coverswitch, level); 572 host->cdet_state = level; 573 } 574 } 575 576 struct omap_mmc_s *omap_mmc_init(hwaddr base, 577 MemoryRegion *sysmem, 578 BlockBackend *blk, 579 qemu_irq irq, qemu_irq dma[], omap_clk clk) 580 { 581 struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1); 582 583 s->irq = irq; 584 s->dma = dma; 585 s->clk = clk; 586 s->lines = 1; /* TODO: needs to be settable per-board */ 587 s->rev = 1; 588 589 omap_mmc_reset(s); 590 591 memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800); 592 memory_region_add_subregion(sysmem, base, &s->iomem); 593 594 /* Instantiate the storage */ 595 s->card = sd_init(blk, false); 596 if (s->card == NULL) { 597 exit(1); 598 } 599 600 return s; 601 } 602 603 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, 604 BlockBackend *blk, qemu_irq irq, qemu_irq dma[], 605 omap_clk fclk, omap_clk iclk) 606 { 607 struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1); 608 609 s->irq = irq; 610 s->dma = dma; 611 s->clk = fclk; 612 s->lines = 4; 613 s->rev = 2; 614 615 omap_mmc_reset(s); 616 617 memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 618 omap_l4_region_size(ta, 0)); 619 omap_l4_attach(ta, 0, &s->iomem); 620 621 /* Instantiate the storage */ 622 s->card = sd_init(blk, false); 623 if (s->card == NULL) { 624 exit(1); 625 } 626 627 s->cdet = qemu_allocate_irq(omap_mmc_cover_cb, s, 0); 628 sd_set_cb(s->card, NULL, s->cdet); 629 630 return s; 631 } 632 633 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover) 634 { 635 if (s->cdet) { 636 sd_set_cb(s->card, ro, s->cdet); 637 s->coverswitch = cover; 638 qemu_set_irq(cover, s->cdet_state); 639 } else 640 sd_set_cb(s->card, ro, cover); 641 } 642 643 void omap_mmc_enable(struct omap_mmc_s *s, int enable) 644 { 645 sd_enable(s->card, enable); 646 } 647