1 /* 2 * OMAP on-chip MMC/SD host emulation. 3 * 4 * Datasheet: TI Multimedia Card (MMC/SD/SDIO) Interface (SPRU765A) 5 * 6 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 or 11 * (at your option) version 3 of the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qemu/log.h" 24 #include "hw/hw.h" 25 #include "hw/irq.h" 26 #include "hw/arm/omap.h" 27 #include "hw/sd/sd.h" 28 29 struct omap_mmc_s { 30 qemu_irq irq; 31 qemu_irq *dma; 32 qemu_irq coverswitch; 33 MemoryRegion iomem; 34 omap_clk clk; 35 SDState *card; 36 uint16_t last_cmd; 37 uint16_t sdio; 38 uint16_t rsp[8]; 39 uint32_t arg; 40 int lines; 41 int dw; 42 int mode; 43 int enable; 44 int be; 45 int rev; 46 uint16_t status; 47 uint16_t mask; 48 uint8_t cto; 49 uint16_t dto; 50 int clkdiv; 51 uint16_t fifo[32]; 52 int fifo_start; 53 int fifo_len; 54 uint16_t blen; 55 uint16_t blen_counter; 56 uint16_t nblk; 57 uint16_t nblk_counter; 58 int tx_dma; 59 int rx_dma; 60 int af_level; 61 int ae_level; 62 63 int ddir; 64 int transfer; 65 66 int cdet_wakeup; 67 int cdet_enable; 68 int cdet_state; 69 qemu_irq cdet; 70 }; 71 72 static void omap_mmc_interrupts_update(struct omap_mmc_s *s) 73 { 74 qemu_set_irq(s->irq, !!(s->status & s->mask)); 75 } 76 77 static void omap_mmc_fifolevel_update(struct omap_mmc_s *host) 78 { 79 if (!host->transfer && !host->fifo_len) { 80 host->status &= 0xf3ff; 81 return; 82 } 83 84 if (host->fifo_len > host->af_level && host->ddir) { 85 if (host->rx_dma) { 86 host->status &= 0xfbff; 87 qemu_irq_raise(host->dma[1]); 88 } else 89 host->status |= 0x0400; 90 } else { 91 host->status &= 0xfbff; 92 qemu_irq_lower(host->dma[1]); 93 } 94 95 if (host->fifo_len < host->ae_level && !host->ddir) { 96 if (host->tx_dma) { 97 host->status &= 0xf7ff; 98 qemu_irq_raise(host->dma[0]); 99 } else 100 host->status |= 0x0800; 101 } else { 102 qemu_irq_lower(host->dma[0]); 103 host->status &= 0xf7ff; 104 } 105 } 106 107 typedef enum { 108 sd_nore = 0, /* no response */ 109 sd_r1, /* normal response command */ 110 sd_r2, /* CID, CSD registers */ 111 sd_r3, /* OCR register */ 112 sd_r6 = 6, /* Published RCA response */ 113 sd_r1b = -1, 114 } sd_rsp_type_t; 115 116 static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir, 117 sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init) 118 { 119 uint32_t rspstatus, mask; 120 int rsplen, timeout; 121 SDRequest request; 122 uint8_t response[16]; 123 124 if (init && cmd == 0) { 125 host->status |= 0x0001; 126 return; 127 } 128 129 if (resptype == sd_r1 && busy) 130 resptype = sd_r1b; 131 132 if (type == sd_adtc) { 133 host->fifo_start = 0; 134 host->fifo_len = 0; 135 host->transfer = 1; 136 host->ddir = dir; 137 } else 138 host->transfer = 0; 139 timeout = 0; 140 mask = 0; 141 rspstatus = 0; 142 143 request.cmd = cmd; 144 request.arg = host->arg; 145 request.crc = 0; /* FIXME */ 146 147 rsplen = sd_do_command(host->card, &request, response); 148 149 /* TODO: validate CRCs */ 150 switch (resptype) { 151 case sd_nore: 152 rsplen = 0; 153 break; 154 155 case sd_r1: 156 case sd_r1b: 157 if (rsplen < 4) { 158 timeout = 1; 159 break; 160 } 161 rsplen = 4; 162 163 mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR | 164 ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION | 165 LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND | 166 CARD_ECC_FAILED | CC_ERROR | SD_ERROR | 167 CID_CSD_OVERWRITE; 168 if (host->sdio & (1 << 13)) 169 mask |= AKE_SEQ_ERROR; 170 rspstatus = ldl_be_p(response); 171 break; 172 173 case sd_r2: 174 if (rsplen < 16) { 175 timeout = 1; 176 break; 177 } 178 rsplen = 16; 179 break; 180 181 case sd_r3: 182 if (rsplen < 4) { 183 timeout = 1; 184 break; 185 } 186 rsplen = 4; 187 188 rspstatus = ldl_be_p(response); 189 if (rspstatus & 0x80000000) 190 host->status &= 0xe000; 191 else 192 host->status |= 0x1000; 193 break; 194 195 case sd_r6: 196 if (rsplen < 4) { 197 timeout = 1; 198 break; 199 } 200 rsplen = 4; 201 202 mask = 0xe000 | AKE_SEQ_ERROR; 203 rspstatus = (response[2] << 8) | (response[3] << 0); 204 } 205 206 if (rspstatus & mask) 207 host->status |= 0x4000; 208 else 209 host->status &= 0xb000; 210 211 if (rsplen) 212 for (rsplen = 0; rsplen < 8; rsplen ++) 213 host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] | 214 (response[(rsplen << 1) | 0] << 8); 215 216 if (timeout) 217 host->status |= 0x0080; 218 else if (cmd == 12) 219 host->status |= 0x0005; /* Makes it more real */ 220 else 221 host->status |= 0x0001; 222 } 223 224 static void omap_mmc_transfer(struct omap_mmc_s *host) 225 { 226 uint8_t value; 227 228 if (!host->transfer) 229 return; 230 231 while (1) { 232 if (host->ddir) { 233 if (host->fifo_len > host->af_level) 234 break; 235 236 value = sd_read_data(host->card); 237 host->fifo[(host->fifo_start + host->fifo_len) & 31] = value; 238 if (-- host->blen_counter) { 239 value = sd_read_data(host->card); 240 host->fifo[(host->fifo_start + host->fifo_len) & 31] |= 241 value << 8; 242 host->blen_counter --; 243 } 244 245 host->fifo_len ++; 246 } else { 247 if (!host->fifo_len) 248 break; 249 250 value = host->fifo[host->fifo_start] & 0xff; 251 sd_write_data(host->card, value); 252 if (-- host->blen_counter) { 253 value = host->fifo[host->fifo_start] >> 8; 254 sd_write_data(host->card, value); 255 host->blen_counter --; 256 } 257 258 host->fifo_start ++; 259 host->fifo_len --; 260 host->fifo_start &= 31; 261 } 262 263 if (host->blen_counter == 0) { 264 host->nblk_counter --; 265 host->blen_counter = host->blen; 266 267 if (host->nblk_counter == 0) { 268 host->nblk_counter = host->nblk; 269 host->transfer = 0; 270 host->status |= 0x0008; 271 break; 272 } 273 } 274 } 275 } 276 277 static void omap_mmc_update(void *opaque) 278 { 279 struct omap_mmc_s *s = opaque; 280 omap_mmc_transfer(s); 281 omap_mmc_fifolevel_update(s); 282 omap_mmc_interrupts_update(s); 283 } 284 285 static void omap_mmc_pseudo_reset(struct omap_mmc_s *host) 286 { 287 host->status = 0; 288 host->fifo_len = 0; 289 } 290 291 void omap_mmc_reset(struct omap_mmc_s *host) 292 { 293 host->last_cmd = 0; 294 memset(host->rsp, 0, sizeof(host->rsp)); 295 host->arg = 0; 296 host->dw = 0; 297 host->mode = 0; 298 host->enable = 0; 299 host->mask = 0; 300 host->cto = 0; 301 host->dto = 0; 302 host->blen = 0; 303 host->blen_counter = 0; 304 host->nblk = 0; 305 host->nblk_counter = 0; 306 host->tx_dma = 0; 307 host->rx_dma = 0; 308 host->ae_level = 0x00; 309 host->af_level = 0x1f; 310 host->transfer = 0; 311 host->cdet_wakeup = 0; 312 host->cdet_enable = 0; 313 qemu_set_irq(host->coverswitch, host->cdet_state); 314 host->clkdiv = 0; 315 316 omap_mmc_pseudo_reset(host); 317 318 /* Since we're still using the legacy SD API the card is not plugged 319 * into any bus, and we must reset it manually. When omap_mmc is 320 * QOMified this must move into the QOM reset function. 321 */ 322 device_reset(DEVICE(host->card)); 323 } 324 325 static uint64_t omap_mmc_read(void *opaque, hwaddr offset, 326 unsigned size) 327 { 328 uint16_t i; 329 struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; 330 331 if (size != 2) { 332 return omap_badwidth_read16(opaque, offset); 333 } 334 335 switch (offset) { 336 case 0x00: /* MMC_CMD */ 337 return s->last_cmd; 338 339 case 0x04: /* MMC_ARGL */ 340 return s->arg & 0x0000ffff; 341 342 case 0x08: /* MMC_ARGH */ 343 return s->arg >> 16; 344 345 case 0x0c: /* MMC_CON */ 346 return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) | 347 (s->be << 10) | s->clkdiv; 348 349 case 0x10: /* MMC_STAT */ 350 return s->status; 351 352 case 0x14: /* MMC_IE */ 353 return s->mask; 354 355 case 0x18: /* MMC_CTO */ 356 return s->cto; 357 358 case 0x1c: /* MMC_DTO */ 359 return s->dto; 360 361 case 0x20: /* MMC_DATA */ 362 /* TODO: support 8-bit access */ 363 i = s->fifo[s->fifo_start]; 364 if (s->fifo_len == 0) { 365 printf("MMC: FIFO underrun\n"); 366 return i; 367 } 368 s->fifo_start ++; 369 s->fifo_len --; 370 s->fifo_start &= 31; 371 omap_mmc_transfer(s); 372 omap_mmc_fifolevel_update(s); 373 omap_mmc_interrupts_update(s); 374 return i; 375 376 case 0x24: /* MMC_BLEN */ 377 return s->blen_counter; 378 379 case 0x28: /* MMC_NBLK */ 380 return s->nblk_counter; 381 382 case 0x2c: /* MMC_BUF */ 383 return (s->rx_dma << 15) | (s->af_level << 8) | 384 (s->tx_dma << 7) | s->ae_level; 385 386 case 0x30: /* MMC_SPI */ 387 return 0x0000; 388 case 0x34: /* MMC_SDIO */ 389 return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio; 390 case 0x38: /* MMC_SYST */ 391 return 0x0000; 392 393 case 0x3c: /* MMC_REV */ 394 return s->rev; 395 396 case 0x40: /* MMC_RSP0 */ 397 case 0x44: /* MMC_RSP1 */ 398 case 0x48: /* MMC_RSP2 */ 399 case 0x4c: /* MMC_RSP3 */ 400 case 0x50: /* MMC_RSP4 */ 401 case 0x54: /* MMC_RSP5 */ 402 case 0x58: /* MMC_RSP6 */ 403 case 0x5c: /* MMC_RSP7 */ 404 return s->rsp[(offset - 0x40) >> 2]; 405 406 /* OMAP2-specific */ 407 case 0x60: /* MMC_IOSR */ 408 case 0x64: /* MMC_SYSC */ 409 return 0; 410 case 0x68: /* MMC_SYSS */ 411 return 1; /* RSTD */ 412 } 413 414 OMAP_BAD_REG(offset); 415 return 0; 416 } 417 418 static void omap_mmc_write(void *opaque, hwaddr offset, 419 uint64_t value, unsigned size) 420 { 421 int i; 422 struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; 423 424 if (size != 2) { 425 omap_badwidth_write16(opaque, offset, value); 426 return; 427 } 428 429 switch (offset) { 430 case 0x00: /* MMC_CMD */ 431 if (!s->enable) 432 break; 433 434 s->last_cmd = value; 435 for (i = 0; i < 8; i ++) 436 s->rsp[i] = 0x0000; 437 omap_mmc_command(s, value & 63, (value >> 15) & 1, 438 (sd_cmd_type_t) ((value >> 12) & 3), 439 (value >> 11) & 1, 440 (sd_rsp_type_t) ((value >> 8) & 7), 441 (value >> 7) & 1); 442 omap_mmc_update(s); 443 break; 444 445 case 0x04: /* MMC_ARGL */ 446 s->arg &= 0xffff0000; 447 s->arg |= 0x0000ffff & value; 448 break; 449 450 case 0x08: /* MMC_ARGH */ 451 s->arg &= 0x0000ffff; 452 s->arg |= value << 16; 453 break; 454 455 case 0x0c: /* MMC_CON */ 456 s->dw = (value >> 15) & 1; 457 s->mode = (value >> 12) & 3; 458 s->enable = (value >> 11) & 1; 459 s->be = (value >> 10) & 1; 460 s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff); 461 if (s->mode != 0) { 462 qemu_log_mask(LOG_UNIMP, 463 "omap_mmc_wr: mode #%i unimplemented\n", s->mode); 464 } 465 if (s->be != 0) { 466 qemu_log_mask(LOG_UNIMP, 467 "omap_mmc_wr: Big Endian not implemented\n"); 468 } 469 if (s->dw != 0 && s->lines < 4) 470 printf("4-bit SD bus enabled\n"); 471 if (!s->enable) 472 omap_mmc_pseudo_reset(s); 473 break; 474 475 case 0x10: /* MMC_STAT */ 476 s->status &= ~value; 477 omap_mmc_interrupts_update(s); 478 break; 479 480 case 0x14: /* MMC_IE */ 481 s->mask = value & 0x7fff; 482 omap_mmc_interrupts_update(s); 483 break; 484 485 case 0x18: /* MMC_CTO */ 486 s->cto = value & 0xff; 487 if (s->cto > 0xfd && s->rev <= 1) 488 printf("MMC: CTO of 0xff and 0xfe cannot be used!\n"); 489 break; 490 491 case 0x1c: /* MMC_DTO */ 492 s->dto = value & 0xffff; 493 break; 494 495 case 0x20: /* MMC_DATA */ 496 /* TODO: support 8-bit access */ 497 if (s->fifo_len == 32) 498 break; 499 s->fifo[(s->fifo_start + s->fifo_len) & 31] = value; 500 s->fifo_len ++; 501 omap_mmc_transfer(s); 502 omap_mmc_fifolevel_update(s); 503 omap_mmc_interrupts_update(s); 504 break; 505 506 case 0x24: /* MMC_BLEN */ 507 s->blen = (value & 0x07ff) + 1; 508 s->blen_counter = s->blen; 509 break; 510 511 case 0x28: /* MMC_NBLK */ 512 s->nblk = (value & 0x07ff) + 1; 513 s->nblk_counter = s->nblk; 514 s->blen_counter = s->blen; 515 break; 516 517 case 0x2c: /* MMC_BUF */ 518 s->rx_dma = (value >> 15) & 1; 519 s->af_level = (value >> 8) & 0x1f; 520 s->tx_dma = (value >> 7) & 1; 521 s->ae_level = value & 0x1f; 522 523 if (s->rx_dma) 524 s->status &= 0xfbff; 525 if (s->tx_dma) 526 s->status &= 0xf7ff; 527 omap_mmc_fifolevel_update(s); 528 omap_mmc_interrupts_update(s); 529 break; 530 531 /* SPI, SDIO and TEST modes unimplemented */ 532 case 0x30: /* MMC_SPI (OMAP1 only) */ 533 break; 534 case 0x34: /* MMC_SDIO */ 535 s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020); 536 s->cdet_wakeup = (value >> 9) & 1; 537 s->cdet_enable = (value >> 2) & 1; 538 break; 539 case 0x38: /* MMC_SYST */ 540 break; 541 542 case 0x3c: /* MMC_REV */ 543 case 0x40: /* MMC_RSP0 */ 544 case 0x44: /* MMC_RSP1 */ 545 case 0x48: /* MMC_RSP2 */ 546 case 0x4c: /* MMC_RSP3 */ 547 case 0x50: /* MMC_RSP4 */ 548 case 0x54: /* MMC_RSP5 */ 549 case 0x58: /* MMC_RSP6 */ 550 case 0x5c: /* MMC_RSP7 */ 551 OMAP_RO_REG(offset); 552 break; 553 554 /* OMAP2-specific */ 555 case 0x60: /* MMC_IOSR */ 556 if (value & 0xf) 557 printf("MMC: SDIO bits used!\n"); 558 break; 559 case 0x64: /* MMC_SYSC */ 560 if (value & (1 << 2)) /* SRTS */ 561 omap_mmc_reset(s); 562 break; 563 case 0x68: /* MMC_SYSS */ 564 OMAP_RO_REG(offset); 565 break; 566 567 default: 568 OMAP_BAD_REG(offset); 569 } 570 } 571 572 static const MemoryRegionOps omap_mmc_ops = { 573 .read = omap_mmc_read, 574 .write = omap_mmc_write, 575 .endianness = DEVICE_NATIVE_ENDIAN, 576 }; 577 578 static void omap_mmc_cover_cb(void *opaque, int line, int level) 579 { 580 struct omap_mmc_s *host = (struct omap_mmc_s *) opaque; 581 582 if (!host->cdet_state && level) { 583 host->status |= 0x0002; 584 omap_mmc_interrupts_update(host); 585 if (host->cdet_wakeup) { 586 /* TODO: Assert wake-up */ 587 } 588 } 589 590 if (host->cdet_state != level) { 591 qemu_set_irq(host->coverswitch, level); 592 host->cdet_state = level; 593 } 594 } 595 596 struct omap_mmc_s *omap_mmc_init(hwaddr base, 597 MemoryRegion *sysmem, 598 BlockBackend *blk, 599 qemu_irq irq, qemu_irq dma[], omap_clk clk) 600 { 601 struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1); 602 603 s->irq = irq; 604 s->dma = dma; 605 s->clk = clk; 606 s->lines = 1; /* TODO: needs to be settable per-board */ 607 s->rev = 1; 608 609 memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800); 610 memory_region_add_subregion(sysmem, base, &s->iomem); 611 612 /* Instantiate the storage */ 613 s->card = sd_init(blk, false); 614 if (s->card == NULL) { 615 exit(1); 616 } 617 618 omap_mmc_reset(s); 619 620 return s; 621 } 622 623 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, 624 BlockBackend *blk, qemu_irq irq, qemu_irq dma[], 625 omap_clk fclk, omap_clk iclk) 626 { 627 struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1); 628 629 s->irq = irq; 630 s->dma = dma; 631 s->clk = fclk; 632 s->lines = 4; 633 s->rev = 2; 634 635 memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 636 omap_l4_region_size(ta, 0)); 637 omap_l4_attach(ta, 0, &s->iomem); 638 639 /* Instantiate the storage */ 640 s->card = sd_init(blk, false); 641 if (s->card == NULL) { 642 exit(1); 643 } 644 645 s->cdet = qemu_allocate_irq(omap_mmc_cover_cb, s, 0); 646 sd_set_cb(s->card, NULL, s->cdet); 647 648 omap_mmc_reset(s); 649 650 return s; 651 } 652 653 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover) 654 { 655 if (s->cdet) { 656 sd_set_cb(s->card, ro, s->cdet); 657 s->coverswitch = cover; 658 qemu_set_irq(cover, s->cdet_state); 659 } else 660 sd_set_cb(s->card, ro, cover); 661 } 662 663 void omap_mmc_enable(struct omap_mmc_s *s, int enable) 664 { 665 sd_enable(s->card, enable); 666 } 667