1 /* 2 * OMAP on-chip MMC/SD host emulation. 3 * 4 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "hw/hw.h" 22 #include "hw/arm/omap.h" 23 #include "hw/sd/sd.h" 24 25 struct omap_mmc_s { 26 qemu_irq irq; 27 qemu_irq *dma; 28 qemu_irq coverswitch; 29 MemoryRegion iomem; 30 omap_clk clk; 31 SDState *card; 32 uint16_t last_cmd; 33 uint16_t sdio; 34 uint16_t rsp[8]; 35 uint32_t arg; 36 int lines; 37 int dw; 38 int mode; 39 int enable; 40 int be; 41 int rev; 42 uint16_t status; 43 uint16_t mask; 44 uint8_t cto; 45 uint16_t dto; 46 int clkdiv; 47 uint16_t fifo[32]; 48 int fifo_start; 49 int fifo_len; 50 uint16_t blen; 51 uint16_t blen_counter; 52 uint16_t nblk; 53 uint16_t nblk_counter; 54 int tx_dma; 55 int rx_dma; 56 int af_level; 57 int ae_level; 58 59 int ddir; 60 int transfer; 61 62 int cdet_wakeup; 63 int cdet_enable; 64 int cdet_state; 65 qemu_irq cdet; 66 }; 67 68 static void omap_mmc_interrupts_update(struct omap_mmc_s *s) 69 { 70 qemu_set_irq(s->irq, !!(s->status & s->mask)); 71 } 72 73 static void omap_mmc_fifolevel_update(struct omap_mmc_s *host) 74 { 75 if (!host->transfer && !host->fifo_len) { 76 host->status &= 0xf3ff; 77 return; 78 } 79 80 if (host->fifo_len > host->af_level && host->ddir) { 81 if (host->rx_dma) { 82 host->status &= 0xfbff; 83 qemu_irq_raise(host->dma[1]); 84 } else 85 host->status |= 0x0400; 86 } else { 87 host->status &= 0xfbff; 88 qemu_irq_lower(host->dma[1]); 89 } 90 91 if (host->fifo_len < host->ae_level && !host->ddir) { 92 if (host->tx_dma) { 93 host->status &= 0xf7ff; 94 qemu_irq_raise(host->dma[0]); 95 } else 96 host->status |= 0x0800; 97 } else { 98 qemu_irq_lower(host->dma[0]); 99 host->status &= 0xf7ff; 100 } 101 } 102 103 typedef enum { 104 sd_nore = 0, /* no response */ 105 sd_r1, /* normal response command */ 106 sd_r2, /* CID, CSD registers */ 107 sd_r3, /* OCR register */ 108 sd_r6 = 6, /* Published RCA response */ 109 sd_r1b = -1, 110 } sd_rsp_type_t; 111 112 static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir, 113 sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init) 114 { 115 uint32_t rspstatus, mask; 116 int rsplen, timeout; 117 SDRequest request; 118 uint8_t response[16]; 119 120 if (init && cmd == 0) { 121 host->status |= 0x0001; 122 return; 123 } 124 125 if (resptype == sd_r1 && busy) 126 resptype = sd_r1b; 127 128 if (type == sd_adtc) { 129 host->fifo_start = 0; 130 host->fifo_len = 0; 131 host->transfer = 1; 132 host->ddir = dir; 133 } else 134 host->transfer = 0; 135 timeout = 0; 136 mask = 0; 137 rspstatus = 0; 138 139 request.cmd = cmd; 140 request.arg = host->arg; 141 request.crc = 0; /* FIXME */ 142 143 rsplen = sd_do_command(host->card, &request, response); 144 145 /* TODO: validate CRCs */ 146 switch (resptype) { 147 case sd_nore: 148 rsplen = 0; 149 break; 150 151 case sd_r1: 152 case sd_r1b: 153 if (rsplen < 4) { 154 timeout = 1; 155 break; 156 } 157 rsplen = 4; 158 159 mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR | 160 ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION | 161 LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND | 162 CARD_ECC_FAILED | CC_ERROR | SD_ERROR | 163 CID_CSD_OVERWRITE; 164 if (host->sdio & (1 << 13)) 165 mask |= AKE_SEQ_ERROR; 166 rspstatus = (response[0] << 24) | (response[1] << 16) | 167 (response[2] << 8) | (response[3] << 0); 168 break; 169 170 case sd_r2: 171 if (rsplen < 16) { 172 timeout = 1; 173 break; 174 } 175 rsplen = 16; 176 break; 177 178 case sd_r3: 179 if (rsplen < 4) { 180 timeout = 1; 181 break; 182 } 183 rsplen = 4; 184 185 rspstatus = (response[0] << 24) | (response[1] << 16) | 186 (response[2] << 8) | (response[3] << 0); 187 if (rspstatus & 0x80000000) 188 host->status &= 0xe000; 189 else 190 host->status |= 0x1000; 191 break; 192 193 case sd_r6: 194 if (rsplen < 4) { 195 timeout = 1; 196 break; 197 } 198 rsplen = 4; 199 200 mask = 0xe000 | AKE_SEQ_ERROR; 201 rspstatus = (response[2] << 8) | (response[3] << 0); 202 } 203 204 if (rspstatus & mask) 205 host->status |= 0x4000; 206 else 207 host->status &= 0xb000; 208 209 if (rsplen) 210 for (rsplen = 0; rsplen < 8; rsplen ++) 211 host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] | 212 (response[(rsplen << 1) | 0] << 8); 213 214 if (timeout) 215 host->status |= 0x0080; 216 else if (cmd == 12) 217 host->status |= 0x0005; /* Makes it more real */ 218 else 219 host->status |= 0x0001; 220 } 221 222 static void omap_mmc_transfer(struct omap_mmc_s *host) 223 { 224 uint8_t value; 225 226 if (!host->transfer) 227 return; 228 229 while (1) { 230 if (host->ddir) { 231 if (host->fifo_len > host->af_level) 232 break; 233 234 value = sd_read_data(host->card); 235 host->fifo[(host->fifo_start + host->fifo_len) & 31] = value; 236 if (-- host->blen_counter) { 237 value = sd_read_data(host->card); 238 host->fifo[(host->fifo_start + host->fifo_len) & 31] |= 239 value << 8; 240 host->blen_counter --; 241 } 242 243 host->fifo_len ++; 244 } else { 245 if (!host->fifo_len) 246 break; 247 248 value = host->fifo[host->fifo_start] & 0xff; 249 sd_write_data(host->card, value); 250 if (-- host->blen_counter) { 251 value = host->fifo[host->fifo_start] >> 8; 252 sd_write_data(host->card, value); 253 host->blen_counter --; 254 } 255 256 host->fifo_start ++; 257 host->fifo_len --; 258 host->fifo_start &= 31; 259 } 260 261 if (host->blen_counter == 0) { 262 host->nblk_counter --; 263 host->blen_counter = host->blen; 264 265 if (host->nblk_counter == 0) { 266 host->nblk_counter = host->nblk; 267 host->transfer = 0; 268 host->status |= 0x0008; 269 break; 270 } 271 } 272 } 273 } 274 275 static void omap_mmc_update(void *opaque) 276 { 277 struct omap_mmc_s *s = opaque; 278 omap_mmc_transfer(s); 279 omap_mmc_fifolevel_update(s); 280 omap_mmc_interrupts_update(s); 281 } 282 283 void omap_mmc_reset(struct omap_mmc_s *host) 284 { 285 host->last_cmd = 0; 286 memset(host->rsp, 0, sizeof(host->rsp)); 287 host->arg = 0; 288 host->dw = 0; 289 host->mode = 0; 290 host->enable = 0; 291 host->status = 0; 292 host->mask = 0; 293 host->cto = 0; 294 host->dto = 0; 295 host->fifo_len = 0; 296 host->blen = 0; 297 host->blen_counter = 0; 298 host->nblk = 0; 299 host->nblk_counter = 0; 300 host->tx_dma = 0; 301 host->rx_dma = 0; 302 host->ae_level = 0x00; 303 host->af_level = 0x1f; 304 host->transfer = 0; 305 host->cdet_wakeup = 0; 306 host->cdet_enable = 0; 307 qemu_set_irq(host->coverswitch, host->cdet_state); 308 host->clkdiv = 0; 309 310 /* Since we're still using the legacy SD API the card is not plugged 311 * into any bus, and we must reset it manually. When omap_mmc is 312 * QOMified this must move into the QOM reset function. 313 */ 314 device_reset(DEVICE(host->card)); 315 } 316 317 static uint64_t omap_mmc_read(void *opaque, hwaddr offset, 318 unsigned size) 319 { 320 uint16_t i; 321 struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; 322 323 if (size != 2) { 324 return omap_badwidth_read16(opaque, offset); 325 } 326 327 switch (offset) { 328 case 0x00: /* MMC_CMD */ 329 return s->last_cmd; 330 331 case 0x04: /* MMC_ARGL */ 332 return s->arg & 0x0000ffff; 333 334 case 0x08: /* MMC_ARGH */ 335 return s->arg >> 16; 336 337 case 0x0c: /* MMC_CON */ 338 return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) | 339 (s->be << 10) | s->clkdiv; 340 341 case 0x10: /* MMC_STAT */ 342 return s->status; 343 344 case 0x14: /* MMC_IE */ 345 return s->mask; 346 347 case 0x18: /* MMC_CTO */ 348 return s->cto; 349 350 case 0x1c: /* MMC_DTO */ 351 return s->dto; 352 353 case 0x20: /* MMC_DATA */ 354 /* TODO: support 8-bit access */ 355 i = s->fifo[s->fifo_start]; 356 if (s->fifo_len == 0) { 357 printf("MMC: FIFO underrun\n"); 358 return i; 359 } 360 s->fifo_start ++; 361 s->fifo_len --; 362 s->fifo_start &= 31; 363 omap_mmc_transfer(s); 364 omap_mmc_fifolevel_update(s); 365 omap_mmc_interrupts_update(s); 366 return i; 367 368 case 0x24: /* MMC_BLEN */ 369 return s->blen_counter; 370 371 case 0x28: /* MMC_NBLK */ 372 return s->nblk_counter; 373 374 case 0x2c: /* MMC_BUF */ 375 return (s->rx_dma << 15) | (s->af_level << 8) | 376 (s->tx_dma << 7) | s->ae_level; 377 378 case 0x30: /* MMC_SPI */ 379 return 0x0000; 380 case 0x34: /* MMC_SDIO */ 381 return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio; 382 case 0x38: /* MMC_SYST */ 383 return 0x0000; 384 385 case 0x3c: /* MMC_REV */ 386 return s->rev; 387 388 case 0x40: /* MMC_RSP0 */ 389 case 0x44: /* MMC_RSP1 */ 390 case 0x48: /* MMC_RSP2 */ 391 case 0x4c: /* MMC_RSP3 */ 392 case 0x50: /* MMC_RSP4 */ 393 case 0x54: /* MMC_RSP5 */ 394 case 0x58: /* MMC_RSP6 */ 395 case 0x5c: /* MMC_RSP7 */ 396 return s->rsp[(offset - 0x40) >> 2]; 397 398 /* OMAP2-specific */ 399 case 0x60: /* MMC_IOSR */ 400 case 0x64: /* MMC_SYSC */ 401 return 0; 402 case 0x68: /* MMC_SYSS */ 403 return 1; /* RSTD */ 404 } 405 406 OMAP_BAD_REG(offset); 407 return 0; 408 } 409 410 static void omap_mmc_write(void *opaque, hwaddr offset, 411 uint64_t value, unsigned size) 412 { 413 int i; 414 struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; 415 416 if (size != 2) { 417 omap_badwidth_write16(opaque, offset, value); 418 return; 419 } 420 421 switch (offset) { 422 case 0x00: /* MMC_CMD */ 423 if (!s->enable) 424 break; 425 426 s->last_cmd = value; 427 for (i = 0; i < 8; i ++) 428 s->rsp[i] = 0x0000; 429 omap_mmc_command(s, value & 63, (value >> 15) & 1, 430 (sd_cmd_type_t) ((value >> 12) & 3), 431 (value >> 11) & 1, 432 (sd_rsp_type_t) ((value >> 8) & 7), 433 (value >> 7) & 1); 434 omap_mmc_update(s); 435 break; 436 437 case 0x04: /* MMC_ARGL */ 438 s->arg &= 0xffff0000; 439 s->arg |= 0x0000ffff & value; 440 break; 441 442 case 0x08: /* MMC_ARGH */ 443 s->arg &= 0x0000ffff; 444 s->arg |= value << 16; 445 break; 446 447 case 0x0c: /* MMC_CON */ 448 s->dw = (value >> 15) & 1; 449 s->mode = (value >> 12) & 3; 450 s->enable = (value >> 11) & 1; 451 s->be = (value >> 10) & 1; 452 s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff); 453 if (s->mode != 0) { 454 qemu_log_mask(LOG_UNIMP, 455 "omap_mmc_wr: mode #%i unimplemented\n", s->mode); 456 } 457 if (s->be != 0) { 458 qemu_log_mask(LOG_UNIMP, 459 "omap_mmc_wr: Big Endian not implemented\n"); 460 } 461 if (s->dw != 0 && s->lines < 4) 462 printf("4-bit SD bus enabled\n"); 463 if (!s->enable) 464 omap_mmc_reset(s); 465 break; 466 467 case 0x10: /* MMC_STAT */ 468 s->status &= ~value; 469 omap_mmc_interrupts_update(s); 470 break; 471 472 case 0x14: /* MMC_IE */ 473 s->mask = value & 0x7fff; 474 omap_mmc_interrupts_update(s); 475 break; 476 477 case 0x18: /* MMC_CTO */ 478 s->cto = value & 0xff; 479 if (s->cto > 0xfd && s->rev <= 1) 480 printf("MMC: CTO of 0xff and 0xfe cannot be used!\n"); 481 break; 482 483 case 0x1c: /* MMC_DTO */ 484 s->dto = value & 0xffff; 485 break; 486 487 case 0x20: /* MMC_DATA */ 488 /* TODO: support 8-bit access */ 489 if (s->fifo_len == 32) 490 break; 491 s->fifo[(s->fifo_start + s->fifo_len) & 31] = value; 492 s->fifo_len ++; 493 omap_mmc_transfer(s); 494 omap_mmc_fifolevel_update(s); 495 omap_mmc_interrupts_update(s); 496 break; 497 498 case 0x24: /* MMC_BLEN */ 499 s->blen = (value & 0x07ff) + 1; 500 s->blen_counter = s->blen; 501 break; 502 503 case 0x28: /* MMC_NBLK */ 504 s->nblk = (value & 0x07ff) + 1; 505 s->nblk_counter = s->nblk; 506 s->blen_counter = s->blen; 507 break; 508 509 case 0x2c: /* MMC_BUF */ 510 s->rx_dma = (value >> 15) & 1; 511 s->af_level = (value >> 8) & 0x1f; 512 s->tx_dma = (value >> 7) & 1; 513 s->ae_level = value & 0x1f; 514 515 if (s->rx_dma) 516 s->status &= 0xfbff; 517 if (s->tx_dma) 518 s->status &= 0xf7ff; 519 omap_mmc_fifolevel_update(s); 520 omap_mmc_interrupts_update(s); 521 break; 522 523 /* SPI, SDIO and TEST modes unimplemented */ 524 case 0x30: /* MMC_SPI (OMAP1 only) */ 525 break; 526 case 0x34: /* MMC_SDIO */ 527 s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020); 528 s->cdet_wakeup = (value >> 9) & 1; 529 s->cdet_enable = (value >> 2) & 1; 530 break; 531 case 0x38: /* MMC_SYST */ 532 break; 533 534 case 0x3c: /* MMC_REV */ 535 case 0x40: /* MMC_RSP0 */ 536 case 0x44: /* MMC_RSP1 */ 537 case 0x48: /* MMC_RSP2 */ 538 case 0x4c: /* MMC_RSP3 */ 539 case 0x50: /* MMC_RSP4 */ 540 case 0x54: /* MMC_RSP5 */ 541 case 0x58: /* MMC_RSP6 */ 542 case 0x5c: /* MMC_RSP7 */ 543 OMAP_RO_REG(offset); 544 break; 545 546 /* OMAP2-specific */ 547 case 0x60: /* MMC_IOSR */ 548 if (value & 0xf) 549 printf("MMC: SDIO bits used!\n"); 550 break; 551 case 0x64: /* MMC_SYSC */ 552 if (value & (1 << 2)) /* SRTS */ 553 omap_mmc_reset(s); 554 break; 555 case 0x68: /* MMC_SYSS */ 556 OMAP_RO_REG(offset); 557 break; 558 559 default: 560 OMAP_BAD_REG(offset); 561 } 562 } 563 564 static const MemoryRegionOps omap_mmc_ops = { 565 .read = omap_mmc_read, 566 .write = omap_mmc_write, 567 .endianness = DEVICE_NATIVE_ENDIAN, 568 }; 569 570 static void omap_mmc_cover_cb(void *opaque, int line, int level) 571 { 572 struct omap_mmc_s *host = (struct omap_mmc_s *) opaque; 573 574 if (!host->cdet_state && level) { 575 host->status |= 0x0002; 576 omap_mmc_interrupts_update(host); 577 if (host->cdet_wakeup) { 578 /* TODO: Assert wake-up */ 579 } 580 } 581 582 if (host->cdet_state != level) { 583 qemu_set_irq(host->coverswitch, level); 584 host->cdet_state = level; 585 } 586 } 587 588 struct omap_mmc_s *omap_mmc_init(hwaddr base, 589 MemoryRegion *sysmem, 590 BlockBackend *blk, 591 qemu_irq irq, qemu_irq dma[], omap_clk clk) 592 { 593 struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1); 594 595 s->irq = irq; 596 s->dma = dma; 597 s->clk = clk; 598 s->lines = 1; /* TODO: needs to be settable per-board */ 599 s->rev = 1; 600 601 memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800); 602 memory_region_add_subregion(sysmem, base, &s->iomem); 603 604 /* Instantiate the storage */ 605 s->card = sd_init(blk, false); 606 if (s->card == NULL) { 607 exit(1); 608 } 609 610 omap_mmc_reset(s); 611 612 return s; 613 } 614 615 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, 616 BlockBackend *blk, qemu_irq irq, qemu_irq dma[], 617 omap_clk fclk, omap_clk iclk) 618 { 619 struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1); 620 621 s->irq = irq; 622 s->dma = dma; 623 s->clk = fclk; 624 s->lines = 4; 625 s->rev = 2; 626 627 memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 628 omap_l4_region_size(ta, 0)); 629 omap_l4_attach(ta, 0, &s->iomem); 630 631 /* Instantiate the storage */ 632 s->card = sd_init(blk, false); 633 if (s->card == NULL) { 634 exit(1); 635 } 636 637 s->cdet = qemu_allocate_irq(omap_mmc_cover_cb, s, 0); 638 sd_set_cb(s->card, NULL, s->cdet); 639 640 omap_mmc_reset(s); 641 642 return s; 643 } 644 645 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover) 646 { 647 if (s->cdet) { 648 sd_set_cb(s->card, ro, s->cdet); 649 s->coverswitch = cover; 650 qemu_set_irq(cover, s->cdet_state); 651 } else 652 sd_set_cb(s->card, ro, cover); 653 } 654 655 void omap_mmc_enable(struct omap_mmc_s *s, int enable) 656 { 657 sd_enable(s->card, enable); 658 } 659