xref: /openbmc/qemu/hw/sd/allwinner-sdhost.c (revision 6c187695)
1 /*
2  * Allwinner (sun4i and above) SD Host Controller emulation
3  *
4  * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
5  *
6  * This program is free software: you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation, either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "qemu/module.h"
23 #include "qemu/units.h"
24 #include "qapi/error.h"
25 #include "sysemu/blockdev.h"
26 #include "sysemu/dma.h"
27 #include "hw/qdev-properties.h"
28 #include "hw/irq.h"
29 #include "hw/sd/allwinner-sdhost.h"
30 #include "migration/vmstate.h"
31 #include "trace.h"
32 #include "qom/object.h"
33 
34 #define TYPE_AW_SDHOST_BUS "allwinner-sdhost-bus"
35 /* This is reusing the SDBus typedef from SD_BUS */
36 DECLARE_INSTANCE_CHECKER(SDBus, AW_SDHOST_BUS,
37                          TYPE_AW_SDHOST_BUS)
38 
39 /* SD Host register offsets */
40 enum {
41     REG_SD_GCTL       = 0x00,  /* Global Control */
42     REG_SD_CKCR       = 0x04,  /* Clock Control */
43     REG_SD_TMOR       = 0x08,  /* Timeout */
44     REG_SD_BWDR       = 0x0C,  /* Bus Width */
45     REG_SD_BKSR       = 0x10,  /* Block Size */
46     REG_SD_BYCR       = 0x14,  /* Byte Count */
47     REG_SD_CMDR       = 0x18,  /* Command */
48     REG_SD_CAGR       = 0x1C,  /* Command Argument */
49     REG_SD_RESP0      = 0x20,  /* Response Zero */
50     REG_SD_RESP1      = 0x24,  /* Response One */
51     REG_SD_RESP2      = 0x28,  /* Response Two */
52     REG_SD_RESP3      = 0x2C,  /* Response Three */
53     REG_SD_IMKR       = 0x30,  /* Interrupt Mask */
54     REG_SD_MISR       = 0x34,  /* Masked Interrupt Status */
55     REG_SD_RISR       = 0x38,  /* Raw Interrupt Status */
56     REG_SD_STAR       = 0x3C,  /* Status */
57     REG_SD_FWLR       = 0x40,  /* FIFO Water Level */
58     REG_SD_FUNS       = 0x44,  /* FIFO Function Select */
59     REG_SD_DBGC       = 0x50,  /* Debug Enable */
60     REG_SD_A12A       = 0x58,  /* Auto command 12 argument */
61     REG_SD_NTSR       = 0x5C,  /* SD NewTiming Set */
62     REG_SD_SDBG       = 0x60,  /* SD newTiming Set Debug */
63     REG_SD_HWRST      = 0x78,  /* Hardware Reset Register */
64     REG_SD_DMAC       = 0x80,  /* Internal DMA Controller Control */
65     REG_SD_DLBA       = 0x84,  /* Descriptor List Base Address */
66     REG_SD_IDST       = 0x88,  /* Internal DMA Controller Status */
67     REG_SD_IDIE       = 0x8C,  /* Internal DMA Controller IRQ Enable */
68     REG_SD_THLDC      = 0x100, /* Card Threshold Control */
69     REG_SD_DSBD       = 0x10C, /* eMMC DDR Start Bit Detection Control */
70     REG_SD_RES_CRC    = 0x110, /* Response CRC from card/eMMC */
71     REG_SD_DATA7_CRC  = 0x114, /* CRC Data 7 from card/eMMC */
72     REG_SD_DATA6_CRC  = 0x118, /* CRC Data 6 from card/eMMC */
73     REG_SD_DATA5_CRC  = 0x11C, /* CRC Data 5 from card/eMMC */
74     REG_SD_DATA4_CRC  = 0x120, /* CRC Data 4 from card/eMMC */
75     REG_SD_DATA3_CRC  = 0x124, /* CRC Data 3 from card/eMMC */
76     REG_SD_DATA2_CRC  = 0x128, /* CRC Data 2 from card/eMMC */
77     REG_SD_DATA1_CRC  = 0x12C, /* CRC Data 1 from card/eMMC */
78     REG_SD_DATA0_CRC  = 0x130, /* CRC Data 0 from card/eMMC */
79     REG_SD_CRC_STA    = 0x134, /* CRC status from card/eMMC during write */
80     REG_SD_FIFO       = 0x200, /* Read/Write FIFO */
81 };
82 
83 /* SD Host register flags */
84 enum {
85     SD_GCTL_FIFO_AC_MOD     = (1 << 31),
86     SD_GCTL_DDR_MOD_SEL     = (1 << 10),
87     SD_GCTL_CD_DBC_ENB      = (1 << 8),
88     SD_GCTL_DMA_ENB         = (1 << 5),
89     SD_GCTL_INT_ENB         = (1 << 4),
90     SD_GCTL_DMA_RST         = (1 << 2),
91     SD_GCTL_FIFO_RST        = (1 << 1),
92     SD_GCTL_SOFT_RST        = (1 << 0),
93 };
94 
95 enum {
96     SD_CMDR_LOAD            = (1 << 31),
97     SD_CMDR_CLKCHANGE       = (1 << 21),
98     SD_CMDR_WRITE           = (1 << 10),
99     SD_CMDR_AUTOSTOP        = (1 << 12),
100     SD_CMDR_DATA            = (1 << 9),
101     SD_CMDR_RESPONSE_LONG   = (1 << 7),
102     SD_CMDR_RESPONSE        = (1 << 6),
103     SD_CMDR_CMDID_MASK      = (0x3f),
104 };
105 
106 enum {
107     SD_RISR_CARD_REMOVE     = (1 << 31),
108     SD_RISR_CARD_INSERT     = (1 << 30),
109     SD_RISR_SDIO_INTR       = (1 << 16),
110     SD_RISR_AUTOCMD_DONE    = (1 << 14),
111     SD_RISR_DATA_COMPLETE   = (1 << 3),
112     SD_RISR_CMD_COMPLETE    = (1 << 2),
113     SD_RISR_NO_RESPONSE     = (1 << 1),
114 };
115 
116 enum {
117     SD_STAR_FIFO_EMPTY      = (1 << 2),
118     SD_STAR_CARD_PRESENT    = (1 << 8),
119     SD_STAR_FIFO_LEVEL_1    = (1 << 17),
120 };
121 
122 enum {
123     SD_IDST_INT_SUMMARY     = (1 << 8),
124     SD_IDST_RECEIVE_IRQ     = (1 << 1),
125     SD_IDST_TRANSMIT_IRQ    = (1 << 0),
126     SD_IDST_IRQ_MASK        = (1 << 1) | (1 << 0) | (1 << 8),
127     SD_IDST_WR_MASK         = (0x3ff),
128 };
129 
130 /* SD Host register reset values */
131 enum {
132     REG_SD_GCTL_RST         = 0x00000300,
133     REG_SD_CKCR_RST         = 0x0,
134     REG_SD_TMOR_RST         = 0xFFFFFF40,
135     REG_SD_BWDR_RST         = 0x0,
136     REG_SD_BKSR_RST         = 0x00000200,
137     REG_SD_BYCR_RST         = 0x00000200,
138     REG_SD_CMDR_RST         = 0x0,
139     REG_SD_CAGR_RST         = 0x0,
140     REG_SD_RESP_RST         = 0x0,
141     REG_SD_IMKR_RST         = 0x0,
142     REG_SD_MISR_RST         = 0x0,
143     REG_SD_RISR_RST         = 0x0,
144     REG_SD_STAR_RST         = 0x00000100,
145     REG_SD_FWLR_RST         = 0x000F0000,
146     REG_SD_FUNS_RST         = 0x0,
147     REG_SD_DBGC_RST         = 0x0,
148     REG_SD_A12A_RST         = 0x0000FFFF,
149     REG_SD_NTSR_RST         = 0x00000001,
150     REG_SD_SDBG_RST         = 0x0,
151     REG_SD_HWRST_RST        = 0x00000001,
152     REG_SD_DMAC_RST         = 0x0,
153     REG_SD_DLBA_RST         = 0x0,
154     REG_SD_IDST_RST         = 0x0,
155     REG_SD_IDIE_RST         = 0x0,
156     REG_SD_THLDC_RST        = 0x0,
157     REG_SD_DSBD_RST         = 0x0,
158     REG_SD_RES_CRC_RST      = 0x0,
159     REG_SD_DATA_CRC_RST     = 0x0,
160     REG_SD_CRC_STA_RST      = 0x0,
161     REG_SD_FIFO_RST         = 0x0,
162 };
163 
164 /* Data transfer descriptor for DMA */
165 typedef struct TransferDescriptor {
166     uint32_t status; /* Status flags */
167     uint32_t size;   /* Data buffer size */
168     uint32_t addr;   /* Data buffer address */
169     uint32_t next;   /* Physical address of next descriptor */
170 } TransferDescriptor;
171 
172 /* Data transfer descriptor flags */
173 enum {
174     DESC_STATUS_HOLD   = (1 << 31), /* Set when descriptor is in use by DMA */
175     DESC_STATUS_ERROR  = (1 << 30), /* Set when DMA transfer error occurred */
176     DESC_STATUS_CHAIN  = (1 << 4),  /* Indicates chained descriptor. */
177     DESC_STATUS_FIRST  = (1 << 3),  /* Set on the first descriptor */
178     DESC_STATUS_LAST   = (1 << 2),  /* Set on the last descriptor */
179     DESC_STATUS_NOIRQ  = (1 << 1),  /* Skip raising interrupt after transfer */
180     DESC_SIZE_MASK     = (0xfffffffc)
181 };
182 
183 static void allwinner_sdhost_update_irq(AwSdHostState *s)
184 {
185     uint32_t irq;
186 
187     if (s->global_ctl & SD_GCTL_INT_ENB) {
188         irq = s->irq_status & s->irq_mask;
189     } else {
190         irq = 0;
191     }
192 
193     trace_allwinner_sdhost_update_irq(irq);
194     qemu_set_irq(s->irq, irq);
195 }
196 
197 static void allwinner_sdhost_update_transfer_cnt(AwSdHostState *s,
198                                                  uint32_t bytes)
199 {
200     if (s->transfer_cnt > bytes) {
201         s->transfer_cnt -= bytes;
202     } else {
203         s->transfer_cnt = 0;
204     }
205 
206     if (!s->transfer_cnt) {
207         s->irq_status |= SD_RISR_DATA_COMPLETE;
208     }
209 }
210 
211 static void allwinner_sdhost_set_inserted(DeviceState *dev, bool inserted)
212 {
213     AwSdHostState *s = AW_SDHOST(dev);
214 
215     trace_allwinner_sdhost_set_inserted(inserted);
216 
217     if (inserted) {
218         s->irq_status |= SD_RISR_CARD_INSERT;
219         s->irq_status &= ~SD_RISR_CARD_REMOVE;
220         s->status |= SD_STAR_CARD_PRESENT;
221     } else {
222         s->irq_status &= ~SD_RISR_CARD_INSERT;
223         s->irq_status |= SD_RISR_CARD_REMOVE;
224         s->status &= ~SD_STAR_CARD_PRESENT;
225     }
226 
227     allwinner_sdhost_update_irq(s);
228 }
229 
230 static void allwinner_sdhost_send_command(AwSdHostState *s)
231 {
232     SDRequest request;
233     uint8_t resp[16];
234     int rlen;
235 
236     /* Auto clear load flag */
237     s->command &= ~SD_CMDR_LOAD;
238 
239     /* Clock change does not actually interact with the SD bus */
240     if (!(s->command & SD_CMDR_CLKCHANGE)) {
241 
242         /* Prepare request */
243         request.cmd = s->command & SD_CMDR_CMDID_MASK;
244         request.arg = s->command_arg;
245 
246         /* Send request to SD bus */
247         rlen = sdbus_do_command(&s->sdbus, &request, resp);
248         if (rlen < 0) {
249             goto error;
250         }
251 
252         /* If the command has a response, store it in the response registers */
253         if ((s->command & SD_CMDR_RESPONSE)) {
254             if (rlen == 4 && !(s->command & SD_CMDR_RESPONSE_LONG)) {
255                 s->response[0] = ldl_be_p(&resp[0]);
256                 s->response[1] = s->response[2] = s->response[3] = 0;
257 
258             } else if (rlen == 16 && (s->command & SD_CMDR_RESPONSE_LONG)) {
259                 s->response[0] = ldl_be_p(&resp[12]);
260                 s->response[1] = ldl_be_p(&resp[8]);
261                 s->response[2] = ldl_be_p(&resp[4]);
262                 s->response[3] = ldl_be_p(&resp[0]);
263             } else {
264                 goto error;
265             }
266         }
267     }
268 
269     /* Set interrupt status bits */
270     s->irq_status |= SD_RISR_CMD_COMPLETE;
271     return;
272 
273 error:
274     s->irq_status |= SD_RISR_NO_RESPONSE;
275 }
276 
277 static void allwinner_sdhost_auto_stop(AwSdHostState *s)
278 {
279     /*
280      * The stop command (CMD12) ensures the SD bus
281      * returns to the transfer state.
282      */
283     if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt == 0)) {
284         /* First save current command registers */
285         uint32_t saved_cmd = s->command;
286         uint32_t saved_arg = s->command_arg;
287 
288         /* Prepare stop command (CMD12) */
289         s->command &= ~SD_CMDR_CMDID_MASK;
290         s->command |= 12; /* CMD12 */
291         s->command_arg = 0;
292 
293         /* Put the command on SD bus */
294         allwinner_sdhost_send_command(s);
295 
296         /* Restore command values */
297         s->command = saved_cmd;
298         s->command_arg = saved_arg;
299 
300         /* Set IRQ status bit for automatic stop done */
301         s->irq_status |= SD_RISR_AUTOCMD_DONE;
302     }
303 }
304 
305 static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s,
306                                               hwaddr desc_addr,
307                                               TransferDescriptor *desc,
308                                               bool is_write, uint32_t max_bytes)
309 {
310     AwSdHostClass *klass = AW_SDHOST_GET_CLASS(s);
311     uint32_t num_done = 0;
312     uint32_t num_bytes = max_bytes;
313     uint8_t buf[1024];
314 
315     /* Read descriptor */
316     dma_memory_read(&s->dma_as, desc_addr, desc, sizeof(*desc),
317                     MEMTXATTRS_UNSPECIFIED);
318     if (desc->size == 0) {
319         desc->size = klass->max_desc_size;
320     } else if (desc->size > klass->max_desc_size) {
321         qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA descriptor buffer size "
322                       " is out-of-bounds: %" PRIu32 " > %zu",
323                       __func__, desc->size, klass->max_desc_size);
324         desc->size = klass->max_desc_size;
325     }
326     if (desc->size < num_bytes) {
327         num_bytes = desc->size;
328     }
329 
330     trace_allwinner_sdhost_process_desc(desc_addr, desc->size,
331                                         is_write, max_bytes);
332 
333     while (num_done < num_bytes) {
334         /* Try to completely fill the local buffer */
335         uint32_t buf_bytes = num_bytes - num_done;
336         if (buf_bytes > sizeof(buf)) {
337             buf_bytes = sizeof(buf);
338         }
339 
340         /* Write to SD bus */
341         if (is_write) {
342             dma_memory_read(&s->dma_as,
343                             (desc->addr & DESC_SIZE_MASK) + num_done, buf,
344                             buf_bytes, MEMTXATTRS_UNSPECIFIED);
345             sdbus_write_data(&s->sdbus, buf, buf_bytes);
346 
347         /* Read from SD bus */
348         } else {
349             sdbus_read_data(&s->sdbus, buf, buf_bytes);
350             dma_memory_write(&s->dma_as,
351                              (desc->addr & DESC_SIZE_MASK) + num_done, buf,
352                              buf_bytes, MEMTXATTRS_UNSPECIFIED);
353         }
354         num_done += buf_bytes;
355     }
356 
357     /* Clear hold flag and flush descriptor */
358     desc->status &= ~DESC_STATUS_HOLD;
359     dma_memory_write(&s->dma_as, desc_addr, desc, sizeof(*desc),
360                      MEMTXATTRS_UNSPECIFIED);
361 
362     return num_done;
363 }
364 
365 static void allwinner_sdhost_dma(AwSdHostState *s)
366 {
367     TransferDescriptor desc;
368     hwaddr desc_addr = s->desc_base;
369     bool is_write = (s->command & SD_CMDR_WRITE);
370     uint32_t bytes_done = 0;
371 
372     /* Check if DMA can be performed */
373     if (s->byte_count == 0 || s->block_size == 0 ||
374       !(s->global_ctl & SD_GCTL_DMA_ENB)) {
375         return;
376     }
377 
378     /*
379      * For read operations, data must be available on the SD bus
380      * If not, it is an error and we should not act at all
381      */
382     if (!is_write && !sdbus_data_ready(&s->sdbus)) {
383         return;
384     }
385 
386     /* Process the DMA descriptors until all data is copied */
387     while (s->byte_count > 0) {
388         bytes_done = allwinner_sdhost_process_desc(s, desc_addr, &desc,
389                                                    is_write, s->byte_count);
390         allwinner_sdhost_update_transfer_cnt(s, bytes_done);
391 
392         if (bytes_done <= s->byte_count) {
393             s->byte_count -= bytes_done;
394         } else {
395             s->byte_count = 0;
396         }
397 
398         if (desc.status & DESC_STATUS_LAST) {
399             break;
400         } else {
401             desc_addr = desc.next;
402         }
403     }
404 
405     /* Raise IRQ to signal DMA is completed */
406     s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_SDIO_INTR;
407 
408     /* Update DMAC bits */
409     s->dmac_status |= SD_IDST_INT_SUMMARY;
410 
411     if (is_write) {
412         s->dmac_status |= SD_IDST_TRANSMIT_IRQ;
413     } else {
414         s->dmac_status |= SD_IDST_RECEIVE_IRQ;
415     }
416 }
417 
418 static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
419                                       unsigned size)
420 {
421     AwSdHostState *s = AW_SDHOST(opaque);
422     uint32_t res = 0;
423 
424     switch (offset) {
425     case REG_SD_GCTL:      /* Global Control */
426         res = s->global_ctl;
427         break;
428     case REG_SD_CKCR:      /* Clock Control */
429         res = s->clock_ctl;
430         break;
431     case REG_SD_TMOR:      /* Timeout */
432         res = s->timeout;
433         break;
434     case REG_SD_BWDR:      /* Bus Width */
435         res = s->bus_width;
436         break;
437     case REG_SD_BKSR:      /* Block Size */
438         res = s->block_size;
439         break;
440     case REG_SD_BYCR:      /* Byte Count */
441         res = s->byte_count;
442         break;
443     case REG_SD_CMDR:      /* Command */
444         res = s->command;
445         break;
446     case REG_SD_CAGR:      /* Command Argument */
447         res = s->command_arg;
448         break;
449     case REG_SD_RESP0:     /* Response Zero */
450         res = s->response[0];
451         break;
452     case REG_SD_RESP1:     /* Response One */
453         res = s->response[1];
454         break;
455     case REG_SD_RESP2:     /* Response Two */
456         res = s->response[2];
457         break;
458     case REG_SD_RESP3:     /* Response Three */
459         res = s->response[3];
460         break;
461     case REG_SD_IMKR:      /* Interrupt Mask */
462         res = s->irq_mask;
463         break;
464     case REG_SD_MISR:      /* Masked Interrupt Status */
465         res = s->irq_status & s->irq_mask;
466         break;
467     case REG_SD_RISR:      /* Raw Interrupt Status */
468         res = s->irq_status;
469         break;
470     case REG_SD_STAR:      /* Status */
471         res = s->status;
472         if (sdbus_data_ready(&s->sdbus)) {
473             res |= SD_STAR_FIFO_LEVEL_1;
474         } else {
475             res |= SD_STAR_FIFO_EMPTY;
476         }
477         break;
478     case REG_SD_FWLR:      /* FIFO Water Level */
479         res = s->fifo_wlevel;
480         break;
481     case REG_SD_FUNS:      /* FIFO Function Select */
482         res = s->fifo_func_sel;
483         break;
484     case REG_SD_DBGC:      /* Debug Enable */
485         res = s->debug_enable;
486         break;
487     case REG_SD_A12A:      /* Auto command 12 argument */
488         res = s->auto12_arg;
489         break;
490     case REG_SD_NTSR:      /* SD NewTiming Set */
491         res = s->newtiming_set;
492         break;
493     case REG_SD_SDBG:      /* SD newTiming Set Debug */
494         res = s->newtiming_debug;
495         break;
496     case REG_SD_HWRST:     /* Hardware Reset Register */
497         res = s->hardware_rst;
498         break;
499     case REG_SD_DMAC:      /* Internal DMA Controller Control */
500         res = s->dmac;
501         break;
502     case REG_SD_DLBA:      /* Descriptor List Base Address */
503         res = s->desc_base;
504         break;
505     case REG_SD_IDST:      /* Internal DMA Controller Status */
506         res = s->dmac_status;
507         break;
508     case REG_SD_IDIE:      /* Internal DMA Controller Interrupt Enable */
509         res = s->dmac_irq;
510         break;
511     case REG_SD_THLDC:     /* Card Threshold Control */
512         res = s->card_threshold;
513         break;
514     case REG_SD_DSBD:      /* eMMC DDR Start Bit Detection Control */
515         res = s->startbit_detect;
516         break;
517     case REG_SD_RES_CRC:   /* Response CRC from card/eMMC */
518         res = s->response_crc;
519         break;
520     case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
521     case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
522     case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
523     case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
524     case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
525     case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
526     case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
527     case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
528         res = s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t))];
529         break;
530     case REG_SD_CRC_STA:   /* CRC status from card/eMMC in write operation */
531         res = s->status_crc;
532         break;
533     case REG_SD_FIFO:      /* Read/Write FIFO */
534         if (sdbus_data_ready(&s->sdbus)) {
535             sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t));
536             le32_to_cpus(&res);
537             allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
538             allwinner_sdhost_auto_stop(s);
539             allwinner_sdhost_update_irq(s);
540         } else {
541             qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
542                           __func__);
543         }
544         break;
545     default:
546         qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
547                       HWADDR_PRIx"\n", __func__, offset);
548         res = 0;
549         break;
550     }
551 
552     trace_allwinner_sdhost_read(offset, res, size);
553     return res;
554 }
555 
556 static void allwinner_sdhost_write(void *opaque, hwaddr offset,
557                                    uint64_t value, unsigned size)
558 {
559     AwSdHostState *s = AW_SDHOST(opaque);
560     uint32_t u32;
561 
562     trace_allwinner_sdhost_write(offset, value, size);
563 
564     switch (offset) {
565     case REG_SD_GCTL:      /* Global Control */
566         s->global_ctl = value;
567         s->global_ctl &= ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST |
568                            SD_GCTL_SOFT_RST);
569         allwinner_sdhost_update_irq(s);
570         break;
571     case REG_SD_CKCR:      /* Clock Control */
572         s->clock_ctl = value;
573         break;
574     case REG_SD_TMOR:      /* Timeout */
575         s->timeout = value;
576         break;
577     case REG_SD_BWDR:      /* Bus Width */
578         s->bus_width = value;
579         break;
580     case REG_SD_BKSR:      /* Block Size */
581         s->block_size = value;
582         break;
583     case REG_SD_BYCR:      /* Byte Count */
584         s->byte_count = value;
585         s->transfer_cnt = value;
586         break;
587     case REG_SD_CMDR:      /* Command */
588         s->command = value;
589         if (value & SD_CMDR_LOAD) {
590             allwinner_sdhost_send_command(s);
591             allwinner_sdhost_dma(s);
592             allwinner_sdhost_auto_stop(s);
593         }
594         allwinner_sdhost_update_irq(s);
595         break;
596     case REG_SD_CAGR:      /* Command Argument */
597         s->command_arg = value;
598         break;
599     case REG_SD_RESP0:     /* Response Zero */
600         s->response[0] = value;
601         break;
602     case REG_SD_RESP1:     /* Response One */
603         s->response[1] = value;
604         break;
605     case REG_SD_RESP2:     /* Response Two */
606         s->response[2] = value;
607         break;
608     case REG_SD_RESP3:     /* Response Three */
609         s->response[3] = value;
610         break;
611     case REG_SD_IMKR:      /* Interrupt Mask */
612         s->irq_mask = value;
613         allwinner_sdhost_update_irq(s);
614         break;
615     case REG_SD_MISR:      /* Masked Interrupt Status */
616     case REG_SD_RISR:      /* Raw Interrupt Status */
617         s->irq_status &= ~value;
618         allwinner_sdhost_update_irq(s);
619         break;
620     case REG_SD_STAR:      /* Status */
621         s->status &= ~value;
622         allwinner_sdhost_update_irq(s);
623         break;
624     case REG_SD_FWLR:      /* FIFO Water Level */
625         s->fifo_wlevel = value;
626         break;
627     case REG_SD_FUNS:      /* FIFO Function Select */
628         s->fifo_func_sel = value;
629         break;
630     case REG_SD_DBGC:      /* Debug Enable */
631         s->debug_enable = value;
632         break;
633     case REG_SD_A12A:      /* Auto command 12 argument */
634         s->auto12_arg = value;
635         break;
636     case REG_SD_NTSR:      /* SD NewTiming Set */
637         s->newtiming_set = value;
638         break;
639     case REG_SD_SDBG:      /* SD newTiming Set Debug */
640         s->newtiming_debug = value;
641         break;
642     case REG_SD_HWRST:     /* Hardware Reset Register */
643         s->hardware_rst = value;
644         break;
645     case REG_SD_DMAC:      /* Internal DMA Controller Control */
646         s->dmac = value;
647         allwinner_sdhost_update_irq(s);
648         break;
649     case REG_SD_DLBA:      /* Descriptor List Base Address */
650         s->desc_base = value;
651         break;
652     case REG_SD_IDST:      /* Internal DMA Controller Status */
653         s->dmac_status &= (~SD_IDST_WR_MASK) | (~value & SD_IDST_WR_MASK);
654         allwinner_sdhost_update_irq(s);
655         break;
656     case REG_SD_IDIE:      /* Internal DMA Controller Interrupt Enable */
657         s->dmac_irq = value;
658         allwinner_sdhost_update_irq(s);
659         break;
660     case REG_SD_THLDC:     /* Card Threshold Control */
661         s->card_threshold = value;
662         break;
663     case REG_SD_DSBD:      /* eMMC DDR Start Bit Detection Control */
664         s->startbit_detect = value;
665         break;
666     case REG_SD_FIFO:      /* Read/Write FIFO */
667         u32 = cpu_to_le32(value);
668         sdbus_write_data(&s->sdbus, &u32, sizeof(u32));
669         allwinner_sdhost_update_transfer_cnt(s, sizeof(u32));
670         allwinner_sdhost_auto_stop(s);
671         allwinner_sdhost_update_irq(s);
672         break;
673     case REG_SD_RES_CRC:   /* Response CRC from card/eMMC */
674     case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
675     case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
676     case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
677     case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
678     case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
679     case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
680     case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
681     case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
682     case REG_SD_CRC_STA:   /* CRC status from card/eMMC in write operation */
683         break;
684     default:
685         qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
686                       HWADDR_PRIx"\n", __func__, offset);
687         break;
688     }
689 }
690 
691 static const MemoryRegionOps allwinner_sdhost_ops = {
692     .read = allwinner_sdhost_read,
693     .write = allwinner_sdhost_write,
694     .endianness = DEVICE_NATIVE_ENDIAN,
695     .valid = {
696         .min_access_size = 4,
697         .max_access_size = 4,
698     },
699     .impl.min_access_size = 4,
700 };
701 
702 static const VMStateDescription vmstate_allwinner_sdhost = {
703     .name = "allwinner-sdhost",
704     .version_id = 1,
705     .minimum_version_id = 1,
706     .fields = (VMStateField[]) {
707         VMSTATE_UINT32(global_ctl, AwSdHostState),
708         VMSTATE_UINT32(clock_ctl, AwSdHostState),
709         VMSTATE_UINT32(timeout, AwSdHostState),
710         VMSTATE_UINT32(bus_width, AwSdHostState),
711         VMSTATE_UINT32(block_size, AwSdHostState),
712         VMSTATE_UINT32(byte_count, AwSdHostState),
713         VMSTATE_UINT32(transfer_cnt, AwSdHostState),
714         VMSTATE_UINT32(command, AwSdHostState),
715         VMSTATE_UINT32(command_arg, AwSdHostState),
716         VMSTATE_UINT32_ARRAY(response, AwSdHostState, 4),
717         VMSTATE_UINT32(irq_mask, AwSdHostState),
718         VMSTATE_UINT32(irq_status, AwSdHostState),
719         VMSTATE_UINT32(status, AwSdHostState),
720         VMSTATE_UINT32(fifo_wlevel, AwSdHostState),
721         VMSTATE_UINT32(fifo_func_sel, AwSdHostState),
722         VMSTATE_UINT32(debug_enable, AwSdHostState),
723         VMSTATE_UINT32(auto12_arg, AwSdHostState),
724         VMSTATE_UINT32(newtiming_set, AwSdHostState),
725         VMSTATE_UINT32(newtiming_debug, AwSdHostState),
726         VMSTATE_UINT32(hardware_rst, AwSdHostState),
727         VMSTATE_UINT32(dmac, AwSdHostState),
728         VMSTATE_UINT32(desc_base, AwSdHostState),
729         VMSTATE_UINT32(dmac_status, AwSdHostState),
730         VMSTATE_UINT32(dmac_irq, AwSdHostState),
731         VMSTATE_UINT32(card_threshold, AwSdHostState),
732         VMSTATE_UINT32(startbit_detect, AwSdHostState),
733         VMSTATE_UINT32(response_crc, AwSdHostState),
734         VMSTATE_UINT32_ARRAY(data_crc, AwSdHostState, 8),
735         VMSTATE_UINT32(status_crc, AwSdHostState),
736         VMSTATE_END_OF_LIST()
737     }
738 };
739 
740 static Property allwinner_sdhost_properties[] = {
741     DEFINE_PROP_LINK("dma-memory", AwSdHostState, dma_mr,
742                      TYPE_MEMORY_REGION, MemoryRegion *),
743     DEFINE_PROP_END_OF_LIST(),
744 };
745 
746 static void allwinner_sdhost_init(Object *obj)
747 {
748     AwSdHostState *s = AW_SDHOST(obj);
749 
750     qbus_init(&s->sdbus, sizeof(s->sdbus),
751               TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus");
752 
753     memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s,
754                            TYPE_AW_SDHOST, 4 * KiB);
755     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
756     sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
757 }
758 
759 static void allwinner_sdhost_realize(DeviceState *dev, Error **errp)
760 {
761     AwSdHostState *s = AW_SDHOST(dev);
762 
763     if (!s->dma_mr) {
764         error_setg(errp, TYPE_AW_SDHOST " 'dma-memory' link not set");
765         return;
766     }
767 
768     address_space_init(&s->dma_as, s->dma_mr, "sdhost-dma");
769 }
770 
771 static void allwinner_sdhost_reset(DeviceState *dev)
772 {
773     AwSdHostState *s = AW_SDHOST(dev);
774 
775     s->global_ctl = REG_SD_GCTL_RST;
776     s->clock_ctl = REG_SD_CKCR_RST;
777     s->timeout = REG_SD_TMOR_RST;
778     s->bus_width = REG_SD_BWDR_RST;
779     s->block_size = REG_SD_BKSR_RST;
780     s->byte_count = REG_SD_BYCR_RST;
781     s->transfer_cnt = 0;
782 
783     s->command = REG_SD_CMDR_RST;
784     s->command_arg = REG_SD_CAGR_RST;
785 
786     for (int i = 0; i < ARRAY_SIZE(s->response); i++) {
787         s->response[i] = REG_SD_RESP_RST;
788     }
789 
790     s->irq_mask = REG_SD_IMKR_RST;
791     s->irq_status = REG_SD_RISR_RST;
792     s->status = REG_SD_STAR_RST;
793 
794     s->fifo_wlevel = REG_SD_FWLR_RST;
795     s->fifo_func_sel = REG_SD_FUNS_RST;
796     s->debug_enable = REG_SD_DBGC_RST;
797     s->auto12_arg = REG_SD_A12A_RST;
798     s->newtiming_set = REG_SD_NTSR_RST;
799     s->newtiming_debug = REG_SD_SDBG_RST;
800     s->hardware_rst = REG_SD_HWRST_RST;
801     s->dmac = REG_SD_DMAC_RST;
802     s->desc_base = REG_SD_DLBA_RST;
803     s->dmac_status = REG_SD_IDST_RST;
804     s->dmac_irq = REG_SD_IDIE_RST;
805     s->card_threshold = REG_SD_THLDC_RST;
806     s->startbit_detect = REG_SD_DSBD_RST;
807     s->response_crc = REG_SD_RES_CRC_RST;
808 
809     for (int i = 0; i < ARRAY_SIZE(s->data_crc); i++) {
810         s->data_crc[i] = REG_SD_DATA_CRC_RST;
811     }
812 
813     s->status_crc = REG_SD_CRC_STA_RST;
814 }
815 
816 static void allwinner_sdhost_bus_class_init(ObjectClass *klass, void *data)
817 {
818     SDBusClass *sbc = SD_BUS_CLASS(klass);
819 
820     sbc->set_inserted = allwinner_sdhost_set_inserted;
821 }
822 
823 static void allwinner_sdhost_class_init(ObjectClass *klass, void *data)
824 {
825     DeviceClass *dc = DEVICE_CLASS(klass);
826 
827     dc->reset = allwinner_sdhost_reset;
828     dc->vmsd = &vmstate_allwinner_sdhost;
829     dc->realize = allwinner_sdhost_realize;
830     device_class_set_props(dc, allwinner_sdhost_properties);
831 }
832 
833 static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
834 {
835     AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
836     sc->max_desc_size = 8 * KiB;
837 }
838 
839 static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
840 {
841     AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
842     sc->max_desc_size = 64 * KiB;
843 }
844 
845 static const TypeInfo allwinner_sdhost_info = {
846     .name          = TYPE_AW_SDHOST,
847     .parent        = TYPE_SYS_BUS_DEVICE,
848     .instance_init = allwinner_sdhost_init,
849     .instance_size = sizeof(AwSdHostState),
850     .class_init    = allwinner_sdhost_class_init,
851     .class_size    = sizeof(AwSdHostClass),
852     .abstract      = true,
853 };
854 
855 static const TypeInfo allwinner_sdhost_sun4i_info = {
856     .name          = TYPE_AW_SDHOST_SUN4I,
857     .parent        = TYPE_AW_SDHOST,
858     .class_init    = allwinner_sdhost_sun4i_class_init,
859 };
860 
861 static const TypeInfo allwinner_sdhost_sun5i_info = {
862     .name          = TYPE_AW_SDHOST_SUN5I,
863     .parent        = TYPE_AW_SDHOST,
864     .class_init    = allwinner_sdhost_sun5i_class_init,
865 };
866 
867 static const TypeInfo allwinner_sdhost_bus_info = {
868     .name = TYPE_AW_SDHOST_BUS,
869     .parent = TYPE_SD_BUS,
870     .instance_size = sizeof(SDBus),
871     .class_init = allwinner_sdhost_bus_class_init,
872 };
873 
874 static void allwinner_sdhost_register_types(void)
875 {
876     type_register_static(&allwinner_sdhost_info);
877     type_register_static(&allwinner_sdhost_sun4i_info);
878     type_register_static(&allwinner_sdhost_sun5i_info);
879     type_register_static(&allwinner_sdhost_bus_info);
880 }
881 
882 type_init(allwinner_sdhost_register_types)
883