1 /* 2 * Allwinner (sun4i and above) SD Host Controller emulation 3 * 4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/module.h" 23 #include "qemu/units.h" 24 #include "qapi/error.h" 25 #include "sysemu/blockdev.h" 26 #include "sysemu/dma.h" 27 #include "hw/qdev-properties.h" 28 #include "hw/irq.h" 29 #include "hw/sd/allwinner-sdhost.h" 30 #include "migration/vmstate.h" 31 #include "trace.h" 32 33 #define TYPE_AW_SDHOST_BUS "allwinner-sdhost-bus" 34 #define AW_SDHOST_BUS(obj) \ 35 OBJECT_CHECK(SDBus, (obj), TYPE_AW_SDHOST_BUS) 36 37 /* SD Host register offsets */ 38 enum { 39 REG_SD_GCTL = 0x00, /* Global Control */ 40 REG_SD_CKCR = 0x04, /* Clock Control */ 41 REG_SD_TMOR = 0x08, /* Timeout */ 42 REG_SD_BWDR = 0x0C, /* Bus Width */ 43 REG_SD_BKSR = 0x10, /* Block Size */ 44 REG_SD_BYCR = 0x14, /* Byte Count */ 45 REG_SD_CMDR = 0x18, /* Command */ 46 REG_SD_CAGR = 0x1C, /* Command Argument */ 47 REG_SD_RESP0 = 0x20, /* Response Zero */ 48 REG_SD_RESP1 = 0x24, /* Response One */ 49 REG_SD_RESP2 = 0x28, /* Response Two */ 50 REG_SD_RESP3 = 0x2C, /* Response Three */ 51 REG_SD_IMKR = 0x30, /* Interrupt Mask */ 52 REG_SD_MISR = 0x34, /* Masked Interrupt Status */ 53 REG_SD_RISR = 0x38, /* Raw Interrupt Status */ 54 REG_SD_STAR = 0x3C, /* Status */ 55 REG_SD_FWLR = 0x40, /* FIFO Water Level */ 56 REG_SD_FUNS = 0x44, /* FIFO Function Select */ 57 REG_SD_DBGC = 0x50, /* Debug Enable */ 58 REG_SD_A12A = 0x58, /* Auto command 12 argument */ 59 REG_SD_NTSR = 0x5C, /* SD NewTiming Set */ 60 REG_SD_SDBG = 0x60, /* SD newTiming Set Debug */ 61 REG_SD_HWRST = 0x78, /* Hardware Reset Register */ 62 REG_SD_DMAC = 0x80, /* Internal DMA Controller Control */ 63 REG_SD_DLBA = 0x84, /* Descriptor List Base Address */ 64 REG_SD_IDST = 0x88, /* Internal DMA Controller Status */ 65 REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */ 66 REG_SD_THLDC = 0x100, /* Card Threshold Control */ 67 REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */ 68 REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */ 69 REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */ 70 REG_SD_DATA6_CRC = 0x118, /* CRC Data 6 from card/eMMC */ 71 REG_SD_DATA5_CRC = 0x11C, /* CRC Data 5 from card/eMMC */ 72 REG_SD_DATA4_CRC = 0x120, /* CRC Data 4 from card/eMMC */ 73 REG_SD_DATA3_CRC = 0x124, /* CRC Data 3 from card/eMMC */ 74 REG_SD_DATA2_CRC = 0x128, /* CRC Data 2 from card/eMMC */ 75 REG_SD_DATA1_CRC = 0x12C, /* CRC Data 1 from card/eMMC */ 76 REG_SD_DATA0_CRC = 0x130, /* CRC Data 0 from card/eMMC */ 77 REG_SD_CRC_STA = 0x134, /* CRC status from card/eMMC during write */ 78 REG_SD_FIFO = 0x200, /* Read/Write FIFO */ 79 }; 80 81 /* SD Host register flags */ 82 enum { 83 SD_GCTL_FIFO_AC_MOD = (1 << 31), 84 SD_GCTL_DDR_MOD_SEL = (1 << 10), 85 SD_GCTL_CD_DBC_ENB = (1 << 8), 86 SD_GCTL_DMA_ENB = (1 << 5), 87 SD_GCTL_INT_ENB = (1 << 4), 88 SD_GCTL_DMA_RST = (1 << 2), 89 SD_GCTL_FIFO_RST = (1 << 1), 90 SD_GCTL_SOFT_RST = (1 << 0), 91 }; 92 93 enum { 94 SD_CMDR_LOAD = (1 << 31), 95 SD_CMDR_CLKCHANGE = (1 << 21), 96 SD_CMDR_WRITE = (1 << 10), 97 SD_CMDR_AUTOSTOP = (1 << 12), 98 SD_CMDR_DATA = (1 << 9), 99 SD_CMDR_RESPONSE_LONG = (1 << 7), 100 SD_CMDR_RESPONSE = (1 << 6), 101 SD_CMDR_CMDID_MASK = (0x3f), 102 }; 103 104 enum { 105 SD_RISR_CARD_REMOVE = (1 << 31), 106 SD_RISR_CARD_INSERT = (1 << 30), 107 SD_RISR_SDIO_INTR = (1 << 16), 108 SD_RISR_AUTOCMD_DONE = (1 << 14), 109 SD_RISR_DATA_COMPLETE = (1 << 3), 110 SD_RISR_CMD_COMPLETE = (1 << 2), 111 SD_RISR_NO_RESPONSE = (1 << 1), 112 }; 113 114 enum { 115 SD_STAR_CARD_PRESENT = (1 << 8), 116 }; 117 118 enum { 119 SD_IDST_INT_SUMMARY = (1 << 8), 120 SD_IDST_RECEIVE_IRQ = (1 << 1), 121 SD_IDST_TRANSMIT_IRQ = (1 << 0), 122 SD_IDST_IRQ_MASK = (1 << 1) | (1 << 0) | (1 << 8), 123 SD_IDST_WR_MASK = (0x3ff), 124 }; 125 126 /* SD Host register reset values */ 127 enum { 128 REG_SD_GCTL_RST = 0x00000300, 129 REG_SD_CKCR_RST = 0x0, 130 REG_SD_TMOR_RST = 0xFFFFFF40, 131 REG_SD_BWDR_RST = 0x0, 132 REG_SD_BKSR_RST = 0x00000200, 133 REG_SD_BYCR_RST = 0x00000200, 134 REG_SD_CMDR_RST = 0x0, 135 REG_SD_CAGR_RST = 0x0, 136 REG_SD_RESP_RST = 0x0, 137 REG_SD_IMKR_RST = 0x0, 138 REG_SD_MISR_RST = 0x0, 139 REG_SD_RISR_RST = 0x0, 140 REG_SD_STAR_RST = 0x00000100, 141 REG_SD_FWLR_RST = 0x000F0000, 142 REG_SD_FUNS_RST = 0x0, 143 REG_SD_DBGC_RST = 0x0, 144 REG_SD_A12A_RST = 0x0000FFFF, 145 REG_SD_NTSR_RST = 0x00000001, 146 REG_SD_SDBG_RST = 0x0, 147 REG_SD_HWRST_RST = 0x00000001, 148 REG_SD_DMAC_RST = 0x0, 149 REG_SD_DLBA_RST = 0x0, 150 REG_SD_IDST_RST = 0x0, 151 REG_SD_IDIE_RST = 0x0, 152 REG_SD_THLDC_RST = 0x0, 153 REG_SD_DSBD_RST = 0x0, 154 REG_SD_RES_CRC_RST = 0x0, 155 REG_SD_DATA_CRC_RST = 0x0, 156 REG_SD_CRC_STA_RST = 0x0, 157 REG_SD_FIFO_RST = 0x0, 158 }; 159 160 /* Data transfer descriptor for DMA */ 161 typedef struct TransferDescriptor { 162 uint32_t status; /* Status flags */ 163 uint32_t size; /* Data buffer size */ 164 uint32_t addr; /* Data buffer address */ 165 uint32_t next; /* Physical address of next descriptor */ 166 } TransferDescriptor; 167 168 /* Data transfer descriptor flags */ 169 enum { 170 DESC_STATUS_HOLD = (1 << 31), /* Set when descriptor is in use by DMA */ 171 DESC_STATUS_ERROR = (1 << 30), /* Set when DMA transfer error occurred */ 172 DESC_STATUS_CHAIN = (1 << 4), /* Indicates chained descriptor. */ 173 DESC_STATUS_FIRST = (1 << 3), /* Set on the first descriptor */ 174 DESC_STATUS_LAST = (1 << 2), /* Set on the last descriptor */ 175 DESC_STATUS_NOIRQ = (1 << 1), /* Skip raising interrupt after transfer */ 176 DESC_SIZE_MASK = (0xfffffffc) 177 }; 178 179 static void allwinner_sdhost_update_irq(AwSdHostState *s) 180 { 181 uint32_t irq; 182 183 if (s->global_ctl & SD_GCTL_INT_ENB) { 184 irq = s->irq_status & s->irq_mask; 185 } else { 186 irq = 0; 187 } 188 189 trace_allwinner_sdhost_update_irq(irq); 190 qemu_set_irq(s->irq, irq); 191 } 192 193 static void allwinner_sdhost_update_transfer_cnt(AwSdHostState *s, 194 uint32_t bytes) 195 { 196 if (s->transfer_cnt > bytes) { 197 s->transfer_cnt -= bytes; 198 } else { 199 s->transfer_cnt = 0; 200 } 201 202 if (!s->transfer_cnt) { 203 s->irq_status |= SD_RISR_DATA_COMPLETE; 204 } 205 } 206 207 static void allwinner_sdhost_set_inserted(DeviceState *dev, bool inserted) 208 { 209 AwSdHostState *s = AW_SDHOST(dev); 210 211 trace_allwinner_sdhost_set_inserted(inserted); 212 213 if (inserted) { 214 s->irq_status |= SD_RISR_CARD_INSERT; 215 s->irq_status &= ~SD_RISR_CARD_REMOVE; 216 s->status |= SD_STAR_CARD_PRESENT; 217 } else { 218 s->irq_status &= ~SD_RISR_CARD_INSERT; 219 s->irq_status |= SD_RISR_CARD_REMOVE; 220 s->status &= ~SD_STAR_CARD_PRESENT; 221 } 222 223 allwinner_sdhost_update_irq(s); 224 } 225 226 static void allwinner_sdhost_send_command(AwSdHostState *s) 227 { 228 SDRequest request; 229 uint8_t resp[16]; 230 int rlen; 231 232 /* Auto clear load flag */ 233 s->command &= ~SD_CMDR_LOAD; 234 235 /* Clock change does not actually interact with the SD bus */ 236 if (!(s->command & SD_CMDR_CLKCHANGE)) { 237 238 /* Prepare request */ 239 request.cmd = s->command & SD_CMDR_CMDID_MASK; 240 request.arg = s->command_arg; 241 242 /* Send request to SD bus */ 243 rlen = sdbus_do_command(&s->sdbus, &request, resp); 244 if (rlen < 0) { 245 goto error; 246 } 247 248 /* If the command has a response, store it in the response registers */ 249 if ((s->command & SD_CMDR_RESPONSE)) { 250 if (rlen == 4 && !(s->command & SD_CMDR_RESPONSE_LONG)) { 251 s->response[0] = ldl_be_p(&resp[0]); 252 s->response[1] = s->response[2] = s->response[3] = 0; 253 254 } else if (rlen == 16 && (s->command & SD_CMDR_RESPONSE_LONG)) { 255 s->response[0] = ldl_be_p(&resp[12]); 256 s->response[1] = ldl_be_p(&resp[8]); 257 s->response[2] = ldl_be_p(&resp[4]); 258 s->response[3] = ldl_be_p(&resp[0]); 259 } else { 260 goto error; 261 } 262 } 263 } 264 265 /* Set interrupt status bits */ 266 s->irq_status |= SD_RISR_CMD_COMPLETE; 267 return; 268 269 error: 270 s->irq_status |= SD_RISR_NO_RESPONSE; 271 } 272 273 static void allwinner_sdhost_auto_stop(AwSdHostState *s) 274 { 275 /* 276 * The stop command (CMD12) ensures the SD bus 277 * returns to the transfer state. 278 */ 279 if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt == 0)) { 280 /* First save current command registers */ 281 uint32_t saved_cmd = s->command; 282 uint32_t saved_arg = s->command_arg; 283 284 /* Prepare stop command (CMD12) */ 285 s->command &= ~SD_CMDR_CMDID_MASK; 286 s->command |= 12; /* CMD12 */ 287 s->command_arg = 0; 288 289 /* Put the command on SD bus */ 290 allwinner_sdhost_send_command(s); 291 292 /* Restore command values */ 293 s->command = saved_cmd; 294 s->command_arg = saved_arg; 295 296 /* Set IRQ status bit for automatic stop done */ 297 s->irq_status |= SD_RISR_AUTOCMD_DONE; 298 } 299 } 300 301 static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s, 302 hwaddr desc_addr, 303 TransferDescriptor *desc, 304 bool is_write, uint32_t max_bytes) 305 { 306 AwSdHostClass *klass = AW_SDHOST_GET_CLASS(s); 307 uint32_t num_done = 0; 308 uint32_t num_bytes = max_bytes; 309 uint8_t buf[1024]; 310 311 /* Read descriptor */ 312 dma_memory_read(&s->dma_as, desc_addr, desc, sizeof(*desc)); 313 if (desc->size == 0) { 314 desc->size = klass->max_desc_size; 315 } else if (desc->size > klass->max_desc_size) { 316 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA descriptor buffer size " 317 " is out-of-bounds: %" PRIu32 " > %zu", 318 __func__, desc->size, klass->max_desc_size); 319 desc->size = klass->max_desc_size; 320 } 321 if (desc->size < num_bytes) { 322 num_bytes = desc->size; 323 } 324 325 trace_allwinner_sdhost_process_desc(desc_addr, desc->size, 326 is_write, max_bytes); 327 328 while (num_done < num_bytes) { 329 /* Try to completely fill the local buffer */ 330 uint32_t buf_bytes = num_bytes - num_done; 331 if (buf_bytes > sizeof(buf)) { 332 buf_bytes = sizeof(buf); 333 } 334 335 /* Write to SD bus */ 336 if (is_write) { 337 dma_memory_read(&s->dma_as, 338 (desc->addr & DESC_SIZE_MASK) + num_done, 339 buf, buf_bytes); 340 sdbus_write_data(&s->sdbus, buf, buf_bytes); 341 342 /* Read from SD bus */ 343 } else { 344 sdbus_read_data(&s->sdbus, buf, buf_bytes); 345 dma_memory_write(&s->dma_as, 346 (desc->addr & DESC_SIZE_MASK) + num_done, 347 buf, buf_bytes); 348 } 349 num_done += buf_bytes; 350 } 351 352 /* Clear hold flag and flush descriptor */ 353 desc->status &= ~DESC_STATUS_HOLD; 354 dma_memory_write(&s->dma_as, desc_addr, desc, sizeof(*desc)); 355 356 return num_done; 357 } 358 359 static void allwinner_sdhost_dma(AwSdHostState *s) 360 { 361 TransferDescriptor desc; 362 hwaddr desc_addr = s->desc_base; 363 bool is_write = (s->command & SD_CMDR_WRITE); 364 uint32_t bytes_done = 0; 365 366 /* Check if DMA can be performed */ 367 if (s->byte_count == 0 || s->block_size == 0 || 368 !(s->global_ctl & SD_GCTL_DMA_ENB)) { 369 return; 370 } 371 372 /* 373 * For read operations, data must be available on the SD bus 374 * If not, it is an error and we should not act at all 375 */ 376 if (!is_write && !sdbus_data_ready(&s->sdbus)) { 377 return; 378 } 379 380 /* Process the DMA descriptors until all data is copied */ 381 while (s->byte_count > 0) { 382 bytes_done = allwinner_sdhost_process_desc(s, desc_addr, &desc, 383 is_write, s->byte_count); 384 allwinner_sdhost_update_transfer_cnt(s, bytes_done); 385 386 if (bytes_done <= s->byte_count) { 387 s->byte_count -= bytes_done; 388 } else { 389 s->byte_count = 0; 390 } 391 392 if (desc.status & DESC_STATUS_LAST) { 393 break; 394 } else { 395 desc_addr = desc.next; 396 } 397 } 398 399 /* Raise IRQ to signal DMA is completed */ 400 s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_SDIO_INTR; 401 402 /* Update DMAC bits */ 403 s->dmac_status |= SD_IDST_INT_SUMMARY; 404 405 if (is_write) { 406 s->dmac_status |= SD_IDST_TRANSMIT_IRQ; 407 } else { 408 s->dmac_status |= SD_IDST_RECEIVE_IRQ; 409 } 410 } 411 412 static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset, 413 unsigned size) 414 { 415 AwSdHostState *s = AW_SDHOST(opaque); 416 uint32_t res = 0; 417 418 switch (offset) { 419 case REG_SD_GCTL: /* Global Control */ 420 res = s->global_ctl; 421 break; 422 case REG_SD_CKCR: /* Clock Control */ 423 res = s->clock_ctl; 424 break; 425 case REG_SD_TMOR: /* Timeout */ 426 res = s->timeout; 427 break; 428 case REG_SD_BWDR: /* Bus Width */ 429 res = s->bus_width; 430 break; 431 case REG_SD_BKSR: /* Block Size */ 432 res = s->block_size; 433 break; 434 case REG_SD_BYCR: /* Byte Count */ 435 res = s->byte_count; 436 break; 437 case REG_SD_CMDR: /* Command */ 438 res = s->command; 439 break; 440 case REG_SD_CAGR: /* Command Argument */ 441 res = s->command_arg; 442 break; 443 case REG_SD_RESP0: /* Response Zero */ 444 res = s->response[0]; 445 break; 446 case REG_SD_RESP1: /* Response One */ 447 res = s->response[1]; 448 break; 449 case REG_SD_RESP2: /* Response Two */ 450 res = s->response[2]; 451 break; 452 case REG_SD_RESP3: /* Response Three */ 453 res = s->response[3]; 454 break; 455 case REG_SD_IMKR: /* Interrupt Mask */ 456 res = s->irq_mask; 457 break; 458 case REG_SD_MISR: /* Masked Interrupt Status */ 459 res = s->irq_status & s->irq_mask; 460 break; 461 case REG_SD_RISR: /* Raw Interrupt Status */ 462 res = s->irq_status; 463 break; 464 case REG_SD_STAR: /* Status */ 465 res = s->status; 466 break; 467 case REG_SD_FWLR: /* FIFO Water Level */ 468 res = s->fifo_wlevel; 469 break; 470 case REG_SD_FUNS: /* FIFO Function Select */ 471 res = s->fifo_func_sel; 472 break; 473 case REG_SD_DBGC: /* Debug Enable */ 474 res = s->debug_enable; 475 break; 476 case REG_SD_A12A: /* Auto command 12 argument */ 477 res = s->auto12_arg; 478 break; 479 case REG_SD_NTSR: /* SD NewTiming Set */ 480 res = s->newtiming_set; 481 break; 482 case REG_SD_SDBG: /* SD newTiming Set Debug */ 483 res = s->newtiming_debug; 484 break; 485 case REG_SD_HWRST: /* Hardware Reset Register */ 486 res = s->hardware_rst; 487 break; 488 case REG_SD_DMAC: /* Internal DMA Controller Control */ 489 res = s->dmac; 490 break; 491 case REG_SD_DLBA: /* Descriptor List Base Address */ 492 res = s->desc_base; 493 break; 494 case REG_SD_IDST: /* Internal DMA Controller Status */ 495 res = s->dmac_status; 496 break; 497 case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */ 498 res = s->dmac_irq; 499 break; 500 case REG_SD_THLDC: /* Card Threshold Control */ 501 res = s->card_threshold; 502 break; 503 case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */ 504 res = s->startbit_detect; 505 break; 506 case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ 507 res = s->response_crc; 508 break; 509 case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ 510 case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ 511 case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ 512 case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ 513 case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ 514 case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ 515 case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ 516 case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ 517 res = s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t))]; 518 break; 519 case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */ 520 res = s->status_crc; 521 break; 522 case REG_SD_FIFO: /* Read/Write FIFO */ 523 if (sdbus_data_ready(&s->sdbus)) { 524 sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t)); 525 le32_to_cpus(&res); 526 allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); 527 allwinner_sdhost_auto_stop(s); 528 allwinner_sdhost_update_irq(s); 529 } else { 530 qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n", 531 __func__); 532 } 533 break; 534 default: 535 qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %" 536 HWADDR_PRIx"\n", __func__, offset); 537 res = 0; 538 break; 539 } 540 541 trace_allwinner_sdhost_read(offset, res, size); 542 return res; 543 } 544 545 static void allwinner_sdhost_write(void *opaque, hwaddr offset, 546 uint64_t value, unsigned size) 547 { 548 AwSdHostState *s = AW_SDHOST(opaque); 549 uint32_t u32; 550 551 trace_allwinner_sdhost_write(offset, value, size); 552 553 switch (offset) { 554 case REG_SD_GCTL: /* Global Control */ 555 s->global_ctl = value; 556 s->global_ctl &= ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST | 557 SD_GCTL_SOFT_RST); 558 allwinner_sdhost_update_irq(s); 559 break; 560 case REG_SD_CKCR: /* Clock Control */ 561 s->clock_ctl = value; 562 break; 563 case REG_SD_TMOR: /* Timeout */ 564 s->timeout = value; 565 break; 566 case REG_SD_BWDR: /* Bus Width */ 567 s->bus_width = value; 568 break; 569 case REG_SD_BKSR: /* Block Size */ 570 s->block_size = value; 571 break; 572 case REG_SD_BYCR: /* Byte Count */ 573 s->byte_count = value; 574 s->transfer_cnt = value; 575 break; 576 case REG_SD_CMDR: /* Command */ 577 s->command = value; 578 if (value & SD_CMDR_LOAD) { 579 allwinner_sdhost_send_command(s); 580 allwinner_sdhost_dma(s); 581 allwinner_sdhost_auto_stop(s); 582 } 583 allwinner_sdhost_update_irq(s); 584 break; 585 case REG_SD_CAGR: /* Command Argument */ 586 s->command_arg = value; 587 break; 588 case REG_SD_RESP0: /* Response Zero */ 589 s->response[0] = value; 590 break; 591 case REG_SD_RESP1: /* Response One */ 592 s->response[1] = value; 593 break; 594 case REG_SD_RESP2: /* Response Two */ 595 s->response[2] = value; 596 break; 597 case REG_SD_RESP3: /* Response Three */ 598 s->response[3] = value; 599 break; 600 case REG_SD_IMKR: /* Interrupt Mask */ 601 s->irq_mask = value; 602 allwinner_sdhost_update_irq(s); 603 break; 604 case REG_SD_MISR: /* Masked Interrupt Status */ 605 case REG_SD_RISR: /* Raw Interrupt Status */ 606 s->irq_status &= ~value; 607 allwinner_sdhost_update_irq(s); 608 break; 609 case REG_SD_STAR: /* Status */ 610 s->status &= ~value; 611 allwinner_sdhost_update_irq(s); 612 break; 613 case REG_SD_FWLR: /* FIFO Water Level */ 614 s->fifo_wlevel = value; 615 break; 616 case REG_SD_FUNS: /* FIFO Function Select */ 617 s->fifo_func_sel = value; 618 break; 619 case REG_SD_DBGC: /* Debug Enable */ 620 s->debug_enable = value; 621 break; 622 case REG_SD_A12A: /* Auto command 12 argument */ 623 s->auto12_arg = value; 624 break; 625 case REG_SD_NTSR: /* SD NewTiming Set */ 626 s->newtiming_set = value; 627 break; 628 case REG_SD_SDBG: /* SD newTiming Set Debug */ 629 s->newtiming_debug = value; 630 break; 631 case REG_SD_HWRST: /* Hardware Reset Register */ 632 s->hardware_rst = value; 633 break; 634 case REG_SD_DMAC: /* Internal DMA Controller Control */ 635 s->dmac = value; 636 allwinner_sdhost_update_irq(s); 637 break; 638 case REG_SD_DLBA: /* Descriptor List Base Address */ 639 s->desc_base = value; 640 break; 641 case REG_SD_IDST: /* Internal DMA Controller Status */ 642 s->dmac_status &= (~SD_IDST_WR_MASK) | (~value & SD_IDST_WR_MASK); 643 allwinner_sdhost_update_irq(s); 644 break; 645 case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */ 646 s->dmac_irq = value; 647 allwinner_sdhost_update_irq(s); 648 break; 649 case REG_SD_THLDC: /* Card Threshold Control */ 650 s->card_threshold = value; 651 break; 652 case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */ 653 s->startbit_detect = value; 654 break; 655 case REG_SD_FIFO: /* Read/Write FIFO */ 656 u32 = cpu_to_le32(value); 657 sdbus_write_data(&s->sdbus, &u32, sizeof(u32)); 658 allwinner_sdhost_update_transfer_cnt(s, sizeof(u32)); 659 allwinner_sdhost_auto_stop(s); 660 allwinner_sdhost_update_irq(s); 661 break; 662 case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ 663 case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ 664 case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ 665 case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ 666 case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ 667 case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ 668 case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ 669 case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ 670 case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ 671 case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */ 672 break; 673 default: 674 qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %" 675 HWADDR_PRIx"\n", __func__, offset); 676 break; 677 } 678 } 679 680 static const MemoryRegionOps allwinner_sdhost_ops = { 681 .read = allwinner_sdhost_read, 682 .write = allwinner_sdhost_write, 683 .endianness = DEVICE_NATIVE_ENDIAN, 684 .valid = { 685 .min_access_size = 4, 686 .max_access_size = 4, 687 }, 688 .impl.min_access_size = 4, 689 }; 690 691 static const VMStateDescription vmstate_allwinner_sdhost = { 692 .name = "allwinner-sdhost", 693 .version_id = 1, 694 .minimum_version_id = 1, 695 .fields = (VMStateField[]) { 696 VMSTATE_UINT32(global_ctl, AwSdHostState), 697 VMSTATE_UINT32(clock_ctl, AwSdHostState), 698 VMSTATE_UINT32(timeout, AwSdHostState), 699 VMSTATE_UINT32(bus_width, AwSdHostState), 700 VMSTATE_UINT32(block_size, AwSdHostState), 701 VMSTATE_UINT32(byte_count, AwSdHostState), 702 VMSTATE_UINT32(transfer_cnt, AwSdHostState), 703 VMSTATE_UINT32(command, AwSdHostState), 704 VMSTATE_UINT32(command_arg, AwSdHostState), 705 VMSTATE_UINT32_ARRAY(response, AwSdHostState, 4), 706 VMSTATE_UINT32(irq_mask, AwSdHostState), 707 VMSTATE_UINT32(irq_status, AwSdHostState), 708 VMSTATE_UINT32(status, AwSdHostState), 709 VMSTATE_UINT32(fifo_wlevel, AwSdHostState), 710 VMSTATE_UINT32(fifo_func_sel, AwSdHostState), 711 VMSTATE_UINT32(debug_enable, AwSdHostState), 712 VMSTATE_UINT32(auto12_arg, AwSdHostState), 713 VMSTATE_UINT32(newtiming_set, AwSdHostState), 714 VMSTATE_UINT32(newtiming_debug, AwSdHostState), 715 VMSTATE_UINT32(hardware_rst, AwSdHostState), 716 VMSTATE_UINT32(dmac, AwSdHostState), 717 VMSTATE_UINT32(desc_base, AwSdHostState), 718 VMSTATE_UINT32(dmac_status, AwSdHostState), 719 VMSTATE_UINT32(dmac_irq, AwSdHostState), 720 VMSTATE_UINT32(card_threshold, AwSdHostState), 721 VMSTATE_UINT32(startbit_detect, AwSdHostState), 722 VMSTATE_UINT32(response_crc, AwSdHostState), 723 VMSTATE_UINT32_ARRAY(data_crc, AwSdHostState, 8), 724 VMSTATE_UINT32(status_crc, AwSdHostState), 725 VMSTATE_END_OF_LIST() 726 } 727 }; 728 729 static Property allwinner_sdhost_properties[] = { 730 DEFINE_PROP_LINK("dma-memory", AwSdHostState, dma_mr, 731 TYPE_MEMORY_REGION, MemoryRegion *), 732 DEFINE_PROP_END_OF_LIST(), 733 }; 734 735 static void allwinner_sdhost_init(Object *obj) 736 { 737 AwSdHostState *s = AW_SDHOST(obj); 738 739 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), 740 TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus"); 741 742 memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s, 743 TYPE_AW_SDHOST, 4 * KiB); 744 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); 745 sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); 746 } 747 748 static void allwinner_sdhost_realize(DeviceState *dev, Error **errp) 749 { 750 AwSdHostState *s = AW_SDHOST(dev); 751 752 if (!s->dma_mr) { 753 error_setg(errp, TYPE_AW_SDHOST " 'dma-memory' link not set"); 754 return; 755 } 756 757 address_space_init(&s->dma_as, s->dma_mr, "sdhost-dma"); 758 } 759 760 static void allwinner_sdhost_reset(DeviceState *dev) 761 { 762 AwSdHostState *s = AW_SDHOST(dev); 763 764 s->global_ctl = REG_SD_GCTL_RST; 765 s->clock_ctl = REG_SD_CKCR_RST; 766 s->timeout = REG_SD_TMOR_RST; 767 s->bus_width = REG_SD_BWDR_RST; 768 s->block_size = REG_SD_BKSR_RST; 769 s->byte_count = REG_SD_BYCR_RST; 770 s->transfer_cnt = 0; 771 772 s->command = REG_SD_CMDR_RST; 773 s->command_arg = REG_SD_CAGR_RST; 774 775 for (int i = 0; i < ARRAY_SIZE(s->response); i++) { 776 s->response[i] = REG_SD_RESP_RST; 777 } 778 779 s->irq_mask = REG_SD_IMKR_RST; 780 s->irq_status = REG_SD_RISR_RST; 781 s->status = REG_SD_STAR_RST; 782 783 s->fifo_wlevel = REG_SD_FWLR_RST; 784 s->fifo_func_sel = REG_SD_FUNS_RST; 785 s->debug_enable = REG_SD_DBGC_RST; 786 s->auto12_arg = REG_SD_A12A_RST; 787 s->newtiming_set = REG_SD_NTSR_RST; 788 s->newtiming_debug = REG_SD_SDBG_RST; 789 s->hardware_rst = REG_SD_HWRST_RST; 790 s->dmac = REG_SD_DMAC_RST; 791 s->desc_base = REG_SD_DLBA_RST; 792 s->dmac_status = REG_SD_IDST_RST; 793 s->dmac_irq = REG_SD_IDIE_RST; 794 s->card_threshold = REG_SD_THLDC_RST; 795 s->startbit_detect = REG_SD_DSBD_RST; 796 s->response_crc = REG_SD_RES_CRC_RST; 797 798 for (int i = 0; i < ARRAY_SIZE(s->data_crc); i++) { 799 s->data_crc[i] = REG_SD_DATA_CRC_RST; 800 } 801 802 s->status_crc = REG_SD_CRC_STA_RST; 803 } 804 805 static void allwinner_sdhost_bus_class_init(ObjectClass *klass, void *data) 806 { 807 SDBusClass *sbc = SD_BUS_CLASS(klass); 808 809 sbc->set_inserted = allwinner_sdhost_set_inserted; 810 } 811 812 static void allwinner_sdhost_class_init(ObjectClass *klass, void *data) 813 { 814 DeviceClass *dc = DEVICE_CLASS(klass); 815 816 dc->reset = allwinner_sdhost_reset; 817 dc->vmsd = &vmstate_allwinner_sdhost; 818 dc->realize = allwinner_sdhost_realize; 819 device_class_set_props(dc, allwinner_sdhost_properties); 820 } 821 822 static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data) 823 { 824 AwSdHostClass *sc = AW_SDHOST_CLASS(klass); 825 sc->max_desc_size = 8 * KiB; 826 } 827 828 static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data) 829 { 830 AwSdHostClass *sc = AW_SDHOST_CLASS(klass); 831 sc->max_desc_size = 64 * KiB; 832 } 833 834 static TypeInfo allwinner_sdhost_info = { 835 .name = TYPE_AW_SDHOST, 836 .parent = TYPE_SYS_BUS_DEVICE, 837 .instance_init = allwinner_sdhost_init, 838 .instance_size = sizeof(AwSdHostState), 839 .class_init = allwinner_sdhost_class_init, 840 .class_size = sizeof(AwSdHostClass), 841 .abstract = true, 842 }; 843 844 static const TypeInfo allwinner_sdhost_sun4i_info = { 845 .name = TYPE_AW_SDHOST_SUN4I, 846 .parent = TYPE_AW_SDHOST, 847 .class_init = allwinner_sdhost_sun4i_class_init, 848 }; 849 850 static const TypeInfo allwinner_sdhost_sun5i_info = { 851 .name = TYPE_AW_SDHOST_SUN5I, 852 .parent = TYPE_AW_SDHOST, 853 .class_init = allwinner_sdhost_sun5i_class_init, 854 }; 855 856 static const TypeInfo allwinner_sdhost_bus_info = { 857 .name = TYPE_AW_SDHOST_BUS, 858 .parent = TYPE_SD_BUS, 859 .instance_size = sizeof(SDBus), 860 .class_init = allwinner_sdhost_bus_class_init, 861 }; 862 863 static void allwinner_sdhost_register_types(void) 864 { 865 type_register_static(&allwinner_sdhost_info); 866 type_register_static(&allwinner_sdhost_sun4i_info); 867 type_register_static(&allwinner_sdhost_sun5i_info); 868 type_register_static(&allwinner_sdhost_bus_info); 869 } 870 871 type_init(allwinner_sdhost_register_types) 872