1 /* 2 * QEMU VMWARE PVSCSI paravirtual SCSI bus 3 * 4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com) 5 * 6 * Developed by Daynix Computing LTD (http://www.daynix.com) 7 * 8 * Based on implementation by Paolo Bonzini 9 * http://lists.gnu.org/archive/html/qemu-devel/2011-08/msg00729.html 10 * 11 * Authors: 12 * Paolo Bonzini <pbonzini@redhat.com> 13 * Dmitry Fleytman <dmitry@daynix.com> 14 * Yan Vugenfirer <yan@daynix.com> 15 * 16 * This work is licensed under the terms of the GNU GPL, version 2. 17 * See the COPYING file in the top-level directory. 18 * 19 * NOTE about MSI-X: 20 * MSI-X support has been removed for the moment because it leads Windows OS 21 * to crash on startup. The crash happens because Windows driver requires 22 * MSI-X shared memory to be part of the same BAR used for rings state 23 * registers, etc. This is not supported by QEMU infrastructure so separate 24 * BAR created from MSI-X purposes. Windows driver fails to deal with 2 BARs. 25 * 26 */ 27 28 #include "hw/scsi/scsi.h" 29 #include <block/scsi.h> 30 #include "hw/pci/msi.h" 31 #include "vmw_pvscsi.h" 32 #include "trace.h" 33 34 35 #define PVSCSI_MSI_OFFSET (0x50) 36 #define PVSCSI_USE_64BIT (true) 37 #define PVSCSI_PER_VECTOR_MASK (false) 38 39 #define PVSCSI_MAX_DEVS (64) 40 #define PVSCSI_MSIX_NUM_VECTORS (1) 41 42 #define PVSCSI_MAX_CMD_DATA_WORDS \ 43 (sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t)) 44 45 #define RS_GET_FIELD(rs_pa, field) \ 46 (ldl_le_phys(&address_space_memory, \ 47 rs_pa + offsetof(struct PVSCSIRingsState, field))) 48 #define RS_SET_FIELD(rs_pa, field, val) \ 49 (stl_le_phys(&address_space_memory, \ 50 rs_pa + offsetof(struct PVSCSIRingsState, field), val)) 51 52 #define TYPE_PVSCSI "pvscsi" 53 #define PVSCSI(obj) OBJECT_CHECK(PVSCSIState, (obj), TYPE_PVSCSI) 54 55 typedef struct PVSCSIRingInfo { 56 uint64_t rs_pa; 57 uint32_t txr_len_mask; 58 uint32_t rxr_len_mask; 59 uint32_t msg_len_mask; 60 uint64_t req_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES]; 61 uint64_t cmp_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES]; 62 uint64_t msg_ring_pages_pa[PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES]; 63 uint64_t consumed_ptr; 64 uint64_t filled_cmp_ptr; 65 uint64_t filled_msg_ptr; 66 } PVSCSIRingInfo; 67 68 typedef struct PVSCSISGState { 69 hwaddr elemAddr; 70 hwaddr dataAddr; 71 uint32_t resid; 72 } PVSCSISGState; 73 74 typedef QTAILQ_HEAD(, PVSCSIRequest) PVSCSIRequestList; 75 76 typedef struct { 77 PCIDevice parent_obj; 78 MemoryRegion io_space; 79 SCSIBus bus; 80 QEMUBH *completion_worker; 81 PVSCSIRequestList pending_queue; 82 PVSCSIRequestList completion_queue; 83 84 uint64_t reg_interrupt_status; /* Interrupt status register value */ 85 uint64_t reg_interrupt_enabled; /* Interrupt mask register value */ 86 uint64_t reg_command_status; /* Command status register value */ 87 88 /* Command data adoption mechanism */ 89 uint64_t curr_cmd; /* Last command arrived */ 90 uint32_t curr_cmd_data_cntr; /* Amount of data for last command */ 91 92 /* Collector for current command data */ 93 uint32_t curr_cmd_data[PVSCSI_MAX_CMD_DATA_WORDS]; 94 95 uint8_t rings_info_valid; /* Whether data rings initialized */ 96 uint8_t msg_ring_info_valid; /* Whether message ring initialized */ 97 uint8_t use_msg; /* Whether to use message ring */ 98 99 uint8_t msi_used; /* Whether MSI support was installed successfully */ 100 101 PVSCSIRingInfo rings; /* Data transfer rings manager */ 102 uint32_t resetting; /* Reset in progress */ 103 } PVSCSIState; 104 105 typedef struct PVSCSIRequest { 106 SCSIRequest *sreq; 107 PVSCSIState *dev; 108 uint8_t sense_key; 109 uint8_t completed; 110 int lun; 111 QEMUSGList sgl; 112 PVSCSISGState sg; 113 struct PVSCSIRingReqDesc req; 114 struct PVSCSIRingCmpDesc cmp; 115 QTAILQ_ENTRY(PVSCSIRequest) next; 116 } PVSCSIRequest; 117 118 /* Integer binary logarithm */ 119 static int 120 pvscsi_log2(uint32_t input) 121 { 122 int log = 0; 123 assert(input > 0); 124 while (input >> ++log) { 125 } 126 return log; 127 } 128 129 static void 130 pvscsi_ring_init_data(PVSCSIRingInfo *m, PVSCSICmdDescSetupRings *ri) 131 { 132 int i; 133 uint32_t txr_len_log2, rxr_len_log2; 134 uint32_t req_ring_size, cmp_ring_size; 135 m->rs_pa = ri->ringsStatePPN << VMW_PAGE_SHIFT; 136 137 req_ring_size = ri->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; 138 cmp_ring_size = ri->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE; 139 txr_len_log2 = pvscsi_log2(req_ring_size - 1); 140 rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1); 141 142 m->txr_len_mask = MASK(txr_len_log2); 143 m->rxr_len_mask = MASK(rxr_len_log2); 144 145 m->consumed_ptr = 0; 146 m->filled_cmp_ptr = 0; 147 148 for (i = 0; i < ri->reqRingNumPages; i++) { 149 m->req_ring_pages_pa[i] = ri->reqRingPPNs[i] << VMW_PAGE_SHIFT; 150 } 151 152 for (i = 0; i < ri->cmpRingNumPages; i++) { 153 m->cmp_ring_pages_pa[i] = ri->cmpRingPPNs[i] << VMW_PAGE_SHIFT; 154 } 155 156 RS_SET_FIELD(m->rs_pa, reqProdIdx, 0); 157 RS_SET_FIELD(m->rs_pa, reqConsIdx, 0); 158 RS_SET_FIELD(m->rs_pa, reqNumEntriesLog2, txr_len_log2); 159 160 RS_SET_FIELD(m->rs_pa, cmpProdIdx, 0); 161 RS_SET_FIELD(m->rs_pa, cmpConsIdx, 0); 162 RS_SET_FIELD(m->rs_pa, cmpNumEntriesLog2, rxr_len_log2); 163 164 trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2); 165 166 /* Flush ring state page changes */ 167 smp_wmb(); 168 } 169 170 static void 171 pvscsi_ring_init_msg(PVSCSIRingInfo *m, PVSCSICmdDescSetupMsgRing *ri) 172 { 173 int i; 174 uint32_t len_log2; 175 uint32_t ring_size; 176 177 ring_size = ri->numPages * PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE; 178 len_log2 = pvscsi_log2(ring_size - 1); 179 180 m->msg_len_mask = MASK(len_log2); 181 182 m->filled_msg_ptr = 0; 183 184 for (i = 0; i < ri->numPages; i++) { 185 m->msg_ring_pages_pa[i] = ri->ringPPNs[i] << VMW_PAGE_SHIFT; 186 } 187 188 RS_SET_FIELD(m->rs_pa, msgProdIdx, 0); 189 RS_SET_FIELD(m->rs_pa, msgConsIdx, 0); 190 RS_SET_FIELD(m->rs_pa, msgNumEntriesLog2, len_log2); 191 192 trace_pvscsi_ring_init_msg(len_log2); 193 194 /* Flush ring state page changes */ 195 smp_wmb(); 196 } 197 198 static void 199 pvscsi_ring_cleanup(PVSCSIRingInfo *mgr) 200 { 201 mgr->rs_pa = 0; 202 mgr->txr_len_mask = 0; 203 mgr->rxr_len_mask = 0; 204 mgr->msg_len_mask = 0; 205 mgr->consumed_ptr = 0; 206 mgr->filled_cmp_ptr = 0; 207 mgr->filled_msg_ptr = 0; 208 memset(mgr->req_ring_pages_pa, 0, sizeof(mgr->req_ring_pages_pa)); 209 memset(mgr->cmp_ring_pages_pa, 0, sizeof(mgr->cmp_ring_pages_pa)); 210 memset(mgr->msg_ring_pages_pa, 0, sizeof(mgr->msg_ring_pages_pa)); 211 } 212 213 static hwaddr 214 pvscsi_ring_pop_req_descr(PVSCSIRingInfo *mgr) 215 { 216 uint32_t ready_ptr = RS_GET_FIELD(mgr->rs_pa, reqProdIdx); 217 218 if (ready_ptr != mgr->consumed_ptr) { 219 uint32_t next_ready_ptr = 220 mgr->consumed_ptr++ & mgr->txr_len_mask; 221 uint32_t next_ready_page = 222 next_ready_ptr / PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; 223 uint32_t inpage_idx = 224 next_ready_ptr % PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; 225 226 return mgr->req_ring_pages_pa[next_ready_page] + 227 inpage_idx * sizeof(PVSCSIRingReqDesc); 228 } else { 229 return 0; 230 } 231 } 232 233 static void 234 pvscsi_ring_flush_req(PVSCSIRingInfo *mgr) 235 { 236 RS_SET_FIELD(mgr->rs_pa, reqConsIdx, mgr->consumed_ptr); 237 } 238 239 static hwaddr 240 pvscsi_ring_pop_cmp_descr(PVSCSIRingInfo *mgr) 241 { 242 /* 243 * According to Linux driver code it explicitly verifies that number 244 * of requests being processed by device is less then the size of 245 * completion queue, so device may omit completion queue overflow 246 * conditions check. We assume that this is true for other (Windows) 247 * drivers as well. 248 */ 249 250 uint32_t free_cmp_ptr = 251 mgr->filled_cmp_ptr++ & mgr->rxr_len_mask; 252 uint32_t free_cmp_page = 253 free_cmp_ptr / PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE; 254 uint32_t inpage_idx = 255 free_cmp_ptr % PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE; 256 return mgr->cmp_ring_pages_pa[free_cmp_page] + 257 inpage_idx * sizeof(PVSCSIRingCmpDesc); 258 } 259 260 static hwaddr 261 pvscsi_ring_pop_msg_descr(PVSCSIRingInfo *mgr) 262 { 263 uint32_t free_msg_ptr = 264 mgr->filled_msg_ptr++ & mgr->msg_len_mask; 265 uint32_t free_msg_page = 266 free_msg_ptr / PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE; 267 uint32_t inpage_idx = 268 free_msg_ptr % PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE; 269 return mgr->msg_ring_pages_pa[free_msg_page] + 270 inpage_idx * sizeof(PVSCSIRingMsgDesc); 271 } 272 273 static void 274 pvscsi_ring_flush_cmp(PVSCSIRingInfo *mgr) 275 { 276 /* Flush descriptor changes */ 277 smp_wmb(); 278 279 trace_pvscsi_ring_flush_cmp(mgr->filled_cmp_ptr); 280 281 RS_SET_FIELD(mgr->rs_pa, cmpProdIdx, mgr->filled_cmp_ptr); 282 } 283 284 static bool 285 pvscsi_ring_msg_has_room(PVSCSIRingInfo *mgr) 286 { 287 uint32_t prodIdx = RS_GET_FIELD(mgr->rs_pa, msgProdIdx); 288 uint32_t consIdx = RS_GET_FIELD(mgr->rs_pa, msgConsIdx); 289 290 return (prodIdx - consIdx) < (mgr->msg_len_mask + 1); 291 } 292 293 static void 294 pvscsi_ring_flush_msg(PVSCSIRingInfo *mgr) 295 { 296 /* Flush descriptor changes */ 297 smp_wmb(); 298 299 trace_pvscsi_ring_flush_msg(mgr->filled_msg_ptr); 300 301 RS_SET_FIELD(mgr->rs_pa, msgProdIdx, mgr->filled_msg_ptr); 302 } 303 304 static void 305 pvscsi_reset_state(PVSCSIState *s) 306 { 307 s->curr_cmd = PVSCSI_CMD_FIRST; 308 s->curr_cmd_data_cntr = 0; 309 s->reg_command_status = PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 310 s->reg_interrupt_status = 0; 311 pvscsi_ring_cleanup(&s->rings); 312 s->rings_info_valid = FALSE; 313 s->msg_ring_info_valid = FALSE; 314 QTAILQ_INIT(&s->pending_queue); 315 QTAILQ_INIT(&s->completion_queue); 316 } 317 318 static void 319 pvscsi_update_irq_status(PVSCSIState *s) 320 { 321 PCIDevice *d = PCI_DEVICE(s); 322 bool should_raise = s->reg_interrupt_enabled & s->reg_interrupt_status; 323 324 trace_pvscsi_update_irq_level(should_raise, s->reg_interrupt_enabled, 325 s->reg_interrupt_status); 326 327 if (s->msi_used && msi_enabled(d)) { 328 if (should_raise) { 329 trace_pvscsi_update_irq_msi(); 330 msi_notify(d, PVSCSI_VECTOR_COMPLETION); 331 } 332 return; 333 } 334 335 pci_set_irq(d, !!should_raise); 336 } 337 338 static void 339 pvscsi_raise_completion_interrupt(PVSCSIState *s) 340 { 341 s->reg_interrupt_status |= PVSCSI_INTR_CMPL_0; 342 343 /* Memory barrier to flush interrupt status register changes*/ 344 smp_wmb(); 345 346 pvscsi_update_irq_status(s); 347 } 348 349 static void 350 pvscsi_raise_message_interrupt(PVSCSIState *s) 351 { 352 s->reg_interrupt_status |= PVSCSI_INTR_MSG_0; 353 354 /* Memory barrier to flush interrupt status register changes*/ 355 smp_wmb(); 356 357 pvscsi_update_irq_status(s); 358 } 359 360 static void 361 pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCmpDesc *cmp_desc) 362 { 363 hwaddr cmp_descr_pa; 364 365 cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings); 366 trace_pvscsi_cmp_ring_put(cmp_descr_pa); 367 cpu_physical_memory_write(cmp_descr_pa, (void *)cmp_desc, 368 sizeof(*cmp_desc)); 369 } 370 371 static void 372 pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMsgDesc *msg_desc) 373 { 374 hwaddr msg_descr_pa; 375 376 msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings); 377 trace_pvscsi_msg_ring_put(msg_descr_pa); 378 cpu_physical_memory_write(msg_descr_pa, (void *)msg_desc, 379 sizeof(*msg_desc)); 380 } 381 382 static void 383 pvscsi_process_completion_queue(void *opaque) 384 { 385 PVSCSIState *s = opaque; 386 PVSCSIRequest *pvscsi_req; 387 bool has_completed = false; 388 389 while (!QTAILQ_EMPTY(&s->completion_queue)) { 390 pvscsi_req = QTAILQ_FIRST(&s->completion_queue); 391 QTAILQ_REMOVE(&s->completion_queue, pvscsi_req, next); 392 pvscsi_cmp_ring_put(s, &pvscsi_req->cmp); 393 g_free(pvscsi_req); 394 has_completed = true; 395 } 396 397 if (has_completed) { 398 pvscsi_ring_flush_cmp(&s->rings); 399 pvscsi_raise_completion_interrupt(s); 400 } 401 } 402 403 static void 404 pvscsi_reset_adapter(PVSCSIState *s) 405 { 406 s->resetting++; 407 qbus_reset_all_fn(&s->bus); 408 s->resetting--; 409 pvscsi_process_completion_queue(s); 410 assert(QTAILQ_EMPTY(&s->pending_queue)); 411 pvscsi_reset_state(s); 412 } 413 414 static void 415 pvscsi_schedule_completion_processing(PVSCSIState *s) 416 { 417 /* Try putting more complete requests on the ring. */ 418 if (!QTAILQ_EMPTY(&s->completion_queue)) { 419 qemu_bh_schedule(s->completion_worker); 420 } 421 } 422 423 static void 424 pvscsi_complete_request(PVSCSIState *s, PVSCSIRequest *r) 425 { 426 assert(!r->completed); 427 428 trace_pvscsi_complete_request(r->cmp.context, r->cmp.dataLen, 429 r->sense_key); 430 if (r->sreq != NULL) { 431 scsi_req_unref(r->sreq); 432 r->sreq = NULL; 433 } 434 r->completed = 1; 435 QTAILQ_REMOVE(&s->pending_queue, r, next); 436 QTAILQ_INSERT_TAIL(&s->completion_queue, r, next); 437 pvscsi_schedule_completion_processing(s); 438 } 439 440 static QEMUSGList *pvscsi_get_sg_list(SCSIRequest *r) 441 { 442 PVSCSIRequest *req = r->hba_private; 443 444 trace_pvscsi_get_sg_list(req->sgl.nsg, req->sgl.size); 445 446 return &req->sgl; 447 } 448 449 static void 450 pvscsi_get_next_sg_elem(PVSCSISGState *sg) 451 { 452 struct PVSCSISGElement elem; 453 454 cpu_physical_memory_read(sg->elemAddr, (void *)&elem, sizeof(elem)); 455 if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) != 0) { 456 /* 457 * There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in 458 * header file but its value is unknown. This flag requires 459 * additional processing, so we put warning here to catch it 460 * some day and make proper implementation 461 */ 462 trace_pvscsi_get_next_sg_elem(elem.flags); 463 } 464 465 sg->elemAddr += sizeof(elem); 466 sg->dataAddr = elem.addr; 467 sg->resid = elem.length; 468 } 469 470 static void 471 pvscsi_write_sense(PVSCSIRequest *r, uint8_t *sense, int len) 472 { 473 r->cmp.senseLen = MIN(r->req.senseLen, len); 474 r->sense_key = sense[(sense[0] & 2) ? 1 : 2]; 475 cpu_physical_memory_write(r->req.senseAddr, sense, r->cmp.senseLen); 476 } 477 478 static void 479 pvscsi_command_complete(SCSIRequest *req, uint32_t status, size_t resid) 480 { 481 PVSCSIRequest *pvscsi_req = req->hba_private; 482 PVSCSIState *s; 483 484 if (!pvscsi_req) { 485 trace_pvscsi_command_complete_not_found(req->tag); 486 return; 487 } 488 s = pvscsi_req->dev; 489 490 if (resid) { 491 /* Short transfer. */ 492 trace_pvscsi_command_complete_data_run(); 493 pvscsi_req->cmp.hostStatus = BTSTAT_DATARUN; 494 } 495 496 pvscsi_req->cmp.scsiStatus = status; 497 if (pvscsi_req->cmp.scsiStatus == CHECK_CONDITION) { 498 uint8_t sense[SCSI_SENSE_BUF_SIZE]; 499 int sense_len = 500 scsi_req_get_sense(pvscsi_req->sreq, sense, sizeof(sense)); 501 502 trace_pvscsi_command_complete_sense_len(sense_len); 503 pvscsi_write_sense(pvscsi_req, sense, sense_len); 504 } 505 qemu_sglist_destroy(&pvscsi_req->sgl); 506 pvscsi_complete_request(s, pvscsi_req); 507 } 508 509 static void 510 pvscsi_send_msg(PVSCSIState *s, SCSIDevice *dev, uint32_t msg_type) 511 { 512 if (s->msg_ring_info_valid && pvscsi_ring_msg_has_room(&s->rings)) { 513 PVSCSIMsgDescDevStatusChanged msg = {0}; 514 515 msg.type = msg_type; 516 msg.bus = dev->channel; 517 msg.target = dev->id; 518 msg.lun[1] = dev->lun; 519 520 pvscsi_msg_ring_put(s, (PVSCSIRingMsgDesc *)&msg); 521 pvscsi_ring_flush_msg(&s->rings); 522 pvscsi_raise_message_interrupt(s); 523 } 524 } 525 526 static void 527 pvscsi_hotplug(SCSIBus *bus, SCSIDevice *dev) 528 { 529 PVSCSIState *s = container_of(bus, PVSCSIState, bus); 530 pvscsi_send_msg(s, dev, PVSCSI_MSG_DEV_ADDED); 531 } 532 533 static void 534 pvscsi_hot_unplug(SCSIBus *bus, SCSIDevice *dev) 535 { 536 PVSCSIState *s = container_of(bus, PVSCSIState, bus); 537 pvscsi_send_msg(s, dev, PVSCSI_MSG_DEV_REMOVED); 538 } 539 540 static void 541 pvscsi_request_cancelled(SCSIRequest *req) 542 { 543 PVSCSIRequest *pvscsi_req = req->hba_private; 544 PVSCSIState *s = pvscsi_req->dev; 545 546 if (pvscsi_req->completed) { 547 return; 548 } 549 550 if (pvscsi_req->dev->resetting) { 551 pvscsi_req->cmp.hostStatus = BTSTAT_BUSRESET; 552 } else { 553 pvscsi_req->cmp.hostStatus = BTSTAT_ABORTQUEUE; 554 } 555 556 pvscsi_complete_request(s, pvscsi_req); 557 } 558 559 static SCSIDevice* 560 pvscsi_device_find(PVSCSIState *s, int channel, int target, 561 uint8_t *requested_lun, uint8_t *target_lun) 562 { 563 if (requested_lun[0] || requested_lun[2] || requested_lun[3] || 564 requested_lun[4] || requested_lun[5] || requested_lun[6] || 565 requested_lun[7] || (target > PVSCSI_MAX_DEVS)) { 566 return NULL; 567 } else { 568 *target_lun = requested_lun[1]; 569 return scsi_device_find(&s->bus, channel, target, *target_lun); 570 } 571 } 572 573 static PVSCSIRequest * 574 pvscsi_queue_pending_descriptor(PVSCSIState *s, SCSIDevice **d, 575 struct PVSCSIRingReqDesc *descr) 576 { 577 PVSCSIRequest *pvscsi_req; 578 uint8_t lun; 579 580 pvscsi_req = g_malloc0(sizeof(*pvscsi_req)); 581 pvscsi_req->dev = s; 582 pvscsi_req->req = *descr; 583 pvscsi_req->cmp.context = pvscsi_req->req.context; 584 QTAILQ_INSERT_TAIL(&s->pending_queue, pvscsi_req, next); 585 586 *d = pvscsi_device_find(s, descr->bus, descr->target, descr->lun, &lun); 587 if (*d) { 588 pvscsi_req->lun = lun; 589 } 590 591 return pvscsi_req; 592 } 593 594 static void 595 pvscsi_convert_sglist(PVSCSIRequest *r) 596 { 597 int chunk_size; 598 uint64_t data_length = r->req.dataLen; 599 PVSCSISGState sg = r->sg; 600 while (data_length) { 601 while (!sg.resid) { 602 pvscsi_get_next_sg_elem(&sg); 603 trace_pvscsi_convert_sglist(r->req.context, r->sg.dataAddr, 604 r->sg.resid); 605 } 606 assert(data_length > 0); 607 chunk_size = MIN((unsigned) data_length, sg.resid); 608 if (chunk_size) { 609 qemu_sglist_add(&r->sgl, sg.dataAddr, chunk_size); 610 } 611 612 sg.dataAddr += chunk_size; 613 data_length -= chunk_size; 614 sg.resid -= chunk_size; 615 } 616 } 617 618 static void 619 pvscsi_build_sglist(PVSCSIState *s, PVSCSIRequest *r) 620 { 621 PCIDevice *d = PCI_DEVICE(s); 622 623 pci_dma_sglist_init(&r->sgl, d, 1); 624 if (r->req.flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) { 625 pvscsi_convert_sglist(r); 626 } else { 627 qemu_sglist_add(&r->sgl, r->req.dataAddr, r->req.dataLen); 628 } 629 } 630 631 static void 632 pvscsi_process_request_descriptor(PVSCSIState *s, 633 struct PVSCSIRingReqDesc *descr) 634 { 635 SCSIDevice *d; 636 PVSCSIRequest *r = pvscsi_queue_pending_descriptor(s, &d, descr); 637 int64_t n; 638 639 trace_pvscsi_process_req_descr(descr->cdb[0], descr->context); 640 641 if (!d) { 642 r->cmp.hostStatus = BTSTAT_SELTIMEO; 643 trace_pvscsi_process_req_descr_unknown_device(); 644 pvscsi_complete_request(s, r); 645 return; 646 } 647 648 if (descr->flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) { 649 r->sg.elemAddr = descr->dataAddr; 650 } 651 652 r->sreq = scsi_req_new(d, descr->context, r->lun, descr->cdb, r); 653 if (r->sreq->cmd.mode == SCSI_XFER_FROM_DEV && 654 (descr->flags & PVSCSI_FLAG_CMD_DIR_TODEVICE)) { 655 r->cmp.hostStatus = BTSTAT_BADMSG; 656 trace_pvscsi_process_req_descr_invalid_dir(); 657 scsi_req_cancel(r->sreq); 658 return; 659 } 660 if (r->sreq->cmd.mode == SCSI_XFER_TO_DEV && 661 (descr->flags & PVSCSI_FLAG_CMD_DIR_TOHOST)) { 662 r->cmp.hostStatus = BTSTAT_BADMSG; 663 trace_pvscsi_process_req_descr_invalid_dir(); 664 scsi_req_cancel(r->sreq); 665 return; 666 } 667 668 pvscsi_build_sglist(s, r); 669 n = scsi_req_enqueue(r->sreq); 670 671 if (n) { 672 scsi_req_continue(r->sreq); 673 } 674 } 675 676 static void 677 pvscsi_process_io(PVSCSIState *s) 678 { 679 PVSCSIRingReqDesc descr; 680 hwaddr next_descr_pa; 681 682 assert(s->rings_info_valid); 683 while ((next_descr_pa = pvscsi_ring_pop_req_descr(&s->rings)) != 0) { 684 685 /* Only read after production index verification */ 686 smp_rmb(); 687 688 trace_pvscsi_process_io(next_descr_pa); 689 cpu_physical_memory_read(next_descr_pa, &descr, sizeof(descr)); 690 pvscsi_process_request_descriptor(s, &descr); 691 } 692 693 pvscsi_ring_flush_req(&s->rings); 694 } 695 696 static void 697 pvscsi_dbg_dump_tx_rings_config(PVSCSICmdDescSetupRings *rc) 698 { 699 int i; 700 trace_pvscsi_tx_rings_ppn("Rings State", rc->ringsStatePPN); 701 702 trace_pvscsi_tx_rings_num_pages("Request Ring", rc->reqRingNumPages); 703 for (i = 0; i < rc->reqRingNumPages; i++) { 704 trace_pvscsi_tx_rings_ppn("Request Ring", rc->reqRingPPNs[i]); 705 } 706 707 trace_pvscsi_tx_rings_num_pages("Confirm Ring", rc->cmpRingNumPages); 708 for (i = 0; i < rc->cmpRingNumPages; i++) { 709 trace_pvscsi_tx_rings_ppn("Confirm Ring", rc->reqRingPPNs[i]); 710 } 711 } 712 713 static uint64_t 714 pvscsi_on_cmd_config(PVSCSIState *s) 715 { 716 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_CONFIG"); 717 return PVSCSI_COMMAND_PROCESSING_FAILED; 718 } 719 720 static uint64_t 721 pvscsi_on_cmd_unplug(PVSCSIState *s) 722 { 723 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_DEVICE_UNPLUG"); 724 return PVSCSI_COMMAND_PROCESSING_FAILED; 725 } 726 727 static uint64_t 728 pvscsi_on_issue_scsi(PVSCSIState *s) 729 { 730 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_ISSUE_SCSI"); 731 return PVSCSI_COMMAND_PROCESSING_FAILED; 732 } 733 734 static uint64_t 735 pvscsi_on_cmd_setup_rings(PVSCSIState *s) 736 { 737 PVSCSICmdDescSetupRings *rc = 738 (PVSCSICmdDescSetupRings *) s->curr_cmd_data; 739 740 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_RINGS"); 741 742 pvscsi_dbg_dump_tx_rings_config(rc); 743 pvscsi_ring_init_data(&s->rings, rc); 744 s->rings_info_valid = TRUE; 745 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 746 } 747 748 static uint64_t 749 pvscsi_on_cmd_abort(PVSCSIState *s) 750 { 751 PVSCSICmdDescAbortCmd *cmd = (PVSCSICmdDescAbortCmd *) s->curr_cmd_data; 752 PVSCSIRequest *r, *next; 753 754 trace_pvscsi_on_cmd_abort(cmd->context, cmd->target); 755 756 QTAILQ_FOREACH_SAFE(r, &s->pending_queue, next, next) { 757 if (r->req.context == cmd->context) { 758 break; 759 } 760 } 761 if (r) { 762 assert(!r->completed); 763 r->cmp.hostStatus = BTSTAT_ABORTQUEUE; 764 scsi_req_cancel(r->sreq); 765 } 766 767 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 768 } 769 770 static uint64_t 771 pvscsi_on_cmd_unknown(PVSCSIState *s) 772 { 773 trace_pvscsi_on_cmd_unknown_data(s->curr_cmd_data[0]); 774 return PVSCSI_COMMAND_PROCESSING_FAILED; 775 } 776 777 static uint64_t 778 pvscsi_on_cmd_reset_device(PVSCSIState *s) 779 { 780 uint8_t target_lun = 0; 781 struct PVSCSICmdDescResetDevice *cmd = 782 (struct PVSCSICmdDescResetDevice *) s->curr_cmd_data; 783 SCSIDevice *sdev; 784 785 sdev = pvscsi_device_find(s, 0, cmd->target, cmd->lun, &target_lun); 786 787 trace_pvscsi_on_cmd_reset_dev(cmd->target, (int) target_lun, sdev); 788 789 if (sdev != NULL) { 790 s->resetting++; 791 device_reset(&sdev->qdev); 792 s->resetting--; 793 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 794 } 795 796 return PVSCSI_COMMAND_PROCESSING_FAILED; 797 } 798 799 static uint64_t 800 pvscsi_on_cmd_reset_bus(PVSCSIState *s) 801 { 802 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_RESET_BUS"); 803 804 s->resetting++; 805 qbus_reset_all_fn(&s->bus); 806 s->resetting--; 807 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 808 } 809 810 static uint64_t 811 pvscsi_on_cmd_setup_msg_ring(PVSCSIState *s) 812 { 813 PVSCSICmdDescSetupMsgRing *rc = 814 (PVSCSICmdDescSetupMsgRing *) s->curr_cmd_data; 815 816 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_MSG_RING"); 817 818 if (!s->use_msg) { 819 return PVSCSI_COMMAND_PROCESSING_FAILED; 820 } 821 822 if (s->rings_info_valid) { 823 pvscsi_ring_init_msg(&s->rings, rc); 824 s->msg_ring_info_valid = TRUE; 825 } 826 return sizeof(PVSCSICmdDescSetupMsgRing) / sizeof(uint32_t); 827 } 828 829 static uint64_t 830 pvscsi_on_cmd_adapter_reset(PVSCSIState *s) 831 { 832 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_ADAPTER_RESET"); 833 834 pvscsi_reset_adapter(s); 835 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 836 } 837 838 static const struct { 839 int data_size; 840 uint64_t (*handler_fn)(PVSCSIState *s); 841 } pvscsi_commands[] = { 842 [PVSCSI_CMD_FIRST] = { 843 .data_size = 0, 844 .handler_fn = pvscsi_on_cmd_unknown, 845 }, 846 847 /* Not implemented, data size defined based on what arrives on windows */ 848 [PVSCSI_CMD_CONFIG] = { 849 .data_size = 6 * sizeof(uint32_t), 850 .handler_fn = pvscsi_on_cmd_config, 851 }, 852 853 /* Command not implemented, data size is unknown */ 854 [PVSCSI_CMD_ISSUE_SCSI] = { 855 .data_size = 0, 856 .handler_fn = pvscsi_on_issue_scsi, 857 }, 858 859 /* Command not implemented, data size is unknown */ 860 [PVSCSI_CMD_DEVICE_UNPLUG] = { 861 .data_size = 0, 862 .handler_fn = pvscsi_on_cmd_unplug, 863 }, 864 865 [PVSCSI_CMD_SETUP_RINGS] = { 866 .data_size = sizeof(PVSCSICmdDescSetupRings), 867 .handler_fn = pvscsi_on_cmd_setup_rings, 868 }, 869 870 [PVSCSI_CMD_RESET_DEVICE] = { 871 .data_size = sizeof(struct PVSCSICmdDescResetDevice), 872 .handler_fn = pvscsi_on_cmd_reset_device, 873 }, 874 875 [PVSCSI_CMD_RESET_BUS] = { 876 .data_size = 0, 877 .handler_fn = pvscsi_on_cmd_reset_bus, 878 }, 879 880 [PVSCSI_CMD_SETUP_MSG_RING] = { 881 .data_size = sizeof(PVSCSICmdDescSetupMsgRing), 882 .handler_fn = pvscsi_on_cmd_setup_msg_ring, 883 }, 884 885 [PVSCSI_CMD_ADAPTER_RESET] = { 886 .data_size = 0, 887 .handler_fn = pvscsi_on_cmd_adapter_reset, 888 }, 889 890 [PVSCSI_CMD_ABORT_CMD] = { 891 .data_size = sizeof(struct PVSCSICmdDescAbortCmd), 892 .handler_fn = pvscsi_on_cmd_abort, 893 }, 894 }; 895 896 static void 897 pvscsi_do_command_processing(PVSCSIState *s) 898 { 899 size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t); 900 901 assert(s->curr_cmd < PVSCSI_CMD_LAST); 902 if (bytes_arrived >= pvscsi_commands[s->curr_cmd].data_size) { 903 s->reg_command_status = pvscsi_commands[s->curr_cmd].handler_fn(s); 904 s->curr_cmd = PVSCSI_CMD_FIRST; 905 s->curr_cmd_data_cntr = 0; 906 } 907 } 908 909 static void 910 pvscsi_on_command_data(PVSCSIState *s, uint32_t value) 911 { 912 size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t); 913 914 assert(bytes_arrived < sizeof(s->curr_cmd_data)); 915 s->curr_cmd_data[s->curr_cmd_data_cntr++] = value; 916 917 pvscsi_do_command_processing(s); 918 } 919 920 static void 921 pvscsi_on_command(PVSCSIState *s, uint64_t cmd_id) 922 { 923 if ((cmd_id > PVSCSI_CMD_FIRST) && (cmd_id < PVSCSI_CMD_LAST)) { 924 s->curr_cmd = cmd_id; 925 } else { 926 s->curr_cmd = PVSCSI_CMD_FIRST; 927 trace_pvscsi_on_cmd_unknown(cmd_id); 928 } 929 930 s->curr_cmd_data_cntr = 0; 931 s->reg_command_status = PVSCSI_COMMAND_NOT_ENOUGH_DATA; 932 933 pvscsi_do_command_processing(s); 934 } 935 936 static void 937 pvscsi_io_write(void *opaque, hwaddr addr, 938 uint64_t val, unsigned size) 939 { 940 PVSCSIState *s = opaque; 941 942 switch (addr) { 943 case PVSCSI_REG_OFFSET_COMMAND: 944 pvscsi_on_command(s, val); 945 break; 946 947 case PVSCSI_REG_OFFSET_COMMAND_DATA: 948 pvscsi_on_command_data(s, (uint32_t) val); 949 break; 950 951 case PVSCSI_REG_OFFSET_INTR_STATUS: 952 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_STATUS", val); 953 s->reg_interrupt_status &= ~val; 954 pvscsi_update_irq_status(s); 955 pvscsi_schedule_completion_processing(s); 956 break; 957 958 case PVSCSI_REG_OFFSET_INTR_MASK: 959 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_MASK", val); 960 s->reg_interrupt_enabled = val; 961 pvscsi_update_irq_status(s); 962 break; 963 964 case PVSCSI_REG_OFFSET_KICK_NON_RW_IO: 965 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_NON_RW_IO", val); 966 pvscsi_process_io(s); 967 break; 968 969 case PVSCSI_REG_OFFSET_KICK_RW_IO: 970 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_RW_IO", val); 971 pvscsi_process_io(s); 972 break; 973 974 case PVSCSI_REG_OFFSET_DEBUG: 975 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_DEBUG", val); 976 break; 977 978 default: 979 trace_pvscsi_io_write_unknown(addr, size, val); 980 break; 981 } 982 983 } 984 985 static uint64_t 986 pvscsi_io_read(void *opaque, hwaddr addr, unsigned size) 987 { 988 PVSCSIState *s = opaque; 989 990 switch (addr) { 991 case PVSCSI_REG_OFFSET_INTR_STATUS: 992 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_STATUS", 993 s->reg_interrupt_status); 994 return s->reg_interrupt_status; 995 996 case PVSCSI_REG_OFFSET_INTR_MASK: 997 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_MASK", 998 s->reg_interrupt_status); 999 return s->reg_interrupt_enabled; 1000 1001 case PVSCSI_REG_OFFSET_COMMAND_STATUS: 1002 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_COMMAND_STATUS", 1003 s->reg_interrupt_status); 1004 return s->reg_command_status; 1005 1006 default: 1007 trace_pvscsi_io_read_unknown(addr, size); 1008 return 0; 1009 } 1010 } 1011 1012 1013 static bool 1014 pvscsi_init_msi(PVSCSIState *s) 1015 { 1016 int res; 1017 PCIDevice *d = PCI_DEVICE(s); 1018 1019 res = msi_init(d, PVSCSI_MSI_OFFSET, PVSCSI_MSIX_NUM_VECTORS, 1020 PVSCSI_USE_64BIT, PVSCSI_PER_VECTOR_MASK); 1021 if (res < 0) { 1022 trace_pvscsi_init_msi_fail(res); 1023 s->msi_used = false; 1024 } else { 1025 s->msi_used = true; 1026 } 1027 1028 return s->msi_used; 1029 } 1030 1031 static void 1032 pvscsi_cleanup_msi(PVSCSIState *s) 1033 { 1034 PCIDevice *d = PCI_DEVICE(s); 1035 1036 if (s->msi_used) { 1037 msi_uninit(d); 1038 } 1039 } 1040 1041 static const MemoryRegionOps pvscsi_ops = { 1042 .read = pvscsi_io_read, 1043 .write = pvscsi_io_write, 1044 .endianness = DEVICE_LITTLE_ENDIAN, 1045 .impl = { 1046 .min_access_size = 4, 1047 .max_access_size = 4, 1048 }, 1049 }; 1050 1051 static const struct SCSIBusInfo pvscsi_scsi_info = { 1052 .tcq = true, 1053 .max_target = PVSCSI_MAX_DEVS, 1054 .max_channel = 0, 1055 .max_lun = 0, 1056 1057 .get_sg_list = pvscsi_get_sg_list, 1058 .complete = pvscsi_command_complete, 1059 .cancel = pvscsi_request_cancelled, 1060 .hotplug = pvscsi_hotplug, 1061 .hot_unplug = pvscsi_hot_unplug, 1062 }; 1063 1064 static int 1065 pvscsi_init(PCIDevice *pci_dev) 1066 { 1067 PVSCSIState *s = PVSCSI(pci_dev); 1068 1069 trace_pvscsi_state("init"); 1070 1071 /* PCI subsystem ID */ 1072 pci_dev->config[PCI_SUBSYSTEM_ID] = 0x00; 1073 pci_dev->config[PCI_SUBSYSTEM_ID + 1] = 0x10; 1074 1075 /* PCI latency timer = 255 */ 1076 pci_dev->config[PCI_LATENCY_TIMER] = 0xff; 1077 1078 /* Interrupt pin A */ 1079 pci_config_set_interrupt_pin(pci_dev->config, 1); 1080 1081 memory_region_init_io(&s->io_space, OBJECT(s), &pvscsi_ops, s, 1082 "pvscsi-io", PVSCSI_MEM_SPACE_SIZE); 1083 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io_space); 1084 1085 pvscsi_init_msi(s); 1086 1087 s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s); 1088 if (!s->completion_worker) { 1089 pvscsi_cleanup_msi(s); 1090 return -ENOMEM; 1091 } 1092 1093 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(pci_dev), 1094 &pvscsi_scsi_info, NULL); 1095 pvscsi_reset_state(s); 1096 1097 return 0; 1098 } 1099 1100 static void 1101 pvscsi_uninit(PCIDevice *pci_dev) 1102 { 1103 PVSCSIState *s = PVSCSI(pci_dev); 1104 1105 trace_pvscsi_state("uninit"); 1106 qemu_bh_delete(s->completion_worker); 1107 1108 pvscsi_cleanup_msi(s); 1109 } 1110 1111 static void 1112 pvscsi_reset(DeviceState *dev) 1113 { 1114 PCIDevice *d = PCI_DEVICE(dev); 1115 PVSCSIState *s = PVSCSI(d); 1116 1117 trace_pvscsi_state("reset"); 1118 pvscsi_reset_adapter(s); 1119 } 1120 1121 static void 1122 pvscsi_pre_save(void *opaque) 1123 { 1124 PVSCSIState *s = (PVSCSIState *) opaque; 1125 1126 trace_pvscsi_state("presave"); 1127 1128 assert(QTAILQ_EMPTY(&s->pending_queue)); 1129 assert(QTAILQ_EMPTY(&s->completion_queue)); 1130 } 1131 1132 static int 1133 pvscsi_post_load(void *opaque, int version_id) 1134 { 1135 trace_pvscsi_state("postload"); 1136 return 0; 1137 } 1138 1139 static const VMStateDescription vmstate_pvscsi = { 1140 .name = "pvscsi", 1141 .version_id = 0, 1142 .minimum_version_id = 0, 1143 .pre_save = pvscsi_pre_save, 1144 .post_load = pvscsi_post_load, 1145 .fields = (VMStateField[]) { 1146 VMSTATE_PCI_DEVICE(parent_obj, PVSCSIState), 1147 VMSTATE_UINT8(msi_used, PVSCSIState), 1148 VMSTATE_UINT32(resetting, PVSCSIState), 1149 VMSTATE_UINT64(reg_interrupt_status, PVSCSIState), 1150 VMSTATE_UINT64(reg_interrupt_enabled, PVSCSIState), 1151 VMSTATE_UINT64(reg_command_status, PVSCSIState), 1152 VMSTATE_UINT64(curr_cmd, PVSCSIState), 1153 VMSTATE_UINT32(curr_cmd_data_cntr, PVSCSIState), 1154 VMSTATE_UINT32_ARRAY(curr_cmd_data, PVSCSIState, 1155 ARRAY_SIZE(((PVSCSIState *)NULL)->curr_cmd_data)), 1156 VMSTATE_UINT8(rings_info_valid, PVSCSIState), 1157 VMSTATE_UINT8(msg_ring_info_valid, PVSCSIState), 1158 VMSTATE_UINT8(use_msg, PVSCSIState), 1159 1160 VMSTATE_UINT64(rings.rs_pa, PVSCSIState), 1161 VMSTATE_UINT32(rings.txr_len_mask, PVSCSIState), 1162 VMSTATE_UINT32(rings.rxr_len_mask, PVSCSIState), 1163 VMSTATE_UINT64_ARRAY(rings.req_ring_pages_pa, PVSCSIState, 1164 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES), 1165 VMSTATE_UINT64_ARRAY(rings.cmp_ring_pages_pa, PVSCSIState, 1166 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES), 1167 VMSTATE_UINT64(rings.consumed_ptr, PVSCSIState), 1168 VMSTATE_UINT64(rings.filled_cmp_ptr, PVSCSIState), 1169 1170 VMSTATE_END_OF_LIST() 1171 } 1172 }; 1173 1174 static void 1175 pvscsi_write_config(PCIDevice *pci, uint32_t addr, uint32_t val, int len) 1176 { 1177 pci_default_write_config(pci, addr, val, len); 1178 msi_write_config(pci, addr, val, len); 1179 } 1180 1181 static Property pvscsi_properties[] = { 1182 DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1), 1183 DEFINE_PROP_END_OF_LIST(), 1184 }; 1185 1186 static void pvscsi_class_init(ObjectClass *klass, void *data) 1187 { 1188 DeviceClass *dc = DEVICE_CLASS(klass); 1189 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1190 1191 k->init = pvscsi_init; 1192 k->exit = pvscsi_uninit; 1193 k->vendor_id = PCI_VENDOR_ID_VMWARE; 1194 k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI; 1195 k->class_id = PCI_CLASS_STORAGE_SCSI; 1196 k->subsystem_id = 0x1000; 1197 dc->reset = pvscsi_reset; 1198 dc->vmsd = &vmstate_pvscsi; 1199 dc->props = pvscsi_properties; 1200 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1201 k->config_write = pvscsi_write_config; 1202 } 1203 1204 static const TypeInfo pvscsi_info = { 1205 .name = TYPE_PVSCSI, 1206 .parent = TYPE_PCI_DEVICE, 1207 .instance_size = sizeof(PVSCSIState), 1208 .class_init = pvscsi_class_init, 1209 }; 1210 1211 static void 1212 pvscsi_register_types(void) 1213 { 1214 type_register_static(&pvscsi_info); 1215 } 1216 1217 type_init(pvscsi_register_types); 1218