1881d588aSDmitry Fleytman /* 2881d588aSDmitry Fleytman * QEMU VMWARE PVSCSI paravirtual SCSI bus 3881d588aSDmitry Fleytman * 4881d588aSDmitry Fleytman * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com) 5881d588aSDmitry Fleytman * 6881d588aSDmitry Fleytman * Developed by Daynix Computing LTD (http://www.daynix.com) 7881d588aSDmitry Fleytman * 8881d588aSDmitry Fleytman * Based on implementation by Paolo Bonzini 9881d588aSDmitry Fleytman * http://lists.gnu.org/archive/html/qemu-devel/2011-08/msg00729.html 10881d588aSDmitry Fleytman * 11881d588aSDmitry Fleytman * Authors: 12881d588aSDmitry Fleytman * Paolo Bonzini <pbonzini@redhat.com> 13881d588aSDmitry Fleytman * Dmitry Fleytman <dmitry@daynix.com> 14881d588aSDmitry Fleytman * Yan Vugenfirer <yan@daynix.com> 15881d588aSDmitry Fleytman * 16881d588aSDmitry Fleytman * This work is licensed under the terms of the GNU GPL, version 2. 17881d588aSDmitry Fleytman * See the COPYING file in the top-level directory. 18881d588aSDmitry Fleytman * 19881d588aSDmitry Fleytman * NOTE about MSI-X: 20881d588aSDmitry Fleytman * MSI-X support has been removed for the moment because it leads Windows OS 21881d588aSDmitry Fleytman * to crash on startup. The crash happens because Windows driver requires 22881d588aSDmitry Fleytman * MSI-X shared memory to be part of the same BAR used for rings state 23881d588aSDmitry Fleytman * registers, etc. This is not supported by QEMU infrastructure so separate 24881d588aSDmitry Fleytman * BAR created from MSI-X purposes. Windows driver fails to deal with 2 BARs. 25881d588aSDmitry Fleytman * 26881d588aSDmitry Fleytman */ 27881d588aSDmitry Fleytman 28881d588aSDmitry Fleytman #include "hw/scsi/scsi.h" 29881d588aSDmitry Fleytman #include <block/scsi.h> 30881d588aSDmitry Fleytman #include "hw/pci/msi.h" 31881d588aSDmitry Fleytman #include "vmw_pvscsi.h" 32881d588aSDmitry Fleytman #include "trace.h" 33881d588aSDmitry Fleytman 34881d588aSDmitry Fleytman 35881d588aSDmitry Fleytman #define PVSCSI_MSI_OFFSET (0x50) 36881d588aSDmitry Fleytman #define PVSCSI_USE_64BIT (true) 37881d588aSDmitry Fleytman #define PVSCSI_PER_VECTOR_MASK (false) 38881d588aSDmitry Fleytman 39881d588aSDmitry Fleytman #define PVSCSI_MAX_DEVS (64) 40881d588aSDmitry Fleytman #define PVSCSI_MSIX_NUM_VECTORS (1) 41881d588aSDmitry Fleytman 42881d588aSDmitry Fleytman #define PVSCSI_MAX_CMD_DATA_WORDS \ 43881d588aSDmitry Fleytman (sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t)) 44881d588aSDmitry Fleytman 45881d588aSDmitry Fleytman #define RS_GET_FIELD(rs_pa, field) \ 46881d588aSDmitry Fleytman (ldl_le_phys(rs_pa + offsetof(struct PVSCSIRingsState, field))) 47881d588aSDmitry Fleytman #define RS_SET_FIELD(rs_pa, field, val) \ 48881d588aSDmitry Fleytman (stl_le_phys(rs_pa + offsetof(struct PVSCSIRingsState, field), val)) 49881d588aSDmitry Fleytman 50881d588aSDmitry Fleytman #define TYPE_PVSCSI "pvscsi" 51881d588aSDmitry Fleytman #define PVSCSI(obj) OBJECT_CHECK(PVSCSIState, (obj), TYPE_PVSCSI) 52881d588aSDmitry Fleytman 53881d588aSDmitry Fleytman typedef struct PVSCSIRingInfo { 54881d588aSDmitry Fleytman uint64_t rs_pa; 55881d588aSDmitry Fleytman uint32_t txr_len_mask; 56881d588aSDmitry Fleytman uint32_t rxr_len_mask; 57881d588aSDmitry Fleytman uint32_t msg_len_mask; 58881d588aSDmitry Fleytman uint64_t req_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES]; 59881d588aSDmitry Fleytman uint64_t cmp_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES]; 60881d588aSDmitry Fleytman uint64_t msg_ring_pages_pa[PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES]; 61881d588aSDmitry Fleytman uint64_t consumed_ptr; 62881d588aSDmitry Fleytman uint64_t filled_cmp_ptr; 63881d588aSDmitry Fleytman uint64_t filled_msg_ptr; 64881d588aSDmitry Fleytman } PVSCSIRingInfo; 65881d588aSDmitry Fleytman 66881d588aSDmitry Fleytman typedef struct PVSCSISGState { 67881d588aSDmitry Fleytman hwaddr elemAddr; 68881d588aSDmitry Fleytman hwaddr dataAddr; 69881d588aSDmitry Fleytman uint32_t resid; 70881d588aSDmitry Fleytman } PVSCSISGState; 71881d588aSDmitry Fleytman 72881d588aSDmitry Fleytman typedef QTAILQ_HEAD(, PVSCSIRequest) PVSCSIRequestList; 73881d588aSDmitry Fleytman 74881d588aSDmitry Fleytman typedef struct { 75881d588aSDmitry Fleytman PCIDevice parent_obj; 76881d588aSDmitry Fleytman MemoryRegion io_space; 77881d588aSDmitry Fleytman SCSIBus bus; 78881d588aSDmitry Fleytman QEMUBH *completion_worker; 79881d588aSDmitry Fleytman PVSCSIRequestList pending_queue; 80881d588aSDmitry Fleytman PVSCSIRequestList completion_queue; 81881d588aSDmitry Fleytman 82881d588aSDmitry Fleytman uint64_t reg_interrupt_status; /* Interrupt status register value */ 83881d588aSDmitry Fleytman uint64_t reg_interrupt_enabled; /* Interrupt mask register value */ 84881d588aSDmitry Fleytman uint64_t reg_command_status; /* Command status register value */ 85881d588aSDmitry Fleytman 86881d588aSDmitry Fleytman /* Command data adoption mechanism */ 87881d588aSDmitry Fleytman uint64_t curr_cmd; /* Last command arrived */ 88881d588aSDmitry Fleytman uint32_t curr_cmd_data_cntr; /* Amount of data for last command */ 89881d588aSDmitry Fleytman 90881d588aSDmitry Fleytman /* Collector for current command data */ 91881d588aSDmitry Fleytman uint32_t curr_cmd_data[PVSCSI_MAX_CMD_DATA_WORDS]; 92881d588aSDmitry Fleytman 93881d588aSDmitry Fleytman uint8_t rings_info_valid; /* Whether data rings initialized */ 94881d588aSDmitry Fleytman uint8_t msg_ring_info_valid; /* Whether message ring initialized */ 95881d588aSDmitry Fleytman uint8_t use_msg; /* Whether to use message ring */ 96881d588aSDmitry Fleytman 97881d588aSDmitry Fleytman uint8_t msi_used; /* Whether MSI support was installed successfully */ 98881d588aSDmitry Fleytman 99881d588aSDmitry Fleytman PVSCSIRingInfo rings; /* Data transfer rings manager */ 100881d588aSDmitry Fleytman uint32_t resetting; /* Reset in progress */ 101881d588aSDmitry Fleytman } PVSCSIState; 102881d588aSDmitry Fleytman 103881d588aSDmitry Fleytman typedef struct PVSCSIRequest { 104881d588aSDmitry Fleytman SCSIRequest *sreq; 105881d588aSDmitry Fleytman PVSCSIState *dev; 106881d588aSDmitry Fleytman uint8_t sense_key; 107881d588aSDmitry Fleytman uint8_t completed; 108881d588aSDmitry Fleytman int lun; 109881d588aSDmitry Fleytman QEMUSGList sgl; 110881d588aSDmitry Fleytman PVSCSISGState sg; 111881d588aSDmitry Fleytman struct PVSCSIRingReqDesc req; 112881d588aSDmitry Fleytman struct PVSCSIRingCmpDesc cmp; 113881d588aSDmitry Fleytman QTAILQ_ENTRY(PVSCSIRequest) next; 114881d588aSDmitry Fleytman } PVSCSIRequest; 115881d588aSDmitry Fleytman 116881d588aSDmitry Fleytman /* Integer binary logarithm */ 117881d588aSDmitry Fleytman static int 118881d588aSDmitry Fleytman pvscsi_log2(uint32_t input) 119881d588aSDmitry Fleytman { 120881d588aSDmitry Fleytman int log = 0; 121881d588aSDmitry Fleytman assert(input > 0); 122881d588aSDmitry Fleytman while (input >> ++log) { 123881d588aSDmitry Fleytman } 124881d588aSDmitry Fleytman return log; 125881d588aSDmitry Fleytman } 126881d588aSDmitry Fleytman 127881d588aSDmitry Fleytman static void 128881d588aSDmitry Fleytman pvscsi_ring_init_data(PVSCSIRingInfo *m, PVSCSICmdDescSetupRings *ri) 129881d588aSDmitry Fleytman { 130881d588aSDmitry Fleytman int i; 131881d588aSDmitry Fleytman uint32_t txr_len_log2, rxr_len_log2; 132881d588aSDmitry Fleytman uint32_t req_ring_size, cmp_ring_size; 133881d588aSDmitry Fleytman m->rs_pa = ri->ringsStatePPN << VMW_PAGE_SHIFT; 134881d588aSDmitry Fleytman 135881d588aSDmitry Fleytman req_ring_size = ri->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; 136881d588aSDmitry Fleytman cmp_ring_size = ri->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE; 137881d588aSDmitry Fleytman txr_len_log2 = pvscsi_log2(req_ring_size - 1); 138881d588aSDmitry Fleytman rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1); 139881d588aSDmitry Fleytman 140881d588aSDmitry Fleytman m->txr_len_mask = MASK(txr_len_log2); 141881d588aSDmitry Fleytman m->rxr_len_mask = MASK(rxr_len_log2); 142881d588aSDmitry Fleytman 143881d588aSDmitry Fleytman m->consumed_ptr = 0; 144881d588aSDmitry Fleytman m->filled_cmp_ptr = 0; 145881d588aSDmitry Fleytman 146881d588aSDmitry Fleytman for (i = 0; i < ri->reqRingNumPages; i++) { 147881d588aSDmitry Fleytman m->req_ring_pages_pa[i] = ri->reqRingPPNs[i] << VMW_PAGE_SHIFT; 148881d588aSDmitry Fleytman } 149881d588aSDmitry Fleytman 150881d588aSDmitry Fleytman for (i = 0; i < ri->cmpRingNumPages; i++) { 151881d588aSDmitry Fleytman m->cmp_ring_pages_pa[i] = ri->cmpRingPPNs[i] << VMW_PAGE_SHIFT; 152881d588aSDmitry Fleytman } 153881d588aSDmitry Fleytman 154881d588aSDmitry Fleytman RS_SET_FIELD(m->rs_pa, reqProdIdx, 0); 155881d588aSDmitry Fleytman RS_SET_FIELD(m->rs_pa, reqConsIdx, 0); 156881d588aSDmitry Fleytman RS_SET_FIELD(m->rs_pa, reqNumEntriesLog2, txr_len_log2); 157881d588aSDmitry Fleytman 158881d588aSDmitry Fleytman RS_SET_FIELD(m->rs_pa, cmpProdIdx, 0); 159881d588aSDmitry Fleytman RS_SET_FIELD(m->rs_pa, cmpConsIdx, 0); 160881d588aSDmitry Fleytman RS_SET_FIELD(m->rs_pa, cmpNumEntriesLog2, rxr_len_log2); 161881d588aSDmitry Fleytman 162881d588aSDmitry Fleytman trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2); 163881d588aSDmitry Fleytman 164881d588aSDmitry Fleytman /* Flush ring state page changes */ 165881d588aSDmitry Fleytman smp_wmb(); 166881d588aSDmitry Fleytman } 167881d588aSDmitry Fleytman 168881d588aSDmitry Fleytman static void 169881d588aSDmitry Fleytman pvscsi_ring_init_msg(PVSCSIRingInfo *m, PVSCSICmdDescSetupMsgRing *ri) 170881d588aSDmitry Fleytman { 171881d588aSDmitry Fleytman int i; 172881d588aSDmitry Fleytman uint32_t len_log2; 173881d588aSDmitry Fleytman uint32_t ring_size; 174881d588aSDmitry Fleytman 175881d588aSDmitry Fleytman ring_size = ri->numPages * PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE; 176881d588aSDmitry Fleytman len_log2 = pvscsi_log2(ring_size - 1); 177881d588aSDmitry Fleytman 178881d588aSDmitry Fleytman m->msg_len_mask = MASK(len_log2); 179881d588aSDmitry Fleytman 180881d588aSDmitry Fleytman m->filled_msg_ptr = 0; 181881d588aSDmitry Fleytman 182881d588aSDmitry Fleytman for (i = 0; i < ri->numPages; i++) { 183881d588aSDmitry Fleytman m->msg_ring_pages_pa[i] = ri->ringPPNs[i] << VMW_PAGE_SHIFT; 184881d588aSDmitry Fleytman } 185881d588aSDmitry Fleytman 186881d588aSDmitry Fleytman RS_SET_FIELD(m->rs_pa, msgProdIdx, 0); 187881d588aSDmitry Fleytman RS_SET_FIELD(m->rs_pa, msgConsIdx, 0); 188881d588aSDmitry Fleytman RS_SET_FIELD(m->rs_pa, msgNumEntriesLog2, len_log2); 189881d588aSDmitry Fleytman 190881d588aSDmitry Fleytman trace_pvscsi_ring_init_msg(len_log2); 191881d588aSDmitry Fleytman 192881d588aSDmitry Fleytman /* Flush ring state page changes */ 193881d588aSDmitry Fleytman smp_wmb(); 194881d588aSDmitry Fleytman } 195881d588aSDmitry Fleytman 196881d588aSDmitry Fleytman static void 197881d588aSDmitry Fleytman pvscsi_ring_cleanup(PVSCSIRingInfo *mgr) 198881d588aSDmitry Fleytman { 199881d588aSDmitry Fleytman mgr->rs_pa = 0; 200881d588aSDmitry Fleytman mgr->txr_len_mask = 0; 201881d588aSDmitry Fleytman mgr->rxr_len_mask = 0; 202881d588aSDmitry Fleytman mgr->msg_len_mask = 0; 203881d588aSDmitry Fleytman mgr->consumed_ptr = 0; 204881d588aSDmitry Fleytman mgr->filled_cmp_ptr = 0; 205881d588aSDmitry Fleytman mgr->filled_msg_ptr = 0; 206881d588aSDmitry Fleytman memset(mgr->req_ring_pages_pa, 0, sizeof(mgr->req_ring_pages_pa)); 207881d588aSDmitry Fleytman memset(mgr->cmp_ring_pages_pa, 0, sizeof(mgr->cmp_ring_pages_pa)); 208881d588aSDmitry Fleytman memset(mgr->msg_ring_pages_pa, 0, sizeof(mgr->msg_ring_pages_pa)); 209881d588aSDmitry Fleytman } 210881d588aSDmitry Fleytman 211881d588aSDmitry Fleytman static hwaddr 212881d588aSDmitry Fleytman pvscsi_ring_pop_req_descr(PVSCSIRingInfo *mgr) 213881d588aSDmitry Fleytman { 214881d588aSDmitry Fleytman uint32_t ready_ptr = RS_GET_FIELD(mgr->rs_pa, reqProdIdx); 215881d588aSDmitry Fleytman 216881d588aSDmitry Fleytman if (ready_ptr != mgr->consumed_ptr) { 217881d588aSDmitry Fleytman uint32_t next_ready_ptr = 218881d588aSDmitry Fleytman mgr->consumed_ptr++ & mgr->txr_len_mask; 219881d588aSDmitry Fleytman uint32_t next_ready_page = 220881d588aSDmitry Fleytman next_ready_ptr / PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; 221881d588aSDmitry Fleytman uint32_t inpage_idx = 222881d588aSDmitry Fleytman next_ready_ptr % PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; 223881d588aSDmitry Fleytman 224881d588aSDmitry Fleytman return mgr->req_ring_pages_pa[next_ready_page] + 225881d588aSDmitry Fleytman inpage_idx * sizeof(PVSCSIRingReqDesc); 226881d588aSDmitry Fleytman } else { 227881d588aSDmitry Fleytman return 0; 228881d588aSDmitry Fleytman } 229881d588aSDmitry Fleytman } 230881d588aSDmitry Fleytman 231881d588aSDmitry Fleytman static void 232881d588aSDmitry Fleytman pvscsi_ring_flush_req(PVSCSIRingInfo *mgr) 233881d588aSDmitry Fleytman { 234881d588aSDmitry Fleytman RS_SET_FIELD(mgr->rs_pa, reqConsIdx, mgr->consumed_ptr); 235881d588aSDmitry Fleytman } 236881d588aSDmitry Fleytman 237881d588aSDmitry Fleytman static hwaddr 238881d588aSDmitry Fleytman pvscsi_ring_pop_cmp_descr(PVSCSIRingInfo *mgr) 239881d588aSDmitry Fleytman { 240881d588aSDmitry Fleytman /* 241881d588aSDmitry Fleytman * According to Linux driver code it explicitly verifies that number 242881d588aSDmitry Fleytman * of requests being processed by device is less then the size of 243881d588aSDmitry Fleytman * completion queue, so device may omit completion queue overflow 244881d588aSDmitry Fleytman * conditions check. We assume that this is true for other (Windows) 245881d588aSDmitry Fleytman * drivers as well. 246881d588aSDmitry Fleytman */ 247881d588aSDmitry Fleytman 248881d588aSDmitry Fleytman uint32_t free_cmp_ptr = 249881d588aSDmitry Fleytman mgr->filled_cmp_ptr++ & mgr->rxr_len_mask; 250881d588aSDmitry Fleytman uint32_t free_cmp_page = 251881d588aSDmitry Fleytman free_cmp_ptr / PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE; 252881d588aSDmitry Fleytman uint32_t inpage_idx = 253881d588aSDmitry Fleytman free_cmp_ptr % PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE; 254881d588aSDmitry Fleytman return mgr->cmp_ring_pages_pa[free_cmp_page] + 255881d588aSDmitry Fleytman inpage_idx * sizeof(PVSCSIRingCmpDesc); 256881d588aSDmitry Fleytman } 257881d588aSDmitry Fleytman 258881d588aSDmitry Fleytman static hwaddr 259881d588aSDmitry Fleytman pvscsi_ring_pop_msg_descr(PVSCSIRingInfo *mgr) 260881d588aSDmitry Fleytman { 261881d588aSDmitry Fleytman uint32_t free_msg_ptr = 262881d588aSDmitry Fleytman mgr->filled_msg_ptr++ & mgr->msg_len_mask; 263881d588aSDmitry Fleytman uint32_t free_msg_page = 264881d588aSDmitry Fleytman free_msg_ptr / PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE; 265881d588aSDmitry Fleytman uint32_t inpage_idx = 266881d588aSDmitry Fleytman free_msg_ptr % PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE; 267881d588aSDmitry Fleytman return mgr->msg_ring_pages_pa[free_msg_page] + 268881d588aSDmitry Fleytman inpage_idx * sizeof(PVSCSIRingMsgDesc); 269881d588aSDmitry Fleytman } 270881d588aSDmitry Fleytman 271881d588aSDmitry Fleytman static void 272881d588aSDmitry Fleytman pvscsi_ring_flush_cmp(PVSCSIRingInfo *mgr) 273881d588aSDmitry Fleytman { 274881d588aSDmitry Fleytman /* Flush descriptor changes */ 275881d588aSDmitry Fleytman smp_wmb(); 276881d588aSDmitry Fleytman 277881d588aSDmitry Fleytman trace_pvscsi_ring_flush_cmp(mgr->filled_cmp_ptr); 278881d588aSDmitry Fleytman 279881d588aSDmitry Fleytman RS_SET_FIELD(mgr->rs_pa, cmpProdIdx, mgr->filled_cmp_ptr); 280881d588aSDmitry Fleytman } 281881d588aSDmitry Fleytman 282881d588aSDmitry Fleytman static bool 283881d588aSDmitry Fleytman pvscsi_ring_msg_has_room(PVSCSIRingInfo *mgr) 284881d588aSDmitry Fleytman { 285881d588aSDmitry Fleytman uint32_t prodIdx = RS_GET_FIELD(mgr->rs_pa, msgProdIdx); 286881d588aSDmitry Fleytman uint32_t consIdx = RS_GET_FIELD(mgr->rs_pa, msgConsIdx); 287881d588aSDmitry Fleytman 288881d588aSDmitry Fleytman return (prodIdx - consIdx) < (mgr->msg_len_mask + 1); 289881d588aSDmitry Fleytman } 290881d588aSDmitry Fleytman 291881d588aSDmitry Fleytman static void 292881d588aSDmitry Fleytman pvscsi_ring_flush_msg(PVSCSIRingInfo *mgr) 293881d588aSDmitry Fleytman { 294881d588aSDmitry Fleytman /* Flush descriptor changes */ 295881d588aSDmitry Fleytman smp_wmb(); 296881d588aSDmitry Fleytman 297881d588aSDmitry Fleytman trace_pvscsi_ring_flush_msg(mgr->filled_msg_ptr); 298881d588aSDmitry Fleytman 299881d588aSDmitry Fleytman RS_SET_FIELD(mgr->rs_pa, msgProdIdx, mgr->filled_msg_ptr); 300881d588aSDmitry Fleytman } 301881d588aSDmitry Fleytman 302881d588aSDmitry Fleytman static void 303881d588aSDmitry Fleytman pvscsi_reset_state(PVSCSIState *s) 304881d588aSDmitry Fleytman { 305881d588aSDmitry Fleytman s->curr_cmd = PVSCSI_CMD_FIRST; 306881d588aSDmitry Fleytman s->curr_cmd_data_cntr = 0; 307881d588aSDmitry Fleytman s->reg_command_status = PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 308881d588aSDmitry Fleytman s->reg_interrupt_status = 0; 309881d588aSDmitry Fleytman pvscsi_ring_cleanup(&s->rings); 310881d588aSDmitry Fleytman s->rings_info_valid = FALSE; 311881d588aSDmitry Fleytman s->msg_ring_info_valid = FALSE; 312881d588aSDmitry Fleytman QTAILQ_INIT(&s->pending_queue); 313881d588aSDmitry Fleytman QTAILQ_INIT(&s->completion_queue); 314881d588aSDmitry Fleytman } 315881d588aSDmitry Fleytman 316881d588aSDmitry Fleytman static void 317881d588aSDmitry Fleytman pvscsi_update_irq_status(PVSCSIState *s) 318881d588aSDmitry Fleytman { 319881d588aSDmitry Fleytman PCIDevice *d = PCI_DEVICE(s); 320881d588aSDmitry Fleytman bool should_raise = s->reg_interrupt_enabled & s->reg_interrupt_status; 321881d588aSDmitry Fleytman 322881d588aSDmitry Fleytman trace_pvscsi_update_irq_level(should_raise, s->reg_interrupt_enabled, 323881d588aSDmitry Fleytman s->reg_interrupt_status); 324881d588aSDmitry Fleytman 325881d588aSDmitry Fleytman if (s->msi_used && msi_enabled(d)) { 326881d588aSDmitry Fleytman if (should_raise) { 327881d588aSDmitry Fleytman trace_pvscsi_update_irq_msi(); 328881d588aSDmitry Fleytman msi_notify(d, PVSCSI_VECTOR_COMPLETION); 329881d588aSDmitry Fleytman } 330881d588aSDmitry Fleytman return; 331881d588aSDmitry Fleytman } 332881d588aSDmitry Fleytman 333881d588aSDmitry Fleytman qemu_set_irq(d->irq[0], !!should_raise); 334881d588aSDmitry Fleytman } 335881d588aSDmitry Fleytman 336881d588aSDmitry Fleytman static void 337881d588aSDmitry Fleytman pvscsi_raise_completion_interrupt(PVSCSIState *s) 338881d588aSDmitry Fleytman { 339881d588aSDmitry Fleytman s->reg_interrupt_status |= PVSCSI_INTR_CMPL_0; 340881d588aSDmitry Fleytman 341881d588aSDmitry Fleytman /* Memory barrier to flush interrupt status register changes*/ 342881d588aSDmitry Fleytman smp_wmb(); 343881d588aSDmitry Fleytman 344881d588aSDmitry Fleytman pvscsi_update_irq_status(s); 345881d588aSDmitry Fleytman } 346881d588aSDmitry Fleytman 347881d588aSDmitry Fleytman static void 348881d588aSDmitry Fleytman pvscsi_raise_message_interrupt(PVSCSIState *s) 349881d588aSDmitry Fleytman { 350881d588aSDmitry Fleytman s->reg_interrupt_status |= PVSCSI_INTR_MSG_0; 351881d588aSDmitry Fleytman 352881d588aSDmitry Fleytman /* Memory barrier to flush interrupt status register changes*/ 353881d588aSDmitry Fleytman smp_wmb(); 354881d588aSDmitry Fleytman 355881d588aSDmitry Fleytman pvscsi_update_irq_status(s); 356881d588aSDmitry Fleytman } 357881d588aSDmitry Fleytman 358881d588aSDmitry Fleytman static void 359881d588aSDmitry Fleytman pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCmpDesc *cmp_desc) 360881d588aSDmitry Fleytman { 361881d588aSDmitry Fleytman hwaddr cmp_descr_pa; 362881d588aSDmitry Fleytman 363881d588aSDmitry Fleytman cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings); 364881d588aSDmitry Fleytman trace_pvscsi_cmp_ring_put(cmp_descr_pa); 365881d588aSDmitry Fleytman cpu_physical_memory_write(cmp_descr_pa, (void *)cmp_desc, 366881d588aSDmitry Fleytman sizeof(*cmp_desc)); 367881d588aSDmitry Fleytman } 368881d588aSDmitry Fleytman 369881d588aSDmitry Fleytman static void 370881d588aSDmitry Fleytman pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMsgDesc *msg_desc) 371881d588aSDmitry Fleytman { 372881d588aSDmitry Fleytman hwaddr msg_descr_pa; 373881d588aSDmitry Fleytman 374881d588aSDmitry Fleytman msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings); 375881d588aSDmitry Fleytman trace_pvscsi_msg_ring_put(msg_descr_pa); 376881d588aSDmitry Fleytman cpu_physical_memory_write(msg_descr_pa, (void *)msg_desc, 377881d588aSDmitry Fleytman sizeof(*msg_desc)); 378881d588aSDmitry Fleytman } 379881d588aSDmitry Fleytman 380881d588aSDmitry Fleytman static void 381881d588aSDmitry Fleytman pvscsi_process_completion_queue(void *opaque) 382881d588aSDmitry Fleytman { 383881d588aSDmitry Fleytman PVSCSIState *s = opaque; 384881d588aSDmitry Fleytman PVSCSIRequest *pvscsi_req; 385881d588aSDmitry Fleytman bool has_completed = false; 386881d588aSDmitry Fleytman 387881d588aSDmitry Fleytman while (!QTAILQ_EMPTY(&s->completion_queue)) { 388881d588aSDmitry Fleytman pvscsi_req = QTAILQ_FIRST(&s->completion_queue); 389881d588aSDmitry Fleytman QTAILQ_REMOVE(&s->completion_queue, pvscsi_req, next); 390881d588aSDmitry Fleytman pvscsi_cmp_ring_put(s, &pvscsi_req->cmp); 391881d588aSDmitry Fleytman g_free(pvscsi_req); 392dcb07809SStefan Weil has_completed = true; 393881d588aSDmitry Fleytman } 394881d588aSDmitry Fleytman 395881d588aSDmitry Fleytman if (has_completed) { 396881d588aSDmitry Fleytman pvscsi_ring_flush_cmp(&s->rings); 397881d588aSDmitry Fleytman pvscsi_raise_completion_interrupt(s); 398881d588aSDmitry Fleytman } 399881d588aSDmitry Fleytman } 400881d588aSDmitry Fleytman 401881d588aSDmitry Fleytman static void 402881d588aSDmitry Fleytman pvscsi_reset_adapter(PVSCSIState *s) 403881d588aSDmitry Fleytman { 404881d588aSDmitry Fleytman s->resetting++; 405881d588aSDmitry Fleytman qbus_reset_all_fn(&s->bus); 406881d588aSDmitry Fleytman s->resetting--; 407881d588aSDmitry Fleytman pvscsi_process_completion_queue(s); 408881d588aSDmitry Fleytman assert(QTAILQ_EMPTY(&s->pending_queue)); 409881d588aSDmitry Fleytman pvscsi_reset_state(s); 410881d588aSDmitry Fleytman } 411881d588aSDmitry Fleytman 412881d588aSDmitry Fleytman static void 413881d588aSDmitry Fleytman pvscsi_schedule_completion_processing(PVSCSIState *s) 414881d588aSDmitry Fleytman { 415881d588aSDmitry Fleytman /* Try putting more complete requests on the ring. */ 416881d588aSDmitry Fleytman if (!QTAILQ_EMPTY(&s->completion_queue)) { 417881d588aSDmitry Fleytman qemu_bh_schedule(s->completion_worker); 418881d588aSDmitry Fleytman } 419881d588aSDmitry Fleytman } 420881d588aSDmitry Fleytman 421881d588aSDmitry Fleytman static void 422881d588aSDmitry Fleytman pvscsi_complete_request(PVSCSIState *s, PVSCSIRequest *r) 423881d588aSDmitry Fleytman { 424881d588aSDmitry Fleytman assert(!r->completed); 425881d588aSDmitry Fleytman 426881d588aSDmitry Fleytman trace_pvscsi_complete_request(r->cmp.context, r->cmp.dataLen, 427881d588aSDmitry Fleytman r->sense_key); 428881d588aSDmitry Fleytman if (r->sreq != NULL) { 429881d588aSDmitry Fleytman scsi_req_unref(r->sreq); 430881d588aSDmitry Fleytman r->sreq = NULL; 431881d588aSDmitry Fleytman } 432881d588aSDmitry Fleytman r->completed = 1; 433881d588aSDmitry Fleytman QTAILQ_REMOVE(&s->pending_queue, r, next); 434881d588aSDmitry Fleytman QTAILQ_INSERT_TAIL(&s->completion_queue, r, next); 435881d588aSDmitry Fleytman pvscsi_schedule_completion_processing(s); 436881d588aSDmitry Fleytman } 437881d588aSDmitry Fleytman 438881d588aSDmitry Fleytman static QEMUSGList *pvscsi_get_sg_list(SCSIRequest *r) 439881d588aSDmitry Fleytman { 440881d588aSDmitry Fleytman PVSCSIRequest *req = r->hba_private; 441881d588aSDmitry Fleytman 442881d588aSDmitry Fleytman trace_pvscsi_get_sg_list(req->sgl.nsg, req->sgl.size); 443881d588aSDmitry Fleytman 444881d588aSDmitry Fleytman return &req->sgl; 445881d588aSDmitry Fleytman } 446881d588aSDmitry Fleytman 447881d588aSDmitry Fleytman static void 448881d588aSDmitry Fleytman pvscsi_get_next_sg_elem(PVSCSISGState *sg) 449881d588aSDmitry Fleytman { 450881d588aSDmitry Fleytman struct PVSCSISGElement elem; 451881d588aSDmitry Fleytman 452881d588aSDmitry Fleytman cpu_physical_memory_read(sg->elemAddr, (void *)&elem, sizeof(elem)); 453881d588aSDmitry Fleytman if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) != 0) { 454881d588aSDmitry Fleytman /* 455881d588aSDmitry Fleytman * There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in 456881d588aSDmitry Fleytman * header file but its value is unknown. This flag requires 457881d588aSDmitry Fleytman * additional processing, so we put warning here to catch it 458881d588aSDmitry Fleytman * some day and make proper implementation 459881d588aSDmitry Fleytman */ 460881d588aSDmitry Fleytman trace_pvscsi_get_next_sg_elem(elem.flags); 461881d588aSDmitry Fleytman } 462881d588aSDmitry Fleytman 463881d588aSDmitry Fleytman sg->elemAddr += sizeof(elem); 464881d588aSDmitry Fleytman sg->dataAddr = elem.addr; 465881d588aSDmitry Fleytman sg->resid = elem.length; 466881d588aSDmitry Fleytman } 467881d588aSDmitry Fleytman 468881d588aSDmitry Fleytman static void 469881d588aSDmitry Fleytman pvscsi_write_sense(PVSCSIRequest *r, uint8_t *sense, int len) 470881d588aSDmitry Fleytman { 471881d588aSDmitry Fleytman r->cmp.senseLen = MIN(r->req.senseLen, len); 472881d588aSDmitry Fleytman r->sense_key = sense[(sense[0] & 2) ? 1 : 2]; 473881d588aSDmitry Fleytman cpu_physical_memory_write(r->req.senseAddr, sense, r->cmp.senseLen); 474881d588aSDmitry Fleytman } 475881d588aSDmitry Fleytman 476881d588aSDmitry Fleytman static void 477881d588aSDmitry Fleytman pvscsi_command_complete(SCSIRequest *req, uint32_t status, size_t resid) 478881d588aSDmitry Fleytman { 479881d588aSDmitry Fleytman PVSCSIRequest *pvscsi_req = req->hba_private; 480881d588aSDmitry Fleytman PVSCSIState *s = pvscsi_req->dev; 481881d588aSDmitry Fleytman 482881d588aSDmitry Fleytman if (!pvscsi_req) { 483881d588aSDmitry Fleytman trace_pvscsi_command_complete_not_found(req->tag); 484881d588aSDmitry Fleytman return; 485881d588aSDmitry Fleytman } 486881d588aSDmitry Fleytman 487881d588aSDmitry Fleytman if (resid) { 488881d588aSDmitry Fleytman /* Short transfer. */ 489881d588aSDmitry Fleytman trace_pvscsi_command_complete_data_run(); 490881d588aSDmitry Fleytman pvscsi_req->cmp.hostStatus = BTSTAT_DATARUN; 491881d588aSDmitry Fleytman } 492881d588aSDmitry Fleytman 493881d588aSDmitry Fleytman pvscsi_req->cmp.scsiStatus = status; 494881d588aSDmitry Fleytman if (pvscsi_req->cmp.scsiStatus == CHECK_CONDITION) { 495881d588aSDmitry Fleytman uint8_t sense[SCSI_SENSE_BUF_SIZE]; 496881d588aSDmitry Fleytman int sense_len = 497881d588aSDmitry Fleytman scsi_req_get_sense(pvscsi_req->sreq, sense, sizeof(sense)); 498881d588aSDmitry Fleytman 499881d588aSDmitry Fleytman trace_pvscsi_command_complete_sense_len(sense_len); 500881d588aSDmitry Fleytman pvscsi_write_sense(pvscsi_req, sense, sense_len); 501881d588aSDmitry Fleytman } 502881d588aSDmitry Fleytman qemu_sglist_destroy(&pvscsi_req->sgl); 503881d588aSDmitry Fleytman pvscsi_complete_request(s, pvscsi_req); 504881d588aSDmitry Fleytman } 505881d588aSDmitry Fleytman 506881d588aSDmitry Fleytman static void 507881d588aSDmitry Fleytman pvscsi_send_msg(PVSCSIState *s, SCSIDevice *dev, uint32_t msg_type) 508881d588aSDmitry Fleytman { 509881d588aSDmitry Fleytman if (s->msg_ring_info_valid && pvscsi_ring_msg_has_room(&s->rings)) { 510881d588aSDmitry Fleytman PVSCSIMsgDescDevStatusChanged msg = {0}; 511881d588aSDmitry Fleytman 512881d588aSDmitry Fleytman msg.type = msg_type; 513881d588aSDmitry Fleytman msg.bus = dev->channel; 514881d588aSDmitry Fleytman msg.target = dev->id; 515881d588aSDmitry Fleytman msg.lun[1] = dev->lun; 516881d588aSDmitry Fleytman 517881d588aSDmitry Fleytman pvscsi_msg_ring_put(s, (PVSCSIRingMsgDesc *)&msg); 518881d588aSDmitry Fleytman pvscsi_ring_flush_msg(&s->rings); 519881d588aSDmitry Fleytman pvscsi_raise_message_interrupt(s); 520881d588aSDmitry Fleytman } 521881d588aSDmitry Fleytman } 522881d588aSDmitry Fleytman 523881d588aSDmitry Fleytman static void 524881d588aSDmitry Fleytman pvscsi_hotplug(SCSIBus *bus, SCSIDevice *dev) 525881d588aSDmitry Fleytman { 526881d588aSDmitry Fleytman PVSCSIState *s = container_of(bus, PVSCSIState, bus); 527881d588aSDmitry Fleytman pvscsi_send_msg(s, dev, PVSCSI_MSG_DEV_ADDED); 528881d588aSDmitry Fleytman } 529881d588aSDmitry Fleytman 530881d588aSDmitry Fleytman static void 531881d588aSDmitry Fleytman pvscsi_hot_unplug(SCSIBus *bus, SCSIDevice *dev) 532881d588aSDmitry Fleytman { 533881d588aSDmitry Fleytman PVSCSIState *s = container_of(bus, PVSCSIState, bus); 534881d588aSDmitry Fleytman pvscsi_send_msg(s, dev, PVSCSI_MSG_DEV_REMOVED); 535881d588aSDmitry Fleytman } 536881d588aSDmitry Fleytman 537881d588aSDmitry Fleytman static void 538881d588aSDmitry Fleytman pvscsi_request_cancelled(SCSIRequest *req) 539881d588aSDmitry Fleytman { 540881d588aSDmitry Fleytman PVSCSIRequest *pvscsi_req = req->hba_private; 541881d588aSDmitry Fleytman PVSCSIState *s = pvscsi_req->dev; 542881d588aSDmitry Fleytman 543881d588aSDmitry Fleytman if (pvscsi_req->completed) { 544881d588aSDmitry Fleytman return; 545881d588aSDmitry Fleytman } 546881d588aSDmitry Fleytman 547881d588aSDmitry Fleytman if (pvscsi_req->dev->resetting) { 548881d588aSDmitry Fleytman pvscsi_req->cmp.hostStatus = BTSTAT_BUSRESET; 549881d588aSDmitry Fleytman } else { 550881d588aSDmitry Fleytman pvscsi_req->cmp.hostStatus = BTSTAT_ABORTQUEUE; 551881d588aSDmitry Fleytman } 552881d588aSDmitry Fleytman 553881d588aSDmitry Fleytman pvscsi_complete_request(s, pvscsi_req); 554881d588aSDmitry Fleytman } 555881d588aSDmitry Fleytman 556881d588aSDmitry Fleytman static SCSIDevice* 557881d588aSDmitry Fleytman pvscsi_device_find(PVSCSIState *s, int channel, int target, 558881d588aSDmitry Fleytman uint8_t *requested_lun, uint8_t *target_lun) 559881d588aSDmitry Fleytman { 560881d588aSDmitry Fleytman if (requested_lun[0] || requested_lun[2] || requested_lun[3] || 561881d588aSDmitry Fleytman requested_lun[4] || requested_lun[5] || requested_lun[6] || 562881d588aSDmitry Fleytman requested_lun[7] || (target > PVSCSI_MAX_DEVS)) { 563881d588aSDmitry Fleytman return NULL; 564881d588aSDmitry Fleytman } else { 565881d588aSDmitry Fleytman *target_lun = requested_lun[1]; 566881d588aSDmitry Fleytman return scsi_device_find(&s->bus, channel, target, *target_lun); 567881d588aSDmitry Fleytman } 568881d588aSDmitry Fleytman } 569881d588aSDmitry Fleytman 570881d588aSDmitry Fleytman static PVSCSIRequest * 571881d588aSDmitry Fleytman pvscsi_queue_pending_descriptor(PVSCSIState *s, SCSIDevice **d, 572881d588aSDmitry Fleytman struct PVSCSIRingReqDesc *descr) 573881d588aSDmitry Fleytman { 574881d588aSDmitry Fleytman PVSCSIRequest *pvscsi_req; 575881d588aSDmitry Fleytman uint8_t lun; 576881d588aSDmitry Fleytman 577881d588aSDmitry Fleytman pvscsi_req = g_malloc0(sizeof(*pvscsi_req)); 578881d588aSDmitry Fleytman pvscsi_req->dev = s; 579881d588aSDmitry Fleytman pvscsi_req->req = *descr; 580881d588aSDmitry Fleytman pvscsi_req->cmp.context = pvscsi_req->req.context; 581881d588aSDmitry Fleytman QTAILQ_INSERT_TAIL(&s->pending_queue, pvscsi_req, next); 582881d588aSDmitry Fleytman 583881d588aSDmitry Fleytman *d = pvscsi_device_find(s, descr->bus, descr->target, descr->lun, &lun); 584881d588aSDmitry Fleytman if (*d) { 585881d588aSDmitry Fleytman pvscsi_req->lun = lun; 586881d588aSDmitry Fleytman } 587881d588aSDmitry Fleytman 588881d588aSDmitry Fleytman return pvscsi_req; 589881d588aSDmitry Fleytman } 590881d588aSDmitry Fleytman 591881d588aSDmitry Fleytman static void 592881d588aSDmitry Fleytman pvscsi_convert_sglist(PVSCSIRequest *r) 593881d588aSDmitry Fleytman { 594881d588aSDmitry Fleytman int chunk_size; 595881d588aSDmitry Fleytman uint64_t data_length = r->req.dataLen; 596881d588aSDmitry Fleytman PVSCSISGState sg = r->sg; 597881d588aSDmitry Fleytman while (data_length) { 598881d588aSDmitry Fleytman while (!sg.resid) { 599881d588aSDmitry Fleytman pvscsi_get_next_sg_elem(&sg); 600881d588aSDmitry Fleytman trace_pvscsi_convert_sglist(r->req.context, r->sg.dataAddr, 601881d588aSDmitry Fleytman r->sg.resid); 602881d588aSDmitry Fleytman } 603881d588aSDmitry Fleytman assert(data_length > 0); 604881d588aSDmitry Fleytman chunk_size = MIN((unsigned) data_length, sg.resid); 605881d588aSDmitry Fleytman if (chunk_size) { 606881d588aSDmitry Fleytman qemu_sglist_add(&r->sgl, sg.dataAddr, chunk_size); 607881d588aSDmitry Fleytman } 608881d588aSDmitry Fleytman 609881d588aSDmitry Fleytman sg.dataAddr += chunk_size; 610881d588aSDmitry Fleytman data_length -= chunk_size; 611881d588aSDmitry Fleytman sg.resid -= chunk_size; 612881d588aSDmitry Fleytman } 613881d588aSDmitry Fleytman } 614881d588aSDmitry Fleytman 615881d588aSDmitry Fleytman static void 616881d588aSDmitry Fleytman pvscsi_build_sglist(PVSCSIState *s, PVSCSIRequest *r) 617881d588aSDmitry Fleytman { 618881d588aSDmitry Fleytman PCIDevice *d = PCI_DEVICE(s); 619881d588aSDmitry Fleytman 620df32fd1cSPaolo Bonzini pci_dma_sglist_init(&r->sgl, d, 1); 621881d588aSDmitry Fleytman if (r->req.flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) { 622881d588aSDmitry Fleytman pvscsi_convert_sglist(r); 623881d588aSDmitry Fleytman } else { 624881d588aSDmitry Fleytman qemu_sglist_add(&r->sgl, r->req.dataAddr, r->req.dataLen); 625881d588aSDmitry Fleytman } 626881d588aSDmitry Fleytman } 627881d588aSDmitry Fleytman 628881d588aSDmitry Fleytman static void 629881d588aSDmitry Fleytman pvscsi_process_request_descriptor(PVSCSIState *s, 630881d588aSDmitry Fleytman struct PVSCSIRingReqDesc *descr) 631881d588aSDmitry Fleytman { 632881d588aSDmitry Fleytman SCSIDevice *d; 633881d588aSDmitry Fleytman PVSCSIRequest *r = pvscsi_queue_pending_descriptor(s, &d, descr); 634881d588aSDmitry Fleytman int64_t n; 635881d588aSDmitry Fleytman 636881d588aSDmitry Fleytman trace_pvscsi_process_req_descr(descr->cdb[0], descr->context); 637881d588aSDmitry Fleytman 638881d588aSDmitry Fleytman if (!d) { 639881d588aSDmitry Fleytman r->cmp.hostStatus = BTSTAT_SELTIMEO; 640881d588aSDmitry Fleytman trace_pvscsi_process_req_descr_unknown_device(); 641881d588aSDmitry Fleytman pvscsi_complete_request(s, r); 642881d588aSDmitry Fleytman return; 643881d588aSDmitry Fleytman } 644881d588aSDmitry Fleytman 645881d588aSDmitry Fleytman if (descr->flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) { 646881d588aSDmitry Fleytman r->sg.elemAddr = descr->dataAddr; 647881d588aSDmitry Fleytman } 648881d588aSDmitry Fleytman 649881d588aSDmitry Fleytman r->sreq = scsi_req_new(d, descr->context, r->lun, descr->cdb, r); 650881d588aSDmitry Fleytman if (r->sreq->cmd.mode == SCSI_XFER_FROM_DEV && 651881d588aSDmitry Fleytman (descr->flags & PVSCSI_FLAG_CMD_DIR_TODEVICE)) { 652881d588aSDmitry Fleytman r->cmp.hostStatus = BTSTAT_BADMSG; 653881d588aSDmitry Fleytman trace_pvscsi_process_req_descr_invalid_dir(); 654881d588aSDmitry Fleytman scsi_req_cancel(r->sreq); 655881d588aSDmitry Fleytman return; 656881d588aSDmitry Fleytman } 657881d588aSDmitry Fleytman if (r->sreq->cmd.mode == SCSI_XFER_TO_DEV && 658881d588aSDmitry Fleytman (descr->flags & PVSCSI_FLAG_CMD_DIR_TOHOST)) { 659881d588aSDmitry Fleytman r->cmp.hostStatus = BTSTAT_BADMSG; 660881d588aSDmitry Fleytman trace_pvscsi_process_req_descr_invalid_dir(); 661881d588aSDmitry Fleytman scsi_req_cancel(r->sreq); 662881d588aSDmitry Fleytman return; 663881d588aSDmitry Fleytman } 664881d588aSDmitry Fleytman 665881d588aSDmitry Fleytman pvscsi_build_sglist(s, r); 666881d588aSDmitry Fleytman n = scsi_req_enqueue(r->sreq); 667881d588aSDmitry Fleytman 668881d588aSDmitry Fleytman if (n) { 669881d588aSDmitry Fleytman scsi_req_continue(r->sreq); 670881d588aSDmitry Fleytman } 671881d588aSDmitry Fleytman } 672881d588aSDmitry Fleytman 673881d588aSDmitry Fleytman static void 674881d588aSDmitry Fleytman pvscsi_process_io(PVSCSIState *s) 675881d588aSDmitry Fleytman { 676881d588aSDmitry Fleytman PVSCSIRingReqDesc descr; 677881d588aSDmitry Fleytman hwaddr next_descr_pa; 678881d588aSDmitry Fleytman 679881d588aSDmitry Fleytman assert(s->rings_info_valid); 680881d588aSDmitry Fleytman while ((next_descr_pa = pvscsi_ring_pop_req_descr(&s->rings)) != 0) { 681881d588aSDmitry Fleytman 682881d588aSDmitry Fleytman /* Only read after production index verification */ 683881d588aSDmitry Fleytman smp_rmb(); 684881d588aSDmitry Fleytman 685881d588aSDmitry Fleytman trace_pvscsi_process_io(next_descr_pa); 686881d588aSDmitry Fleytman cpu_physical_memory_read(next_descr_pa, &descr, sizeof(descr)); 687881d588aSDmitry Fleytman pvscsi_process_request_descriptor(s, &descr); 688881d588aSDmitry Fleytman } 689881d588aSDmitry Fleytman 690881d588aSDmitry Fleytman pvscsi_ring_flush_req(&s->rings); 691881d588aSDmitry Fleytman } 692881d588aSDmitry Fleytman 693881d588aSDmitry Fleytman static void 694881d588aSDmitry Fleytman pvscsi_dbg_dump_tx_rings_config(PVSCSICmdDescSetupRings *rc) 695881d588aSDmitry Fleytman { 696881d588aSDmitry Fleytman int i; 697881d588aSDmitry Fleytman trace_pvscsi_tx_rings_ppn("Rings State", rc->ringsStatePPN); 698881d588aSDmitry Fleytman 699881d588aSDmitry Fleytman trace_pvscsi_tx_rings_num_pages("Request Ring", rc->reqRingNumPages); 700881d588aSDmitry Fleytman for (i = 0; i < rc->reqRingNumPages; i++) { 701881d588aSDmitry Fleytman trace_pvscsi_tx_rings_ppn("Request Ring", rc->reqRingPPNs[i]); 702881d588aSDmitry Fleytman } 703881d588aSDmitry Fleytman 704881d588aSDmitry Fleytman trace_pvscsi_tx_rings_num_pages("Confirm Ring", rc->cmpRingNumPages); 705881d588aSDmitry Fleytman for (i = 0; i < rc->cmpRingNumPages; i++) { 706881d588aSDmitry Fleytman trace_pvscsi_tx_rings_ppn("Confirm Ring", rc->reqRingPPNs[i]); 707881d588aSDmitry Fleytman } 708881d588aSDmitry Fleytman } 709881d588aSDmitry Fleytman 710881d588aSDmitry Fleytman static uint64_t 711881d588aSDmitry Fleytman pvscsi_on_cmd_config(PVSCSIState *s) 712881d588aSDmitry Fleytman { 713881d588aSDmitry Fleytman trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_CONFIG"); 714881d588aSDmitry Fleytman return PVSCSI_COMMAND_PROCESSING_FAILED; 715881d588aSDmitry Fleytman } 716881d588aSDmitry Fleytman 717881d588aSDmitry Fleytman static uint64_t 718881d588aSDmitry Fleytman pvscsi_on_cmd_unplug(PVSCSIState *s) 719881d588aSDmitry Fleytman { 720881d588aSDmitry Fleytman trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_DEVICE_UNPLUG"); 721881d588aSDmitry Fleytman return PVSCSI_COMMAND_PROCESSING_FAILED; 722881d588aSDmitry Fleytman } 723881d588aSDmitry Fleytman 724881d588aSDmitry Fleytman static uint64_t 725881d588aSDmitry Fleytman pvscsi_on_issue_scsi(PVSCSIState *s) 726881d588aSDmitry Fleytman { 727881d588aSDmitry Fleytman trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_ISSUE_SCSI"); 728881d588aSDmitry Fleytman return PVSCSI_COMMAND_PROCESSING_FAILED; 729881d588aSDmitry Fleytman } 730881d588aSDmitry Fleytman 731881d588aSDmitry Fleytman static uint64_t 732881d588aSDmitry Fleytman pvscsi_on_cmd_setup_rings(PVSCSIState *s) 733881d588aSDmitry Fleytman { 734881d588aSDmitry Fleytman PVSCSICmdDescSetupRings *rc = 735881d588aSDmitry Fleytman (PVSCSICmdDescSetupRings *) s->curr_cmd_data; 736881d588aSDmitry Fleytman 737881d588aSDmitry Fleytman trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_RINGS"); 738881d588aSDmitry Fleytman 739881d588aSDmitry Fleytman pvscsi_dbg_dump_tx_rings_config(rc); 740881d588aSDmitry Fleytman pvscsi_ring_init_data(&s->rings, rc); 741881d588aSDmitry Fleytman s->rings_info_valid = TRUE; 742881d588aSDmitry Fleytman return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 743881d588aSDmitry Fleytman } 744881d588aSDmitry Fleytman 745881d588aSDmitry Fleytman static uint64_t 746881d588aSDmitry Fleytman pvscsi_on_cmd_abort(PVSCSIState *s) 747881d588aSDmitry Fleytman { 748881d588aSDmitry Fleytman PVSCSICmdDescAbortCmd *cmd = (PVSCSICmdDescAbortCmd *) s->curr_cmd_data; 749881d588aSDmitry Fleytman PVSCSIRequest *r, *next; 750881d588aSDmitry Fleytman 751881d588aSDmitry Fleytman trace_pvscsi_on_cmd_abort(cmd->context, cmd->target); 752881d588aSDmitry Fleytman 753881d588aSDmitry Fleytman QTAILQ_FOREACH_SAFE(r, &s->pending_queue, next, next) { 754881d588aSDmitry Fleytman if (r->req.context == cmd->context) { 755881d588aSDmitry Fleytman break; 756881d588aSDmitry Fleytman } 757881d588aSDmitry Fleytman } 758881d588aSDmitry Fleytman if (r) { 759881d588aSDmitry Fleytman assert(!r->completed); 760881d588aSDmitry Fleytman r->cmp.hostStatus = BTSTAT_ABORTQUEUE; 761881d588aSDmitry Fleytman scsi_req_cancel(r->sreq); 762881d588aSDmitry Fleytman } 763881d588aSDmitry Fleytman 764881d588aSDmitry Fleytman return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 765881d588aSDmitry Fleytman } 766881d588aSDmitry Fleytman 767881d588aSDmitry Fleytman static uint64_t 768881d588aSDmitry Fleytman pvscsi_on_cmd_unknown(PVSCSIState *s) 769881d588aSDmitry Fleytman { 770881d588aSDmitry Fleytman trace_pvscsi_on_cmd_unknown_data(s->curr_cmd_data[0]); 771881d588aSDmitry Fleytman return PVSCSI_COMMAND_PROCESSING_FAILED; 772881d588aSDmitry Fleytman } 773881d588aSDmitry Fleytman 774881d588aSDmitry Fleytman static uint64_t 775881d588aSDmitry Fleytman pvscsi_on_cmd_reset_device(PVSCSIState *s) 776881d588aSDmitry Fleytman { 777881d588aSDmitry Fleytman uint8_t target_lun = 0; 778881d588aSDmitry Fleytman struct PVSCSICmdDescResetDevice *cmd = 779881d588aSDmitry Fleytman (struct PVSCSICmdDescResetDevice *) s->curr_cmd_data; 780881d588aSDmitry Fleytman SCSIDevice *sdev; 781881d588aSDmitry Fleytman 782881d588aSDmitry Fleytman sdev = pvscsi_device_find(s, 0, cmd->target, cmd->lun, &target_lun); 783881d588aSDmitry Fleytman 784881d588aSDmitry Fleytman trace_pvscsi_on_cmd_reset_dev(cmd->target, (int) target_lun, sdev); 785881d588aSDmitry Fleytman 786881d588aSDmitry Fleytman if (sdev != NULL) { 787881d588aSDmitry Fleytman s->resetting++; 788881d588aSDmitry Fleytman device_reset(&sdev->qdev); 789881d588aSDmitry Fleytman s->resetting--; 790881d588aSDmitry Fleytman return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 791881d588aSDmitry Fleytman } 792881d588aSDmitry Fleytman 793881d588aSDmitry Fleytman return PVSCSI_COMMAND_PROCESSING_FAILED; 794881d588aSDmitry Fleytman } 795881d588aSDmitry Fleytman 796881d588aSDmitry Fleytman static uint64_t 797881d588aSDmitry Fleytman pvscsi_on_cmd_reset_bus(PVSCSIState *s) 798881d588aSDmitry Fleytman { 799881d588aSDmitry Fleytman trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_RESET_BUS"); 800881d588aSDmitry Fleytman 801881d588aSDmitry Fleytman s->resetting++; 802881d588aSDmitry Fleytman qbus_reset_all_fn(&s->bus); 803881d588aSDmitry Fleytman s->resetting--; 804881d588aSDmitry Fleytman return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 805881d588aSDmitry Fleytman } 806881d588aSDmitry Fleytman 807881d588aSDmitry Fleytman static uint64_t 808881d588aSDmitry Fleytman pvscsi_on_cmd_setup_msg_ring(PVSCSIState *s) 809881d588aSDmitry Fleytman { 810881d588aSDmitry Fleytman PVSCSICmdDescSetupMsgRing *rc = 811881d588aSDmitry Fleytman (PVSCSICmdDescSetupMsgRing *) s->curr_cmd_data; 812881d588aSDmitry Fleytman 813881d588aSDmitry Fleytman trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_MSG_RING"); 814881d588aSDmitry Fleytman 815881d588aSDmitry Fleytman if (!s->use_msg) { 816881d588aSDmitry Fleytman return PVSCSI_COMMAND_PROCESSING_FAILED; 817881d588aSDmitry Fleytman } 818881d588aSDmitry Fleytman 819881d588aSDmitry Fleytman if (s->rings_info_valid) { 820881d588aSDmitry Fleytman pvscsi_ring_init_msg(&s->rings, rc); 821881d588aSDmitry Fleytman s->msg_ring_info_valid = TRUE; 822881d588aSDmitry Fleytman } 823881d588aSDmitry Fleytman return sizeof(PVSCSICmdDescSetupMsgRing) / sizeof(uint32_t); 824881d588aSDmitry Fleytman } 825881d588aSDmitry Fleytman 826881d588aSDmitry Fleytman static uint64_t 827881d588aSDmitry Fleytman pvscsi_on_cmd_adapter_reset(PVSCSIState *s) 828881d588aSDmitry Fleytman { 829881d588aSDmitry Fleytman trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_ADAPTER_RESET"); 830881d588aSDmitry Fleytman 831881d588aSDmitry Fleytman pvscsi_reset_adapter(s); 832881d588aSDmitry Fleytman return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 833881d588aSDmitry Fleytman } 834881d588aSDmitry Fleytman 835881d588aSDmitry Fleytman static const struct { 836881d588aSDmitry Fleytman int data_size; 837881d588aSDmitry Fleytman uint64_t (*handler_fn)(PVSCSIState *s); 838881d588aSDmitry Fleytman } pvscsi_commands[] = { 839881d588aSDmitry Fleytman [PVSCSI_CMD_FIRST] = { 840881d588aSDmitry Fleytman .data_size = 0, 841881d588aSDmitry Fleytman .handler_fn = pvscsi_on_cmd_unknown, 842881d588aSDmitry Fleytman }, 843881d588aSDmitry Fleytman 844881d588aSDmitry Fleytman /* Not implemented, data size defined based on what arrives on windows */ 845881d588aSDmitry Fleytman [PVSCSI_CMD_CONFIG] = { 846881d588aSDmitry Fleytman .data_size = 6 * sizeof(uint32_t), 847881d588aSDmitry Fleytman .handler_fn = pvscsi_on_cmd_config, 848881d588aSDmitry Fleytman }, 849881d588aSDmitry Fleytman 850881d588aSDmitry Fleytman /* Command not implemented, data size is unknown */ 851881d588aSDmitry Fleytman [PVSCSI_CMD_ISSUE_SCSI] = { 852881d588aSDmitry Fleytman .data_size = 0, 853881d588aSDmitry Fleytman .handler_fn = pvscsi_on_issue_scsi, 854881d588aSDmitry Fleytman }, 855881d588aSDmitry Fleytman 856881d588aSDmitry Fleytman /* Command not implemented, data size is unknown */ 857881d588aSDmitry Fleytman [PVSCSI_CMD_DEVICE_UNPLUG] = { 858881d588aSDmitry Fleytman .data_size = 0, 859881d588aSDmitry Fleytman .handler_fn = pvscsi_on_cmd_unplug, 860881d588aSDmitry Fleytman }, 861881d588aSDmitry Fleytman 862881d588aSDmitry Fleytman [PVSCSI_CMD_SETUP_RINGS] = { 863881d588aSDmitry Fleytman .data_size = sizeof(PVSCSICmdDescSetupRings), 864881d588aSDmitry Fleytman .handler_fn = pvscsi_on_cmd_setup_rings, 865881d588aSDmitry Fleytman }, 866881d588aSDmitry Fleytman 867881d588aSDmitry Fleytman [PVSCSI_CMD_RESET_DEVICE] = { 868881d588aSDmitry Fleytman .data_size = sizeof(struct PVSCSICmdDescResetDevice), 869881d588aSDmitry Fleytman .handler_fn = pvscsi_on_cmd_reset_device, 870881d588aSDmitry Fleytman }, 871881d588aSDmitry Fleytman 872881d588aSDmitry Fleytman [PVSCSI_CMD_RESET_BUS] = { 873881d588aSDmitry Fleytman .data_size = 0, 874881d588aSDmitry Fleytman .handler_fn = pvscsi_on_cmd_reset_bus, 875881d588aSDmitry Fleytman }, 876881d588aSDmitry Fleytman 877881d588aSDmitry Fleytman [PVSCSI_CMD_SETUP_MSG_RING] = { 878881d588aSDmitry Fleytman .data_size = sizeof(PVSCSICmdDescSetupMsgRing), 879881d588aSDmitry Fleytman .handler_fn = pvscsi_on_cmd_setup_msg_ring, 880881d588aSDmitry Fleytman }, 881881d588aSDmitry Fleytman 882881d588aSDmitry Fleytman [PVSCSI_CMD_ADAPTER_RESET] = { 883881d588aSDmitry Fleytman .data_size = 0, 884881d588aSDmitry Fleytman .handler_fn = pvscsi_on_cmd_adapter_reset, 885881d588aSDmitry Fleytman }, 886881d588aSDmitry Fleytman 887881d588aSDmitry Fleytman [PVSCSI_CMD_ABORT_CMD] = { 888881d588aSDmitry Fleytman .data_size = sizeof(struct PVSCSICmdDescAbortCmd), 889881d588aSDmitry Fleytman .handler_fn = pvscsi_on_cmd_abort, 890881d588aSDmitry Fleytman }, 891881d588aSDmitry Fleytman }; 892881d588aSDmitry Fleytman 893881d588aSDmitry Fleytman static void 894881d588aSDmitry Fleytman pvscsi_do_command_processing(PVSCSIState *s) 895881d588aSDmitry Fleytman { 896881d588aSDmitry Fleytman size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t); 897881d588aSDmitry Fleytman 898881d588aSDmitry Fleytman assert(s->curr_cmd < PVSCSI_CMD_LAST); 899881d588aSDmitry Fleytman if (bytes_arrived >= pvscsi_commands[s->curr_cmd].data_size) { 900881d588aSDmitry Fleytman s->reg_command_status = pvscsi_commands[s->curr_cmd].handler_fn(s); 901881d588aSDmitry Fleytman s->curr_cmd = PVSCSI_CMD_FIRST; 902881d588aSDmitry Fleytman s->curr_cmd_data_cntr = 0; 903881d588aSDmitry Fleytman } 904881d588aSDmitry Fleytman } 905881d588aSDmitry Fleytman 906881d588aSDmitry Fleytman static void 907881d588aSDmitry Fleytman pvscsi_on_command_data(PVSCSIState *s, uint32_t value) 908881d588aSDmitry Fleytman { 909881d588aSDmitry Fleytman size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t); 910881d588aSDmitry Fleytman 911881d588aSDmitry Fleytman assert(bytes_arrived < sizeof(s->curr_cmd_data)); 912881d588aSDmitry Fleytman s->curr_cmd_data[s->curr_cmd_data_cntr++] = value; 913881d588aSDmitry Fleytman 914881d588aSDmitry Fleytman pvscsi_do_command_processing(s); 915881d588aSDmitry Fleytman } 916881d588aSDmitry Fleytman 917881d588aSDmitry Fleytman static void 918881d588aSDmitry Fleytman pvscsi_on_command(PVSCSIState *s, uint64_t cmd_id) 919881d588aSDmitry Fleytman { 920881d588aSDmitry Fleytman if ((cmd_id > PVSCSI_CMD_FIRST) && (cmd_id < PVSCSI_CMD_LAST)) { 921881d588aSDmitry Fleytman s->curr_cmd = cmd_id; 922881d588aSDmitry Fleytman } else { 923881d588aSDmitry Fleytman s->curr_cmd = PVSCSI_CMD_FIRST; 924881d588aSDmitry Fleytman trace_pvscsi_on_cmd_unknown(cmd_id); 925881d588aSDmitry Fleytman } 926881d588aSDmitry Fleytman 927881d588aSDmitry Fleytman s->curr_cmd_data_cntr = 0; 928881d588aSDmitry Fleytman s->reg_command_status = PVSCSI_COMMAND_NOT_ENOUGH_DATA; 929881d588aSDmitry Fleytman 930881d588aSDmitry Fleytman pvscsi_do_command_processing(s); 931881d588aSDmitry Fleytman } 932881d588aSDmitry Fleytman 933881d588aSDmitry Fleytman static void 934881d588aSDmitry Fleytman pvscsi_io_write(void *opaque, hwaddr addr, 935881d588aSDmitry Fleytman uint64_t val, unsigned size) 936881d588aSDmitry Fleytman { 937881d588aSDmitry Fleytman PVSCSIState *s = opaque; 938881d588aSDmitry Fleytman 939881d588aSDmitry Fleytman switch (addr) { 940881d588aSDmitry Fleytman case PVSCSI_REG_OFFSET_COMMAND: 941881d588aSDmitry Fleytman pvscsi_on_command(s, val); 942881d588aSDmitry Fleytman break; 943881d588aSDmitry Fleytman 944881d588aSDmitry Fleytman case PVSCSI_REG_OFFSET_COMMAND_DATA: 945881d588aSDmitry Fleytman pvscsi_on_command_data(s, (uint32_t) val); 946881d588aSDmitry Fleytman break; 947881d588aSDmitry Fleytman 948881d588aSDmitry Fleytman case PVSCSI_REG_OFFSET_INTR_STATUS: 949881d588aSDmitry Fleytman trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_STATUS", val); 950881d588aSDmitry Fleytman s->reg_interrupt_status &= ~val; 951881d588aSDmitry Fleytman pvscsi_update_irq_status(s); 952881d588aSDmitry Fleytman pvscsi_schedule_completion_processing(s); 953881d588aSDmitry Fleytman break; 954881d588aSDmitry Fleytman 955881d588aSDmitry Fleytman case PVSCSI_REG_OFFSET_INTR_MASK: 956881d588aSDmitry Fleytman trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_MASK", val); 957881d588aSDmitry Fleytman s->reg_interrupt_enabled = val; 958881d588aSDmitry Fleytman pvscsi_update_irq_status(s); 959881d588aSDmitry Fleytman break; 960881d588aSDmitry Fleytman 961881d588aSDmitry Fleytman case PVSCSI_REG_OFFSET_KICK_NON_RW_IO: 962881d588aSDmitry Fleytman trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_NON_RW_IO", val); 963881d588aSDmitry Fleytman pvscsi_process_io(s); 964881d588aSDmitry Fleytman break; 965881d588aSDmitry Fleytman 966881d588aSDmitry Fleytman case PVSCSI_REG_OFFSET_KICK_RW_IO: 967881d588aSDmitry Fleytman trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_RW_IO", val); 968881d588aSDmitry Fleytman pvscsi_process_io(s); 969881d588aSDmitry Fleytman break; 970881d588aSDmitry Fleytman 971881d588aSDmitry Fleytman case PVSCSI_REG_OFFSET_DEBUG: 972881d588aSDmitry Fleytman trace_pvscsi_io_write("PVSCSI_REG_OFFSET_DEBUG", val); 973881d588aSDmitry Fleytman break; 974881d588aSDmitry Fleytman 975881d588aSDmitry Fleytman default: 976881d588aSDmitry Fleytman trace_pvscsi_io_write_unknown(addr, size, val); 977881d588aSDmitry Fleytman break; 978881d588aSDmitry Fleytman } 979881d588aSDmitry Fleytman 980881d588aSDmitry Fleytman } 981881d588aSDmitry Fleytman 982881d588aSDmitry Fleytman static uint64_t 983881d588aSDmitry Fleytman pvscsi_io_read(void *opaque, hwaddr addr, unsigned size) 984881d588aSDmitry Fleytman { 985881d588aSDmitry Fleytman PVSCSIState *s = opaque; 986881d588aSDmitry Fleytman 987881d588aSDmitry Fleytman switch (addr) { 988881d588aSDmitry Fleytman case PVSCSI_REG_OFFSET_INTR_STATUS: 989881d588aSDmitry Fleytman trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_STATUS", 990881d588aSDmitry Fleytman s->reg_interrupt_status); 991881d588aSDmitry Fleytman return s->reg_interrupt_status; 992881d588aSDmitry Fleytman 993881d588aSDmitry Fleytman case PVSCSI_REG_OFFSET_INTR_MASK: 994881d588aSDmitry Fleytman trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_MASK", 995881d588aSDmitry Fleytman s->reg_interrupt_status); 996881d588aSDmitry Fleytman return s->reg_interrupt_enabled; 997881d588aSDmitry Fleytman 998881d588aSDmitry Fleytman case PVSCSI_REG_OFFSET_COMMAND_STATUS: 999881d588aSDmitry Fleytman trace_pvscsi_io_read("PVSCSI_REG_OFFSET_COMMAND_STATUS", 1000881d588aSDmitry Fleytman s->reg_interrupt_status); 1001881d588aSDmitry Fleytman return s->reg_command_status; 1002881d588aSDmitry Fleytman 1003881d588aSDmitry Fleytman default: 1004881d588aSDmitry Fleytman trace_pvscsi_io_read_unknown(addr, size); 1005881d588aSDmitry Fleytman return 0; 1006881d588aSDmitry Fleytman } 1007881d588aSDmitry Fleytman } 1008881d588aSDmitry Fleytman 1009881d588aSDmitry Fleytman 1010881d588aSDmitry Fleytman static bool 1011881d588aSDmitry Fleytman pvscsi_init_msi(PVSCSIState *s) 1012881d588aSDmitry Fleytman { 1013881d588aSDmitry Fleytman int res; 1014881d588aSDmitry Fleytman PCIDevice *d = PCI_DEVICE(s); 1015881d588aSDmitry Fleytman 1016881d588aSDmitry Fleytman res = msi_init(d, PVSCSI_MSI_OFFSET, PVSCSI_MSIX_NUM_VECTORS, 1017881d588aSDmitry Fleytman PVSCSI_USE_64BIT, PVSCSI_PER_VECTOR_MASK); 1018881d588aSDmitry Fleytman if (res < 0) { 1019881d588aSDmitry Fleytman trace_pvscsi_init_msi_fail(res); 1020881d588aSDmitry Fleytman s->msi_used = false; 1021881d588aSDmitry Fleytman } else { 1022881d588aSDmitry Fleytman s->msi_used = true; 1023881d588aSDmitry Fleytman } 1024881d588aSDmitry Fleytman 1025881d588aSDmitry Fleytman return s->msi_used; 1026881d588aSDmitry Fleytman } 1027881d588aSDmitry Fleytman 1028881d588aSDmitry Fleytman static void 1029881d588aSDmitry Fleytman pvscsi_cleanup_msi(PVSCSIState *s) 1030881d588aSDmitry Fleytman { 1031881d588aSDmitry Fleytman PCIDevice *d = PCI_DEVICE(s); 1032881d588aSDmitry Fleytman 1033881d588aSDmitry Fleytman if (s->msi_used) { 1034881d588aSDmitry Fleytman msi_uninit(d); 1035881d588aSDmitry Fleytman } 1036881d588aSDmitry Fleytman } 1037881d588aSDmitry Fleytman 1038881d588aSDmitry Fleytman static const MemoryRegionOps pvscsi_ops = { 1039881d588aSDmitry Fleytman .read = pvscsi_io_read, 1040881d588aSDmitry Fleytman .write = pvscsi_io_write, 1041881d588aSDmitry Fleytman .endianness = DEVICE_LITTLE_ENDIAN, 1042881d588aSDmitry Fleytman .impl = { 1043881d588aSDmitry Fleytman .min_access_size = 4, 1044881d588aSDmitry Fleytman .max_access_size = 4, 1045881d588aSDmitry Fleytman }, 1046881d588aSDmitry Fleytman }; 1047881d588aSDmitry Fleytman 1048881d588aSDmitry Fleytman static const struct SCSIBusInfo pvscsi_scsi_info = { 1049881d588aSDmitry Fleytman .tcq = true, 1050881d588aSDmitry Fleytman .max_target = PVSCSI_MAX_DEVS, 1051881d588aSDmitry Fleytman .max_channel = 0, 1052881d588aSDmitry Fleytman .max_lun = 0, 1053881d588aSDmitry Fleytman 1054881d588aSDmitry Fleytman .get_sg_list = pvscsi_get_sg_list, 1055881d588aSDmitry Fleytman .complete = pvscsi_command_complete, 1056881d588aSDmitry Fleytman .cancel = pvscsi_request_cancelled, 1057881d588aSDmitry Fleytman .hotplug = pvscsi_hotplug, 1058881d588aSDmitry Fleytman .hot_unplug = pvscsi_hot_unplug, 1059881d588aSDmitry Fleytman }; 1060881d588aSDmitry Fleytman 1061881d588aSDmitry Fleytman static int 1062881d588aSDmitry Fleytman pvscsi_init(PCIDevice *pci_dev) 1063881d588aSDmitry Fleytman { 1064881d588aSDmitry Fleytman PVSCSIState *s = PVSCSI(pci_dev); 1065881d588aSDmitry Fleytman 1066881d588aSDmitry Fleytman trace_pvscsi_state("init"); 1067881d588aSDmitry Fleytman 1068881d588aSDmitry Fleytman /* PCI subsystem ID */ 1069881d588aSDmitry Fleytman pci_dev->config[PCI_SUBSYSTEM_ID] = 0x00; 1070881d588aSDmitry Fleytman pci_dev->config[PCI_SUBSYSTEM_ID + 1] = 0x10; 1071881d588aSDmitry Fleytman 1072881d588aSDmitry Fleytman /* PCI latency timer = 255 */ 1073881d588aSDmitry Fleytman pci_dev->config[PCI_LATENCY_TIMER] = 0xff; 1074881d588aSDmitry Fleytman 1075881d588aSDmitry Fleytman /* Interrupt pin A */ 1076881d588aSDmitry Fleytman pci_config_set_interrupt_pin(pci_dev->config, 1); 1077881d588aSDmitry Fleytman 107829776739SPaolo Bonzini memory_region_init_io(&s->io_space, OBJECT(s), &pvscsi_ops, s, 1079881d588aSDmitry Fleytman "pvscsi-io", PVSCSI_MEM_SPACE_SIZE); 1080881d588aSDmitry Fleytman pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io_space); 1081881d588aSDmitry Fleytman 1082881d588aSDmitry Fleytman pvscsi_init_msi(s); 1083881d588aSDmitry Fleytman 1084881d588aSDmitry Fleytman s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s); 1085881d588aSDmitry Fleytman if (!s->completion_worker) { 1086881d588aSDmitry Fleytman pvscsi_cleanup_msi(s); 1087881d588aSDmitry Fleytman memory_region_destroy(&s->io_space); 1088881d588aSDmitry Fleytman return -ENOMEM; 1089881d588aSDmitry Fleytman } 1090881d588aSDmitry Fleytman 1091*b1187b51SAndreas Färber scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(pci_dev), 1092*b1187b51SAndreas Färber &pvscsi_scsi_info, NULL); 1093881d588aSDmitry Fleytman pvscsi_reset_state(s); 1094881d588aSDmitry Fleytman 1095881d588aSDmitry Fleytman return 0; 1096881d588aSDmitry Fleytman } 1097881d588aSDmitry Fleytman 1098881d588aSDmitry Fleytman static void 1099881d588aSDmitry Fleytman pvscsi_uninit(PCIDevice *pci_dev) 1100881d588aSDmitry Fleytman { 1101881d588aSDmitry Fleytman PVSCSIState *s = PVSCSI(pci_dev); 1102881d588aSDmitry Fleytman 1103881d588aSDmitry Fleytman trace_pvscsi_state("uninit"); 1104881d588aSDmitry Fleytman qemu_bh_delete(s->completion_worker); 1105881d588aSDmitry Fleytman 1106881d588aSDmitry Fleytman pvscsi_cleanup_msi(s); 1107881d588aSDmitry Fleytman 1108881d588aSDmitry Fleytman memory_region_destroy(&s->io_space); 1109881d588aSDmitry Fleytman } 1110881d588aSDmitry Fleytman 1111881d588aSDmitry Fleytman static void 1112881d588aSDmitry Fleytman pvscsi_reset(DeviceState *dev) 1113881d588aSDmitry Fleytman { 1114881d588aSDmitry Fleytman PCIDevice *d = PCI_DEVICE(dev); 1115881d588aSDmitry Fleytman PVSCSIState *s = PVSCSI(d); 1116881d588aSDmitry Fleytman 1117881d588aSDmitry Fleytman trace_pvscsi_state("reset"); 1118881d588aSDmitry Fleytman pvscsi_reset_adapter(s); 1119881d588aSDmitry Fleytman } 1120881d588aSDmitry Fleytman 1121881d588aSDmitry Fleytman static void 1122881d588aSDmitry Fleytman pvscsi_pre_save(void *opaque) 1123881d588aSDmitry Fleytman { 1124881d588aSDmitry Fleytman PVSCSIState *s = (PVSCSIState *) opaque; 1125881d588aSDmitry Fleytman 1126881d588aSDmitry Fleytman trace_pvscsi_state("presave"); 1127881d588aSDmitry Fleytman 1128881d588aSDmitry Fleytman assert(QTAILQ_EMPTY(&s->pending_queue)); 1129881d588aSDmitry Fleytman assert(QTAILQ_EMPTY(&s->completion_queue)); 1130881d588aSDmitry Fleytman } 1131881d588aSDmitry Fleytman 1132881d588aSDmitry Fleytman static int 1133881d588aSDmitry Fleytman pvscsi_post_load(void *opaque, int version_id) 1134881d588aSDmitry Fleytman { 1135881d588aSDmitry Fleytman trace_pvscsi_state("postload"); 1136881d588aSDmitry Fleytman return 0; 1137881d588aSDmitry Fleytman } 1138881d588aSDmitry Fleytman 1139881d588aSDmitry Fleytman static const VMStateDescription vmstate_pvscsi = { 11406783ecf1SPeter Maydell .name = "pvscsi", 1141881d588aSDmitry Fleytman .version_id = 0, 1142881d588aSDmitry Fleytman .minimum_version_id = 0, 1143881d588aSDmitry Fleytman .minimum_version_id_old = 0, 1144881d588aSDmitry Fleytman .pre_save = pvscsi_pre_save, 1145881d588aSDmitry Fleytman .post_load = pvscsi_post_load, 1146881d588aSDmitry Fleytman .fields = (VMStateField[]) { 1147881d588aSDmitry Fleytman VMSTATE_PCI_DEVICE(parent_obj, PVSCSIState), 1148881d588aSDmitry Fleytman VMSTATE_UINT8(msi_used, PVSCSIState), 1149881d588aSDmitry Fleytman VMSTATE_UINT32(resetting, PVSCSIState), 1150881d588aSDmitry Fleytman VMSTATE_UINT64(reg_interrupt_status, PVSCSIState), 1151881d588aSDmitry Fleytman VMSTATE_UINT64(reg_interrupt_enabled, PVSCSIState), 1152881d588aSDmitry Fleytman VMSTATE_UINT64(reg_command_status, PVSCSIState), 1153881d588aSDmitry Fleytman VMSTATE_UINT64(curr_cmd, PVSCSIState), 1154881d588aSDmitry Fleytman VMSTATE_UINT32(curr_cmd_data_cntr, PVSCSIState), 1155881d588aSDmitry Fleytman VMSTATE_UINT32_ARRAY(curr_cmd_data, PVSCSIState, 1156881d588aSDmitry Fleytman ARRAY_SIZE(((PVSCSIState *)NULL)->curr_cmd_data)), 1157881d588aSDmitry Fleytman VMSTATE_UINT8(rings_info_valid, PVSCSIState), 1158881d588aSDmitry Fleytman VMSTATE_UINT8(msg_ring_info_valid, PVSCSIState), 1159881d588aSDmitry Fleytman VMSTATE_UINT8(use_msg, PVSCSIState), 1160881d588aSDmitry Fleytman 1161881d588aSDmitry Fleytman VMSTATE_UINT64(rings.rs_pa, PVSCSIState), 1162881d588aSDmitry Fleytman VMSTATE_UINT32(rings.txr_len_mask, PVSCSIState), 1163881d588aSDmitry Fleytman VMSTATE_UINT32(rings.rxr_len_mask, PVSCSIState), 1164881d588aSDmitry Fleytman VMSTATE_UINT64_ARRAY(rings.req_ring_pages_pa, PVSCSIState, 1165881d588aSDmitry Fleytman PVSCSI_SETUP_RINGS_MAX_NUM_PAGES), 1166881d588aSDmitry Fleytman VMSTATE_UINT64_ARRAY(rings.cmp_ring_pages_pa, PVSCSIState, 1167881d588aSDmitry Fleytman PVSCSI_SETUP_RINGS_MAX_NUM_PAGES), 1168881d588aSDmitry Fleytman VMSTATE_UINT64(rings.consumed_ptr, PVSCSIState), 1169881d588aSDmitry Fleytman VMSTATE_UINT64(rings.filled_cmp_ptr, PVSCSIState), 1170881d588aSDmitry Fleytman 1171881d588aSDmitry Fleytman VMSTATE_END_OF_LIST() 1172881d588aSDmitry Fleytman } 1173881d588aSDmitry Fleytman }; 1174881d588aSDmitry Fleytman 1175881d588aSDmitry Fleytman static void 1176881d588aSDmitry Fleytman pvscsi_write_config(PCIDevice *pci, uint32_t addr, uint32_t val, int len) 1177881d588aSDmitry Fleytman { 1178881d588aSDmitry Fleytman pci_default_write_config(pci, addr, val, len); 1179881d588aSDmitry Fleytman msi_write_config(pci, addr, val, len); 1180881d588aSDmitry Fleytman } 1181881d588aSDmitry Fleytman 1182881d588aSDmitry Fleytman static Property pvscsi_properties[] = { 1183881d588aSDmitry Fleytman DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1), 1184881d588aSDmitry Fleytman DEFINE_PROP_END_OF_LIST(), 1185881d588aSDmitry Fleytman }; 1186881d588aSDmitry Fleytman 1187881d588aSDmitry Fleytman static void pvscsi_class_init(ObjectClass *klass, void *data) 1188881d588aSDmitry Fleytman { 1189881d588aSDmitry Fleytman DeviceClass *dc = DEVICE_CLASS(klass); 1190881d588aSDmitry Fleytman PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1191881d588aSDmitry Fleytman 1192881d588aSDmitry Fleytman k->init = pvscsi_init; 1193881d588aSDmitry Fleytman k->exit = pvscsi_uninit; 1194881d588aSDmitry Fleytman k->vendor_id = PCI_VENDOR_ID_VMWARE; 1195881d588aSDmitry Fleytman k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI; 1196881d588aSDmitry Fleytman k->class_id = PCI_CLASS_STORAGE_SCSI; 1197881d588aSDmitry Fleytman k->subsystem_id = 0x1000; 1198881d588aSDmitry Fleytman dc->reset = pvscsi_reset; 1199881d588aSDmitry Fleytman dc->vmsd = &vmstate_pvscsi; 1200881d588aSDmitry Fleytman dc->props = pvscsi_properties; 1201125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1202881d588aSDmitry Fleytman k->config_write = pvscsi_write_config; 1203881d588aSDmitry Fleytman } 1204881d588aSDmitry Fleytman 1205881d588aSDmitry Fleytman static const TypeInfo pvscsi_info = { 12066783ecf1SPeter Maydell .name = TYPE_PVSCSI, 1207881d588aSDmitry Fleytman .parent = TYPE_PCI_DEVICE, 1208881d588aSDmitry Fleytman .instance_size = sizeof(PVSCSIState), 1209881d588aSDmitry Fleytman .class_init = pvscsi_class_init, 1210881d588aSDmitry Fleytman }; 1211881d588aSDmitry Fleytman 1212881d588aSDmitry Fleytman static void 1213881d588aSDmitry Fleytman pvscsi_register_types(void) 1214881d588aSDmitry Fleytman { 1215881d588aSDmitry Fleytman type_register_static(&pvscsi_info); 1216881d588aSDmitry Fleytman } 1217881d588aSDmitry Fleytman 1218881d588aSDmitry Fleytman type_init(pvscsi_register_types); 1219