1 /* 2 * QEMU LSI SAS1068 Host Bus Adapter emulation 3 * Based on the QEMU Megaraid emulator 4 * 5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs 6 * Copyright (c) 2012 Verizon, Inc. 7 * Copyright (c) 2016 Red Hat, Inc. 8 * 9 * Authors: Don Slutz, Paolo Bonzini 10 * 11 * This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU Lesser General Public 13 * License as published by the Free Software Foundation; either 14 * version 2.1 of the License, or (at your option) any later version. 15 * 16 * This library is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * Lesser General Public License for more details. 20 * 21 * You should have received a copy of the GNU Lesser General Public 22 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/pci/pci.h" 27 #include "hw/qdev-properties.h" 28 #include "sysemu/dma.h" 29 #include "hw/pci/msi.h" 30 #include "qemu/iov.h" 31 #include "qemu/main-loop.h" 32 #include "qemu/module.h" 33 #include "hw/scsi/scsi.h" 34 #include "scsi/constants.h" 35 #include "trace.h" 36 #include "qapi/error.h" 37 #include "mptsas.h" 38 #include "migration/qemu-file-types.h" 39 #include "migration/vmstate.h" 40 #include "mpi.h" 41 42 #define NAA_LOCALLY_ASSIGNED_ID 0x3ULL 43 #define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400 44 45 #define MPTSAS1068_PRODUCT_ID \ 46 (MPI_FW_HEADER_PID_FAMILY_1068_SAS | \ 47 MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI | \ 48 MPI_FW_HEADER_PID_TYPE_SAS) 49 50 struct MPTSASRequest { 51 MPIMsgSCSIIORequest scsi_io; 52 SCSIRequest *sreq; 53 QEMUSGList qsg; 54 MPTSASState *dev; 55 56 QTAILQ_ENTRY(MPTSASRequest) next; 57 }; 58 59 static void mptsas_update_interrupt(MPTSASState *s) 60 { 61 PCIDevice *pci = (PCIDevice *) s; 62 uint32_t state = s->intr_status & ~(s->intr_mask | MPI_HIS_IOP_DOORBELL_STATUS); 63 64 if (msi_enabled(pci)) { 65 if (state) { 66 trace_mptsas_irq_msi(s); 67 msi_notify(pci, 0); 68 } 69 } 70 71 trace_mptsas_irq_intx(s, !!state); 72 pci_set_irq(pci, !!state); 73 } 74 75 static void mptsas_set_fault(MPTSASState *s, uint32_t code) 76 { 77 if ((s->state & MPI_IOC_STATE_FAULT) == 0) { 78 s->state = MPI_IOC_STATE_FAULT | code; 79 } 80 } 81 82 #define MPTSAS_FIFO_INVALID(s, name) \ 83 ((s)->name##_head > ARRAY_SIZE((s)->name) || \ 84 (s)->name##_tail > ARRAY_SIZE((s)->name)) 85 86 #define MPTSAS_FIFO_EMPTY(s, name) \ 87 ((s)->name##_head == (s)->name##_tail) 88 89 #define MPTSAS_FIFO_FULL(s, name) \ 90 ((s)->name##_head == ((s)->name##_tail + 1) % ARRAY_SIZE((s)->name)) 91 92 #define MPTSAS_FIFO_GET(s, name) ({ \ 93 uint32_t _val = (s)->name[(s)->name##_head++]; \ 94 (s)->name##_head %= ARRAY_SIZE((s)->name); \ 95 _val; \ 96 }) 97 98 #define MPTSAS_FIFO_PUT(s, name, val) do { \ 99 (s)->name[(s)->name##_tail++] = (val); \ 100 (s)->name##_tail %= ARRAY_SIZE((s)->name); \ 101 } while(0) 102 103 static void mptsas_post_reply(MPTSASState *s, MPIDefaultReply *reply) 104 { 105 PCIDevice *pci = (PCIDevice *) s; 106 uint32_t addr_lo; 107 108 if (MPTSAS_FIFO_EMPTY(s, reply_free) || MPTSAS_FIFO_FULL(s, reply_post)) { 109 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); 110 return; 111 } 112 113 addr_lo = MPTSAS_FIFO_GET(s, reply_free); 114 115 pci_dma_write(pci, addr_lo | s->host_mfa_high_addr, reply, 116 MIN(s->reply_frame_size, 4 * reply->MsgLength)); 117 118 MPTSAS_FIFO_PUT(s, reply_post, MPI_ADDRESS_REPLY_A_BIT | (addr_lo >> 1)); 119 120 s->intr_status |= MPI_HIS_REPLY_MESSAGE_INTERRUPT; 121 if (s->doorbell_state == DOORBELL_WRITE) { 122 s->doorbell_state = DOORBELL_NONE; 123 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT; 124 } 125 mptsas_update_interrupt(s); 126 } 127 128 void mptsas_reply(MPTSASState *s, MPIDefaultReply *reply) 129 { 130 if (s->doorbell_state == DOORBELL_WRITE) { 131 /* The reply is sent out in 16 bit chunks, while the size 132 * in the reply is in 32 bit units. 133 */ 134 s->doorbell_state = DOORBELL_READ; 135 s->doorbell_reply_idx = 0; 136 s->doorbell_reply_size = reply->MsgLength * 2; 137 memcpy(s->doorbell_reply, reply, s->doorbell_reply_size * 2); 138 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT; 139 mptsas_update_interrupt(s); 140 } else { 141 mptsas_post_reply(s, reply); 142 } 143 } 144 145 static void mptsas_turbo_reply(MPTSASState *s, uint32_t msgctx) 146 { 147 if (MPTSAS_FIFO_FULL(s, reply_post)) { 148 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); 149 return; 150 } 151 152 /* The reply is just the message context ID (bit 31 = clear). */ 153 MPTSAS_FIFO_PUT(s, reply_post, msgctx); 154 155 s->intr_status |= MPI_HIS_REPLY_MESSAGE_INTERRUPT; 156 mptsas_update_interrupt(s); 157 } 158 159 #define MPTSAS_MAX_REQUEST_SIZE 52 160 161 static const int mpi_request_sizes[] = { 162 [MPI_FUNCTION_SCSI_IO_REQUEST] = sizeof(MPIMsgSCSIIORequest), 163 [MPI_FUNCTION_SCSI_TASK_MGMT] = sizeof(MPIMsgSCSITaskMgmt), 164 [MPI_FUNCTION_IOC_INIT] = sizeof(MPIMsgIOCInit), 165 [MPI_FUNCTION_IOC_FACTS] = sizeof(MPIMsgIOCFacts), 166 [MPI_FUNCTION_CONFIG] = sizeof(MPIMsgConfig), 167 [MPI_FUNCTION_PORT_FACTS] = sizeof(MPIMsgPortFacts), 168 [MPI_FUNCTION_PORT_ENABLE] = sizeof(MPIMsgPortEnable), 169 [MPI_FUNCTION_EVENT_NOTIFICATION] = sizeof(MPIMsgEventNotify), 170 }; 171 172 static dma_addr_t mptsas_ld_sg_base(MPTSASState *s, uint32_t flags_and_length, 173 dma_addr_t *sgaddr) 174 { 175 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 176 PCIDevice *pci = (PCIDevice *) s; 177 dma_addr_t addr; 178 179 if (flags_and_length & MPI_SGE_FLAGS_64_BIT_ADDRESSING) { 180 uint64_t addr64; 181 182 ldq_le_pci_dma(pci, *sgaddr + 4, &addr64, attrs); 183 addr = addr64; 184 *sgaddr += 12; 185 } else { 186 uint32_t addr32; 187 188 ldl_le_pci_dma(pci, *sgaddr + 4, &addr32, attrs); 189 addr = addr32; 190 *sgaddr += 8; 191 } 192 return addr; 193 } 194 195 static int mptsas_build_sgl(MPTSASState *s, MPTSASRequest *req, hwaddr addr) 196 { 197 PCIDevice *pci = (PCIDevice *) s; 198 hwaddr next_chain_addr; 199 uint32_t left; 200 hwaddr sgaddr; 201 uint32_t chain_offset; 202 203 chain_offset = req->scsi_io.ChainOffset; 204 next_chain_addr = addr + chain_offset * sizeof(uint32_t); 205 sgaddr = addr + sizeof(MPIMsgSCSIIORequest); 206 pci_dma_sglist_init(&req->qsg, pci, 4); 207 left = req->scsi_io.DataLength; 208 209 for(;;) { 210 dma_addr_t addr, len; 211 uint32_t flags_and_length; 212 213 ldl_le_pci_dma(pci, sgaddr, &flags_and_length, MEMTXATTRS_UNSPECIFIED); 214 len = flags_and_length & MPI_SGE_LENGTH_MASK; 215 if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK) 216 != MPI_SGE_FLAGS_SIMPLE_ELEMENT || 217 (!len && 218 !(flags_and_length & MPI_SGE_FLAGS_END_OF_LIST) && 219 !(flags_and_length & MPI_SGE_FLAGS_END_OF_BUFFER))) { 220 return MPI_IOCSTATUS_INVALID_SGL; 221 } 222 223 len = MIN(len, left); 224 if (!len) { 225 /* We reached the desired transfer length, ignore extra 226 * elements of the s/g list. 227 */ 228 break; 229 } 230 231 addr = mptsas_ld_sg_base(s, flags_and_length, &sgaddr); 232 qemu_sglist_add(&req->qsg, addr, len); 233 left -= len; 234 235 if (flags_and_length & MPI_SGE_FLAGS_END_OF_LIST) { 236 break; 237 } 238 239 if (flags_and_length & MPI_SGE_FLAGS_LAST_ELEMENT) { 240 if (!chain_offset) { 241 break; 242 } 243 244 ldl_le_pci_dma(pci, next_chain_addr, &flags_and_length, 245 MEMTXATTRS_UNSPECIFIED); 246 if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK) 247 != MPI_SGE_FLAGS_CHAIN_ELEMENT) { 248 return MPI_IOCSTATUS_INVALID_SGL; 249 } 250 251 sgaddr = mptsas_ld_sg_base(s, flags_and_length, &next_chain_addr); 252 chain_offset = 253 (flags_and_length & MPI_SGE_CHAIN_OFFSET_MASK) >> MPI_SGE_CHAIN_OFFSET_SHIFT; 254 next_chain_addr = sgaddr + chain_offset * sizeof(uint32_t); 255 } 256 } 257 return 0; 258 } 259 260 static void mptsas_free_request(MPTSASRequest *req) 261 { 262 if (req->sreq != NULL) { 263 req->sreq->hba_private = NULL; 264 scsi_req_unref(req->sreq); 265 req->sreq = NULL; 266 } 267 qemu_sglist_destroy(&req->qsg); 268 g_free(req); 269 } 270 271 static int mptsas_scsi_device_find(MPTSASState *s, int bus, int target, 272 uint8_t *lun, SCSIDevice **sdev) 273 { 274 if (bus != 0) { 275 return MPI_IOCSTATUS_SCSI_INVALID_BUS; 276 } 277 278 if (target >= s->max_devices) { 279 return MPI_IOCSTATUS_SCSI_INVALID_TARGETID; 280 } 281 282 *sdev = scsi_device_find(&s->bus, bus, target, lun[1]); 283 if (!*sdev) { 284 return MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE; 285 } 286 287 return 0; 288 } 289 290 static int mptsas_process_scsi_io_request(MPTSASState *s, 291 MPIMsgSCSIIORequest *scsi_io, 292 hwaddr addr) 293 { 294 MPTSASRequest *req; 295 MPIMsgSCSIIOReply reply; 296 SCSIDevice *sdev; 297 int status; 298 299 mptsas_fix_scsi_io_endianness(scsi_io); 300 301 trace_mptsas_process_scsi_io_request(s, scsi_io->Bus, scsi_io->TargetID, 302 scsi_io->LUN[1], scsi_io->DataLength); 303 304 status = mptsas_scsi_device_find(s, scsi_io->Bus, scsi_io->TargetID, 305 scsi_io->LUN, &sdev); 306 if (status) { 307 goto bad; 308 } 309 310 req = g_new0(MPTSASRequest, 1); 311 req->scsi_io = *scsi_io; 312 req->dev = s; 313 314 status = mptsas_build_sgl(s, req, addr); 315 if (status) { 316 goto free_bad; 317 } 318 319 if (req->qsg.size < scsi_io->DataLength) { 320 trace_mptsas_sgl_overflow(s, scsi_io->MsgContext, scsi_io->DataLength, 321 req->qsg.size); 322 status = MPI_IOCSTATUS_INVALID_SGL; 323 goto free_bad; 324 } 325 326 req->sreq = scsi_req_new(sdev, scsi_io->MsgContext, 327 scsi_io->LUN[1], scsi_io->CDB, req); 328 329 if (req->sreq->cmd.xfer > scsi_io->DataLength) { 330 goto overrun; 331 } 332 switch (scsi_io->Control & MPI_SCSIIO_CONTROL_DATADIRECTION_MASK) { 333 case MPI_SCSIIO_CONTROL_NODATATRANSFER: 334 if (req->sreq->cmd.mode != SCSI_XFER_NONE) { 335 goto overrun; 336 } 337 break; 338 339 case MPI_SCSIIO_CONTROL_WRITE: 340 if (req->sreq->cmd.mode != SCSI_XFER_TO_DEV) { 341 goto overrun; 342 } 343 break; 344 345 case MPI_SCSIIO_CONTROL_READ: 346 if (req->sreq->cmd.mode != SCSI_XFER_FROM_DEV) { 347 goto overrun; 348 } 349 break; 350 } 351 352 if (scsi_req_enqueue(req->sreq)) { 353 scsi_req_continue(req->sreq); 354 } 355 return 0; 356 357 overrun: 358 trace_mptsas_scsi_overflow(s, scsi_io->MsgContext, req->sreq->cmd.xfer, 359 scsi_io->DataLength); 360 status = MPI_IOCSTATUS_SCSI_DATA_OVERRUN; 361 free_bad: 362 mptsas_free_request(req); 363 bad: 364 memset(&reply, 0, sizeof(reply)); 365 reply.TargetID = scsi_io->TargetID; 366 reply.Bus = scsi_io->Bus; 367 reply.MsgLength = sizeof(reply) / 4; 368 reply.Function = scsi_io->Function; 369 reply.CDBLength = scsi_io->CDBLength; 370 reply.SenseBufferLength = scsi_io->SenseBufferLength; 371 reply.MsgContext = scsi_io->MsgContext; 372 reply.SCSIState = MPI_SCSI_STATE_NO_SCSI_STATUS; 373 reply.IOCStatus = status; 374 375 mptsas_fix_scsi_io_reply_endianness(&reply); 376 mptsas_reply(s, (MPIDefaultReply *)&reply); 377 378 return 0; 379 } 380 381 typedef struct { 382 Notifier notifier; 383 MPTSASState *s; 384 MPIMsgSCSITaskMgmtReply *reply; 385 } MPTSASCancelNotifier; 386 387 static void mptsas_cancel_notify(Notifier *notifier, void *data) 388 { 389 MPTSASCancelNotifier *n = container_of(notifier, 390 MPTSASCancelNotifier, 391 notifier); 392 393 /* Abusing IOCLogInfo to store the expected number of requests... */ 394 if (++n->reply->TerminationCount == n->reply->IOCLogInfo) { 395 n->reply->IOCLogInfo = 0; 396 mptsas_fix_scsi_task_mgmt_reply_endianness(n->reply); 397 mptsas_post_reply(n->s, (MPIDefaultReply *)n->reply); 398 g_free(n->reply); 399 } 400 g_free(n); 401 } 402 403 static void mptsas_process_scsi_task_mgmt(MPTSASState *s, MPIMsgSCSITaskMgmt *req) 404 { 405 MPIMsgSCSITaskMgmtReply reply; 406 MPIMsgSCSITaskMgmtReply *reply_async; 407 int status, count; 408 SCSIDevice *sdev; 409 SCSIRequest *r, *next; 410 BusChild *kid; 411 412 mptsas_fix_scsi_task_mgmt_endianness(req); 413 414 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 415 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 416 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 417 418 memset(&reply, 0, sizeof(reply)); 419 reply.TargetID = req->TargetID; 420 reply.Bus = req->Bus; 421 reply.MsgLength = sizeof(reply) / 4; 422 reply.Function = req->Function; 423 reply.TaskType = req->TaskType; 424 reply.MsgContext = req->MsgContext; 425 426 switch (req->TaskType) { 427 case MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK: 428 case MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK: 429 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID, 430 req->LUN, &sdev); 431 if (status) { 432 reply.IOCStatus = status; 433 goto out; 434 } 435 if (sdev->lun != req->LUN[1]) { 436 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN; 437 goto out; 438 } 439 440 QTAILQ_FOREACH_SAFE(r, &sdev->requests, next, next) { 441 MPTSASRequest *cmd_req = r->hba_private; 442 if (cmd_req && cmd_req->scsi_io.MsgContext == req->TaskMsgContext) { 443 break; 444 } 445 } 446 if (r) { 447 /* 448 * Assert that the request has not been completed yet, we 449 * check for it in the loop above. 450 */ 451 assert(r->hba_private); 452 if (req->TaskType == MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK) { 453 /* "If the specified command is present in the task set, then 454 * return a service response set to FUNCTION SUCCEEDED". 455 */ 456 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_SUCCEEDED; 457 } else { 458 MPTSASCancelNotifier *notifier; 459 460 reply_async = g_memdup(&reply, sizeof(MPIMsgSCSITaskMgmtReply)); 461 reply_async->IOCLogInfo = INT_MAX; 462 463 count = 1; 464 notifier = g_new(MPTSASCancelNotifier, 1); 465 notifier->s = s; 466 notifier->reply = reply_async; 467 notifier->notifier.notify = mptsas_cancel_notify; 468 scsi_req_cancel_async(r, ¬ifier->notifier); 469 goto reply_maybe_async; 470 } 471 } 472 break; 473 474 case MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 475 case MPI_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET: 476 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID, 477 req->LUN, &sdev); 478 if (status) { 479 reply.IOCStatus = status; 480 goto out; 481 } 482 if (sdev->lun != req->LUN[1]) { 483 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN; 484 goto out; 485 } 486 487 reply_async = g_memdup(&reply, sizeof(MPIMsgSCSITaskMgmtReply)); 488 reply_async->IOCLogInfo = INT_MAX; 489 490 count = 0; 491 QTAILQ_FOREACH_SAFE(r, &sdev->requests, next, next) { 492 if (r->hba_private) { 493 MPTSASCancelNotifier *notifier; 494 495 count++; 496 notifier = g_new(MPTSASCancelNotifier, 1); 497 notifier->s = s; 498 notifier->reply = reply_async; 499 notifier->notifier.notify = mptsas_cancel_notify; 500 scsi_req_cancel_async(r, ¬ifier->notifier); 501 } 502 } 503 504 reply_maybe_async: 505 if (reply_async->TerminationCount < count) { 506 reply_async->IOCLogInfo = count; 507 return; 508 } 509 g_free(reply_async); 510 reply.TerminationCount = count; 511 break; 512 513 case MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 514 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID, 515 req->LUN, &sdev); 516 if (status) { 517 reply.IOCStatus = status; 518 goto out; 519 } 520 if (sdev->lun != req->LUN[1]) { 521 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN; 522 goto out; 523 } 524 qdev_reset_all(&sdev->qdev); 525 break; 526 527 case MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 528 if (req->Bus != 0) { 529 reply.IOCStatus = MPI_IOCSTATUS_SCSI_INVALID_BUS; 530 goto out; 531 } 532 if (req->TargetID > s->max_devices) { 533 reply.IOCStatus = MPI_IOCSTATUS_SCSI_INVALID_TARGETID; 534 goto out; 535 } 536 537 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { 538 sdev = SCSI_DEVICE(kid->child); 539 if (sdev->channel == 0 && sdev->id == req->TargetID) { 540 qdev_reset_all(kid->child); 541 } 542 } 543 break; 544 545 case MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS: 546 qbus_reset_all(BUS(&s->bus)); 547 break; 548 549 default: 550 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED; 551 break; 552 } 553 554 out: 555 mptsas_fix_scsi_task_mgmt_reply_endianness(&reply); 556 mptsas_post_reply(s, (MPIDefaultReply *)&reply); 557 } 558 559 static void mptsas_process_ioc_init(MPTSASState *s, MPIMsgIOCInit *req) 560 { 561 MPIMsgIOCInitReply reply; 562 563 mptsas_fix_ioc_init_endianness(req); 564 565 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 566 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 567 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 568 569 s->who_init = req->WhoInit; 570 s->reply_frame_size = req->ReplyFrameSize; 571 s->max_buses = req->MaxBuses; 572 s->max_devices = req->MaxDevices ? req->MaxDevices : 256; 573 s->host_mfa_high_addr = (hwaddr)req->HostMfaHighAddr << 32; 574 s->sense_buffer_high_addr = (hwaddr)req->SenseBufferHighAddr << 32; 575 576 if (s->state == MPI_IOC_STATE_READY) { 577 s->state = MPI_IOC_STATE_OPERATIONAL; 578 } 579 580 memset(&reply, 0, sizeof(reply)); 581 reply.WhoInit = s->who_init; 582 reply.MsgLength = sizeof(reply) / 4; 583 reply.Function = req->Function; 584 reply.MaxDevices = s->max_devices; 585 reply.MaxBuses = s->max_buses; 586 reply.MsgContext = req->MsgContext; 587 588 mptsas_fix_ioc_init_reply_endianness(&reply); 589 mptsas_reply(s, (MPIDefaultReply *)&reply); 590 } 591 592 static void mptsas_process_ioc_facts(MPTSASState *s, 593 MPIMsgIOCFacts *req) 594 { 595 MPIMsgIOCFactsReply reply; 596 597 mptsas_fix_ioc_facts_endianness(req); 598 599 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 600 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 601 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 602 603 memset(&reply, 0, sizeof(reply)); 604 reply.MsgVersion = 0x0105; 605 reply.MsgLength = sizeof(reply) / 4; 606 reply.Function = req->Function; 607 reply.MsgContext = req->MsgContext; 608 reply.MaxChainDepth = MPTSAS_MAXIMUM_CHAIN_DEPTH; 609 reply.WhoInit = s->who_init; 610 reply.BlockSize = MPTSAS_MAX_REQUEST_SIZE / sizeof(uint32_t); 611 reply.ReplyQueueDepth = ARRAY_SIZE(s->reply_post) - 1; 612 QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->reply_post) != ARRAY_SIZE(s->reply_free)); 613 614 reply.RequestFrameSize = 128; 615 reply.ProductID = MPTSAS1068_PRODUCT_ID; 616 reply.CurrentHostMfaHighAddr = s->host_mfa_high_addr >> 32; 617 reply.GlobalCredits = ARRAY_SIZE(s->request_post) - 1; 618 reply.NumberOfPorts = MPTSAS_NUM_PORTS; 619 reply.CurrentSenseBufferHighAddr = s->sense_buffer_high_addr >> 32; 620 reply.CurReplyFrameSize = s->reply_frame_size; 621 reply.MaxDevices = s->max_devices; 622 reply.MaxBuses = s->max_buses; 623 reply.FWVersionDev = 0; 624 reply.FWVersionUnit = 0x92; 625 reply.FWVersionMinor = 0x32; 626 reply.FWVersionMajor = 0x1; 627 628 mptsas_fix_ioc_facts_reply_endianness(&reply); 629 mptsas_reply(s, (MPIDefaultReply *)&reply); 630 } 631 632 static void mptsas_process_port_facts(MPTSASState *s, 633 MPIMsgPortFacts *req) 634 { 635 MPIMsgPortFactsReply reply; 636 637 mptsas_fix_port_facts_endianness(req); 638 639 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 640 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 641 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 642 643 memset(&reply, 0, sizeof(reply)); 644 reply.MsgLength = sizeof(reply) / 4; 645 reply.Function = req->Function; 646 reply.PortNumber = req->PortNumber; 647 reply.MsgContext = req->MsgContext; 648 649 if (req->PortNumber < MPTSAS_NUM_PORTS) { 650 reply.PortType = MPI_PORTFACTS_PORTTYPE_SAS; 651 reply.MaxDevices = MPTSAS_NUM_PORTS; 652 reply.PortSCSIID = MPTSAS_NUM_PORTS; 653 reply.ProtocolFlags = MPI_PORTFACTS_PROTOCOL_LOGBUSADDR | MPI_PORTFACTS_PROTOCOL_INITIATOR; 654 } 655 656 mptsas_fix_port_facts_reply_endianness(&reply); 657 mptsas_reply(s, (MPIDefaultReply *)&reply); 658 } 659 660 static void mptsas_process_port_enable(MPTSASState *s, 661 MPIMsgPortEnable *req) 662 { 663 MPIMsgPortEnableReply reply; 664 665 mptsas_fix_port_enable_endianness(req); 666 667 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 668 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 669 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 670 671 memset(&reply, 0, sizeof(reply)); 672 reply.MsgLength = sizeof(reply) / 4; 673 reply.PortNumber = req->PortNumber; 674 reply.Function = req->Function; 675 reply.MsgContext = req->MsgContext; 676 677 mptsas_fix_port_enable_reply_endianness(&reply); 678 mptsas_reply(s, (MPIDefaultReply *)&reply); 679 } 680 681 static void mptsas_process_event_notification(MPTSASState *s, 682 MPIMsgEventNotify *req) 683 { 684 MPIMsgEventNotifyReply reply; 685 686 mptsas_fix_event_notification_endianness(req); 687 688 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 689 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 690 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 691 692 /* Don't even bother storing whether event notification is enabled, 693 * since it is not accessible. 694 */ 695 696 memset(&reply, 0, sizeof(reply)); 697 reply.EventDataLength = sizeof(reply.Data) / 4; 698 reply.MsgLength = sizeof(reply) / 4; 699 reply.Function = req->Function; 700 701 /* This is set because events are sent through the reply FIFOs. */ 702 reply.MsgFlags = MPI_MSGFLAGS_CONTINUATION_REPLY; 703 704 reply.MsgContext = req->MsgContext; 705 reply.Event = MPI_EVENT_EVENT_CHANGE; 706 reply.Data[0] = !!req->Switch; 707 708 mptsas_fix_event_notification_reply_endianness(&reply); 709 mptsas_reply(s, (MPIDefaultReply *)&reply); 710 } 711 712 static void mptsas_process_message(MPTSASState *s, MPIRequestHeader *req) 713 { 714 trace_mptsas_process_message(s, req->Function, req->MsgContext); 715 switch (req->Function) { 716 case MPI_FUNCTION_SCSI_TASK_MGMT: 717 mptsas_process_scsi_task_mgmt(s, (MPIMsgSCSITaskMgmt *)req); 718 break; 719 720 case MPI_FUNCTION_IOC_INIT: 721 mptsas_process_ioc_init(s, (MPIMsgIOCInit *)req); 722 break; 723 724 case MPI_FUNCTION_IOC_FACTS: 725 mptsas_process_ioc_facts(s, (MPIMsgIOCFacts *)req); 726 break; 727 728 case MPI_FUNCTION_PORT_FACTS: 729 mptsas_process_port_facts(s, (MPIMsgPortFacts *)req); 730 break; 731 732 case MPI_FUNCTION_PORT_ENABLE: 733 mptsas_process_port_enable(s, (MPIMsgPortEnable *)req); 734 break; 735 736 case MPI_FUNCTION_EVENT_NOTIFICATION: 737 mptsas_process_event_notification(s, (MPIMsgEventNotify *)req); 738 break; 739 740 case MPI_FUNCTION_CONFIG: 741 mptsas_process_config(s, (MPIMsgConfig *)req); 742 break; 743 744 default: 745 trace_mptsas_unhandled_cmd(s, req->Function, 0); 746 mptsas_set_fault(s, MPI_IOCSTATUS_INVALID_FUNCTION); 747 break; 748 } 749 } 750 751 static void mptsas_fetch_request(MPTSASState *s) 752 { 753 PCIDevice *pci = (PCIDevice *) s; 754 char req[MPTSAS_MAX_REQUEST_SIZE]; 755 MPIRequestHeader *hdr = (MPIRequestHeader *)req; 756 hwaddr addr; 757 int size; 758 759 /* Read the message header from the guest first. */ 760 addr = s->host_mfa_high_addr | MPTSAS_FIFO_GET(s, request_post); 761 pci_dma_read(pci, addr, req, sizeof(*hdr)); 762 763 if (hdr->Function < ARRAY_SIZE(mpi_request_sizes) && 764 mpi_request_sizes[hdr->Function]) { 765 /* Read the rest of the request based on the type. Do not 766 * reread everything, as that could cause a TOC/TOU mismatch 767 * and leak data from the QEMU stack. 768 */ 769 size = mpi_request_sizes[hdr->Function]; 770 assert(size <= MPTSAS_MAX_REQUEST_SIZE); 771 pci_dma_read(pci, addr + sizeof(*hdr), &req[sizeof(*hdr)], 772 size - sizeof(*hdr)); 773 } 774 775 if (hdr->Function == MPI_FUNCTION_SCSI_IO_REQUEST) { 776 /* SCSI I/O requests are separate from mptsas_process_message 777 * because they cannot be sent through the doorbell yet. 778 */ 779 mptsas_process_scsi_io_request(s, (MPIMsgSCSIIORequest *)req, addr); 780 } else { 781 mptsas_process_message(s, (MPIRequestHeader *)req); 782 } 783 } 784 785 static void mptsas_fetch_requests(void *opaque) 786 { 787 MPTSASState *s = opaque; 788 789 if (s->state != MPI_IOC_STATE_OPERATIONAL) { 790 mptsas_set_fault(s, MPI_IOCSTATUS_INVALID_STATE); 791 return; 792 } 793 while (!MPTSAS_FIFO_EMPTY(s, request_post)) { 794 mptsas_fetch_request(s); 795 } 796 } 797 798 static void mptsas_soft_reset(MPTSASState *s) 799 { 800 uint32_t save_mask; 801 802 trace_mptsas_reset(s); 803 804 /* Temporarily disable interrupts */ 805 save_mask = s->intr_mask; 806 s->intr_mask = MPI_HIM_DIM | MPI_HIM_RIM; 807 mptsas_update_interrupt(s); 808 809 qbus_reset_all(BUS(&s->bus)); 810 s->intr_status = 0; 811 s->intr_mask = save_mask; 812 813 s->reply_free_tail = 0; 814 s->reply_free_head = 0; 815 s->reply_post_tail = 0; 816 s->reply_post_head = 0; 817 s->request_post_tail = 0; 818 s->request_post_head = 0; 819 qemu_bh_cancel(s->request_bh); 820 821 s->state = MPI_IOC_STATE_READY; 822 } 823 824 static uint32_t mptsas_doorbell_read(MPTSASState *s) 825 { 826 uint32_t ret; 827 828 ret = (s->who_init << MPI_DOORBELL_WHO_INIT_SHIFT) & MPI_DOORBELL_WHO_INIT_MASK; 829 ret |= s->state; 830 switch (s->doorbell_state) { 831 case DOORBELL_NONE: 832 break; 833 834 case DOORBELL_WRITE: 835 ret |= MPI_DOORBELL_ACTIVE; 836 break; 837 838 case DOORBELL_READ: 839 /* Get rid of the IOC fault code. */ 840 ret &= ~MPI_DOORBELL_DATA_MASK; 841 842 assert(s->intr_status & MPI_HIS_DOORBELL_INTERRUPT); 843 assert(s->doorbell_reply_idx <= s->doorbell_reply_size); 844 845 ret |= MPI_DOORBELL_ACTIVE; 846 if (s->doorbell_reply_idx < s->doorbell_reply_size) { 847 /* For more information about this endian switch, see the 848 * commit message for commit 36b62ae ("fw_cfg: fix endianness in 849 * fw_cfg_data_mem_read() / _write()", 2015-01-16). 850 */ 851 ret |= le16_to_cpu(s->doorbell_reply[s->doorbell_reply_idx++]); 852 } 853 break; 854 855 default: 856 abort(); 857 } 858 859 return ret; 860 } 861 862 static void mptsas_doorbell_write(MPTSASState *s, uint32_t val) 863 { 864 if (s->doorbell_state == DOORBELL_WRITE) { 865 if (s->doorbell_idx < s->doorbell_cnt) { 866 /* For more information about this endian switch, see the 867 * commit message for commit 36b62ae ("fw_cfg: fix endianness in 868 * fw_cfg_data_mem_read() / _write()", 2015-01-16). 869 */ 870 s->doorbell_msg[s->doorbell_idx++] = cpu_to_le32(val); 871 if (s->doorbell_idx == s->doorbell_cnt) { 872 mptsas_process_message(s, (MPIRequestHeader *)s->doorbell_msg); 873 } 874 } 875 return; 876 } 877 878 switch ((val & MPI_DOORBELL_FUNCTION_MASK) >> MPI_DOORBELL_FUNCTION_SHIFT) { 879 case MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET: 880 mptsas_soft_reset(s); 881 break; 882 case MPI_FUNCTION_IO_UNIT_RESET: 883 break; 884 case MPI_FUNCTION_HANDSHAKE: 885 s->doorbell_state = DOORBELL_WRITE; 886 s->doorbell_idx = 0; 887 s->doorbell_cnt = (val & MPI_DOORBELL_ADD_DWORDS_MASK) 888 >> MPI_DOORBELL_ADD_DWORDS_SHIFT; 889 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT; 890 mptsas_update_interrupt(s); 891 break; 892 default: 893 trace_mptsas_unhandled_doorbell_cmd(s, val); 894 break; 895 } 896 } 897 898 static void mptsas_write_sequence_write(MPTSASState *s, uint32_t val) 899 { 900 /* If the diagnostic register is enabled, any write to this register 901 * will disable it. Otherwise, the guest has to do a magic five-write 902 * sequence. 903 */ 904 if (s->diagnostic & MPI_DIAG_DRWE) { 905 goto disable; 906 } 907 908 switch (s->diagnostic_idx) { 909 case 0: 910 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_1ST_KEY_VALUE) { 911 goto disable; 912 } 913 break; 914 case 1: 915 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_2ND_KEY_VALUE) { 916 goto disable; 917 } 918 break; 919 case 2: 920 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_3RD_KEY_VALUE) { 921 goto disable; 922 } 923 break; 924 case 3: 925 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_4TH_KEY_VALUE) { 926 goto disable; 927 } 928 break; 929 case 4: 930 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_5TH_KEY_VALUE) { 931 goto disable; 932 } 933 /* Prepare Spaceball One for departure, and change the 934 * combination on my luggage! 935 */ 936 s->diagnostic |= MPI_DIAG_DRWE; 937 break; 938 } 939 s->diagnostic_idx++; 940 return; 941 942 disable: 943 s->diagnostic &= ~MPI_DIAG_DRWE; 944 s->diagnostic_idx = 0; 945 } 946 947 static int mptsas_hard_reset(MPTSASState *s) 948 { 949 mptsas_soft_reset(s); 950 951 s->intr_mask = MPI_HIM_DIM | MPI_HIM_RIM; 952 953 s->host_mfa_high_addr = 0; 954 s->sense_buffer_high_addr = 0; 955 s->reply_frame_size = 0; 956 s->max_devices = MPTSAS_NUM_PORTS; 957 s->max_buses = 1; 958 959 return 0; 960 } 961 962 static void mptsas_interrupt_status_write(MPTSASState *s) 963 { 964 switch (s->doorbell_state) { 965 case DOORBELL_NONE: 966 case DOORBELL_WRITE: 967 s->intr_status &= ~MPI_HIS_DOORBELL_INTERRUPT; 968 break; 969 970 case DOORBELL_READ: 971 /* The reply can be read continuously, so leave the interrupt up. */ 972 assert(s->intr_status & MPI_HIS_DOORBELL_INTERRUPT); 973 if (s->doorbell_reply_idx == s->doorbell_reply_size) { 974 s->doorbell_state = DOORBELL_NONE; 975 } 976 break; 977 978 default: 979 abort(); 980 } 981 mptsas_update_interrupt(s); 982 } 983 984 static uint32_t mptsas_reply_post_read(MPTSASState *s) 985 { 986 uint32_t ret; 987 988 if (!MPTSAS_FIFO_EMPTY(s, reply_post)) { 989 ret = MPTSAS_FIFO_GET(s, reply_post); 990 } else { 991 ret = -1; 992 s->intr_status &= ~MPI_HIS_REPLY_MESSAGE_INTERRUPT; 993 mptsas_update_interrupt(s); 994 } 995 996 return ret; 997 } 998 999 static uint64_t mptsas_mmio_read(void *opaque, hwaddr addr, 1000 unsigned size) 1001 { 1002 MPTSASState *s = opaque; 1003 uint32_t ret = 0; 1004 1005 switch (addr & ~3) { 1006 case MPI_DOORBELL_OFFSET: 1007 ret = mptsas_doorbell_read(s); 1008 break; 1009 1010 case MPI_DIAGNOSTIC_OFFSET: 1011 ret = s->diagnostic; 1012 break; 1013 1014 case MPI_HOST_INTERRUPT_STATUS_OFFSET: 1015 ret = s->intr_status; 1016 break; 1017 1018 case MPI_HOST_INTERRUPT_MASK_OFFSET: 1019 ret = s->intr_mask; 1020 break; 1021 1022 case MPI_REPLY_POST_FIFO_OFFSET: 1023 ret = mptsas_reply_post_read(s); 1024 break; 1025 1026 default: 1027 trace_mptsas_mmio_unhandled_read(s, addr); 1028 break; 1029 } 1030 trace_mptsas_mmio_read(s, addr, ret); 1031 return ret; 1032 } 1033 1034 static void mptsas_mmio_write(void *opaque, hwaddr addr, 1035 uint64_t val, unsigned size) 1036 { 1037 MPTSASState *s = opaque; 1038 1039 trace_mptsas_mmio_write(s, addr, val); 1040 switch (addr) { 1041 case MPI_DOORBELL_OFFSET: 1042 mptsas_doorbell_write(s, val); 1043 break; 1044 1045 case MPI_WRITE_SEQUENCE_OFFSET: 1046 mptsas_write_sequence_write(s, val); 1047 break; 1048 1049 case MPI_DIAGNOSTIC_OFFSET: 1050 if (val & MPI_DIAG_RESET_ADAPTER) { 1051 mptsas_hard_reset(s); 1052 } 1053 break; 1054 1055 case MPI_HOST_INTERRUPT_STATUS_OFFSET: 1056 mptsas_interrupt_status_write(s); 1057 break; 1058 1059 case MPI_HOST_INTERRUPT_MASK_OFFSET: 1060 s->intr_mask = val & (MPI_HIM_RIM | MPI_HIM_DIM); 1061 mptsas_update_interrupt(s); 1062 break; 1063 1064 case MPI_REQUEST_POST_FIFO_OFFSET: 1065 if (MPTSAS_FIFO_FULL(s, request_post)) { 1066 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); 1067 } else { 1068 MPTSAS_FIFO_PUT(s, request_post, val & ~0x03); 1069 qemu_bh_schedule(s->request_bh); 1070 } 1071 break; 1072 1073 case MPI_REPLY_FREE_FIFO_OFFSET: 1074 if (MPTSAS_FIFO_FULL(s, reply_free)) { 1075 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); 1076 } else { 1077 MPTSAS_FIFO_PUT(s, reply_free, val); 1078 } 1079 break; 1080 1081 default: 1082 trace_mptsas_mmio_unhandled_write(s, addr, val); 1083 break; 1084 } 1085 } 1086 1087 static const MemoryRegionOps mptsas_mmio_ops = { 1088 .read = mptsas_mmio_read, 1089 .write = mptsas_mmio_write, 1090 .endianness = DEVICE_LITTLE_ENDIAN, 1091 .impl = { 1092 .min_access_size = 4, 1093 .max_access_size = 4, 1094 } 1095 }; 1096 1097 static const MemoryRegionOps mptsas_port_ops = { 1098 .read = mptsas_mmio_read, 1099 .write = mptsas_mmio_write, 1100 .endianness = DEVICE_LITTLE_ENDIAN, 1101 .impl = { 1102 .min_access_size = 4, 1103 .max_access_size = 4, 1104 } 1105 }; 1106 1107 static uint64_t mptsas_diag_read(void *opaque, hwaddr addr, 1108 unsigned size) 1109 { 1110 MPTSASState *s = opaque; 1111 trace_mptsas_diag_read(s, addr, 0); 1112 return 0; 1113 } 1114 1115 static void mptsas_diag_write(void *opaque, hwaddr addr, 1116 uint64_t val, unsigned size) 1117 { 1118 MPTSASState *s = opaque; 1119 trace_mptsas_diag_write(s, addr, val); 1120 } 1121 1122 static const MemoryRegionOps mptsas_diag_ops = { 1123 .read = mptsas_diag_read, 1124 .write = mptsas_diag_write, 1125 .endianness = DEVICE_LITTLE_ENDIAN, 1126 .impl = { 1127 .min_access_size = 4, 1128 .max_access_size = 4, 1129 } 1130 }; 1131 1132 static QEMUSGList *mptsas_get_sg_list(SCSIRequest *sreq) 1133 { 1134 MPTSASRequest *req = sreq->hba_private; 1135 1136 return &req->qsg; 1137 } 1138 1139 static void mptsas_command_complete(SCSIRequest *sreq, 1140 size_t resid) 1141 { 1142 MPTSASRequest *req = sreq->hba_private; 1143 MPTSASState *s = req->dev; 1144 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE]; 1145 uint8_t sense_len; 1146 1147 hwaddr sense_buffer_addr = req->dev->sense_buffer_high_addr | 1148 req->scsi_io.SenseBufferLowAddr; 1149 1150 trace_mptsas_command_complete(s, req->scsi_io.MsgContext, 1151 sreq->status, resid); 1152 1153 sense_len = scsi_req_get_sense(sreq, sense_buf, SCSI_SENSE_BUF_SIZE); 1154 if (sense_len > 0) { 1155 pci_dma_write(PCI_DEVICE(s), sense_buffer_addr, sense_buf, 1156 MIN(req->scsi_io.SenseBufferLength, sense_len)); 1157 } 1158 1159 if (sreq->status != GOOD || resid || 1160 req->dev->doorbell_state == DOORBELL_WRITE) { 1161 MPIMsgSCSIIOReply reply; 1162 1163 memset(&reply, 0, sizeof(reply)); 1164 reply.TargetID = req->scsi_io.TargetID; 1165 reply.Bus = req->scsi_io.Bus; 1166 reply.MsgLength = sizeof(reply) / 4; 1167 reply.Function = req->scsi_io.Function; 1168 reply.CDBLength = req->scsi_io.CDBLength; 1169 reply.SenseBufferLength = req->scsi_io.SenseBufferLength; 1170 reply.MsgFlags = req->scsi_io.MsgFlags; 1171 reply.MsgContext = req->scsi_io.MsgContext; 1172 reply.SCSIStatus = sreq->status; 1173 if (sreq->status == GOOD) { 1174 reply.TransferCount = req->scsi_io.DataLength - resid; 1175 if (resid) { 1176 reply.IOCStatus = MPI_IOCSTATUS_SCSI_DATA_UNDERRUN; 1177 } 1178 } else { 1179 reply.SCSIState = MPI_SCSI_STATE_AUTOSENSE_VALID; 1180 reply.SenseCount = sense_len; 1181 reply.IOCStatus = MPI_IOCSTATUS_SCSI_DATA_UNDERRUN; 1182 } 1183 1184 mptsas_fix_scsi_io_reply_endianness(&reply); 1185 mptsas_post_reply(req->dev, (MPIDefaultReply *)&reply); 1186 } else { 1187 mptsas_turbo_reply(req->dev, req->scsi_io.MsgContext); 1188 } 1189 1190 mptsas_free_request(req); 1191 } 1192 1193 static void mptsas_request_cancelled(SCSIRequest *sreq) 1194 { 1195 MPTSASRequest *req = sreq->hba_private; 1196 MPIMsgSCSIIOReply reply; 1197 1198 memset(&reply, 0, sizeof(reply)); 1199 reply.TargetID = req->scsi_io.TargetID; 1200 reply.Bus = req->scsi_io.Bus; 1201 reply.MsgLength = sizeof(reply) / 4; 1202 reply.Function = req->scsi_io.Function; 1203 reply.CDBLength = req->scsi_io.CDBLength; 1204 reply.SenseBufferLength = req->scsi_io.SenseBufferLength; 1205 reply.MsgFlags = req->scsi_io.MsgFlags; 1206 reply.MsgContext = req->scsi_io.MsgContext; 1207 reply.SCSIState = MPI_SCSI_STATE_NO_SCSI_STATUS; 1208 reply.IOCStatus = MPI_IOCSTATUS_SCSI_TASK_TERMINATED; 1209 1210 mptsas_fix_scsi_io_reply_endianness(&reply); 1211 mptsas_post_reply(req->dev, (MPIDefaultReply *)&reply); 1212 mptsas_free_request(req); 1213 } 1214 1215 static void mptsas_save_request(QEMUFile *f, SCSIRequest *sreq) 1216 { 1217 MPTSASRequest *req = sreq->hba_private; 1218 int i; 1219 1220 qemu_put_buffer(f, (unsigned char *)&req->scsi_io, sizeof(req->scsi_io)); 1221 qemu_put_be32(f, req->qsg.nsg); 1222 for (i = 0; i < req->qsg.nsg; i++) { 1223 qemu_put_be64(f, req->qsg.sg[i].base); 1224 qemu_put_be64(f, req->qsg.sg[i].len); 1225 } 1226 } 1227 1228 static void *mptsas_load_request(QEMUFile *f, SCSIRequest *sreq) 1229 { 1230 SCSIBus *bus = sreq->bus; 1231 MPTSASState *s = container_of(bus, MPTSASState, bus); 1232 PCIDevice *pci = PCI_DEVICE(s); 1233 MPTSASRequest *req; 1234 int i, n; 1235 1236 req = g_new(MPTSASRequest, 1); 1237 qemu_get_buffer(f, (unsigned char *)&req->scsi_io, sizeof(req->scsi_io)); 1238 1239 n = qemu_get_be32(f); 1240 /* TODO: add a way for SCSIBusInfo's load_request to fail, 1241 * and fail migration instead of asserting here. 1242 * This is just one thing (there are probably more) that must be 1243 * fixed before we can allow NDEBUG compilation. 1244 */ 1245 assert(n >= 0); 1246 1247 pci_dma_sglist_init(&req->qsg, pci, n); 1248 for (i = 0; i < n; i++) { 1249 uint64_t base = qemu_get_be64(f); 1250 uint64_t len = qemu_get_be64(f); 1251 qemu_sglist_add(&req->qsg, base, len); 1252 } 1253 1254 scsi_req_ref(sreq); 1255 req->sreq = sreq; 1256 req->dev = s; 1257 1258 return req; 1259 } 1260 1261 static const struct SCSIBusInfo mptsas_scsi_info = { 1262 .tcq = true, 1263 .max_target = MPTSAS_NUM_PORTS, 1264 .max_lun = 1, 1265 1266 .get_sg_list = mptsas_get_sg_list, 1267 .complete = mptsas_command_complete, 1268 .cancel = mptsas_request_cancelled, 1269 .save_request = mptsas_save_request, 1270 .load_request = mptsas_load_request, 1271 }; 1272 1273 static void mptsas_scsi_realize(PCIDevice *dev, Error **errp) 1274 { 1275 MPTSASState *s = MPT_SAS(dev); 1276 Error *err = NULL; 1277 int ret; 1278 1279 dev->config[PCI_LATENCY_TIMER] = 0; 1280 dev->config[PCI_INTERRUPT_PIN] = 0x01; 1281 1282 if (s->msi != ON_OFF_AUTO_OFF) { 1283 ret = msi_init(dev, 0, 1, true, false, &err); 1284 /* Any error other than -ENOTSUP(board's MSI support is broken) 1285 * is a programming error */ 1286 assert(!ret || ret == -ENOTSUP); 1287 if (ret && s->msi == ON_OFF_AUTO_ON) { 1288 /* Can't satisfy user's explicit msi=on request, fail */ 1289 error_append_hint(&err, "You have to use msi=auto (default) or " 1290 "msi=off with this machine type.\n"); 1291 error_propagate(errp, err); 1292 return; 1293 } 1294 assert(!err || s->msi == ON_OFF_AUTO_AUTO); 1295 /* With msi=auto, we fall back to MSI off silently */ 1296 error_free(err); 1297 1298 /* Only used for migration. */ 1299 s->msi_in_use = (ret == 0); 1300 } 1301 1302 memory_region_init_io(&s->mmio_io, OBJECT(s), &mptsas_mmio_ops, s, 1303 "mptsas-mmio", 0x4000); 1304 memory_region_init_io(&s->port_io, OBJECT(s), &mptsas_port_ops, s, 1305 "mptsas-io", 256); 1306 memory_region_init_io(&s->diag_io, OBJECT(s), &mptsas_diag_ops, s, 1307 "mptsas-diag", 0x10000); 1308 1309 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->port_io); 1310 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY | 1311 PCI_BASE_ADDRESS_MEM_TYPE_32, &s->mmio_io); 1312 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY | 1313 PCI_BASE_ADDRESS_MEM_TYPE_32, &s->diag_io); 1314 1315 if (!s->sas_addr) { 1316 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) | 1317 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36; 1318 s->sas_addr |= (pci_dev_bus_num(dev) << 16); 1319 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8); 1320 s->sas_addr |= PCI_FUNC(dev->devfn); 1321 } 1322 s->max_devices = MPTSAS_NUM_PORTS; 1323 1324 s->request_bh = qemu_bh_new(mptsas_fetch_requests, s); 1325 1326 scsi_bus_init(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info); 1327 } 1328 1329 static void mptsas_scsi_uninit(PCIDevice *dev) 1330 { 1331 MPTSASState *s = MPT_SAS(dev); 1332 1333 qemu_bh_delete(s->request_bh); 1334 msi_uninit(dev); 1335 } 1336 1337 static void mptsas_reset(DeviceState *dev) 1338 { 1339 MPTSASState *s = MPT_SAS(dev); 1340 1341 mptsas_hard_reset(s); 1342 } 1343 1344 static int mptsas_post_load(void *opaque, int version_id) 1345 { 1346 MPTSASState *s = opaque; 1347 1348 if (s->doorbell_idx > s->doorbell_cnt || 1349 s->doorbell_cnt > ARRAY_SIZE(s->doorbell_msg) || 1350 s->doorbell_reply_idx > s->doorbell_reply_size || 1351 s->doorbell_reply_size > ARRAY_SIZE(s->doorbell_reply) || 1352 MPTSAS_FIFO_INVALID(s, request_post) || 1353 MPTSAS_FIFO_INVALID(s, reply_post) || 1354 MPTSAS_FIFO_INVALID(s, reply_free) || 1355 s->diagnostic_idx > 4) { 1356 return -EINVAL; 1357 } 1358 1359 return 0; 1360 } 1361 1362 static const VMStateDescription vmstate_mptsas = { 1363 .name = "mptsas", 1364 .version_id = 0, 1365 .minimum_version_id = 0, 1366 .post_load = mptsas_post_load, 1367 .fields = (VMStateField[]) { 1368 VMSTATE_PCI_DEVICE(dev, MPTSASState), 1369 VMSTATE_BOOL(msi_in_use, MPTSASState), 1370 VMSTATE_UINT32(state, MPTSASState), 1371 VMSTATE_UINT8(who_init, MPTSASState), 1372 VMSTATE_UINT8(doorbell_state, MPTSASState), 1373 VMSTATE_UINT32_ARRAY(doorbell_msg, MPTSASState, 256), 1374 VMSTATE_INT32(doorbell_idx, MPTSASState), 1375 VMSTATE_INT32(doorbell_cnt, MPTSASState), 1376 1377 VMSTATE_UINT16_ARRAY(doorbell_reply, MPTSASState, 256), 1378 VMSTATE_INT32(doorbell_reply_idx, MPTSASState), 1379 VMSTATE_INT32(doorbell_reply_size, MPTSASState), 1380 1381 VMSTATE_UINT32(diagnostic, MPTSASState), 1382 VMSTATE_UINT8(diagnostic_idx, MPTSASState), 1383 1384 VMSTATE_UINT32(intr_status, MPTSASState), 1385 VMSTATE_UINT32(intr_mask, MPTSASState), 1386 1387 VMSTATE_UINT32_ARRAY(request_post, MPTSASState, 1388 MPTSAS_REQUEST_QUEUE_DEPTH + 1), 1389 VMSTATE_UINT16(request_post_head, MPTSASState), 1390 VMSTATE_UINT16(request_post_tail, MPTSASState), 1391 1392 VMSTATE_UINT32_ARRAY(reply_post, MPTSASState, 1393 MPTSAS_REPLY_QUEUE_DEPTH + 1), 1394 VMSTATE_UINT16(reply_post_head, MPTSASState), 1395 VMSTATE_UINT16(reply_post_tail, MPTSASState), 1396 1397 VMSTATE_UINT32_ARRAY(reply_free, MPTSASState, 1398 MPTSAS_REPLY_QUEUE_DEPTH + 1), 1399 VMSTATE_UINT16(reply_free_head, MPTSASState), 1400 VMSTATE_UINT16(reply_free_tail, MPTSASState), 1401 1402 VMSTATE_UINT16(max_buses, MPTSASState), 1403 VMSTATE_UINT16(max_devices, MPTSASState), 1404 VMSTATE_UINT16(reply_frame_size, MPTSASState), 1405 VMSTATE_UINT64(host_mfa_high_addr, MPTSASState), 1406 VMSTATE_UINT64(sense_buffer_high_addr, MPTSASState), 1407 VMSTATE_END_OF_LIST() 1408 } 1409 }; 1410 1411 static Property mptsas_properties[] = { 1412 DEFINE_PROP_UINT64("sas_address", MPTSASState, sas_addr, 0), 1413 /* TODO: test MSI support under Windows */ 1414 DEFINE_PROP_ON_OFF_AUTO("msi", MPTSASState, msi, ON_OFF_AUTO_AUTO), 1415 DEFINE_PROP_END_OF_LIST(), 1416 }; 1417 1418 static void mptsas1068_class_init(ObjectClass *oc, void *data) 1419 { 1420 DeviceClass *dc = DEVICE_CLASS(oc); 1421 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc); 1422 1423 pc->realize = mptsas_scsi_realize; 1424 pc->exit = mptsas_scsi_uninit; 1425 pc->romfile = 0; 1426 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC; 1427 pc->device_id = PCI_DEVICE_ID_LSI_SAS1068; 1428 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC; 1429 pc->subsystem_id = 0x8000; 1430 pc->class_id = PCI_CLASS_STORAGE_SCSI; 1431 device_class_set_props(dc, mptsas_properties); 1432 dc->reset = mptsas_reset; 1433 dc->vmsd = &vmstate_mptsas; 1434 dc->desc = "LSI SAS 1068"; 1435 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1436 } 1437 1438 static const TypeInfo mptsas_info = { 1439 .name = TYPE_MPTSAS1068, 1440 .parent = TYPE_PCI_DEVICE, 1441 .instance_size = sizeof(MPTSASState), 1442 .class_init = mptsas1068_class_init, 1443 .interfaces = (InterfaceInfo[]) { 1444 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1445 { }, 1446 }, 1447 }; 1448 1449 static void mptsas_register_types(void) 1450 { 1451 type_register(&mptsas_info); 1452 } 1453 1454 type_init(mptsas_register_types) 1455