1 /* 2 * QEMU LSI SAS1068 Host Bus Adapter emulation 3 * Based on the QEMU Megaraid emulator 4 * 5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs 6 * Copyright (c) 2012 Verizon, Inc. 7 * Copyright (c) 2016 Red Hat, Inc. 8 * 9 * Authors: Don Slutz, Paolo Bonzini 10 * 11 * This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU Lesser General Public 13 * License as published by the Free Software Foundation; either 14 * version 2 of the License, or (at your option) any later version. 15 * 16 * This library is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * Lesser General Public License for more details. 20 * 21 * You should have received a copy of the GNU Lesser General Public 22 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/pci/pci.h" 28 #include "sysemu/dma.h" 29 #include "sysemu/block-backend.h" 30 #include "hw/pci/msi.h" 31 #include "qemu/iov.h" 32 #include "hw/scsi/scsi.h" 33 #include "block/scsi.h" 34 #include "trace.h" 35 36 #include "mptsas.h" 37 #include "mpi.h" 38 39 #define NAA_LOCALLY_ASSIGNED_ID 0x3ULL 40 #define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400 41 42 #define TYPE_MPTSAS1068 "mptsas1068" 43 44 #define MPT_SAS(obj) \ 45 OBJECT_CHECK(MPTSASState, (obj), TYPE_MPTSAS1068) 46 47 #define MPTSAS1068_PRODUCT_ID \ 48 (MPI_FW_HEADER_PID_FAMILY_1068_SAS | \ 49 MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI | \ 50 MPI_FW_HEADER_PID_TYPE_SAS) 51 52 struct MPTSASRequest { 53 MPIMsgSCSIIORequest scsi_io; 54 SCSIRequest *sreq; 55 QEMUSGList qsg; 56 MPTSASState *dev; 57 58 QTAILQ_ENTRY(MPTSASRequest) next; 59 }; 60 61 static void mptsas_update_interrupt(MPTSASState *s) 62 { 63 PCIDevice *pci = (PCIDevice *) s; 64 uint32_t state = s->intr_status & ~(s->intr_mask | MPI_HIS_IOP_DOORBELL_STATUS); 65 66 if (s->msi_in_use && msi_enabled(pci)) { 67 if (state) { 68 trace_mptsas_irq_msi(s); 69 msi_notify(pci, 0); 70 } 71 } 72 73 trace_mptsas_irq_intx(s, !!state); 74 pci_set_irq(pci, !!state); 75 } 76 77 static void mptsas_set_fault(MPTSASState *s, uint32_t code) 78 { 79 if ((s->state & MPI_IOC_STATE_FAULT) == 0) { 80 s->state = MPI_IOC_STATE_FAULT | code; 81 } 82 } 83 84 #define MPTSAS_FIFO_INVALID(s, name) \ 85 ((s)->name##_head > ARRAY_SIZE((s)->name) || \ 86 (s)->name##_tail > ARRAY_SIZE((s)->name)) 87 88 #define MPTSAS_FIFO_EMPTY(s, name) \ 89 ((s)->name##_head == (s)->name##_tail) 90 91 #define MPTSAS_FIFO_FULL(s, name) \ 92 ((s)->name##_head == ((s)->name##_tail + 1) % ARRAY_SIZE((s)->name)) 93 94 #define MPTSAS_FIFO_GET(s, name) ({ \ 95 uint32_t _val = (s)->name[(s)->name##_head++]; \ 96 (s)->name##_head %= ARRAY_SIZE((s)->name); \ 97 _val; \ 98 }) 99 100 #define MPTSAS_FIFO_PUT(s, name, val) do { \ 101 (s)->name[(s)->name##_tail++] = (val); \ 102 (s)->name##_tail %= ARRAY_SIZE((s)->name); \ 103 } while(0) 104 105 static void mptsas_post_reply(MPTSASState *s, MPIDefaultReply *reply) 106 { 107 PCIDevice *pci = (PCIDevice *) s; 108 uint32_t addr_lo; 109 110 if (MPTSAS_FIFO_EMPTY(s, reply_free) || MPTSAS_FIFO_FULL(s, reply_post)) { 111 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); 112 return; 113 } 114 115 addr_lo = MPTSAS_FIFO_GET(s, reply_free); 116 117 pci_dma_write(pci, addr_lo | s->host_mfa_high_addr, reply, 118 MIN(s->reply_frame_size, 4 * reply->MsgLength)); 119 120 MPTSAS_FIFO_PUT(s, reply_post, MPI_ADDRESS_REPLY_A_BIT | (addr_lo >> 1)); 121 122 s->intr_status |= MPI_HIS_REPLY_MESSAGE_INTERRUPT; 123 if (s->doorbell_state == DOORBELL_WRITE) { 124 s->doorbell_state = DOORBELL_NONE; 125 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT; 126 } 127 mptsas_update_interrupt(s); 128 } 129 130 void mptsas_reply(MPTSASState *s, MPIDefaultReply *reply) 131 { 132 if (s->doorbell_state == DOORBELL_WRITE) { 133 /* The reply is sent out in 16 bit chunks, while the size 134 * in the reply is in 32 bit units. 135 */ 136 s->doorbell_state = DOORBELL_READ; 137 s->doorbell_reply_idx = 0; 138 s->doorbell_reply_size = reply->MsgLength * 2; 139 memcpy(s->doorbell_reply, reply, s->doorbell_reply_size * 2); 140 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT; 141 mptsas_update_interrupt(s); 142 } else { 143 mptsas_post_reply(s, reply); 144 } 145 } 146 147 static void mptsas_turbo_reply(MPTSASState *s, uint32_t msgctx) 148 { 149 if (MPTSAS_FIFO_FULL(s, reply_post)) { 150 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); 151 return; 152 } 153 154 /* The reply is just the message context ID (bit 31 = clear). */ 155 MPTSAS_FIFO_PUT(s, reply_post, msgctx); 156 157 s->intr_status |= MPI_HIS_REPLY_MESSAGE_INTERRUPT; 158 mptsas_update_interrupt(s); 159 } 160 161 #define MPTSAS_MAX_REQUEST_SIZE 52 162 163 static const int mpi_request_sizes[] = { 164 [MPI_FUNCTION_SCSI_IO_REQUEST] = sizeof(MPIMsgSCSIIORequest), 165 [MPI_FUNCTION_SCSI_TASK_MGMT] = sizeof(MPIMsgSCSITaskMgmt), 166 [MPI_FUNCTION_IOC_INIT] = sizeof(MPIMsgIOCInit), 167 [MPI_FUNCTION_IOC_FACTS] = sizeof(MPIMsgIOCFacts), 168 [MPI_FUNCTION_CONFIG] = sizeof(MPIMsgConfig), 169 [MPI_FUNCTION_PORT_FACTS] = sizeof(MPIMsgPortFacts), 170 [MPI_FUNCTION_PORT_ENABLE] = sizeof(MPIMsgPortEnable), 171 [MPI_FUNCTION_EVENT_NOTIFICATION] = sizeof(MPIMsgEventNotify), 172 }; 173 174 static dma_addr_t mptsas_ld_sg_base(MPTSASState *s, uint32_t flags_and_length, 175 dma_addr_t *sgaddr) 176 { 177 PCIDevice *pci = (PCIDevice *) s; 178 dma_addr_t addr; 179 180 if (flags_and_length & MPI_SGE_FLAGS_64_BIT_ADDRESSING) { 181 addr = ldq_le_pci_dma(pci, *sgaddr + 4); 182 *sgaddr += 12; 183 } else { 184 addr = ldl_le_pci_dma(pci, *sgaddr + 4); 185 *sgaddr += 8; 186 } 187 return addr; 188 } 189 190 static int mptsas_build_sgl(MPTSASState *s, MPTSASRequest *req, hwaddr addr) 191 { 192 PCIDevice *pci = (PCIDevice *) s; 193 hwaddr next_chain_addr; 194 uint32_t left; 195 hwaddr sgaddr; 196 uint32_t chain_offset; 197 198 chain_offset = req->scsi_io.ChainOffset; 199 next_chain_addr = addr + chain_offset * sizeof(uint32_t); 200 sgaddr = addr + sizeof(MPIMsgSCSIIORequest); 201 pci_dma_sglist_init(&req->qsg, pci, 4); 202 left = req->scsi_io.DataLength; 203 204 for(;;) { 205 dma_addr_t addr, len; 206 uint32_t flags_and_length; 207 208 flags_and_length = ldl_le_pci_dma(pci, sgaddr); 209 len = flags_and_length & MPI_SGE_LENGTH_MASK; 210 if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK) 211 != MPI_SGE_FLAGS_SIMPLE_ELEMENT || 212 (!len && 213 !(flags_and_length & MPI_SGE_FLAGS_END_OF_LIST) && 214 !(flags_and_length & MPI_SGE_FLAGS_END_OF_BUFFER))) { 215 return MPI_IOCSTATUS_INVALID_SGL; 216 } 217 218 len = MIN(len, left); 219 if (!len) { 220 /* We reached the desired transfer length, ignore extra 221 * elements of the s/g list. 222 */ 223 break; 224 } 225 226 addr = mptsas_ld_sg_base(s, flags_and_length, &sgaddr); 227 qemu_sglist_add(&req->qsg, addr, len); 228 left -= len; 229 230 if (flags_and_length & MPI_SGE_FLAGS_END_OF_LIST) { 231 break; 232 } 233 234 if (flags_and_length & MPI_SGE_FLAGS_LAST_ELEMENT) { 235 if (!chain_offset) { 236 break; 237 } 238 239 flags_and_length = ldl_le_pci_dma(pci, next_chain_addr); 240 if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK) 241 != MPI_SGE_FLAGS_CHAIN_ELEMENT) { 242 return MPI_IOCSTATUS_INVALID_SGL; 243 } 244 245 sgaddr = mptsas_ld_sg_base(s, flags_and_length, &next_chain_addr); 246 chain_offset = 247 (flags_and_length & MPI_SGE_CHAIN_OFFSET_MASK) >> MPI_SGE_CHAIN_OFFSET_SHIFT; 248 next_chain_addr = sgaddr + chain_offset * sizeof(uint32_t); 249 } 250 } 251 return 0; 252 } 253 254 static void mptsas_free_request(MPTSASRequest *req) 255 { 256 MPTSASState *s = req->dev; 257 258 if (req->sreq != NULL) { 259 req->sreq->hba_private = NULL; 260 scsi_req_unref(req->sreq); 261 req->sreq = NULL; 262 QTAILQ_REMOVE(&s->pending, req, next); 263 } 264 qemu_sglist_destroy(&req->qsg); 265 g_free(req); 266 } 267 268 static int mptsas_scsi_device_find(MPTSASState *s, int bus, int target, 269 uint8_t *lun, SCSIDevice **sdev) 270 { 271 if (bus != 0) { 272 return MPI_IOCSTATUS_SCSI_INVALID_BUS; 273 } 274 275 if (target >= s->max_devices) { 276 return MPI_IOCSTATUS_SCSI_INVALID_TARGETID; 277 } 278 279 *sdev = scsi_device_find(&s->bus, bus, target, lun[1]); 280 if (!*sdev) { 281 return MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE; 282 } 283 284 return 0; 285 } 286 287 static int mptsas_process_scsi_io_request(MPTSASState *s, 288 MPIMsgSCSIIORequest *scsi_io, 289 hwaddr addr) 290 { 291 MPTSASRequest *req; 292 MPIMsgSCSIIOReply reply; 293 SCSIDevice *sdev; 294 int status; 295 296 mptsas_fix_scsi_io_endianness(scsi_io); 297 298 trace_mptsas_process_scsi_io_request(s, scsi_io->Bus, scsi_io->TargetID, 299 scsi_io->LUN[1], scsi_io->DataLength); 300 301 status = mptsas_scsi_device_find(s, scsi_io->Bus, scsi_io->TargetID, 302 scsi_io->LUN, &sdev); 303 if (status) { 304 goto bad; 305 } 306 307 req = g_new(MPTSASRequest, 1); 308 QTAILQ_INSERT_TAIL(&s->pending, req, next); 309 req->scsi_io = *scsi_io; 310 req->dev = s; 311 312 status = mptsas_build_sgl(s, req, addr); 313 if (status) { 314 goto free_bad; 315 } 316 317 if (req->qsg.size < scsi_io->DataLength) { 318 trace_mptsas_sgl_overflow(s, scsi_io->MsgContext, scsi_io->DataLength, 319 req->qsg.size); 320 status = MPI_IOCSTATUS_INVALID_SGL; 321 goto free_bad; 322 } 323 324 req->sreq = scsi_req_new(sdev, scsi_io->MsgContext, 325 scsi_io->LUN[1], scsi_io->CDB, req); 326 327 if (req->sreq->cmd.xfer > scsi_io->DataLength) { 328 goto overrun; 329 } 330 switch (scsi_io->Control & MPI_SCSIIO_CONTROL_DATADIRECTION_MASK) { 331 case MPI_SCSIIO_CONTROL_NODATATRANSFER: 332 if (req->sreq->cmd.mode != SCSI_XFER_NONE) { 333 goto overrun; 334 } 335 break; 336 337 case MPI_SCSIIO_CONTROL_WRITE: 338 if (req->sreq->cmd.mode != SCSI_XFER_TO_DEV) { 339 goto overrun; 340 } 341 break; 342 343 case MPI_SCSIIO_CONTROL_READ: 344 if (req->sreq->cmd.mode != SCSI_XFER_FROM_DEV) { 345 goto overrun; 346 } 347 break; 348 } 349 350 if (scsi_req_enqueue(req->sreq)) { 351 scsi_req_continue(req->sreq); 352 } 353 return 0; 354 355 overrun: 356 trace_mptsas_scsi_overflow(s, scsi_io->MsgContext, req->sreq->cmd.xfer, 357 scsi_io->DataLength); 358 status = MPI_IOCSTATUS_SCSI_DATA_OVERRUN; 359 free_bad: 360 mptsas_free_request(req); 361 bad: 362 memset(&reply, 0, sizeof(reply)); 363 reply.TargetID = scsi_io->TargetID; 364 reply.Bus = scsi_io->Bus; 365 reply.MsgLength = sizeof(reply) / 4; 366 reply.Function = scsi_io->Function; 367 reply.CDBLength = scsi_io->CDBLength; 368 reply.SenseBufferLength = scsi_io->SenseBufferLength; 369 reply.MsgContext = scsi_io->MsgContext; 370 reply.SCSIState = MPI_SCSI_STATE_NO_SCSI_STATUS; 371 reply.IOCStatus = status; 372 373 mptsas_fix_scsi_io_reply_endianness(&reply); 374 mptsas_reply(s, (MPIDefaultReply *)&reply); 375 376 return 0; 377 } 378 379 typedef struct { 380 Notifier notifier; 381 MPTSASState *s; 382 MPIMsgSCSITaskMgmtReply *reply; 383 } MPTSASCancelNotifier; 384 385 static void mptsas_cancel_notify(Notifier *notifier, void *data) 386 { 387 MPTSASCancelNotifier *n = container_of(notifier, 388 MPTSASCancelNotifier, 389 notifier); 390 391 /* Abusing IOCLogInfo to store the expected number of requests... */ 392 if (++n->reply->TerminationCount == n->reply->IOCLogInfo) { 393 n->reply->IOCLogInfo = 0; 394 mptsas_fix_scsi_task_mgmt_reply_endianness(n->reply); 395 mptsas_post_reply(n->s, (MPIDefaultReply *)n->reply); 396 g_free(n->reply); 397 } 398 g_free(n); 399 } 400 401 static void mptsas_process_scsi_task_mgmt(MPTSASState *s, MPIMsgSCSITaskMgmt *req) 402 { 403 MPIMsgSCSITaskMgmtReply reply; 404 MPIMsgSCSITaskMgmtReply *reply_async; 405 int status, count; 406 SCSIDevice *sdev; 407 SCSIRequest *r, *next; 408 BusChild *kid; 409 410 mptsas_fix_scsi_task_mgmt_endianness(req); 411 412 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 413 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 414 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 415 416 memset(&reply, 0, sizeof(reply)); 417 reply.TargetID = req->TargetID; 418 reply.Bus = req->Bus; 419 reply.MsgLength = sizeof(reply) / 4; 420 reply.Function = req->Function; 421 reply.TaskType = req->TaskType; 422 reply.MsgContext = req->MsgContext; 423 424 switch (req->TaskType) { 425 case MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK: 426 case MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK: 427 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID, 428 req->LUN, &sdev); 429 if (status) { 430 reply.IOCStatus = status; 431 goto out; 432 } 433 if (sdev->lun != req->LUN[1]) { 434 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN; 435 goto out; 436 } 437 438 QTAILQ_FOREACH_SAFE(r, &sdev->requests, next, next) { 439 MPTSASRequest *cmd_req = r->hba_private; 440 if (cmd_req && cmd_req->scsi_io.MsgContext == req->TaskMsgContext) { 441 break; 442 } 443 } 444 if (r) { 445 /* 446 * Assert that the request has not been completed yet, we 447 * check for it in the loop above. 448 */ 449 assert(r->hba_private); 450 if (req->TaskType == MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK) { 451 /* "If the specified command is present in the task set, then 452 * return a service response set to FUNCTION SUCCEEDED". 453 */ 454 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_SUCCEEDED; 455 } else { 456 MPTSASCancelNotifier *notifier; 457 458 reply_async = g_memdup(&reply, sizeof(MPIMsgSCSITaskMgmtReply)); 459 reply_async->IOCLogInfo = INT_MAX; 460 461 count = 1; 462 notifier = g_new(MPTSASCancelNotifier, 1); 463 notifier->s = s; 464 notifier->reply = reply_async; 465 notifier->notifier.notify = mptsas_cancel_notify; 466 scsi_req_cancel_async(r, ¬ifier->notifier); 467 goto reply_maybe_async; 468 } 469 } 470 break; 471 472 case MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 473 case MPI_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET: 474 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID, 475 req->LUN, &sdev); 476 if (status) { 477 reply.IOCStatus = status; 478 goto out; 479 } 480 if (sdev->lun != req->LUN[1]) { 481 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN; 482 goto out; 483 } 484 485 reply_async = g_memdup(&reply, sizeof(MPIMsgSCSITaskMgmtReply)); 486 reply_async->IOCLogInfo = INT_MAX; 487 488 count = 0; 489 QTAILQ_FOREACH_SAFE(r, &sdev->requests, next, next) { 490 if (r->hba_private) { 491 MPTSASCancelNotifier *notifier; 492 493 count++; 494 notifier = g_new(MPTSASCancelNotifier, 1); 495 notifier->s = s; 496 notifier->reply = reply_async; 497 notifier->notifier.notify = mptsas_cancel_notify; 498 scsi_req_cancel_async(r, ¬ifier->notifier); 499 } 500 } 501 502 reply_maybe_async: 503 if (reply_async->TerminationCount < count) { 504 reply_async->IOCLogInfo = count; 505 return; 506 } 507 g_free(reply_async); 508 reply.TerminationCount = count; 509 break; 510 511 case MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 512 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID, 513 req->LUN, &sdev); 514 if (status) { 515 reply.IOCStatus = status; 516 goto out; 517 } 518 if (sdev->lun != req->LUN[1]) { 519 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN; 520 goto out; 521 } 522 qdev_reset_all(&sdev->qdev); 523 break; 524 525 case MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 526 if (req->Bus != 0) { 527 reply.IOCStatus = MPI_IOCSTATUS_SCSI_INVALID_BUS; 528 goto out; 529 } 530 if (req->TargetID > s->max_devices) { 531 reply.IOCStatus = MPI_IOCSTATUS_SCSI_INVALID_TARGETID; 532 goto out; 533 } 534 535 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { 536 sdev = SCSI_DEVICE(kid->child); 537 if (sdev->channel == 0 && sdev->id == req->TargetID) { 538 qdev_reset_all(kid->child); 539 } 540 } 541 break; 542 543 case MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS: 544 qbus_reset_all(&s->bus.qbus); 545 break; 546 547 default: 548 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED; 549 break; 550 } 551 552 out: 553 mptsas_fix_scsi_task_mgmt_reply_endianness(&reply); 554 mptsas_post_reply(s, (MPIDefaultReply *)&reply); 555 } 556 557 static void mptsas_process_ioc_init(MPTSASState *s, MPIMsgIOCInit *req) 558 { 559 MPIMsgIOCInitReply reply; 560 561 mptsas_fix_ioc_init_endianness(req); 562 563 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 564 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 565 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 566 567 s->who_init = req->WhoInit; 568 s->reply_frame_size = req->ReplyFrameSize; 569 s->max_buses = req->MaxBuses; 570 s->max_devices = req->MaxDevices ? req->MaxDevices : 256; 571 s->host_mfa_high_addr = (hwaddr)req->HostMfaHighAddr << 32; 572 s->sense_buffer_high_addr = (hwaddr)req->SenseBufferHighAddr << 32; 573 574 if (s->state == MPI_IOC_STATE_READY) { 575 s->state = MPI_IOC_STATE_OPERATIONAL; 576 } 577 578 memset(&reply, 0, sizeof(reply)); 579 reply.WhoInit = s->who_init; 580 reply.MsgLength = sizeof(reply) / 4; 581 reply.Function = req->Function; 582 reply.MaxDevices = s->max_devices; 583 reply.MaxBuses = s->max_buses; 584 reply.MsgContext = req->MsgContext; 585 586 mptsas_fix_ioc_init_reply_endianness(&reply); 587 mptsas_reply(s, (MPIDefaultReply *)&reply); 588 } 589 590 static void mptsas_process_ioc_facts(MPTSASState *s, 591 MPIMsgIOCFacts *req) 592 { 593 MPIMsgIOCFactsReply reply; 594 595 mptsas_fix_ioc_facts_endianness(req); 596 597 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 598 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 599 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 600 601 memset(&reply, 0, sizeof(reply)); 602 reply.MsgVersion = 0x0105; 603 reply.MsgLength = sizeof(reply) / 4; 604 reply.Function = req->Function; 605 reply.MsgContext = req->MsgContext; 606 reply.MaxChainDepth = MPTSAS_MAXIMUM_CHAIN_DEPTH; 607 reply.WhoInit = s->who_init; 608 reply.BlockSize = MPTSAS_MAX_REQUEST_SIZE / sizeof(uint32_t); 609 reply.ReplyQueueDepth = ARRAY_SIZE(s->reply_post) - 1; 610 QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->reply_post) != ARRAY_SIZE(s->reply_free)); 611 612 reply.RequestFrameSize = 128; 613 reply.ProductID = MPTSAS1068_PRODUCT_ID; 614 reply.CurrentHostMfaHighAddr = s->host_mfa_high_addr >> 32; 615 reply.GlobalCredits = ARRAY_SIZE(s->request_post) - 1; 616 reply.NumberOfPorts = MPTSAS_NUM_PORTS; 617 reply.CurrentSenseBufferHighAddr = s->sense_buffer_high_addr >> 32; 618 reply.CurReplyFrameSize = s->reply_frame_size; 619 reply.MaxDevices = s->max_devices; 620 reply.MaxBuses = s->max_buses; 621 reply.FWVersionDev = 0; 622 reply.FWVersionUnit = 0x92; 623 reply.FWVersionMinor = 0x32; 624 reply.FWVersionMajor = 0x1; 625 626 mptsas_fix_ioc_facts_reply_endianness(&reply); 627 mptsas_reply(s, (MPIDefaultReply *)&reply); 628 } 629 630 static void mptsas_process_port_facts(MPTSASState *s, 631 MPIMsgPortFacts *req) 632 { 633 MPIMsgPortFactsReply reply; 634 635 mptsas_fix_port_facts_endianness(req); 636 637 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 638 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 639 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 640 641 memset(&reply, 0, sizeof(reply)); 642 reply.MsgLength = sizeof(reply) / 4; 643 reply.Function = req->Function; 644 reply.PortNumber = req->PortNumber; 645 reply.MsgContext = req->MsgContext; 646 647 if (req->PortNumber < MPTSAS_NUM_PORTS) { 648 reply.PortType = MPI_PORTFACTS_PORTTYPE_SAS; 649 reply.MaxDevices = MPTSAS_NUM_PORTS; 650 reply.PortSCSIID = MPTSAS_NUM_PORTS; 651 reply.ProtocolFlags = MPI_PORTFACTS_PROTOCOL_LOGBUSADDR | MPI_PORTFACTS_PROTOCOL_INITIATOR; 652 } 653 654 mptsas_fix_port_facts_reply_endianness(&reply); 655 mptsas_reply(s, (MPIDefaultReply *)&reply); 656 } 657 658 static void mptsas_process_port_enable(MPTSASState *s, 659 MPIMsgPortEnable *req) 660 { 661 MPIMsgPortEnableReply reply; 662 663 mptsas_fix_port_enable_endianness(req); 664 665 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 666 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 667 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 668 669 memset(&reply, 0, sizeof(reply)); 670 reply.MsgLength = sizeof(reply) / 4; 671 reply.PortNumber = req->PortNumber; 672 reply.Function = req->Function; 673 reply.MsgContext = req->MsgContext; 674 675 mptsas_fix_port_enable_reply_endianness(&reply); 676 mptsas_reply(s, (MPIDefaultReply *)&reply); 677 } 678 679 static void mptsas_process_event_notification(MPTSASState *s, 680 MPIMsgEventNotify *req) 681 { 682 MPIMsgEventNotifyReply reply; 683 684 mptsas_fix_event_notification_endianness(req); 685 686 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 687 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 688 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 689 690 /* Don't even bother storing whether event notification is enabled, 691 * since it is not accessible. 692 */ 693 694 memset(&reply, 0, sizeof(reply)); 695 reply.EventDataLength = sizeof(reply.Data) / 4; 696 reply.MsgLength = sizeof(reply) / 4; 697 reply.Function = req->Function; 698 699 /* This is set because events are sent through the reply FIFOs. */ 700 reply.MsgFlags = MPI_MSGFLAGS_CONTINUATION_REPLY; 701 702 reply.MsgContext = req->MsgContext; 703 reply.Event = MPI_EVENT_EVENT_CHANGE; 704 reply.Data[0] = !!req->Switch; 705 706 mptsas_fix_event_notification_reply_endianness(&reply); 707 mptsas_reply(s, (MPIDefaultReply *)&reply); 708 } 709 710 static void mptsas_process_message(MPTSASState *s, MPIRequestHeader *req) 711 { 712 trace_mptsas_process_message(s, req->Function, req->MsgContext); 713 switch (req->Function) { 714 case MPI_FUNCTION_SCSI_TASK_MGMT: 715 mptsas_process_scsi_task_mgmt(s, (MPIMsgSCSITaskMgmt *)req); 716 break; 717 718 case MPI_FUNCTION_IOC_INIT: 719 mptsas_process_ioc_init(s, (MPIMsgIOCInit *)req); 720 break; 721 722 case MPI_FUNCTION_IOC_FACTS: 723 mptsas_process_ioc_facts(s, (MPIMsgIOCFacts *)req); 724 break; 725 726 case MPI_FUNCTION_PORT_FACTS: 727 mptsas_process_port_facts(s, (MPIMsgPortFacts *)req); 728 break; 729 730 case MPI_FUNCTION_PORT_ENABLE: 731 mptsas_process_port_enable(s, (MPIMsgPortEnable *)req); 732 break; 733 734 case MPI_FUNCTION_EVENT_NOTIFICATION: 735 mptsas_process_event_notification(s, (MPIMsgEventNotify *)req); 736 break; 737 738 case MPI_FUNCTION_CONFIG: 739 mptsas_process_config(s, (MPIMsgConfig *)req); 740 break; 741 742 default: 743 trace_mptsas_unhandled_cmd(s, req->Function, 0); 744 mptsas_set_fault(s, MPI_IOCSTATUS_INVALID_FUNCTION); 745 break; 746 } 747 } 748 749 static void mptsas_fetch_request(MPTSASState *s) 750 { 751 PCIDevice *pci = (PCIDevice *) s; 752 char req[MPTSAS_MAX_REQUEST_SIZE]; 753 MPIRequestHeader *hdr = (MPIRequestHeader *)req; 754 hwaddr addr; 755 int size; 756 757 if (s->state != MPI_IOC_STATE_OPERATIONAL) { 758 mptsas_set_fault(s, MPI_IOCSTATUS_INVALID_STATE); 759 return; 760 } 761 762 /* Read the message header from the guest first. */ 763 addr = s->host_mfa_high_addr | MPTSAS_FIFO_GET(s, request_post); 764 pci_dma_read(pci, addr, req, sizeof(hdr)); 765 766 if (hdr->Function < ARRAY_SIZE(mpi_request_sizes) && 767 mpi_request_sizes[hdr->Function]) { 768 /* Read the rest of the request based on the type. Do not 769 * reread everything, as that could cause a TOC/TOU mismatch 770 * and leak data from the QEMU stack. 771 */ 772 size = mpi_request_sizes[hdr->Function]; 773 assert(size <= MPTSAS_MAX_REQUEST_SIZE); 774 pci_dma_read(pci, addr + sizeof(hdr), &req[sizeof(hdr)], 775 size - sizeof(hdr)); 776 } 777 778 if (hdr->Function == MPI_FUNCTION_SCSI_IO_REQUEST) { 779 /* SCSI I/O requests are separate from mptsas_process_message 780 * because they cannot be sent through the doorbell yet. 781 */ 782 mptsas_process_scsi_io_request(s, (MPIMsgSCSIIORequest *)req, addr); 783 } else { 784 mptsas_process_message(s, (MPIRequestHeader *)req); 785 } 786 } 787 788 static void mptsas_fetch_requests(void *opaque) 789 { 790 MPTSASState *s = opaque; 791 792 while (!MPTSAS_FIFO_EMPTY(s, request_post)) { 793 mptsas_fetch_request(s); 794 } 795 } 796 797 static void mptsas_soft_reset(MPTSASState *s) 798 { 799 uint32_t save_mask; 800 801 trace_mptsas_reset(s); 802 803 /* Temporarily disable interrupts */ 804 save_mask = s->intr_mask; 805 s->intr_mask = MPI_HIM_DIM | MPI_HIM_RIM; 806 mptsas_update_interrupt(s); 807 808 qbus_reset_all(&s->bus.qbus); 809 s->intr_status = 0; 810 s->intr_mask = save_mask; 811 812 s->reply_free_tail = 0; 813 s->reply_free_head = 0; 814 s->reply_post_tail = 0; 815 s->reply_post_head = 0; 816 s->request_post_tail = 0; 817 s->request_post_head = 0; 818 qemu_bh_cancel(s->request_bh); 819 820 s->state = MPI_IOC_STATE_READY; 821 } 822 823 static uint32_t mptsas_doorbell_read(MPTSASState *s) 824 { 825 uint32_t ret; 826 827 ret = (s->who_init << MPI_DOORBELL_WHO_INIT_SHIFT) & MPI_DOORBELL_WHO_INIT_MASK; 828 ret |= s->state; 829 switch (s->doorbell_state) { 830 case DOORBELL_NONE: 831 break; 832 833 case DOORBELL_WRITE: 834 ret |= MPI_DOORBELL_ACTIVE; 835 break; 836 837 case DOORBELL_READ: 838 /* Get rid of the IOC fault code. */ 839 ret &= ~MPI_DOORBELL_DATA_MASK; 840 841 assert(s->intr_status & MPI_HIS_DOORBELL_INTERRUPT); 842 assert(s->doorbell_reply_idx <= s->doorbell_reply_size); 843 844 ret |= MPI_DOORBELL_ACTIVE; 845 if (s->doorbell_reply_idx < s->doorbell_reply_size) { 846 /* For more information about this endian switch, see the 847 * commit message for commit 36b62ae ("fw_cfg: fix endianness in 848 * fw_cfg_data_mem_read() / _write()", 2015-01-16). 849 */ 850 ret |= le16_to_cpu(s->doorbell_reply[s->doorbell_reply_idx++]); 851 } 852 break; 853 854 default: 855 abort(); 856 } 857 858 return ret; 859 } 860 861 static void mptsas_doorbell_write(MPTSASState *s, uint32_t val) 862 { 863 if (s->doorbell_state == DOORBELL_WRITE) { 864 if (s->doorbell_idx < s->doorbell_cnt) { 865 /* For more information about this endian switch, see the 866 * commit message for commit 36b62ae ("fw_cfg: fix endianness in 867 * fw_cfg_data_mem_read() / _write()", 2015-01-16). 868 */ 869 s->doorbell_msg[s->doorbell_idx++] = cpu_to_le32(val); 870 if (s->doorbell_idx == s->doorbell_cnt) { 871 mptsas_process_message(s, (MPIRequestHeader *)s->doorbell_msg); 872 } 873 } 874 return; 875 } 876 877 switch ((val & MPI_DOORBELL_FUNCTION_MASK) >> MPI_DOORBELL_FUNCTION_SHIFT) { 878 case MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET: 879 mptsas_soft_reset(s); 880 break; 881 case MPI_FUNCTION_IO_UNIT_RESET: 882 break; 883 case MPI_FUNCTION_HANDSHAKE: 884 s->doorbell_state = DOORBELL_WRITE; 885 s->doorbell_idx = 0; 886 s->doorbell_cnt = (val & MPI_DOORBELL_ADD_DWORDS_MASK) 887 >> MPI_DOORBELL_ADD_DWORDS_SHIFT; 888 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT; 889 mptsas_update_interrupt(s); 890 break; 891 default: 892 trace_mptsas_unhandled_doorbell_cmd(s, val); 893 break; 894 } 895 } 896 897 static void mptsas_write_sequence_write(MPTSASState *s, uint32_t val) 898 { 899 /* If the diagnostic register is enabled, any write to this register 900 * will disable it. Otherwise, the guest has to do a magic five-write 901 * sequence. 902 */ 903 if (s->diagnostic & MPI_DIAG_DRWE) { 904 goto disable; 905 } 906 907 switch (s->diagnostic_idx) { 908 case 0: 909 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_1ST_KEY_VALUE) { 910 goto disable; 911 } 912 break; 913 case 1: 914 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_2ND_KEY_VALUE) { 915 goto disable; 916 } 917 break; 918 case 2: 919 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_3RD_KEY_VALUE) { 920 goto disable; 921 } 922 break; 923 case 3: 924 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_4TH_KEY_VALUE) { 925 goto disable; 926 } 927 break; 928 case 4: 929 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_5TH_KEY_VALUE) { 930 goto disable; 931 } 932 /* Prepare Spaceball One for departure, and change the 933 * combination on my luggage! 934 */ 935 s->diagnostic |= MPI_DIAG_DRWE; 936 break; 937 } 938 s->diagnostic_idx++; 939 return; 940 941 disable: 942 s->diagnostic &= ~MPI_DIAG_DRWE; 943 s->diagnostic_idx = 0; 944 } 945 946 static int mptsas_hard_reset(MPTSASState *s) 947 { 948 mptsas_soft_reset(s); 949 950 s->intr_mask = MPI_HIM_DIM | MPI_HIM_RIM; 951 952 s->host_mfa_high_addr = 0; 953 s->sense_buffer_high_addr = 0; 954 s->reply_frame_size = 0; 955 s->max_devices = MPTSAS_NUM_PORTS; 956 s->max_buses = 1; 957 958 return 0; 959 } 960 961 static void mptsas_interrupt_status_write(MPTSASState *s) 962 { 963 switch (s->doorbell_state) { 964 case DOORBELL_NONE: 965 case DOORBELL_WRITE: 966 s->intr_status &= ~MPI_HIS_DOORBELL_INTERRUPT; 967 break; 968 969 case DOORBELL_READ: 970 /* The reply can be read continuously, so leave the interrupt up. */ 971 assert(s->intr_status & MPI_HIS_DOORBELL_INTERRUPT); 972 if (s->doorbell_reply_idx == s->doorbell_reply_size) { 973 s->doorbell_state = DOORBELL_NONE; 974 } 975 break; 976 977 default: 978 abort(); 979 } 980 mptsas_update_interrupt(s); 981 } 982 983 static uint32_t mptsas_reply_post_read(MPTSASState *s) 984 { 985 uint32_t ret; 986 987 if (!MPTSAS_FIFO_EMPTY(s, reply_post)) { 988 ret = MPTSAS_FIFO_GET(s, reply_post); 989 } else { 990 ret = -1; 991 s->intr_status &= ~MPI_HIS_REPLY_MESSAGE_INTERRUPT; 992 mptsas_update_interrupt(s); 993 } 994 995 return ret; 996 } 997 998 static uint64_t mptsas_mmio_read(void *opaque, hwaddr addr, 999 unsigned size) 1000 { 1001 MPTSASState *s = opaque; 1002 uint32_t ret = 0; 1003 1004 switch (addr & ~3) { 1005 case MPI_DOORBELL_OFFSET: 1006 ret = mptsas_doorbell_read(s); 1007 break; 1008 1009 case MPI_DIAGNOSTIC_OFFSET: 1010 ret = s->diagnostic; 1011 break; 1012 1013 case MPI_HOST_INTERRUPT_STATUS_OFFSET: 1014 ret = s->intr_status; 1015 break; 1016 1017 case MPI_HOST_INTERRUPT_MASK_OFFSET: 1018 ret = s->intr_mask; 1019 break; 1020 1021 case MPI_REPLY_POST_FIFO_OFFSET: 1022 ret = mptsas_reply_post_read(s); 1023 break; 1024 1025 default: 1026 trace_mptsas_mmio_unhandled_read(s, addr); 1027 break; 1028 } 1029 trace_mptsas_mmio_read(s, addr, ret); 1030 return ret; 1031 } 1032 1033 static void mptsas_mmio_write(void *opaque, hwaddr addr, 1034 uint64_t val, unsigned size) 1035 { 1036 MPTSASState *s = opaque; 1037 1038 trace_mptsas_mmio_write(s, addr, val); 1039 switch (addr) { 1040 case MPI_DOORBELL_OFFSET: 1041 mptsas_doorbell_write(s, val); 1042 break; 1043 1044 case MPI_WRITE_SEQUENCE_OFFSET: 1045 mptsas_write_sequence_write(s, val); 1046 break; 1047 1048 case MPI_DIAGNOSTIC_OFFSET: 1049 if (val & MPI_DIAG_RESET_ADAPTER) { 1050 mptsas_hard_reset(s); 1051 } 1052 break; 1053 1054 case MPI_HOST_INTERRUPT_STATUS_OFFSET: 1055 mptsas_interrupt_status_write(s); 1056 break; 1057 1058 case MPI_HOST_INTERRUPT_MASK_OFFSET: 1059 s->intr_mask = val & (MPI_HIM_RIM | MPI_HIM_DIM); 1060 mptsas_update_interrupt(s); 1061 break; 1062 1063 case MPI_REQUEST_POST_FIFO_OFFSET: 1064 if (MPTSAS_FIFO_FULL(s, request_post)) { 1065 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); 1066 } else { 1067 MPTSAS_FIFO_PUT(s, request_post, val & ~0x03); 1068 qemu_bh_schedule(s->request_bh); 1069 } 1070 break; 1071 1072 case MPI_REPLY_FREE_FIFO_OFFSET: 1073 if (MPTSAS_FIFO_FULL(s, reply_free)) { 1074 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); 1075 } else { 1076 MPTSAS_FIFO_PUT(s, reply_free, val); 1077 } 1078 break; 1079 1080 default: 1081 trace_mptsas_mmio_unhandled_write(s, addr, val); 1082 break; 1083 } 1084 } 1085 1086 static const MemoryRegionOps mptsas_mmio_ops = { 1087 .read = mptsas_mmio_read, 1088 .write = mptsas_mmio_write, 1089 .endianness = DEVICE_LITTLE_ENDIAN, 1090 .impl = { 1091 .min_access_size = 4, 1092 .max_access_size = 4, 1093 } 1094 }; 1095 1096 static const MemoryRegionOps mptsas_port_ops = { 1097 .read = mptsas_mmio_read, 1098 .write = mptsas_mmio_write, 1099 .endianness = DEVICE_LITTLE_ENDIAN, 1100 .impl = { 1101 .min_access_size = 4, 1102 .max_access_size = 4, 1103 } 1104 }; 1105 1106 static uint64_t mptsas_diag_read(void *opaque, hwaddr addr, 1107 unsigned size) 1108 { 1109 MPTSASState *s = opaque; 1110 trace_mptsas_diag_read(s, addr, 0); 1111 return 0; 1112 } 1113 1114 static void mptsas_diag_write(void *opaque, hwaddr addr, 1115 uint64_t val, unsigned size) 1116 { 1117 MPTSASState *s = opaque; 1118 trace_mptsas_diag_write(s, addr, val); 1119 } 1120 1121 static const MemoryRegionOps mptsas_diag_ops = { 1122 .read = mptsas_diag_read, 1123 .write = mptsas_diag_write, 1124 .endianness = DEVICE_LITTLE_ENDIAN, 1125 .impl = { 1126 .min_access_size = 4, 1127 .max_access_size = 4, 1128 } 1129 }; 1130 1131 static QEMUSGList *mptsas_get_sg_list(SCSIRequest *sreq) 1132 { 1133 MPTSASRequest *req = sreq->hba_private; 1134 1135 return &req->qsg; 1136 } 1137 1138 static void mptsas_command_complete(SCSIRequest *sreq, 1139 uint32_t status, size_t resid) 1140 { 1141 MPTSASRequest *req = sreq->hba_private; 1142 MPTSASState *s = req->dev; 1143 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE]; 1144 uint8_t sense_len; 1145 1146 hwaddr sense_buffer_addr = req->dev->sense_buffer_high_addr | 1147 req->scsi_io.SenseBufferLowAddr; 1148 1149 trace_mptsas_command_complete(s, req->scsi_io.MsgContext, status, resid); 1150 1151 sense_len = scsi_req_get_sense(sreq, sense_buf, SCSI_SENSE_BUF_SIZE); 1152 if (sense_len > 0) { 1153 pci_dma_write(PCI_DEVICE(s), sense_buffer_addr, sense_buf, 1154 MIN(req->scsi_io.SenseBufferLength, sense_len)); 1155 } 1156 1157 if (sreq->status != GOOD || resid || 1158 req->dev->doorbell_state == DOORBELL_WRITE) { 1159 MPIMsgSCSIIOReply reply; 1160 1161 memset(&reply, 0, sizeof(reply)); 1162 reply.TargetID = req->scsi_io.TargetID; 1163 reply.Bus = req->scsi_io.Bus; 1164 reply.MsgLength = sizeof(reply) / 4; 1165 reply.Function = req->scsi_io.Function; 1166 reply.CDBLength = req->scsi_io.CDBLength; 1167 reply.SenseBufferLength = req->scsi_io.SenseBufferLength; 1168 reply.MsgFlags = req->scsi_io.MsgFlags; 1169 reply.MsgContext = req->scsi_io.MsgContext; 1170 reply.SCSIStatus = sreq->status; 1171 if (sreq->status == GOOD) { 1172 reply.TransferCount = req->scsi_io.DataLength - resid; 1173 if (resid) { 1174 reply.IOCStatus = MPI_IOCSTATUS_SCSI_DATA_UNDERRUN; 1175 } 1176 } else { 1177 reply.SCSIState = MPI_SCSI_STATE_AUTOSENSE_VALID; 1178 reply.SenseCount = sense_len; 1179 reply.IOCStatus = MPI_IOCSTATUS_SCSI_DATA_UNDERRUN; 1180 } 1181 1182 mptsas_fix_scsi_io_reply_endianness(&reply); 1183 mptsas_post_reply(req->dev, (MPIDefaultReply *)&reply); 1184 } else { 1185 mptsas_turbo_reply(req->dev, req->scsi_io.MsgContext); 1186 } 1187 1188 mptsas_free_request(req); 1189 } 1190 1191 static void mptsas_request_cancelled(SCSIRequest *sreq) 1192 { 1193 MPTSASRequest *req = sreq->hba_private; 1194 MPIMsgSCSIIOReply reply; 1195 1196 memset(&reply, 0, sizeof(reply)); 1197 reply.TargetID = req->scsi_io.TargetID; 1198 reply.Bus = req->scsi_io.Bus; 1199 reply.MsgLength = sizeof(reply) / 4; 1200 reply.Function = req->scsi_io.Function; 1201 reply.CDBLength = req->scsi_io.CDBLength; 1202 reply.SenseBufferLength = req->scsi_io.SenseBufferLength; 1203 reply.MsgFlags = req->scsi_io.MsgFlags; 1204 reply.MsgContext = req->scsi_io.MsgContext; 1205 reply.SCSIState = MPI_SCSI_STATE_NO_SCSI_STATUS; 1206 reply.IOCStatus = MPI_IOCSTATUS_SCSI_TASK_TERMINATED; 1207 1208 mptsas_fix_scsi_io_reply_endianness(&reply); 1209 mptsas_post_reply(req->dev, (MPIDefaultReply *)&reply); 1210 mptsas_free_request(req); 1211 } 1212 1213 static void mptsas_save_request(QEMUFile *f, SCSIRequest *sreq) 1214 { 1215 MPTSASRequest *req = sreq->hba_private; 1216 int i; 1217 1218 qemu_put_buffer(f, (unsigned char *)&req->scsi_io, sizeof(req->scsi_io)); 1219 qemu_put_be32(f, req->qsg.nsg); 1220 for (i = 0; i < req->qsg.nsg; i++) { 1221 qemu_put_be64(f, req->qsg.sg[i].base); 1222 qemu_put_be64(f, req->qsg.sg[i].len); 1223 } 1224 } 1225 1226 static void *mptsas_load_request(QEMUFile *f, SCSIRequest *sreq) 1227 { 1228 SCSIBus *bus = sreq->bus; 1229 MPTSASState *s = container_of(bus, MPTSASState, bus); 1230 PCIDevice *pci = PCI_DEVICE(s); 1231 MPTSASRequest *req; 1232 int i, n; 1233 1234 req = g_new(MPTSASRequest, 1); 1235 qemu_get_buffer(f, (unsigned char *)&req->scsi_io, sizeof(req->scsi_io)); 1236 1237 n = qemu_get_be32(f); 1238 /* TODO: add a way for SCSIBusInfo's load_request to fail, 1239 * and fail migration instead of asserting here. 1240 * When we do, we might be able to re-enable NDEBUG below. 1241 */ 1242 #ifdef NDEBUG 1243 #error building with NDEBUG is not supported 1244 #endif 1245 assert(n >= 0); 1246 1247 pci_dma_sglist_init(&req->qsg, pci, n); 1248 for (i = 0; i < n; i++) { 1249 uint64_t base = qemu_get_be64(f); 1250 uint64_t len = qemu_get_be64(f); 1251 qemu_sglist_add(&req->qsg, base, len); 1252 } 1253 1254 scsi_req_ref(sreq); 1255 req->sreq = sreq; 1256 req->dev = s; 1257 1258 return req; 1259 } 1260 1261 static const struct SCSIBusInfo mptsas_scsi_info = { 1262 .tcq = true, 1263 .max_target = MPTSAS_NUM_PORTS, 1264 .max_lun = 1, 1265 1266 .get_sg_list = mptsas_get_sg_list, 1267 .complete = mptsas_command_complete, 1268 .cancel = mptsas_request_cancelled, 1269 .save_request = mptsas_save_request, 1270 .load_request = mptsas_load_request, 1271 }; 1272 1273 static void mptsas_scsi_init(PCIDevice *dev, Error **errp) 1274 { 1275 DeviceState *d = DEVICE(dev); 1276 MPTSASState *s = MPT_SAS(dev); 1277 1278 dev->config[PCI_LATENCY_TIMER] = 0; 1279 dev->config[PCI_INTERRUPT_PIN] = 0x01; 1280 1281 memory_region_init_io(&s->mmio_io, OBJECT(s), &mptsas_mmio_ops, s, 1282 "mptsas-mmio", 0x4000); 1283 memory_region_init_io(&s->port_io, OBJECT(s), &mptsas_port_ops, s, 1284 "mptsas-io", 256); 1285 memory_region_init_io(&s->diag_io, OBJECT(s), &mptsas_diag_ops, s, 1286 "mptsas-diag", 0x10000); 1287 1288 if (s->msi_available && 1289 msi_init(dev, 0, 1, true, false) >= 0) { 1290 s->msi_in_use = true; 1291 } 1292 1293 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->port_io); 1294 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY | 1295 PCI_BASE_ADDRESS_MEM_TYPE_32, &s->mmio_io); 1296 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY | 1297 PCI_BASE_ADDRESS_MEM_TYPE_32, &s->diag_io); 1298 1299 if (!s->sas_addr) { 1300 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) | 1301 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36; 1302 s->sas_addr |= (pci_bus_num(dev->bus) << 16); 1303 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8); 1304 s->sas_addr |= PCI_FUNC(dev->devfn); 1305 } 1306 s->max_devices = MPTSAS_NUM_PORTS; 1307 1308 s->request_bh = qemu_bh_new(mptsas_fetch_requests, s); 1309 1310 QTAILQ_INIT(&s->pending); 1311 1312 scsi_bus_new(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info, NULL); 1313 if (!d->hotplugged) { 1314 scsi_bus_legacy_handle_cmdline(&s->bus, errp); 1315 } 1316 } 1317 1318 static void mptsas_scsi_uninit(PCIDevice *dev) 1319 { 1320 MPTSASState *s = MPT_SAS(dev); 1321 1322 qemu_bh_delete(s->request_bh); 1323 if (s->msi_in_use) { 1324 msi_uninit(dev); 1325 } 1326 } 1327 1328 static void mptsas_reset(DeviceState *dev) 1329 { 1330 MPTSASState *s = MPT_SAS(dev); 1331 1332 mptsas_hard_reset(s); 1333 } 1334 1335 static int mptsas_post_load(void *opaque, int version_id) 1336 { 1337 MPTSASState *s = opaque; 1338 1339 if (s->doorbell_idx > s->doorbell_cnt || 1340 s->doorbell_cnt > ARRAY_SIZE(s->doorbell_msg) || 1341 s->doorbell_reply_idx > s->doorbell_reply_size || 1342 s->doorbell_reply_size > ARRAY_SIZE(s->doorbell_reply) || 1343 MPTSAS_FIFO_INVALID(s, request_post) || 1344 MPTSAS_FIFO_INVALID(s, reply_post) || 1345 MPTSAS_FIFO_INVALID(s, reply_free) || 1346 s->diagnostic_idx > 4) { 1347 return -EINVAL; 1348 } 1349 1350 return 0; 1351 } 1352 1353 static const VMStateDescription vmstate_mptsas = { 1354 .name = "mptsas", 1355 .version_id = 0, 1356 .minimum_version_id = 0, 1357 .minimum_version_id_old = 0, 1358 .post_load = mptsas_post_load, 1359 .fields = (VMStateField[]) { 1360 VMSTATE_PCI_DEVICE(dev, MPTSASState), 1361 VMSTATE_BOOL(msi_in_use, MPTSASState), 1362 1363 VMSTATE_UINT32(state, MPTSASState), 1364 VMSTATE_UINT8(who_init, MPTSASState), 1365 VMSTATE_UINT8(doorbell_state, MPTSASState), 1366 VMSTATE_UINT32_ARRAY(doorbell_msg, MPTSASState, 256), 1367 VMSTATE_INT32(doorbell_idx, MPTSASState), 1368 VMSTATE_INT32(doorbell_cnt, MPTSASState), 1369 1370 VMSTATE_UINT16_ARRAY(doorbell_reply, MPTSASState, 256), 1371 VMSTATE_INT32(doorbell_reply_idx, MPTSASState), 1372 VMSTATE_INT32(doorbell_reply_size, MPTSASState), 1373 1374 VMSTATE_UINT32(diagnostic, MPTSASState), 1375 VMSTATE_UINT8(diagnostic_idx, MPTSASState), 1376 1377 VMSTATE_UINT32(intr_status, MPTSASState), 1378 VMSTATE_UINT32(intr_mask, MPTSASState), 1379 1380 VMSTATE_UINT32_ARRAY(request_post, MPTSASState, 1381 MPTSAS_REQUEST_QUEUE_DEPTH + 1), 1382 VMSTATE_UINT16(request_post_head, MPTSASState), 1383 VMSTATE_UINT16(request_post_tail, MPTSASState), 1384 1385 VMSTATE_UINT32_ARRAY(reply_post, MPTSASState, 1386 MPTSAS_REPLY_QUEUE_DEPTH + 1), 1387 VMSTATE_UINT16(reply_post_head, MPTSASState), 1388 VMSTATE_UINT16(reply_post_tail, MPTSASState), 1389 1390 VMSTATE_UINT32_ARRAY(reply_free, MPTSASState, 1391 MPTSAS_REPLY_QUEUE_DEPTH + 1), 1392 VMSTATE_UINT16(reply_free_head, MPTSASState), 1393 VMSTATE_UINT16(reply_free_tail, MPTSASState), 1394 1395 VMSTATE_UINT16(max_buses, MPTSASState), 1396 VMSTATE_UINT16(max_devices, MPTSASState), 1397 VMSTATE_UINT16(reply_frame_size, MPTSASState), 1398 VMSTATE_UINT64(host_mfa_high_addr, MPTSASState), 1399 VMSTATE_UINT64(sense_buffer_high_addr, MPTSASState), 1400 VMSTATE_END_OF_LIST() 1401 } 1402 }; 1403 1404 static Property mptsas_properties[] = { 1405 DEFINE_PROP_UINT64("sas_address", MPTSASState, sas_addr, 0), 1406 /* TODO: test MSI support under Windows */ 1407 DEFINE_PROP_BIT("msi", MPTSASState, msi_available, 0, true), 1408 DEFINE_PROP_END_OF_LIST(), 1409 }; 1410 1411 static void mptsas1068_class_init(ObjectClass *oc, void *data) 1412 { 1413 DeviceClass *dc = DEVICE_CLASS(oc); 1414 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc); 1415 1416 pc->realize = mptsas_scsi_init; 1417 pc->exit = mptsas_scsi_uninit; 1418 pc->romfile = 0; 1419 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC; 1420 pc->device_id = PCI_DEVICE_ID_LSI_SAS1068; 1421 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC; 1422 pc->subsystem_id = 0x8000; 1423 pc->class_id = PCI_CLASS_STORAGE_SCSI; 1424 dc->props = mptsas_properties; 1425 dc->reset = mptsas_reset; 1426 dc->vmsd = &vmstate_mptsas; 1427 dc->desc = "LSI SAS 1068"; 1428 } 1429 1430 static const TypeInfo mptsas_info = { 1431 .name = TYPE_MPTSAS1068, 1432 .parent = TYPE_PCI_DEVICE, 1433 .instance_size = sizeof(MPTSASState), 1434 .class_init = mptsas1068_class_init, 1435 }; 1436 1437 static void mptsas_register_types(void) 1438 { 1439 type_register(&mptsas_info); 1440 } 1441 1442 type_init(mptsas_register_types) 1443