1 /* 2 * QEMU LSI SAS1068 Host Bus Adapter emulation 3 * Based on the QEMU Megaraid emulator 4 * 5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs 6 * Copyright (c) 2012 Verizon, Inc. 7 * Copyright (c) 2016 Red Hat, Inc. 8 * 9 * Authors: Don Slutz, Paolo Bonzini 10 * 11 * This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU Lesser General Public 13 * License as published by the Free Software Foundation; either 14 * version 2 of the License, or (at your option) any later version. 15 * 16 * This library is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * Lesser General Public License for more details. 20 * 21 * You should have received a copy of the GNU Lesser General Public 22 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/pci/pci.h" 28 #include "sysemu/dma.h" 29 #include "hw/pci/msi.h" 30 #include "qemu/iov.h" 31 #include "qemu/module.h" 32 #include "hw/scsi/scsi.h" 33 #include "scsi/constants.h" 34 #include "trace.h" 35 #include "qapi/error.h" 36 #include "mptsas.h" 37 #include "migration/qemu-file-types.h" 38 #include "mpi.h" 39 40 #define NAA_LOCALLY_ASSIGNED_ID 0x3ULL 41 #define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400 42 43 #define TYPE_MPTSAS1068 "mptsas1068" 44 45 #define MPT_SAS(obj) \ 46 OBJECT_CHECK(MPTSASState, (obj), TYPE_MPTSAS1068) 47 48 #define MPTSAS1068_PRODUCT_ID \ 49 (MPI_FW_HEADER_PID_FAMILY_1068_SAS | \ 50 MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI | \ 51 MPI_FW_HEADER_PID_TYPE_SAS) 52 53 struct MPTSASRequest { 54 MPIMsgSCSIIORequest scsi_io; 55 SCSIRequest *sreq; 56 QEMUSGList qsg; 57 MPTSASState *dev; 58 59 QTAILQ_ENTRY(MPTSASRequest) next; 60 }; 61 62 static void mptsas_update_interrupt(MPTSASState *s) 63 { 64 PCIDevice *pci = (PCIDevice *) s; 65 uint32_t state = s->intr_status & ~(s->intr_mask | MPI_HIS_IOP_DOORBELL_STATUS); 66 67 if (msi_enabled(pci)) { 68 if (state) { 69 trace_mptsas_irq_msi(s); 70 msi_notify(pci, 0); 71 } 72 } 73 74 trace_mptsas_irq_intx(s, !!state); 75 pci_set_irq(pci, !!state); 76 } 77 78 static void mptsas_set_fault(MPTSASState *s, uint32_t code) 79 { 80 if ((s->state & MPI_IOC_STATE_FAULT) == 0) { 81 s->state = MPI_IOC_STATE_FAULT | code; 82 } 83 } 84 85 #define MPTSAS_FIFO_INVALID(s, name) \ 86 ((s)->name##_head > ARRAY_SIZE((s)->name) || \ 87 (s)->name##_tail > ARRAY_SIZE((s)->name)) 88 89 #define MPTSAS_FIFO_EMPTY(s, name) \ 90 ((s)->name##_head == (s)->name##_tail) 91 92 #define MPTSAS_FIFO_FULL(s, name) \ 93 ((s)->name##_head == ((s)->name##_tail + 1) % ARRAY_SIZE((s)->name)) 94 95 #define MPTSAS_FIFO_GET(s, name) ({ \ 96 uint32_t _val = (s)->name[(s)->name##_head++]; \ 97 (s)->name##_head %= ARRAY_SIZE((s)->name); \ 98 _val; \ 99 }) 100 101 #define MPTSAS_FIFO_PUT(s, name, val) do { \ 102 (s)->name[(s)->name##_tail++] = (val); \ 103 (s)->name##_tail %= ARRAY_SIZE((s)->name); \ 104 } while(0) 105 106 static void mptsas_post_reply(MPTSASState *s, MPIDefaultReply *reply) 107 { 108 PCIDevice *pci = (PCIDevice *) s; 109 uint32_t addr_lo; 110 111 if (MPTSAS_FIFO_EMPTY(s, reply_free) || MPTSAS_FIFO_FULL(s, reply_post)) { 112 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); 113 return; 114 } 115 116 addr_lo = MPTSAS_FIFO_GET(s, reply_free); 117 118 pci_dma_write(pci, addr_lo | s->host_mfa_high_addr, reply, 119 MIN(s->reply_frame_size, 4 * reply->MsgLength)); 120 121 MPTSAS_FIFO_PUT(s, reply_post, MPI_ADDRESS_REPLY_A_BIT | (addr_lo >> 1)); 122 123 s->intr_status |= MPI_HIS_REPLY_MESSAGE_INTERRUPT; 124 if (s->doorbell_state == DOORBELL_WRITE) { 125 s->doorbell_state = DOORBELL_NONE; 126 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT; 127 } 128 mptsas_update_interrupt(s); 129 } 130 131 void mptsas_reply(MPTSASState *s, MPIDefaultReply *reply) 132 { 133 if (s->doorbell_state == DOORBELL_WRITE) { 134 /* The reply is sent out in 16 bit chunks, while the size 135 * in the reply is in 32 bit units. 136 */ 137 s->doorbell_state = DOORBELL_READ; 138 s->doorbell_reply_idx = 0; 139 s->doorbell_reply_size = reply->MsgLength * 2; 140 memcpy(s->doorbell_reply, reply, s->doorbell_reply_size * 2); 141 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT; 142 mptsas_update_interrupt(s); 143 } else { 144 mptsas_post_reply(s, reply); 145 } 146 } 147 148 static void mptsas_turbo_reply(MPTSASState *s, uint32_t msgctx) 149 { 150 if (MPTSAS_FIFO_FULL(s, reply_post)) { 151 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); 152 return; 153 } 154 155 /* The reply is just the message context ID (bit 31 = clear). */ 156 MPTSAS_FIFO_PUT(s, reply_post, msgctx); 157 158 s->intr_status |= MPI_HIS_REPLY_MESSAGE_INTERRUPT; 159 mptsas_update_interrupt(s); 160 } 161 162 #define MPTSAS_MAX_REQUEST_SIZE 52 163 164 static const int mpi_request_sizes[] = { 165 [MPI_FUNCTION_SCSI_IO_REQUEST] = sizeof(MPIMsgSCSIIORequest), 166 [MPI_FUNCTION_SCSI_TASK_MGMT] = sizeof(MPIMsgSCSITaskMgmt), 167 [MPI_FUNCTION_IOC_INIT] = sizeof(MPIMsgIOCInit), 168 [MPI_FUNCTION_IOC_FACTS] = sizeof(MPIMsgIOCFacts), 169 [MPI_FUNCTION_CONFIG] = sizeof(MPIMsgConfig), 170 [MPI_FUNCTION_PORT_FACTS] = sizeof(MPIMsgPortFacts), 171 [MPI_FUNCTION_PORT_ENABLE] = sizeof(MPIMsgPortEnable), 172 [MPI_FUNCTION_EVENT_NOTIFICATION] = sizeof(MPIMsgEventNotify), 173 }; 174 175 static dma_addr_t mptsas_ld_sg_base(MPTSASState *s, uint32_t flags_and_length, 176 dma_addr_t *sgaddr) 177 { 178 PCIDevice *pci = (PCIDevice *) s; 179 dma_addr_t addr; 180 181 if (flags_and_length & MPI_SGE_FLAGS_64_BIT_ADDRESSING) { 182 addr = ldq_le_pci_dma(pci, *sgaddr + 4); 183 *sgaddr += 12; 184 } else { 185 addr = ldl_le_pci_dma(pci, *sgaddr + 4); 186 *sgaddr += 8; 187 } 188 return addr; 189 } 190 191 static int mptsas_build_sgl(MPTSASState *s, MPTSASRequest *req, hwaddr addr) 192 { 193 PCIDevice *pci = (PCIDevice *) s; 194 hwaddr next_chain_addr; 195 uint32_t left; 196 hwaddr sgaddr; 197 uint32_t chain_offset; 198 199 chain_offset = req->scsi_io.ChainOffset; 200 next_chain_addr = addr + chain_offset * sizeof(uint32_t); 201 sgaddr = addr + sizeof(MPIMsgSCSIIORequest); 202 pci_dma_sglist_init(&req->qsg, pci, 4); 203 left = req->scsi_io.DataLength; 204 205 for(;;) { 206 dma_addr_t addr, len; 207 uint32_t flags_and_length; 208 209 flags_and_length = ldl_le_pci_dma(pci, sgaddr); 210 len = flags_and_length & MPI_SGE_LENGTH_MASK; 211 if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK) 212 != MPI_SGE_FLAGS_SIMPLE_ELEMENT || 213 (!len && 214 !(flags_and_length & MPI_SGE_FLAGS_END_OF_LIST) && 215 !(flags_and_length & MPI_SGE_FLAGS_END_OF_BUFFER))) { 216 return MPI_IOCSTATUS_INVALID_SGL; 217 } 218 219 len = MIN(len, left); 220 if (!len) { 221 /* We reached the desired transfer length, ignore extra 222 * elements of the s/g list. 223 */ 224 break; 225 } 226 227 addr = mptsas_ld_sg_base(s, flags_and_length, &sgaddr); 228 qemu_sglist_add(&req->qsg, addr, len); 229 left -= len; 230 231 if (flags_and_length & MPI_SGE_FLAGS_END_OF_LIST) { 232 break; 233 } 234 235 if (flags_and_length & MPI_SGE_FLAGS_LAST_ELEMENT) { 236 if (!chain_offset) { 237 break; 238 } 239 240 flags_and_length = ldl_le_pci_dma(pci, next_chain_addr); 241 if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK) 242 != MPI_SGE_FLAGS_CHAIN_ELEMENT) { 243 return MPI_IOCSTATUS_INVALID_SGL; 244 } 245 246 sgaddr = mptsas_ld_sg_base(s, flags_and_length, &next_chain_addr); 247 chain_offset = 248 (flags_and_length & MPI_SGE_CHAIN_OFFSET_MASK) >> MPI_SGE_CHAIN_OFFSET_SHIFT; 249 next_chain_addr = sgaddr + chain_offset * sizeof(uint32_t); 250 } 251 } 252 return 0; 253 } 254 255 static void mptsas_free_request(MPTSASRequest *req) 256 { 257 MPTSASState *s = req->dev; 258 259 if (req->sreq != NULL) { 260 req->sreq->hba_private = NULL; 261 scsi_req_unref(req->sreq); 262 req->sreq = NULL; 263 QTAILQ_REMOVE(&s->pending, req, next); 264 } 265 qemu_sglist_destroy(&req->qsg); 266 g_free(req); 267 } 268 269 static int mptsas_scsi_device_find(MPTSASState *s, int bus, int target, 270 uint8_t *lun, SCSIDevice **sdev) 271 { 272 if (bus != 0) { 273 return MPI_IOCSTATUS_SCSI_INVALID_BUS; 274 } 275 276 if (target >= s->max_devices) { 277 return MPI_IOCSTATUS_SCSI_INVALID_TARGETID; 278 } 279 280 *sdev = scsi_device_find(&s->bus, bus, target, lun[1]); 281 if (!*sdev) { 282 return MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE; 283 } 284 285 return 0; 286 } 287 288 static int mptsas_process_scsi_io_request(MPTSASState *s, 289 MPIMsgSCSIIORequest *scsi_io, 290 hwaddr addr) 291 { 292 MPTSASRequest *req; 293 MPIMsgSCSIIOReply reply; 294 SCSIDevice *sdev; 295 int status; 296 297 mptsas_fix_scsi_io_endianness(scsi_io); 298 299 trace_mptsas_process_scsi_io_request(s, scsi_io->Bus, scsi_io->TargetID, 300 scsi_io->LUN[1], scsi_io->DataLength); 301 302 status = mptsas_scsi_device_find(s, scsi_io->Bus, scsi_io->TargetID, 303 scsi_io->LUN, &sdev); 304 if (status) { 305 goto bad; 306 } 307 308 req = g_new0(MPTSASRequest, 1); 309 QTAILQ_INSERT_TAIL(&s->pending, req, next); 310 req->scsi_io = *scsi_io; 311 req->dev = s; 312 313 status = mptsas_build_sgl(s, req, addr); 314 if (status) { 315 goto free_bad; 316 } 317 318 if (req->qsg.size < scsi_io->DataLength) { 319 trace_mptsas_sgl_overflow(s, scsi_io->MsgContext, scsi_io->DataLength, 320 req->qsg.size); 321 status = MPI_IOCSTATUS_INVALID_SGL; 322 goto free_bad; 323 } 324 325 req->sreq = scsi_req_new(sdev, scsi_io->MsgContext, 326 scsi_io->LUN[1], scsi_io->CDB, req); 327 328 if (req->sreq->cmd.xfer > scsi_io->DataLength) { 329 goto overrun; 330 } 331 switch (scsi_io->Control & MPI_SCSIIO_CONTROL_DATADIRECTION_MASK) { 332 case MPI_SCSIIO_CONTROL_NODATATRANSFER: 333 if (req->sreq->cmd.mode != SCSI_XFER_NONE) { 334 goto overrun; 335 } 336 break; 337 338 case MPI_SCSIIO_CONTROL_WRITE: 339 if (req->sreq->cmd.mode != SCSI_XFER_TO_DEV) { 340 goto overrun; 341 } 342 break; 343 344 case MPI_SCSIIO_CONTROL_READ: 345 if (req->sreq->cmd.mode != SCSI_XFER_FROM_DEV) { 346 goto overrun; 347 } 348 break; 349 } 350 351 if (scsi_req_enqueue(req->sreq)) { 352 scsi_req_continue(req->sreq); 353 } 354 return 0; 355 356 overrun: 357 trace_mptsas_scsi_overflow(s, scsi_io->MsgContext, req->sreq->cmd.xfer, 358 scsi_io->DataLength); 359 status = MPI_IOCSTATUS_SCSI_DATA_OVERRUN; 360 free_bad: 361 mptsas_free_request(req); 362 bad: 363 memset(&reply, 0, sizeof(reply)); 364 reply.TargetID = scsi_io->TargetID; 365 reply.Bus = scsi_io->Bus; 366 reply.MsgLength = sizeof(reply) / 4; 367 reply.Function = scsi_io->Function; 368 reply.CDBLength = scsi_io->CDBLength; 369 reply.SenseBufferLength = scsi_io->SenseBufferLength; 370 reply.MsgContext = scsi_io->MsgContext; 371 reply.SCSIState = MPI_SCSI_STATE_NO_SCSI_STATUS; 372 reply.IOCStatus = status; 373 374 mptsas_fix_scsi_io_reply_endianness(&reply); 375 mptsas_reply(s, (MPIDefaultReply *)&reply); 376 377 return 0; 378 } 379 380 typedef struct { 381 Notifier notifier; 382 MPTSASState *s; 383 MPIMsgSCSITaskMgmtReply *reply; 384 } MPTSASCancelNotifier; 385 386 static void mptsas_cancel_notify(Notifier *notifier, void *data) 387 { 388 MPTSASCancelNotifier *n = container_of(notifier, 389 MPTSASCancelNotifier, 390 notifier); 391 392 /* Abusing IOCLogInfo to store the expected number of requests... */ 393 if (++n->reply->TerminationCount == n->reply->IOCLogInfo) { 394 n->reply->IOCLogInfo = 0; 395 mptsas_fix_scsi_task_mgmt_reply_endianness(n->reply); 396 mptsas_post_reply(n->s, (MPIDefaultReply *)n->reply); 397 g_free(n->reply); 398 } 399 g_free(n); 400 } 401 402 static void mptsas_process_scsi_task_mgmt(MPTSASState *s, MPIMsgSCSITaskMgmt *req) 403 { 404 MPIMsgSCSITaskMgmtReply reply; 405 MPIMsgSCSITaskMgmtReply *reply_async; 406 int status, count; 407 SCSIDevice *sdev; 408 SCSIRequest *r, *next; 409 BusChild *kid; 410 411 mptsas_fix_scsi_task_mgmt_endianness(req); 412 413 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 414 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 415 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 416 417 memset(&reply, 0, sizeof(reply)); 418 reply.TargetID = req->TargetID; 419 reply.Bus = req->Bus; 420 reply.MsgLength = sizeof(reply) / 4; 421 reply.Function = req->Function; 422 reply.TaskType = req->TaskType; 423 reply.MsgContext = req->MsgContext; 424 425 switch (req->TaskType) { 426 case MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK: 427 case MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK: 428 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID, 429 req->LUN, &sdev); 430 if (status) { 431 reply.IOCStatus = status; 432 goto out; 433 } 434 if (sdev->lun != req->LUN[1]) { 435 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN; 436 goto out; 437 } 438 439 QTAILQ_FOREACH_SAFE(r, &sdev->requests, next, next) { 440 MPTSASRequest *cmd_req = r->hba_private; 441 if (cmd_req && cmd_req->scsi_io.MsgContext == req->TaskMsgContext) { 442 break; 443 } 444 } 445 if (r) { 446 /* 447 * Assert that the request has not been completed yet, we 448 * check for it in the loop above. 449 */ 450 assert(r->hba_private); 451 if (req->TaskType == MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK) { 452 /* "If the specified command is present in the task set, then 453 * return a service response set to FUNCTION SUCCEEDED". 454 */ 455 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_SUCCEEDED; 456 } else { 457 MPTSASCancelNotifier *notifier; 458 459 reply_async = g_memdup(&reply, sizeof(MPIMsgSCSITaskMgmtReply)); 460 reply_async->IOCLogInfo = INT_MAX; 461 462 count = 1; 463 notifier = g_new(MPTSASCancelNotifier, 1); 464 notifier->s = s; 465 notifier->reply = reply_async; 466 notifier->notifier.notify = mptsas_cancel_notify; 467 scsi_req_cancel_async(r, ¬ifier->notifier); 468 goto reply_maybe_async; 469 } 470 } 471 break; 472 473 case MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 474 case MPI_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET: 475 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID, 476 req->LUN, &sdev); 477 if (status) { 478 reply.IOCStatus = status; 479 goto out; 480 } 481 if (sdev->lun != req->LUN[1]) { 482 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN; 483 goto out; 484 } 485 486 reply_async = g_memdup(&reply, sizeof(MPIMsgSCSITaskMgmtReply)); 487 reply_async->IOCLogInfo = INT_MAX; 488 489 count = 0; 490 QTAILQ_FOREACH_SAFE(r, &sdev->requests, next, next) { 491 if (r->hba_private) { 492 MPTSASCancelNotifier *notifier; 493 494 count++; 495 notifier = g_new(MPTSASCancelNotifier, 1); 496 notifier->s = s; 497 notifier->reply = reply_async; 498 notifier->notifier.notify = mptsas_cancel_notify; 499 scsi_req_cancel_async(r, ¬ifier->notifier); 500 } 501 } 502 503 reply_maybe_async: 504 if (reply_async->TerminationCount < count) { 505 reply_async->IOCLogInfo = count; 506 return; 507 } 508 g_free(reply_async); 509 reply.TerminationCount = count; 510 break; 511 512 case MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 513 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID, 514 req->LUN, &sdev); 515 if (status) { 516 reply.IOCStatus = status; 517 goto out; 518 } 519 if (sdev->lun != req->LUN[1]) { 520 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN; 521 goto out; 522 } 523 qdev_reset_all(&sdev->qdev); 524 break; 525 526 case MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 527 if (req->Bus != 0) { 528 reply.IOCStatus = MPI_IOCSTATUS_SCSI_INVALID_BUS; 529 goto out; 530 } 531 if (req->TargetID > s->max_devices) { 532 reply.IOCStatus = MPI_IOCSTATUS_SCSI_INVALID_TARGETID; 533 goto out; 534 } 535 536 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { 537 sdev = SCSI_DEVICE(kid->child); 538 if (sdev->channel == 0 && sdev->id == req->TargetID) { 539 qdev_reset_all(kid->child); 540 } 541 } 542 break; 543 544 case MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS: 545 qbus_reset_all(BUS(&s->bus)); 546 break; 547 548 default: 549 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED; 550 break; 551 } 552 553 out: 554 mptsas_fix_scsi_task_mgmt_reply_endianness(&reply); 555 mptsas_post_reply(s, (MPIDefaultReply *)&reply); 556 } 557 558 static void mptsas_process_ioc_init(MPTSASState *s, MPIMsgIOCInit *req) 559 { 560 MPIMsgIOCInitReply reply; 561 562 mptsas_fix_ioc_init_endianness(req); 563 564 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 565 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 566 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 567 568 s->who_init = req->WhoInit; 569 s->reply_frame_size = req->ReplyFrameSize; 570 s->max_buses = req->MaxBuses; 571 s->max_devices = req->MaxDevices ? req->MaxDevices : 256; 572 s->host_mfa_high_addr = (hwaddr)req->HostMfaHighAddr << 32; 573 s->sense_buffer_high_addr = (hwaddr)req->SenseBufferHighAddr << 32; 574 575 if (s->state == MPI_IOC_STATE_READY) { 576 s->state = MPI_IOC_STATE_OPERATIONAL; 577 } 578 579 memset(&reply, 0, sizeof(reply)); 580 reply.WhoInit = s->who_init; 581 reply.MsgLength = sizeof(reply) / 4; 582 reply.Function = req->Function; 583 reply.MaxDevices = s->max_devices; 584 reply.MaxBuses = s->max_buses; 585 reply.MsgContext = req->MsgContext; 586 587 mptsas_fix_ioc_init_reply_endianness(&reply); 588 mptsas_reply(s, (MPIDefaultReply *)&reply); 589 } 590 591 static void mptsas_process_ioc_facts(MPTSASState *s, 592 MPIMsgIOCFacts *req) 593 { 594 MPIMsgIOCFactsReply reply; 595 596 mptsas_fix_ioc_facts_endianness(req); 597 598 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 599 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 600 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 601 602 memset(&reply, 0, sizeof(reply)); 603 reply.MsgVersion = 0x0105; 604 reply.MsgLength = sizeof(reply) / 4; 605 reply.Function = req->Function; 606 reply.MsgContext = req->MsgContext; 607 reply.MaxChainDepth = MPTSAS_MAXIMUM_CHAIN_DEPTH; 608 reply.WhoInit = s->who_init; 609 reply.BlockSize = MPTSAS_MAX_REQUEST_SIZE / sizeof(uint32_t); 610 reply.ReplyQueueDepth = ARRAY_SIZE(s->reply_post) - 1; 611 QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->reply_post) != ARRAY_SIZE(s->reply_free)); 612 613 reply.RequestFrameSize = 128; 614 reply.ProductID = MPTSAS1068_PRODUCT_ID; 615 reply.CurrentHostMfaHighAddr = s->host_mfa_high_addr >> 32; 616 reply.GlobalCredits = ARRAY_SIZE(s->request_post) - 1; 617 reply.NumberOfPorts = MPTSAS_NUM_PORTS; 618 reply.CurrentSenseBufferHighAddr = s->sense_buffer_high_addr >> 32; 619 reply.CurReplyFrameSize = s->reply_frame_size; 620 reply.MaxDevices = s->max_devices; 621 reply.MaxBuses = s->max_buses; 622 reply.FWVersionDev = 0; 623 reply.FWVersionUnit = 0x92; 624 reply.FWVersionMinor = 0x32; 625 reply.FWVersionMajor = 0x1; 626 627 mptsas_fix_ioc_facts_reply_endianness(&reply); 628 mptsas_reply(s, (MPIDefaultReply *)&reply); 629 } 630 631 static void mptsas_process_port_facts(MPTSASState *s, 632 MPIMsgPortFacts *req) 633 { 634 MPIMsgPortFactsReply reply; 635 636 mptsas_fix_port_facts_endianness(req); 637 638 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 639 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 640 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 641 642 memset(&reply, 0, sizeof(reply)); 643 reply.MsgLength = sizeof(reply) / 4; 644 reply.Function = req->Function; 645 reply.PortNumber = req->PortNumber; 646 reply.MsgContext = req->MsgContext; 647 648 if (req->PortNumber < MPTSAS_NUM_PORTS) { 649 reply.PortType = MPI_PORTFACTS_PORTTYPE_SAS; 650 reply.MaxDevices = MPTSAS_NUM_PORTS; 651 reply.PortSCSIID = MPTSAS_NUM_PORTS; 652 reply.ProtocolFlags = MPI_PORTFACTS_PROTOCOL_LOGBUSADDR | MPI_PORTFACTS_PROTOCOL_INITIATOR; 653 } 654 655 mptsas_fix_port_facts_reply_endianness(&reply); 656 mptsas_reply(s, (MPIDefaultReply *)&reply); 657 } 658 659 static void mptsas_process_port_enable(MPTSASState *s, 660 MPIMsgPortEnable *req) 661 { 662 MPIMsgPortEnableReply reply; 663 664 mptsas_fix_port_enable_endianness(req); 665 666 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 667 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 668 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 669 670 memset(&reply, 0, sizeof(reply)); 671 reply.MsgLength = sizeof(reply) / 4; 672 reply.PortNumber = req->PortNumber; 673 reply.Function = req->Function; 674 reply.MsgContext = req->MsgContext; 675 676 mptsas_fix_port_enable_reply_endianness(&reply); 677 mptsas_reply(s, (MPIDefaultReply *)&reply); 678 } 679 680 static void mptsas_process_event_notification(MPTSASState *s, 681 MPIMsgEventNotify *req) 682 { 683 MPIMsgEventNotifyReply reply; 684 685 mptsas_fix_event_notification_endianness(req); 686 687 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 688 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 689 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 690 691 /* Don't even bother storing whether event notification is enabled, 692 * since it is not accessible. 693 */ 694 695 memset(&reply, 0, sizeof(reply)); 696 reply.EventDataLength = sizeof(reply.Data) / 4; 697 reply.MsgLength = sizeof(reply) / 4; 698 reply.Function = req->Function; 699 700 /* This is set because events are sent through the reply FIFOs. */ 701 reply.MsgFlags = MPI_MSGFLAGS_CONTINUATION_REPLY; 702 703 reply.MsgContext = req->MsgContext; 704 reply.Event = MPI_EVENT_EVENT_CHANGE; 705 reply.Data[0] = !!req->Switch; 706 707 mptsas_fix_event_notification_reply_endianness(&reply); 708 mptsas_reply(s, (MPIDefaultReply *)&reply); 709 } 710 711 static void mptsas_process_message(MPTSASState *s, MPIRequestHeader *req) 712 { 713 trace_mptsas_process_message(s, req->Function, req->MsgContext); 714 switch (req->Function) { 715 case MPI_FUNCTION_SCSI_TASK_MGMT: 716 mptsas_process_scsi_task_mgmt(s, (MPIMsgSCSITaskMgmt *)req); 717 break; 718 719 case MPI_FUNCTION_IOC_INIT: 720 mptsas_process_ioc_init(s, (MPIMsgIOCInit *)req); 721 break; 722 723 case MPI_FUNCTION_IOC_FACTS: 724 mptsas_process_ioc_facts(s, (MPIMsgIOCFacts *)req); 725 break; 726 727 case MPI_FUNCTION_PORT_FACTS: 728 mptsas_process_port_facts(s, (MPIMsgPortFacts *)req); 729 break; 730 731 case MPI_FUNCTION_PORT_ENABLE: 732 mptsas_process_port_enable(s, (MPIMsgPortEnable *)req); 733 break; 734 735 case MPI_FUNCTION_EVENT_NOTIFICATION: 736 mptsas_process_event_notification(s, (MPIMsgEventNotify *)req); 737 break; 738 739 case MPI_FUNCTION_CONFIG: 740 mptsas_process_config(s, (MPIMsgConfig *)req); 741 break; 742 743 default: 744 trace_mptsas_unhandled_cmd(s, req->Function, 0); 745 mptsas_set_fault(s, MPI_IOCSTATUS_INVALID_FUNCTION); 746 break; 747 } 748 } 749 750 static void mptsas_fetch_request(MPTSASState *s) 751 { 752 PCIDevice *pci = (PCIDevice *) s; 753 char req[MPTSAS_MAX_REQUEST_SIZE]; 754 MPIRequestHeader *hdr = (MPIRequestHeader *)req; 755 hwaddr addr; 756 int size; 757 758 /* Read the message header from the guest first. */ 759 addr = s->host_mfa_high_addr | MPTSAS_FIFO_GET(s, request_post); 760 pci_dma_read(pci, addr, req, sizeof(*hdr)); 761 762 if (hdr->Function < ARRAY_SIZE(mpi_request_sizes) && 763 mpi_request_sizes[hdr->Function]) { 764 /* Read the rest of the request based on the type. Do not 765 * reread everything, as that could cause a TOC/TOU mismatch 766 * and leak data from the QEMU stack. 767 */ 768 size = mpi_request_sizes[hdr->Function]; 769 assert(size <= MPTSAS_MAX_REQUEST_SIZE); 770 pci_dma_read(pci, addr + sizeof(*hdr), &req[sizeof(*hdr)], 771 size - sizeof(*hdr)); 772 } 773 774 if (hdr->Function == MPI_FUNCTION_SCSI_IO_REQUEST) { 775 /* SCSI I/O requests are separate from mptsas_process_message 776 * because they cannot be sent through the doorbell yet. 777 */ 778 mptsas_process_scsi_io_request(s, (MPIMsgSCSIIORequest *)req, addr); 779 } else { 780 mptsas_process_message(s, (MPIRequestHeader *)req); 781 } 782 } 783 784 static void mptsas_fetch_requests(void *opaque) 785 { 786 MPTSASState *s = opaque; 787 788 if (s->state != MPI_IOC_STATE_OPERATIONAL) { 789 mptsas_set_fault(s, MPI_IOCSTATUS_INVALID_STATE); 790 return; 791 } 792 while (!MPTSAS_FIFO_EMPTY(s, request_post)) { 793 mptsas_fetch_request(s); 794 } 795 } 796 797 static void mptsas_soft_reset(MPTSASState *s) 798 { 799 uint32_t save_mask; 800 801 trace_mptsas_reset(s); 802 803 /* Temporarily disable interrupts */ 804 save_mask = s->intr_mask; 805 s->intr_mask = MPI_HIM_DIM | MPI_HIM_RIM; 806 mptsas_update_interrupt(s); 807 808 qbus_reset_all(BUS(&s->bus)); 809 s->intr_status = 0; 810 s->intr_mask = save_mask; 811 812 s->reply_free_tail = 0; 813 s->reply_free_head = 0; 814 s->reply_post_tail = 0; 815 s->reply_post_head = 0; 816 s->request_post_tail = 0; 817 s->request_post_head = 0; 818 qemu_bh_cancel(s->request_bh); 819 820 s->state = MPI_IOC_STATE_READY; 821 } 822 823 static uint32_t mptsas_doorbell_read(MPTSASState *s) 824 { 825 uint32_t ret; 826 827 ret = (s->who_init << MPI_DOORBELL_WHO_INIT_SHIFT) & MPI_DOORBELL_WHO_INIT_MASK; 828 ret |= s->state; 829 switch (s->doorbell_state) { 830 case DOORBELL_NONE: 831 break; 832 833 case DOORBELL_WRITE: 834 ret |= MPI_DOORBELL_ACTIVE; 835 break; 836 837 case DOORBELL_READ: 838 /* Get rid of the IOC fault code. */ 839 ret &= ~MPI_DOORBELL_DATA_MASK; 840 841 assert(s->intr_status & MPI_HIS_DOORBELL_INTERRUPT); 842 assert(s->doorbell_reply_idx <= s->doorbell_reply_size); 843 844 ret |= MPI_DOORBELL_ACTIVE; 845 if (s->doorbell_reply_idx < s->doorbell_reply_size) { 846 /* For more information about this endian switch, see the 847 * commit message for commit 36b62ae ("fw_cfg: fix endianness in 848 * fw_cfg_data_mem_read() / _write()", 2015-01-16). 849 */ 850 ret |= le16_to_cpu(s->doorbell_reply[s->doorbell_reply_idx++]); 851 } 852 break; 853 854 default: 855 abort(); 856 } 857 858 return ret; 859 } 860 861 static void mptsas_doorbell_write(MPTSASState *s, uint32_t val) 862 { 863 if (s->doorbell_state == DOORBELL_WRITE) { 864 if (s->doorbell_idx < s->doorbell_cnt) { 865 /* For more information about this endian switch, see the 866 * commit message for commit 36b62ae ("fw_cfg: fix endianness in 867 * fw_cfg_data_mem_read() / _write()", 2015-01-16). 868 */ 869 s->doorbell_msg[s->doorbell_idx++] = cpu_to_le32(val); 870 if (s->doorbell_idx == s->doorbell_cnt) { 871 mptsas_process_message(s, (MPIRequestHeader *)s->doorbell_msg); 872 } 873 } 874 return; 875 } 876 877 switch ((val & MPI_DOORBELL_FUNCTION_MASK) >> MPI_DOORBELL_FUNCTION_SHIFT) { 878 case MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET: 879 mptsas_soft_reset(s); 880 break; 881 case MPI_FUNCTION_IO_UNIT_RESET: 882 break; 883 case MPI_FUNCTION_HANDSHAKE: 884 s->doorbell_state = DOORBELL_WRITE; 885 s->doorbell_idx = 0; 886 s->doorbell_cnt = (val & MPI_DOORBELL_ADD_DWORDS_MASK) 887 >> MPI_DOORBELL_ADD_DWORDS_SHIFT; 888 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT; 889 mptsas_update_interrupt(s); 890 break; 891 default: 892 trace_mptsas_unhandled_doorbell_cmd(s, val); 893 break; 894 } 895 } 896 897 static void mptsas_write_sequence_write(MPTSASState *s, uint32_t val) 898 { 899 /* If the diagnostic register is enabled, any write to this register 900 * will disable it. Otherwise, the guest has to do a magic five-write 901 * sequence. 902 */ 903 if (s->diagnostic & MPI_DIAG_DRWE) { 904 goto disable; 905 } 906 907 switch (s->diagnostic_idx) { 908 case 0: 909 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_1ST_KEY_VALUE) { 910 goto disable; 911 } 912 break; 913 case 1: 914 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_2ND_KEY_VALUE) { 915 goto disable; 916 } 917 break; 918 case 2: 919 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_3RD_KEY_VALUE) { 920 goto disable; 921 } 922 break; 923 case 3: 924 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_4TH_KEY_VALUE) { 925 goto disable; 926 } 927 break; 928 case 4: 929 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_5TH_KEY_VALUE) { 930 goto disable; 931 } 932 /* Prepare Spaceball One for departure, and change the 933 * combination on my luggage! 934 */ 935 s->diagnostic |= MPI_DIAG_DRWE; 936 break; 937 } 938 s->diagnostic_idx++; 939 return; 940 941 disable: 942 s->diagnostic &= ~MPI_DIAG_DRWE; 943 s->diagnostic_idx = 0; 944 } 945 946 static int mptsas_hard_reset(MPTSASState *s) 947 { 948 mptsas_soft_reset(s); 949 950 s->intr_mask = MPI_HIM_DIM | MPI_HIM_RIM; 951 952 s->host_mfa_high_addr = 0; 953 s->sense_buffer_high_addr = 0; 954 s->reply_frame_size = 0; 955 s->max_devices = MPTSAS_NUM_PORTS; 956 s->max_buses = 1; 957 958 return 0; 959 } 960 961 static void mptsas_interrupt_status_write(MPTSASState *s) 962 { 963 switch (s->doorbell_state) { 964 case DOORBELL_NONE: 965 case DOORBELL_WRITE: 966 s->intr_status &= ~MPI_HIS_DOORBELL_INTERRUPT; 967 break; 968 969 case DOORBELL_READ: 970 /* The reply can be read continuously, so leave the interrupt up. */ 971 assert(s->intr_status & MPI_HIS_DOORBELL_INTERRUPT); 972 if (s->doorbell_reply_idx == s->doorbell_reply_size) { 973 s->doorbell_state = DOORBELL_NONE; 974 } 975 break; 976 977 default: 978 abort(); 979 } 980 mptsas_update_interrupt(s); 981 } 982 983 static uint32_t mptsas_reply_post_read(MPTSASState *s) 984 { 985 uint32_t ret; 986 987 if (!MPTSAS_FIFO_EMPTY(s, reply_post)) { 988 ret = MPTSAS_FIFO_GET(s, reply_post); 989 } else { 990 ret = -1; 991 s->intr_status &= ~MPI_HIS_REPLY_MESSAGE_INTERRUPT; 992 mptsas_update_interrupt(s); 993 } 994 995 return ret; 996 } 997 998 static uint64_t mptsas_mmio_read(void *opaque, hwaddr addr, 999 unsigned size) 1000 { 1001 MPTSASState *s = opaque; 1002 uint32_t ret = 0; 1003 1004 switch (addr & ~3) { 1005 case MPI_DOORBELL_OFFSET: 1006 ret = mptsas_doorbell_read(s); 1007 break; 1008 1009 case MPI_DIAGNOSTIC_OFFSET: 1010 ret = s->diagnostic; 1011 break; 1012 1013 case MPI_HOST_INTERRUPT_STATUS_OFFSET: 1014 ret = s->intr_status; 1015 break; 1016 1017 case MPI_HOST_INTERRUPT_MASK_OFFSET: 1018 ret = s->intr_mask; 1019 break; 1020 1021 case MPI_REPLY_POST_FIFO_OFFSET: 1022 ret = mptsas_reply_post_read(s); 1023 break; 1024 1025 default: 1026 trace_mptsas_mmio_unhandled_read(s, addr); 1027 break; 1028 } 1029 trace_mptsas_mmio_read(s, addr, ret); 1030 return ret; 1031 } 1032 1033 static void mptsas_mmio_write(void *opaque, hwaddr addr, 1034 uint64_t val, unsigned size) 1035 { 1036 MPTSASState *s = opaque; 1037 1038 trace_mptsas_mmio_write(s, addr, val); 1039 switch (addr) { 1040 case MPI_DOORBELL_OFFSET: 1041 mptsas_doorbell_write(s, val); 1042 break; 1043 1044 case MPI_WRITE_SEQUENCE_OFFSET: 1045 mptsas_write_sequence_write(s, val); 1046 break; 1047 1048 case MPI_DIAGNOSTIC_OFFSET: 1049 if (val & MPI_DIAG_RESET_ADAPTER) { 1050 mptsas_hard_reset(s); 1051 } 1052 break; 1053 1054 case MPI_HOST_INTERRUPT_STATUS_OFFSET: 1055 mptsas_interrupt_status_write(s); 1056 break; 1057 1058 case MPI_HOST_INTERRUPT_MASK_OFFSET: 1059 s->intr_mask = val & (MPI_HIM_RIM | MPI_HIM_DIM); 1060 mptsas_update_interrupt(s); 1061 break; 1062 1063 case MPI_REQUEST_POST_FIFO_OFFSET: 1064 if (MPTSAS_FIFO_FULL(s, request_post)) { 1065 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); 1066 } else { 1067 MPTSAS_FIFO_PUT(s, request_post, val & ~0x03); 1068 qemu_bh_schedule(s->request_bh); 1069 } 1070 break; 1071 1072 case MPI_REPLY_FREE_FIFO_OFFSET: 1073 if (MPTSAS_FIFO_FULL(s, reply_free)) { 1074 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); 1075 } else { 1076 MPTSAS_FIFO_PUT(s, reply_free, val); 1077 } 1078 break; 1079 1080 default: 1081 trace_mptsas_mmio_unhandled_write(s, addr, val); 1082 break; 1083 } 1084 } 1085 1086 static const MemoryRegionOps mptsas_mmio_ops = { 1087 .read = mptsas_mmio_read, 1088 .write = mptsas_mmio_write, 1089 .endianness = DEVICE_LITTLE_ENDIAN, 1090 .impl = { 1091 .min_access_size = 4, 1092 .max_access_size = 4, 1093 } 1094 }; 1095 1096 static const MemoryRegionOps mptsas_port_ops = { 1097 .read = mptsas_mmio_read, 1098 .write = mptsas_mmio_write, 1099 .endianness = DEVICE_LITTLE_ENDIAN, 1100 .impl = { 1101 .min_access_size = 4, 1102 .max_access_size = 4, 1103 } 1104 }; 1105 1106 static uint64_t mptsas_diag_read(void *opaque, hwaddr addr, 1107 unsigned size) 1108 { 1109 MPTSASState *s = opaque; 1110 trace_mptsas_diag_read(s, addr, 0); 1111 return 0; 1112 } 1113 1114 static void mptsas_diag_write(void *opaque, hwaddr addr, 1115 uint64_t val, unsigned size) 1116 { 1117 MPTSASState *s = opaque; 1118 trace_mptsas_diag_write(s, addr, val); 1119 } 1120 1121 static const MemoryRegionOps mptsas_diag_ops = { 1122 .read = mptsas_diag_read, 1123 .write = mptsas_diag_write, 1124 .endianness = DEVICE_LITTLE_ENDIAN, 1125 .impl = { 1126 .min_access_size = 4, 1127 .max_access_size = 4, 1128 } 1129 }; 1130 1131 static QEMUSGList *mptsas_get_sg_list(SCSIRequest *sreq) 1132 { 1133 MPTSASRequest *req = sreq->hba_private; 1134 1135 return &req->qsg; 1136 } 1137 1138 static void mptsas_command_complete(SCSIRequest *sreq, 1139 uint32_t status, size_t resid) 1140 { 1141 MPTSASRequest *req = sreq->hba_private; 1142 MPTSASState *s = req->dev; 1143 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE]; 1144 uint8_t sense_len; 1145 1146 hwaddr sense_buffer_addr = req->dev->sense_buffer_high_addr | 1147 req->scsi_io.SenseBufferLowAddr; 1148 1149 trace_mptsas_command_complete(s, req->scsi_io.MsgContext, status, resid); 1150 1151 sense_len = scsi_req_get_sense(sreq, sense_buf, SCSI_SENSE_BUF_SIZE); 1152 if (sense_len > 0) { 1153 pci_dma_write(PCI_DEVICE(s), sense_buffer_addr, sense_buf, 1154 MIN(req->scsi_io.SenseBufferLength, sense_len)); 1155 } 1156 1157 if (sreq->status != GOOD || resid || 1158 req->dev->doorbell_state == DOORBELL_WRITE) { 1159 MPIMsgSCSIIOReply reply; 1160 1161 memset(&reply, 0, sizeof(reply)); 1162 reply.TargetID = req->scsi_io.TargetID; 1163 reply.Bus = req->scsi_io.Bus; 1164 reply.MsgLength = sizeof(reply) / 4; 1165 reply.Function = req->scsi_io.Function; 1166 reply.CDBLength = req->scsi_io.CDBLength; 1167 reply.SenseBufferLength = req->scsi_io.SenseBufferLength; 1168 reply.MsgFlags = req->scsi_io.MsgFlags; 1169 reply.MsgContext = req->scsi_io.MsgContext; 1170 reply.SCSIStatus = sreq->status; 1171 if (sreq->status == GOOD) { 1172 reply.TransferCount = req->scsi_io.DataLength - resid; 1173 if (resid) { 1174 reply.IOCStatus = MPI_IOCSTATUS_SCSI_DATA_UNDERRUN; 1175 } 1176 } else { 1177 reply.SCSIState = MPI_SCSI_STATE_AUTOSENSE_VALID; 1178 reply.SenseCount = sense_len; 1179 reply.IOCStatus = MPI_IOCSTATUS_SCSI_DATA_UNDERRUN; 1180 } 1181 1182 mptsas_fix_scsi_io_reply_endianness(&reply); 1183 mptsas_post_reply(req->dev, (MPIDefaultReply *)&reply); 1184 } else { 1185 mptsas_turbo_reply(req->dev, req->scsi_io.MsgContext); 1186 } 1187 1188 mptsas_free_request(req); 1189 } 1190 1191 static void mptsas_request_cancelled(SCSIRequest *sreq) 1192 { 1193 MPTSASRequest *req = sreq->hba_private; 1194 MPIMsgSCSIIOReply reply; 1195 1196 memset(&reply, 0, sizeof(reply)); 1197 reply.TargetID = req->scsi_io.TargetID; 1198 reply.Bus = req->scsi_io.Bus; 1199 reply.MsgLength = sizeof(reply) / 4; 1200 reply.Function = req->scsi_io.Function; 1201 reply.CDBLength = req->scsi_io.CDBLength; 1202 reply.SenseBufferLength = req->scsi_io.SenseBufferLength; 1203 reply.MsgFlags = req->scsi_io.MsgFlags; 1204 reply.MsgContext = req->scsi_io.MsgContext; 1205 reply.SCSIState = MPI_SCSI_STATE_NO_SCSI_STATUS; 1206 reply.IOCStatus = MPI_IOCSTATUS_SCSI_TASK_TERMINATED; 1207 1208 mptsas_fix_scsi_io_reply_endianness(&reply); 1209 mptsas_post_reply(req->dev, (MPIDefaultReply *)&reply); 1210 mptsas_free_request(req); 1211 } 1212 1213 static void mptsas_save_request(QEMUFile *f, SCSIRequest *sreq) 1214 { 1215 MPTSASRequest *req = sreq->hba_private; 1216 int i; 1217 1218 qemu_put_buffer(f, (unsigned char *)&req->scsi_io, sizeof(req->scsi_io)); 1219 qemu_put_be32(f, req->qsg.nsg); 1220 for (i = 0; i < req->qsg.nsg; i++) { 1221 qemu_put_be64(f, req->qsg.sg[i].base); 1222 qemu_put_be64(f, req->qsg.sg[i].len); 1223 } 1224 } 1225 1226 static void *mptsas_load_request(QEMUFile *f, SCSIRequest *sreq) 1227 { 1228 SCSIBus *bus = sreq->bus; 1229 MPTSASState *s = container_of(bus, MPTSASState, bus); 1230 PCIDevice *pci = PCI_DEVICE(s); 1231 MPTSASRequest *req; 1232 int i, n; 1233 1234 req = g_new(MPTSASRequest, 1); 1235 qemu_get_buffer(f, (unsigned char *)&req->scsi_io, sizeof(req->scsi_io)); 1236 1237 n = qemu_get_be32(f); 1238 /* TODO: add a way for SCSIBusInfo's load_request to fail, 1239 * and fail migration instead of asserting here. 1240 * This is just one thing (there are probably more) that must be 1241 * fixed before we can allow NDEBUG compilation. 1242 */ 1243 assert(n >= 0); 1244 1245 pci_dma_sglist_init(&req->qsg, pci, n); 1246 for (i = 0; i < n; i++) { 1247 uint64_t base = qemu_get_be64(f); 1248 uint64_t len = qemu_get_be64(f); 1249 qemu_sglist_add(&req->qsg, base, len); 1250 } 1251 1252 scsi_req_ref(sreq); 1253 req->sreq = sreq; 1254 req->dev = s; 1255 1256 return req; 1257 } 1258 1259 static const struct SCSIBusInfo mptsas_scsi_info = { 1260 .tcq = true, 1261 .max_target = MPTSAS_NUM_PORTS, 1262 .max_lun = 1, 1263 1264 .get_sg_list = mptsas_get_sg_list, 1265 .complete = mptsas_command_complete, 1266 .cancel = mptsas_request_cancelled, 1267 .save_request = mptsas_save_request, 1268 .load_request = mptsas_load_request, 1269 }; 1270 1271 static void mptsas_scsi_realize(PCIDevice *dev, Error **errp) 1272 { 1273 MPTSASState *s = MPT_SAS(dev); 1274 Error *err = NULL; 1275 int ret; 1276 1277 dev->config[PCI_LATENCY_TIMER] = 0; 1278 dev->config[PCI_INTERRUPT_PIN] = 0x01; 1279 1280 if (s->msi != ON_OFF_AUTO_OFF) { 1281 ret = msi_init(dev, 0, 1, true, false, &err); 1282 /* Any error other than -ENOTSUP(board's MSI support is broken) 1283 * is a programming error */ 1284 assert(!ret || ret == -ENOTSUP); 1285 if (ret && s->msi == ON_OFF_AUTO_ON) { 1286 /* Can't satisfy user's explicit msi=on request, fail */ 1287 error_append_hint(&err, "You have to use msi=auto (default) or " 1288 "msi=off with this machine type.\n"); 1289 error_propagate(errp, err); 1290 return; 1291 } 1292 assert(!err || s->msi == ON_OFF_AUTO_AUTO); 1293 /* With msi=auto, we fall back to MSI off silently */ 1294 error_free(err); 1295 1296 /* Only used for migration. */ 1297 s->msi_in_use = (ret == 0); 1298 } 1299 1300 memory_region_init_io(&s->mmio_io, OBJECT(s), &mptsas_mmio_ops, s, 1301 "mptsas-mmio", 0x4000); 1302 memory_region_init_io(&s->port_io, OBJECT(s), &mptsas_port_ops, s, 1303 "mptsas-io", 256); 1304 memory_region_init_io(&s->diag_io, OBJECT(s), &mptsas_diag_ops, s, 1305 "mptsas-diag", 0x10000); 1306 1307 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->port_io); 1308 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY | 1309 PCI_BASE_ADDRESS_MEM_TYPE_32, &s->mmio_io); 1310 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY | 1311 PCI_BASE_ADDRESS_MEM_TYPE_32, &s->diag_io); 1312 1313 if (!s->sas_addr) { 1314 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) | 1315 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36; 1316 s->sas_addr |= (pci_dev_bus_num(dev) << 16); 1317 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8); 1318 s->sas_addr |= PCI_FUNC(dev->devfn); 1319 } 1320 s->max_devices = MPTSAS_NUM_PORTS; 1321 1322 s->request_bh = qemu_bh_new(mptsas_fetch_requests, s); 1323 1324 QTAILQ_INIT(&s->pending); 1325 1326 scsi_bus_new(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info, NULL); 1327 } 1328 1329 static void mptsas_scsi_uninit(PCIDevice *dev) 1330 { 1331 MPTSASState *s = MPT_SAS(dev); 1332 1333 qemu_bh_delete(s->request_bh); 1334 msi_uninit(dev); 1335 } 1336 1337 static void mptsas_reset(DeviceState *dev) 1338 { 1339 MPTSASState *s = MPT_SAS(dev); 1340 1341 mptsas_hard_reset(s); 1342 } 1343 1344 static int mptsas_post_load(void *opaque, int version_id) 1345 { 1346 MPTSASState *s = opaque; 1347 1348 if (s->doorbell_idx > s->doorbell_cnt || 1349 s->doorbell_cnt > ARRAY_SIZE(s->doorbell_msg) || 1350 s->doorbell_reply_idx > s->doorbell_reply_size || 1351 s->doorbell_reply_size > ARRAY_SIZE(s->doorbell_reply) || 1352 MPTSAS_FIFO_INVALID(s, request_post) || 1353 MPTSAS_FIFO_INVALID(s, reply_post) || 1354 MPTSAS_FIFO_INVALID(s, reply_free) || 1355 s->diagnostic_idx > 4) { 1356 return -EINVAL; 1357 } 1358 1359 return 0; 1360 } 1361 1362 static const VMStateDescription vmstate_mptsas = { 1363 .name = "mptsas", 1364 .version_id = 0, 1365 .minimum_version_id = 0, 1366 .minimum_version_id_old = 0, 1367 .post_load = mptsas_post_load, 1368 .fields = (VMStateField[]) { 1369 VMSTATE_PCI_DEVICE(dev, MPTSASState), 1370 VMSTATE_BOOL(msi_in_use, MPTSASState), 1371 VMSTATE_UINT32(state, MPTSASState), 1372 VMSTATE_UINT8(who_init, MPTSASState), 1373 VMSTATE_UINT8(doorbell_state, MPTSASState), 1374 VMSTATE_UINT32_ARRAY(doorbell_msg, MPTSASState, 256), 1375 VMSTATE_INT32(doorbell_idx, MPTSASState), 1376 VMSTATE_INT32(doorbell_cnt, MPTSASState), 1377 1378 VMSTATE_UINT16_ARRAY(doorbell_reply, MPTSASState, 256), 1379 VMSTATE_INT32(doorbell_reply_idx, MPTSASState), 1380 VMSTATE_INT32(doorbell_reply_size, MPTSASState), 1381 1382 VMSTATE_UINT32(diagnostic, MPTSASState), 1383 VMSTATE_UINT8(diagnostic_idx, MPTSASState), 1384 1385 VMSTATE_UINT32(intr_status, MPTSASState), 1386 VMSTATE_UINT32(intr_mask, MPTSASState), 1387 1388 VMSTATE_UINT32_ARRAY(request_post, MPTSASState, 1389 MPTSAS_REQUEST_QUEUE_DEPTH + 1), 1390 VMSTATE_UINT16(request_post_head, MPTSASState), 1391 VMSTATE_UINT16(request_post_tail, MPTSASState), 1392 1393 VMSTATE_UINT32_ARRAY(reply_post, MPTSASState, 1394 MPTSAS_REPLY_QUEUE_DEPTH + 1), 1395 VMSTATE_UINT16(reply_post_head, MPTSASState), 1396 VMSTATE_UINT16(reply_post_tail, MPTSASState), 1397 1398 VMSTATE_UINT32_ARRAY(reply_free, MPTSASState, 1399 MPTSAS_REPLY_QUEUE_DEPTH + 1), 1400 VMSTATE_UINT16(reply_free_head, MPTSASState), 1401 VMSTATE_UINT16(reply_free_tail, MPTSASState), 1402 1403 VMSTATE_UINT16(max_buses, MPTSASState), 1404 VMSTATE_UINT16(max_devices, MPTSASState), 1405 VMSTATE_UINT16(reply_frame_size, MPTSASState), 1406 VMSTATE_UINT64(host_mfa_high_addr, MPTSASState), 1407 VMSTATE_UINT64(sense_buffer_high_addr, MPTSASState), 1408 VMSTATE_END_OF_LIST() 1409 } 1410 }; 1411 1412 static Property mptsas_properties[] = { 1413 DEFINE_PROP_UINT64("sas_address", MPTSASState, sas_addr, 0), 1414 /* TODO: test MSI support under Windows */ 1415 DEFINE_PROP_ON_OFF_AUTO("msi", MPTSASState, msi, ON_OFF_AUTO_AUTO), 1416 DEFINE_PROP_END_OF_LIST(), 1417 }; 1418 1419 static void mptsas1068_class_init(ObjectClass *oc, void *data) 1420 { 1421 DeviceClass *dc = DEVICE_CLASS(oc); 1422 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc); 1423 1424 pc->realize = mptsas_scsi_realize; 1425 pc->exit = mptsas_scsi_uninit; 1426 pc->romfile = 0; 1427 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC; 1428 pc->device_id = PCI_DEVICE_ID_LSI_SAS1068; 1429 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC; 1430 pc->subsystem_id = 0x8000; 1431 pc->class_id = PCI_CLASS_STORAGE_SCSI; 1432 dc->props = mptsas_properties; 1433 dc->reset = mptsas_reset; 1434 dc->vmsd = &vmstate_mptsas; 1435 dc->desc = "LSI SAS 1068"; 1436 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1437 } 1438 1439 static const TypeInfo mptsas_info = { 1440 .name = TYPE_MPTSAS1068, 1441 .parent = TYPE_PCI_DEVICE, 1442 .instance_size = sizeof(MPTSASState), 1443 .class_init = mptsas1068_class_init, 1444 .interfaces = (InterfaceInfo[]) { 1445 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1446 { }, 1447 }, 1448 }; 1449 1450 static void mptsas_register_types(void) 1451 { 1452 type_register(&mptsas_info); 1453 } 1454 1455 type_init(mptsas_register_types) 1456