1 /* 2 * QEMU LSI SAS1068 Host Bus Adapter emulation 3 * Based on the QEMU Megaraid emulator 4 * 5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs 6 * Copyright (c) 2012 Verizon, Inc. 7 * Copyright (c) 2016 Red Hat, Inc. 8 * 9 * Authors: Don Slutz, Paolo Bonzini 10 * 11 * This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU Lesser General Public 13 * License as published by the Free Software Foundation; either 14 * version 2.1 of the License, or (at your option) any later version. 15 * 16 * This library is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * Lesser General Public License for more details. 20 * 21 * You should have received a copy of the GNU Lesser General Public 22 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/pci/pci.h" 27 #include "hw/qdev-properties.h" 28 #include "sysemu/dma.h" 29 #include "hw/pci/msi.h" 30 #include "qemu/iov.h" 31 #include "qemu/main-loop.h" 32 #include "qemu/module.h" 33 #include "hw/scsi/scsi.h" 34 #include "scsi/constants.h" 35 #include "trace.h" 36 #include "qapi/error.h" 37 #include "mptsas.h" 38 #include "migration/qemu-file-types.h" 39 #include "migration/vmstate.h" 40 #include "mpi.h" 41 42 #define NAA_LOCALLY_ASSIGNED_ID 0x3ULL 43 #define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400 44 45 #define MPTSAS1068_PRODUCT_ID \ 46 (MPI_FW_HEADER_PID_FAMILY_1068_SAS | \ 47 MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI | \ 48 MPI_FW_HEADER_PID_TYPE_SAS) 49 50 struct MPTSASRequest { 51 MPIMsgSCSIIORequest scsi_io; 52 SCSIRequest *sreq; 53 QEMUSGList qsg; 54 MPTSASState *dev; 55 56 QTAILQ_ENTRY(MPTSASRequest) next; 57 }; 58 59 static void mptsas_update_interrupt(MPTSASState *s) 60 { 61 PCIDevice *pci = (PCIDevice *) s; 62 uint32_t state = s->intr_status & ~(s->intr_mask | MPI_HIS_IOP_DOORBELL_STATUS); 63 64 if (msi_enabled(pci)) { 65 if (state) { 66 trace_mptsas_irq_msi(s); 67 msi_notify(pci, 0); 68 } 69 } 70 71 trace_mptsas_irq_intx(s, !!state); 72 pci_set_irq(pci, !!state); 73 } 74 75 static void mptsas_set_fault(MPTSASState *s, uint32_t code) 76 { 77 if ((s->state & MPI_IOC_STATE_FAULT) == 0) { 78 s->state = MPI_IOC_STATE_FAULT | code; 79 } 80 } 81 82 #define MPTSAS_FIFO_INVALID(s, name) \ 83 ((s)->name##_head > ARRAY_SIZE((s)->name) || \ 84 (s)->name##_tail > ARRAY_SIZE((s)->name)) 85 86 #define MPTSAS_FIFO_EMPTY(s, name) \ 87 ((s)->name##_head == (s)->name##_tail) 88 89 #define MPTSAS_FIFO_FULL(s, name) \ 90 ((s)->name##_head == ((s)->name##_tail + 1) % ARRAY_SIZE((s)->name)) 91 92 #define MPTSAS_FIFO_GET(s, name) ({ \ 93 uint32_t _val = (s)->name[(s)->name##_head++]; \ 94 (s)->name##_head %= ARRAY_SIZE((s)->name); \ 95 _val; \ 96 }) 97 98 #define MPTSAS_FIFO_PUT(s, name, val) do { \ 99 (s)->name[(s)->name##_tail++] = (val); \ 100 (s)->name##_tail %= ARRAY_SIZE((s)->name); \ 101 } while(0) 102 103 static void mptsas_post_reply(MPTSASState *s, MPIDefaultReply *reply) 104 { 105 PCIDevice *pci = (PCIDevice *) s; 106 uint32_t addr_lo; 107 108 if (MPTSAS_FIFO_EMPTY(s, reply_free) || MPTSAS_FIFO_FULL(s, reply_post)) { 109 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); 110 return; 111 } 112 113 addr_lo = MPTSAS_FIFO_GET(s, reply_free); 114 115 pci_dma_write(pci, addr_lo | s->host_mfa_high_addr, reply, 116 MIN(s->reply_frame_size, 4 * reply->MsgLength)); 117 118 MPTSAS_FIFO_PUT(s, reply_post, MPI_ADDRESS_REPLY_A_BIT | (addr_lo >> 1)); 119 120 s->intr_status |= MPI_HIS_REPLY_MESSAGE_INTERRUPT; 121 if (s->doorbell_state == DOORBELL_WRITE) { 122 s->doorbell_state = DOORBELL_NONE; 123 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT; 124 } 125 mptsas_update_interrupt(s); 126 } 127 128 void mptsas_reply(MPTSASState *s, MPIDefaultReply *reply) 129 { 130 if (s->doorbell_state == DOORBELL_WRITE) { 131 /* The reply is sent out in 16 bit chunks, while the size 132 * in the reply is in 32 bit units. 133 */ 134 s->doorbell_state = DOORBELL_READ; 135 s->doorbell_reply_idx = 0; 136 s->doorbell_reply_size = reply->MsgLength * 2; 137 memcpy(s->doorbell_reply, reply, s->doorbell_reply_size * 2); 138 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT; 139 mptsas_update_interrupt(s); 140 } else { 141 mptsas_post_reply(s, reply); 142 } 143 } 144 145 static void mptsas_turbo_reply(MPTSASState *s, uint32_t msgctx) 146 { 147 if (MPTSAS_FIFO_FULL(s, reply_post)) { 148 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); 149 return; 150 } 151 152 /* The reply is just the message context ID (bit 31 = clear). */ 153 MPTSAS_FIFO_PUT(s, reply_post, msgctx); 154 155 s->intr_status |= MPI_HIS_REPLY_MESSAGE_INTERRUPT; 156 mptsas_update_interrupt(s); 157 } 158 159 #define MPTSAS_MAX_REQUEST_SIZE 52 160 161 static const int mpi_request_sizes[] = { 162 [MPI_FUNCTION_SCSI_IO_REQUEST] = sizeof(MPIMsgSCSIIORequest), 163 [MPI_FUNCTION_SCSI_TASK_MGMT] = sizeof(MPIMsgSCSITaskMgmt), 164 [MPI_FUNCTION_IOC_INIT] = sizeof(MPIMsgIOCInit), 165 [MPI_FUNCTION_IOC_FACTS] = sizeof(MPIMsgIOCFacts), 166 [MPI_FUNCTION_CONFIG] = sizeof(MPIMsgConfig), 167 [MPI_FUNCTION_PORT_FACTS] = sizeof(MPIMsgPortFacts), 168 [MPI_FUNCTION_PORT_ENABLE] = sizeof(MPIMsgPortEnable), 169 [MPI_FUNCTION_EVENT_NOTIFICATION] = sizeof(MPIMsgEventNotify), 170 }; 171 172 static dma_addr_t mptsas_ld_sg_base(MPTSASState *s, uint32_t flags_and_length, 173 dma_addr_t *sgaddr) 174 { 175 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 176 PCIDevice *pci = (PCIDevice *) s; 177 dma_addr_t addr; 178 179 if (flags_and_length & MPI_SGE_FLAGS_64_BIT_ADDRESSING) { 180 addr = ldq_le_pci_dma(pci, *sgaddr + 4, attrs); 181 *sgaddr += 12; 182 } else { 183 addr = ldl_le_pci_dma(pci, *sgaddr + 4, attrs); 184 *sgaddr += 8; 185 } 186 return addr; 187 } 188 189 static int mptsas_build_sgl(MPTSASState *s, MPTSASRequest *req, hwaddr addr) 190 { 191 PCIDevice *pci = (PCIDevice *) s; 192 hwaddr next_chain_addr; 193 uint32_t left; 194 hwaddr sgaddr; 195 uint32_t chain_offset; 196 197 chain_offset = req->scsi_io.ChainOffset; 198 next_chain_addr = addr + chain_offset * sizeof(uint32_t); 199 sgaddr = addr + sizeof(MPIMsgSCSIIORequest); 200 pci_dma_sglist_init(&req->qsg, pci, 4); 201 left = req->scsi_io.DataLength; 202 203 for(;;) { 204 dma_addr_t addr, len; 205 uint32_t flags_and_length; 206 207 flags_and_length = ldl_le_pci_dma(pci, sgaddr, MEMTXATTRS_UNSPECIFIED); 208 len = flags_and_length & MPI_SGE_LENGTH_MASK; 209 if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK) 210 != MPI_SGE_FLAGS_SIMPLE_ELEMENT || 211 (!len && 212 !(flags_and_length & MPI_SGE_FLAGS_END_OF_LIST) && 213 !(flags_and_length & MPI_SGE_FLAGS_END_OF_BUFFER))) { 214 return MPI_IOCSTATUS_INVALID_SGL; 215 } 216 217 len = MIN(len, left); 218 if (!len) { 219 /* We reached the desired transfer length, ignore extra 220 * elements of the s/g list. 221 */ 222 break; 223 } 224 225 addr = mptsas_ld_sg_base(s, flags_and_length, &sgaddr); 226 qemu_sglist_add(&req->qsg, addr, len); 227 left -= len; 228 229 if (flags_and_length & MPI_SGE_FLAGS_END_OF_LIST) { 230 break; 231 } 232 233 if (flags_and_length & MPI_SGE_FLAGS_LAST_ELEMENT) { 234 if (!chain_offset) { 235 break; 236 } 237 238 flags_and_length = ldl_le_pci_dma(pci, next_chain_addr, 239 MEMTXATTRS_UNSPECIFIED); 240 if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK) 241 != MPI_SGE_FLAGS_CHAIN_ELEMENT) { 242 return MPI_IOCSTATUS_INVALID_SGL; 243 } 244 245 sgaddr = mptsas_ld_sg_base(s, flags_and_length, &next_chain_addr); 246 chain_offset = 247 (flags_and_length & MPI_SGE_CHAIN_OFFSET_MASK) >> MPI_SGE_CHAIN_OFFSET_SHIFT; 248 next_chain_addr = sgaddr + chain_offset * sizeof(uint32_t); 249 } 250 } 251 return 0; 252 } 253 254 static void mptsas_free_request(MPTSASRequest *req) 255 { 256 if (req->sreq != NULL) { 257 req->sreq->hba_private = NULL; 258 scsi_req_unref(req->sreq); 259 req->sreq = NULL; 260 } 261 qemu_sglist_destroy(&req->qsg); 262 g_free(req); 263 } 264 265 static int mptsas_scsi_device_find(MPTSASState *s, int bus, int target, 266 uint8_t *lun, SCSIDevice **sdev) 267 { 268 if (bus != 0) { 269 return MPI_IOCSTATUS_SCSI_INVALID_BUS; 270 } 271 272 if (target >= s->max_devices) { 273 return MPI_IOCSTATUS_SCSI_INVALID_TARGETID; 274 } 275 276 *sdev = scsi_device_find(&s->bus, bus, target, lun[1]); 277 if (!*sdev) { 278 return MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE; 279 } 280 281 return 0; 282 } 283 284 static int mptsas_process_scsi_io_request(MPTSASState *s, 285 MPIMsgSCSIIORequest *scsi_io, 286 hwaddr addr) 287 { 288 MPTSASRequest *req; 289 MPIMsgSCSIIOReply reply; 290 SCSIDevice *sdev; 291 int status; 292 293 mptsas_fix_scsi_io_endianness(scsi_io); 294 295 trace_mptsas_process_scsi_io_request(s, scsi_io->Bus, scsi_io->TargetID, 296 scsi_io->LUN[1], scsi_io->DataLength); 297 298 status = mptsas_scsi_device_find(s, scsi_io->Bus, scsi_io->TargetID, 299 scsi_io->LUN, &sdev); 300 if (status) { 301 goto bad; 302 } 303 304 req = g_new0(MPTSASRequest, 1); 305 req->scsi_io = *scsi_io; 306 req->dev = s; 307 308 status = mptsas_build_sgl(s, req, addr); 309 if (status) { 310 goto free_bad; 311 } 312 313 if (req->qsg.size < scsi_io->DataLength) { 314 trace_mptsas_sgl_overflow(s, scsi_io->MsgContext, scsi_io->DataLength, 315 req->qsg.size); 316 status = MPI_IOCSTATUS_INVALID_SGL; 317 goto free_bad; 318 } 319 320 req->sreq = scsi_req_new(sdev, scsi_io->MsgContext, 321 scsi_io->LUN[1], scsi_io->CDB, req); 322 323 if (req->sreq->cmd.xfer > scsi_io->DataLength) { 324 goto overrun; 325 } 326 switch (scsi_io->Control & MPI_SCSIIO_CONTROL_DATADIRECTION_MASK) { 327 case MPI_SCSIIO_CONTROL_NODATATRANSFER: 328 if (req->sreq->cmd.mode != SCSI_XFER_NONE) { 329 goto overrun; 330 } 331 break; 332 333 case MPI_SCSIIO_CONTROL_WRITE: 334 if (req->sreq->cmd.mode != SCSI_XFER_TO_DEV) { 335 goto overrun; 336 } 337 break; 338 339 case MPI_SCSIIO_CONTROL_READ: 340 if (req->sreq->cmd.mode != SCSI_XFER_FROM_DEV) { 341 goto overrun; 342 } 343 break; 344 } 345 346 if (scsi_req_enqueue(req->sreq)) { 347 scsi_req_continue(req->sreq); 348 } 349 return 0; 350 351 overrun: 352 trace_mptsas_scsi_overflow(s, scsi_io->MsgContext, req->sreq->cmd.xfer, 353 scsi_io->DataLength); 354 status = MPI_IOCSTATUS_SCSI_DATA_OVERRUN; 355 free_bad: 356 mptsas_free_request(req); 357 bad: 358 memset(&reply, 0, sizeof(reply)); 359 reply.TargetID = scsi_io->TargetID; 360 reply.Bus = scsi_io->Bus; 361 reply.MsgLength = sizeof(reply) / 4; 362 reply.Function = scsi_io->Function; 363 reply.CDBLength = scsi_io->CDBLength; 364 reply.SenseBufferLength = scsi_io->SenseBufferLength; 365 reply.MsgContext = scsi_io->MsgContext; 366 reply.SCSIState = MPI_SCSI_STATE_NO_SCSI_STATUS; 367 reply.IOCStatus = status; 368 369 mptsas_fix_scsi_io_reply_endianness(&reply); 370 mptsas_reply(s, (MPIDefaultReply *)&reply); 371 372 return 0; 373 } 374 375 typedef struct { 376 Notifier notifier; 377 MPTSASState *s; 378 MPIMsgSCSITaskMgmtReply *reply; 379 } MPTSASCancelNotifier; 380 381 static void mptsas_cancel_notify(Notifier *notifier, void *data) 382 { 383 MPTSASCancelNotifier *n = container_of(notifier, 384 MPTSASCancelNotifier, 385 notifier); 386 387 /* Abusing IOCLogInfo to store the expected number of requests... */ 388 if (++n->reply->TerminationCount == n->reply->IOCLogInfo) { 389 n->reply->IOCLogInfo = 0; 390 mptsas_fix_scsi_task_mgmt_reply_endianness(n->reply); 391 mptsas_post_reply(n->s, (MPIDefaultReply *)n->reply); 392 g_free(n->reply); 393 } 394 g_free(n); 395 } 396 397 static void mptsas_process_scsi_task_mgmt(MPTSASState *s, MPIMsgSCSITaskMgmt *req) 398 { 399 MPIMsgSCSITaskMgmtReply reply; 400 MPIMsgSCSITaskMgmtReply *reply_async; 401 int status, count; 402 SCSIDevice *sdev; 403 SCSIRequest *r, *next; 404 BusChild *kid; 405 406 mptsas_fix_scsi_task_mgmt_endianness(req); 407 408 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 409 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 410 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 411 412 memset(&reply, 0, sizeof(reply)); 413 reply.TargetID = req->TargetID; 414 reply.Bus = req->Bus; 415 reply.MsgLength = sizeof(reply) / 4; 416 reply.Function = req->Function; 417 reply.TaskType = req->TaskType; 418 reply.MsgContext = req->MsgContext; 419 420 switch (req->TaskType) { 421 case MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK: 422 case MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK: 423 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID, 424 req->LUN, &sdev); 425 if (status) { 426 reply.IOCStatus = status; 427 goto out; 428 } 429 if (sdev->lun != req->LUN[1]) { 430 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN; 431 goto out; 432 } 433 434 QTAILQ_FOREACH_SAFE(r, &sdev->requests, next, next) { 435 MPTSASRequest *cmd_req = r->hba_private; 436 if (cmd_req && cmd_req->scsi_io.MsgContext == req->TaskMsgContext) { 437 break; 438 } 439 } 440 if (r) { 441 /* 442 * Assert that the request has not been completed yet, we 443 * check for it in the loop above. 444 */ 445 assert(r->hba_private); 446 if (req->TaskType == MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK) { 447 /* "If the specified command is present in the task set, then 448 * return a service response set to FUNCTION SUCCEEDED". 449 */ 450 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_SUCCEEDED; 451 } else { 452 MPTSASCancelNotifier *notifier; 453 454 reply_async = g_memdup(&reply, sizeof(MPIMsgSCSITaskMgmtReply)); 455 reply_async->IOCLogInfo = INT_MAX; 456 457 count = 1; 458 notifier = g_new(MPTSASCancelNotifier, 1); 459 notifier->s = s; 460 notifier->reply = reply_async; 461 notifier->notifier.notify = mptsas_cancel_notify; 462 scsi_req_cancel_async(r, ¬ifier->notifier); 463 goto reply_maybe_async; 464 } 465 } 466 break; 467 468 case MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 469 case MPI_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET: 470 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID, 471 req->LUN, &sdev); 472 if (status) { 473 reply.IOCStatus = status; 474 goto out; 475 } 476 if (sdev->lun != req->LUN[1]) { 477 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN; 478 goto out; 479 } 480 481 reply_async = g_memdup(&reply, sizeof(MPIMsgSCSITaskMgmtReply)); 482 reply_async->IOCLogInfo = INT_MAX; 483 484 count = 0; 485 QTAILQ_FOREACH_SAFE(r, &sdev->requests, next, next) { 486 if (r->hba_private) { 487 MPTSASCancelNotifier *notifier; 488 489 count++; 490 notifier = g_new(MPTSASCancelNotifier, 1); 491 notifier->s = s; 492 notifier->reply = reply_async; 493 notifier->notifier.notify = mptsas_cancel_notify; 494 scsi_req_cancel_async(r, ¬ifier->notifier); 495 } 496 } 497 498 reply_maybe_async: 499 if (reply_async->TerminationCount < count) { 500 reply_async->IOCLogInfo = count; 501 return; 502 } 503 g_free(reply_async); 504 reply.TerminationCount = count; 505 break; 506 507 case MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 508 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID, 509 req->LUN, &sdev); 510 if (status) { 511 reply.IOCStatus = status; 512 goto out; 513 } 514 if (sdev->lun != req->LUN[1]) { 515 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN; 516 goto out; 517 } 518 qdev_reset_all(&sdev->qdev); 519 break; 520 521 case MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 522 if (req->Bus != 0) { 523 reply.IOCStatus = MPI_IOCSTATUS_SCSI_INVALID_BUS; 524 goto out; 525 } 526 if (req->TargetID > s->max_devices) { 527 reply.IOCStatus = MPI_IOCSTATUS_SCSI_INVALID_TARGETID; 528 goto out; 529 } 530 531 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { 532 sdev = SCSI_DEVICE(kid->child); 533 if (sdev->channel == 0 && sdev->id == req->TargetID) { 534 qdev_reset_all(kid->child); 535 } 536 } 537 break; 538 539 case MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS: 540 qbus_reset_all(BUS(&s->bus)); 541 break; 542 543 default: 544 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED; 545 break; 546 } 547 548 out: 549 mptsas_fix_scsi_task_mgmt_reply_endianness(&reply); 550 mptsas_post_reply(s, (MPIDefaultReply *)&reply); 551 } 552 553 static void mptsas_process_ioc_init(MPTSASState *s, MPIMsgIOCInit *req) 554 { 555 MPIMsgIOCInitReply reply; 556 557 mptsas_fix_ioc_init_endianness(req); 558 559 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 560 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 561 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 562 563 s->who_init = req->WhoInit; 564 s->reply_frame_size = req->ReplyFrameSize; 565 s->max_buses = req->MaxBuses; 566 s->max_devices = req->MaxDevices ? req->MaxDevices : 256; 567 s->host_mfa_high_addr = (hwaddr)req->HostMfaHighAddr << 32; 568 s->sense_buffer_high_addr = (hwaddr)req->SenseBufferHighAddr << 32; 569 570 if (s->state == MPI_IOC_STATE_READY) { 571 s->state = MPI_IOC_STATE_OPERATIONAL; 572 } 573 574 memset(&reply, 0, sizeof(reply)); 575 reply.WhoInit = s->who_init; 576 reply.MsgLength = sizeof(reply) / 4; 577 reply.Function = req->Function; 578 reply.MaxDevices = s->max_devices; 579 reply.MaxBuses = s->max_buses; 580 reply.MsgContext = req->MsgContext; 581 582 mptsas_fix_ioc_init_reply_endianness(&reply); 583 mptsas_reply(s, (MPIDefaultReply *)&reply); 584 } 585 586 static void mptsas_process_ioc_facts(MPTSASState *s, 587 MPIMsgIOCFacts *req) 588 { 589 MPIMsgIOCFactsReply reply; 590 591 mptsas_fix_ioc_facts_endianness(req); 592 593 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 594 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 595 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 596 597 memset(&reply, 0, sizeof(reply)); 598 reply.MsgVersion = 0x0105; 599 reply.MsgLength = sizeof(reply) / 4; 600 reply.Function = req->Function; 601 reply.MsgContext = req->MsgContext; 602 reply.MaxChainDepth = MPTSAS_MAXIMUM_CHAIN_DEPTH; 603 reply.WhoInit = s->who_init; 604 reply.BlockSize = MPTSAS_MAX_REQUEST_SIZE / sizeof(uint32_t); 605 reply.ReplyQueueDepth = ARRAY_SIZE(s->reply_post) - 1; 606 QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->reply_post) != ARRAY_SIZE(s->reply_free)); 607 608 reply.RequestFrameSize = 128; 609 reply.ProductID = MPTSAS1068_PRODUCT_ID; 610 reply.CurrentHostMfaHighAddr = s->host_mfa_high_addr >> 32; 611 reply.GlobalCredits = ARRAY_SIZE(s->request_post) - 1; 612 reply.NumberOfPorts = MPTSAS_NUM_PORTS; 613 reply.CurrentSenseBufferHighAddr = s->sense_buffer_high_addr >> 32; 614 reply.CurReplyFrameSize = s->reply_frame_size; 615 reply.MaxDevices = s->max_devices; 616 reply.MaxBuses = s->max_buses; 617 reply.FWVersionDev = 0; 618 reply.FWVersionUnit = 0x92; 619 reply.FWVersionMinor = 0x32; 620 reply.FWVersionMajor = 0x1; 621 622 mptsas_fix_ioc_facts_reply_endianness(&reply); 623 mptsas_reply(s, (MPIDefaultReply *)&reply); 624 } 625 626 static void mptsas_process_port_facts(MPTSASState *s, 627 MPIMsgPortFacts *req) 628 { 629 MPIMsgPortFactsReply reply; 630 631 mptsas_fix_port_facts_endianness(req); 632 633 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 634 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 635 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 636 637 memset(&reply, 0, sizeof(reply)); 638 reply.MsgLength = sizeof(reply) / 4; 639 reply.Function = req->Function; 640 reply.PortNumber = req->PortNumber; 641 reply.MsgContext = req->MsgContext; 642 643 if (req->PortNumber < MPTSAS_NUM_PORTS) { 644 reply.PortType = MPI_PORTFACTS_PORTTYPE_SAS; 645 reply.MaxDevices = MPTSAS_NUM_PORTS; 646 reply.PortSCSIID = MPTSAS_NUM_PORTS; 647 reply.ProtocolFlags = MPI_PORTFACTS_PROTOCOL_LOGBUSADDR | MPI_PORTFACTS_PROTOCOL_INITIATOR; 648 } 649 650 mptsas_fix_port_facts_reply_endianness(&reply); 651 mptsas_reply(s, (MPIDefaultReply *)&reply); 652 } 653 654 static void mptsas_process_port_enable(MPTSASState *s, 655 MPIMsgPortEnable *req) 656 { 657 MPIMsgPortEnableReply reply; 658 659 mptsas_fix_port_enable_endianness(req); 660 661 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 662 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 663 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 664 665 memset(&reply, 0, sizeof(reply)); 666 reply.MsgLength = sizeof(reply) / 4; 667 reply.PortNumber = req->PortNumber; 668 reply.Function = req->Function; 669 reply.MsgContext = req->MsgContext; 670 671 mptsas_fix_port_enable_reply_endianness(&reply); 672 mptsas_reply(s, (MPIDefaultReply *)&reply); 673 } 674 675 static void mptsas_process_event_notification(MPTSASState *s, 676 MPIMsgEventNotify *req) 677 { 678 MPIMsgEventNotifyReply reply; 679 680 mptsas_fix_event_notification_endianness(req); 681 682 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); 683 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); 684 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); 685 686 /* Don't even bother storing whether event notification is enabled, 687 * since it is not accessible. 688 */ 689 690 memset(&reply, 0, sizeof(reply)); 691 reply.EventDataLength = sizeof(reply.Data) / 4; 692 reply.MsgLength = sizeof(reply) / 4; 693 reply.Function = req->Function; 694 695 /* This is set because events are sent through the reply FIFOs. */ 696 reply.MsgFlags = MPI_MSGFLAGS_CONTINUATION_REPLY; 697 698 reply.MsgContext = req->MsgContext; 699 reply.Event = MPI_EVENT_EVENT_CHANGE; 700 reply.Data[0] = !!req->Switch; 701 702 mptsas_fix_event_notification_reply_endianness(&reply); 703 mptsas_reply(s, (MPIDefaultReply *)&reply); 704 } 705 706 static void mptsas_process_message(MPTSASState *s, MPIRequestHeader *req) 707 { 708 trace_mptsas_process_message(s, req->Function, req->MsgContext); 709 switch (req->Function) { 710 case MPI_FUNCTION_SCSI_TASK_MGMT: 711 mptsas_process_scsi_task_mgmt(s, (MPIMsgSCSITaskMgmt *)req); 712 break; 713 714 case MPI_FUNCTION_IOC_INIT: 715 mptsas_process_ioc_init(s, (MPIMsgIOCInit *)req); 716 break; 717 718 case MPI_FUNCTION_IOC_FACTS: 719 mptsas_process_ioc_facts(s, (MPIMsgIOCFacts *)req); 720 break; 721 722 case MPI_FUNCTION_PORT_FACTS: 723 mptsas_process_port_facts(s, (MPIMsgPortFacts *)req); 724 break; 725 726 case MPI_FUNCTION_PORT_ENABLE: 727 mptsas_process_port_enable(s, (MPIMsgPortEnable *)req); 728 break; 729 730 case MPI_FUNCTION_EVENT_NOTIFICATION: 731 mptsas_process_event_notification(s, (MPIMsgEventNotify *)req); 732 break; 733 734 case MPI_FUNCTION_CONFIG: 735 mptsas_process_config(s, (MPIMsgConfig *)req); 736 break; 737 738 default: 739 trace_mptsas_unhandled_cmd(s, req->Function, 0); 740 mptsas_set_fault(s, MPI_IOCSTATUS_INVALID_FUNCTION); 741 break; 742 } 743 } 744 745 static void mptsas_fetch_request(MPTSASState *s) 746 { 747 PCIDevice *pci = (PCIDevice *) s; 748 char req[MPTSAS_MAX_REQUEST_SIZE]; 749 MPIRequestHeader *hdr = (MPIRequestHeader *)req; 750 hwaddr addr; 751 int size; 752 753 /* Read the message header from the guest first. */ 754 addr = s->host_mfa_high_addr | MPTSAS_FIFO_GET(s, request_post); 755 pci_dma_read(pci, addr, req, sizeof(*hdr)); 756 757 if (hdr->Function < ARRAY_SIZE(mpi_request_sizes) && 758 mpi_request_sizes[hdr->Function]) { 759 /* Read the rest of the request based on the type. Do not 760 * reread everything, as that could cause a TOC/TOU mismatch 761 * and leak data from the QEMU stack. 762 */ 763 size = mpi_request_sizes[hdr->Function]; 764 assert(size <= MPTSAS_MAX_REQUEST_SIZE); 765 pci_dma_read(pci, addr + sizeof(*hdr), &req[sizeof(*hdr)], 766 size - sizeof(*hdr)); 767 } 768 769 if (hdr->Function == MPI_FUNCTION_SCSI_IO_REQUEST) { 770 /* SCSI I/O requests are separate from mptsas_process_message 771 * because they cannot be sent through the doorbell yet. 772 */ 773 mptsas_process_scsi_io_request(s, (MPIMsgSCSIIORequest *)req, addr); 774 } else { 775 mptsas_process_message(s, (MPIRequestHeader *)req); 776 } 777 } 778 779 static void mptsas_fetch_requests(void *opaque) 780 { 781 MPTSASState *s = opaque; 782 783 if (s->state != MPI_IOC_STATE_OPERATIONAL) { 784 mptsas_set_fault(s, MPI_IOCSTATUS_INVALID_STATE); 785 return; 786 } 787 while (!MPTSAS_FIFO_EMPTY(s, request_post)) { 788 mptsas_fetch_request(s); 789 } 790 } 791 792 static void mptsas_soft_reset(MPTSASState *s) 793 { 794 uint32_t save_mask; 795 796 trace_mptsas_reset(s); 797 798 /* Temporarily disable interrupts */ 799 save_mask = s->intr_mask; 800 s->intr_mask = MPI_HIM_DIM | MPI_HIM_RIM; 801 mptsas_update_interrupt(s); 802 803 qbus_reset_all(BUS(&s->bus)); 804 s->intr_status = 0; 805 s->intr_mask = save_mask; 806 807 s->reply_free_tail = 0; 808 s->reply_free_head = 0; 809 s->reply_post_tail = 0; 810 s->reply_post_head = 0; 811 s->request_post_tail = 0; 812 s->request_post_head = 0; 813 qemu_bh_cancel(s->request_bh); 814 815 s->state = MPI_IOC_STATE_READY; 816 } 817 818 static uint32_t mptsas_doorbell_read(MPTSASState *s) 819 { 820 uint32_t ret; 821 822 ret = (s->who_init << MPI_DOORBELL_WHO_INIT_SHIFT) & MPI_DOORBELL_WHO_INIT_MASK; 823 ret |= s->state; 824 switch (s->doorbell_state) { 825 case DOORBELL_NONE: 826 break; 827 828 case DOORBELL_WRITE: 829 ret |= MPI_DOORBELL_ACTIVE; 830 break; 831 832 case DOORBELL_READ: 833 /* Get rid of the IOC fault code. */ 834 ret &= ~MPI_DOORBELL_DATA_MASK; 835 836 assert(s->intr_status & MPI_HIS_DOORBELL_INTERRUPT); 837 assert(s->doorbell_reply_idx <= s->doorbell_reply_size); 838 839 ret |= MPI_DOORBELL_ACTIVE; 840 if (s->doorbell_reply_idx < s->doorbell_reply_size) { 841 /* For more information about this endian switch, see the 842 * commit message for commit 36b62ae ("fw_cfg: fix endianness in 843 * fw_cfg_data_mem_read() / _write()", 2015-01-16). 844 */ 845 ret |= le16_to_cpu(s->doorbell_reply[s->doorbell_reply_idx++]); 846 } 847 break; 848 849 default: 850 abort(); 851 } 852 853 return ret; 854 } 855 856 static void mptsas_doorbell_write(MPTSASState *s, uint32_t val) 857 { 858 if (s->doorbell_state == DOORBELL_WRITE) { 859 if (s->doorbell_idx < s->doorbell_cnt) { 860 /* For more information about this endian switch, see the 861 * commit message for commit 36b62ae ("fw_cfg: fix endianness in 862 * fw_cfg_data_mem_read() / _write()", 2015-01-16). 863 */ 864 s->doorbell_msg[s->doorbell_idx++] = cpu_to_le32(val); 865 if (s->doorbell_idx == s->doorbell_cnt) { 866 mptsas_process_message(s, (MPIRequestHeader *)s->doorbell_msg); 867 } 868 } 869 return; 870 } 871 872 switch ((val & MPI_DOORBELL_FUNCTION_MASK) >> MPI_DOORBELL_FUNCTION_SHIFT) { 873 case MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET: 874 mptsas_soft_reset(s); 875 break; 876 case MPI_FUNCTION_IO_UNIT_RESET: 877 break; 878 case MPI_FUNCTION_HANDSHAKE: 879 s->doorbell_state = DOORBELL_WRITE; 880 s->doorbell_idx = 0; 881 s->doorbell_cnt = (val & MPI_DOORBELL_ADD_DWORDS_MASK) 882 >> MPI_DOORBELL_ADD_DWORDS_SHIFT; 883 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT; 884 mptsas_update_interrupt(s); 885 break; 886 default: 887 trace_mptsas_unhandled_doorbell_cmd(s, val); 888 break; 889 } 890 } 891 892 static void mptsas_write_sequence_write(MPTSASState *s, uint32_t val) 893 { 894 /* If the diagnostic register is enabled, any write to this register 895 * will disable it. Otherwise, the guest has to do a magic five-write 896 * sequence. 897 */ 898 if (s->diagnostic & MPI_DIAG_DRWE) { 899 goto disable; 900 } 901 902 switch (s->diagnostic_idx) { 903 case 0: 904 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_1ST_KEY_VALUE) { 905 goto disable; 906 } 907 break; 908 case 1: 909 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_2ND_KEY_VALUE) { 910 goto disable; 911 } 912 break; 913 case 2: 914 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_3RD_KEY_VALUE) { 915 goto disable; 916 } 917 break; 918 case 3: 919 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_4TH_KEY_VALUE) { 920 goto disable; 921 } 922 break; 923 case 4: 924 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_5TH_KEY_VALUE) { 925 goto disable; 926 } 927 /* Prepare Spaceball One for departure, and change the 928 * combination on my luggage! 929 */ 930 s->diagnostic |= MPI_DIAG_DRWE; 931 break; 932 } 933 s->diagnostic_idx++; 934 return; 935 936 disable: 937 s->diagnostic &= ~MPI_DIAG_DRWE; 938 s->diagnostic_idx = 0; 939 } 940 941 static int mptsas_hard_reset(MPTSASState *s) 942 { 943 mptsas_soft_reset(s); 944 945 s->intr_mask = MPI_HIM_DIM | MPI_HIM_RIM; 946 947 s->host_mfa_high_addr = 0; 948 s->sense_buffer_high_addr = 0; 949 s->reply_frame_size = 0; 950 s->max_devices = MPTSAS_NUM_PORTS; 951 s->max_buses = 1; 952 953 return 0; 954 } 955 956 static void mptsas_interrupt_status_write(MPTSASState *s) 957 { 958 switch (s->doorbell_state) { 959 case DOORBELL_NONE: 960 case DOORBELL_WRITE: 961 s->intr_status &= ~MPI_HIS_DOORBELL_INTERRUPT; 962 break; 963 964 case DOORBELL_READ: 965 /* The reply can be read continuously, so leave the interrupt up. */ 966 assert(s->intr_status & MPI_HIS_DOORBELL_INTERRUPT); 967 if (s->doorbell_reply_idx == s->doorbell_reply_size) { 968 s->doorbell_state = DOORBELL_NONE; 969 } 970 break; 971 972 default: 973 abort(); 974 } 975 mptsas_update_interrupt(s); 976 } 977 978 static uint32_t mptsas_reply_post_read(MPTSASState *s) 979 { 980 uint32_t ret; 981 982 if (!MPTSAS_FIFO_EMPTY(s, reply_post)) { 983 ret = MPTSAS_FIFO_GET(s, reply_post); 984 } else { 985 ret = -1; 986 s->intr_status &= ~MPI_HIS_REPLY_MESSAGE_INTERRUPT; 987 mptsas_update_interrupt(s); 988 } 989 990 return ret; 991 } 992 993 static uint64_t mptsas_mmio_read(void *opaque, hwaddr addr, 994 unsigned size) 995 { 996 MPTSASState *s = opaque; 997 uint32_t ret = 0; 998 999 switch (addr & ~3) { 1000 case MPI_DOORBELL_OFFSET: 1001 ret = mptsas_doorbell_read(s); 1002 break; 1003 1004 case MPI_DIAGNOSTIC_OFFSET: 1005 ret = s->diagnostic; 1006 break; 1007 1008 case MPI_HOST_INTERRUPT_STATUS_OFFSET: 1009 ret = s->intr_status; 1010 break; 1011 1012 case MPI_HOST_INTERRUPT_MASK_OFFSET: 1013 ret = s->intr_mask; 1014 break; 1015 1016 case MPI_REPLY_POST_FIFO_OFFSET: 1017 ret = mptsas_reply_post_read(s); 1018 break; 1019 1020 default: 1021 trace_mptsas_mmio_unhandled_read(s, addr); 1022 break; 1023 } 1024 trace_mptsas_mmio_read(s, addr, ret); 1025 return ret; 1026 } 1027 1028 static void mptsas_mmio_write(void *opaque, hwaddr addr, 1029 uint64_t val, unsigned size) 1030 { 1031 MPTSASState *s = opaque; 1032 1033 trace_mptsas_mmio_write(s, addr, val); 1034 switch (addr) { 1035 case MPI_DOORBELL_OFFSET: 1036 mptsas_doorbell_write(s, val); 1037 break; 1038 1039 case MPI_WRITE_SEQUENCE_OFFSET: 1040 mptsas_write_sequence_write(s, val); 1041 break; 1042 1043 case MPI_DIAGNOSTIC_OFFSET: 1044 if (val & MPI_DIAG_RESET_ADAPTER) { 1045 mptsas_hard_reset(s); 1046 } 1047 break; 1048 1049 case MPI_HOST_INTERRUPT_STATUS_OFFSET: 1050 mptsas_interrupt_status_write(s); 1051 break; 1052 1053 case MPI_HOST_INTERRUPT_MASK_OFFSET: 1054 s->intr_mask = val & (MPI_HIM_RIM | MPI_HIM_DIM); 1055 mptsas_update_interrupt(s); 1056 break; 1057 1058 case MPI_REQUEST_POST_FIFO_OFFSET: 1059 if (MPTSAS_FIFO_FULL(s, request_post)) { 1060 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); 1061 } else { 1062 MPTSAS_FIFO_PUT(s, request_post, val & ~0x03); 1063 qemu_bh_schedule(s->request_bh); 1064 } 1065 break; 1066 1067 case MPI_REPLY_FREE_FIFO_OFFSET: 1068 if (MPTSAS_FIFO_FULL(s, reply_free)) { 1069 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); 1070 } else { 1071 MPTSAS_FIFO_PUT(s, reply_free, val); 1072 } 1073 break; 1074 1075 default: 1076 trace_mptsas_mmio_unhandled_write(s, addr, val); 1077 break; 1078 } 1079 } 1080 1081 static const MemoryRegionOps mptsas_mmio_ops = { 1082 .read = mptsas_mmio_read, 1083 .write = mptsas_mmio_write, 1084 .endianness = DEVICE_LITTLE_ENDIAN, 1085 .impl = { 1086 .min_access_size = 4, 1087 .max_access_size = 4, 1088 } 1089 }; 1090 1091 static const MemoryRegionOps mptsas_port_ops = { 1092 .read = mptsas_mmio_read, 1093 .write = mptsas_mmio_write, 1094 .endianness = DEVICE_LITTLE_ENDIAN, 1095 .impl = { 1096 .min_access_size = 4, 1097 .max_access_size = 4, 1098 } 1099 }; 1100 1101 static uint64_t mptsas_diag_read(void *opaque, hwaddr addr, 1102 unsigned size) 1103 { 1104 MPTSASState *s = opaque; 1105 trace_mptsas_diag_read(s, addr, 0); 1106 return 0; 1107 } 1108 1109 static void mptsas_diag_write(void *opaque, hwaddr addr, 1110 uint64_t val, unsigned size) 1111 { 1112 MPTSASState *s = opaque; 1113 trace_mptsas_diag_write(s, addr, val); 1114 } 1115 1116 static const MemoryRegionOps mptsas_diag_ops = { 1117 .read = mptsas_diag_read, 1118 .write = mptsas_diag_write, 1119 .endianness = DEVICE_LITTLE_ENDIAN, 1120 .impl = { 1121 .min_access_size = 4, 1122 .max_access_size = 4, 1123 } 1124 }; 1125 1126 static QEMUSGList *mptsas_get_sg_list(SCSIRequest *sreq) 1127 { 1128 MPTSASRequest *req = sreq->hba_private; 1129 1130 return &req->qsg; 1131 } 1132 1133 static void mptsas_command_complete(SCSIRequest *sreq, 1134 size_t resid) 1135 { 1136 MPTSASRequest *req = sreq->hba_private; 1137 MPTSASState *s = req->dev; 1138 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE]; 1139 uint8_t sense_len; 1140 1141 hwaddr sense_buffer_addr = req->dev->sense_buffer_high_addr | 1142 req->scsi_io.SenseBufferLowAddr; 1143 1144 trace_mptsas_command_complete(s, req->scsi_io.MsgContext, 1145 sreq->status, resid); 1146 1147 sense_len = scsi_req_get_sense(sreq, sense_buf, SCSI_SENSE_BUF_SIZE); 1148 if (sense_len > 0) { 1149 pci_dma_write(PCI_DEVICE(s), sense_buffer_addr, sense_buf, 1150 MIN(req->scsi_io.SenseBufferLength, sense_len)); 1151 } 1152 1153 if (sreq->status != GOOD || resid || 1154 req->dev->doorbell_state == DOORBELL_WRITE) { 1155 MPIMsgSCSIIOReply reply; 1156 1157 memset(&reply, 0, sizeof(reply)); 1158 reply.TargetID = req->scsi_io.TargetID; 1159 reply.Bus = req->scsi_io.Bus; 1160 reply.MsgLength = sizeof(reply) / 4; 1161 reply.Function = req->scsi_io.Function; 1162 reply.CDBLength = req->scsi_io.CDBLength; 1163 reply.SenseBufferLength = req->scsi_io.SenseBufferLength; 1164 reply.MsgFlags = req->scsi_io.MsgFlags; 1165 reply.MsgContext = req->scsi_io.MsgContext; 1166 reply.SCSIStatus = sreq->status; 1167 if (sreq->status == GOOD) { 1168 reply.TransferCount = req->scsi_io.DataLength - resid; 1169 if (resid) { 1170 reply.IOCStatus = MPI_IOCSTATUS_SCSI_DATA_UNDERRUN; 1171 } 1172 } else { 1173 reply.SCSIState = MPI_SCSI_STATE_AUTOSENSE_VALID; 1174 reply.SenseCount = sense_len; 1175 reply.IOCStatus = MPI_IOCSTATUS_SCSI_DATA_UNDERRUN; 1176 } 1177 1178 mptsas_fix_scsi_io_reply_endianness(&reply); 1179 mptsas_post_reply(req->dev, (MPIDefaultReply *)&reply); 1180 } else { 1181 mptsas_turbo_reply(req->dev, req->scsi_io.MsgContext); 1182 } 1183 1184 mptsas_free_request(req); 1185 } 1186 1187 static void mptsas_request_cancelled(SCSIRequest *sreq) 1188 { 1189 MPTSASRequest *req = sreq->hba_private; 1190 MPIMsgSCSIIOReply reply; 1191 1192 memset(&reply, 0, sizeof(reply)); 1193 reply.TargetID = req->scsi_io.TargetID; 1194 reply.Bus = req->scsi_io.Bus; 1195 reply.MsgLength = sizeof(reply) / 4; 1196 reply.Function = req->scsi_io.Function; 1197 reply.CDBLength = req->scsi_io.CDBLength; 1198 reply.SenseBufferLength = req->scsi_io.SenseBufferLength; 1199 reply.MsgFlags = req->scsi_io.MsgFlags; 1200 reply.MsgContext = req->scsi_io.MsgContext; 1201 reply.SCSIState = MPI_SCSI_STATE_NO_SCSI_STATUS; 1202 reply.IOCStatus = MPI_IOCSTATUS_SCSI_TASK_TERMINATED; 1203 1204 mptsas_fix_scsi_io_reply_endianness(&reply); 1205 mptsas_post_reply(req->dev, (MPIDefaultReply *)&reply); 1206 mptsas_free_request(req); 1207 } 1208 1209 static void mptsas_save_request(QEMUFile *f, SCSIRequest *sreq) 1210 { 1211 MPTSASRequest *req = sreq->hba_private; 1212 int i; 1213 1214 qemu_put_buffer(f, (unsigned char *)&req->scsi_io, sizeof(req->scsi_io)); 1215 qemu_put_be32(f, req->qsg.nsg); 1216 for (i = 0; i < req->qsg.nsg; i++) { 1217 qemu_put_be64(f, req->qsg.sg[i].base); 1218 qemu_put_be64(f, req->qsg.sg[i].len); 1219 } 1220 } 1221 1222 static void *mptsas_load_request(QEMUFile *f, SCSIRequest *sreq) 1223 { 1224 SCSIBus *bus = sreq->bus; 1225 MPTSASState *s = container_of(bus, MPTSASState, bus); 1226 PCIDevice *pci = PCI_DEVICE(s); 1227 MPTSASRequest *req; 1228 int i, n; 1229 1230 req = g_new(MPTSASRequest, 1); 1231 qemu_get_buffer(f, (unsigned char *)&req->scsi_io, sizeof(req->scsi_io)); 1232 1233 n = qemu_get_be32(f); 1234 /* TODO: add a way for SCSIBusInfo's load_request to fail, 1235 * and fail migration instead of asserting here. 1236 * This is just one thing (there are probably more) that must be 1237 * fixed before we can allow NDEBUG compilation. 1238 */ 1239 assert(n >= 0); 1240 1241 pci_dma_sglist_init(&req->qsg, pci, n); 1242 for (i = 0; i < n; i++) { 1243 uint64_t base = qemu_get_be64(f); 1244 uint64_t len = qemu_get_be64(f); 1245 qemu_sglist_add(&req->qsg, base, len); 1246 } 1247 1248 scsi_req_ref(sreq); 1249 req->sreq = sreq; 1250 req->dev = s; 1251 1252 return req; 1253 } 1254 1255 static const struct SCSIBusInfo mptsas_scsi_info = { 1256 .tcq = true, 1257 .max_target = MPTSAS_NUM_PORTS, 1258 .max_lun = 1, 1259 1260 .get_sg_list = mptsas_get_sg_list, 1261 .complete = mptsas_command_complete, 1262 .cancel = mptsas_request_cancelled, 1263 .save_request = mptsas_save_request, 1264 .load_request = mptsas_load_request, 1265 }; 1266 1267 static void mptsas_scsi_realize(PCIDevice *dev, Error **errp) 1268 { 1269 MPTSASState *s = MPT_SAS(dev); 1270 Error *err = NULL; 1271 int ret; 1272 1273 dev->config[PCI_LATENCY_TIMER] = 0; 1274 dev->config[PCI_INTERRUPT_PIN] = 0x01; 1275 1276 if (s->msi != ON_OFF_AUTO_OFF) { 1277 ret = msi_init(dev, 0, 1, true, false, &err); 1278 /* Any error other than -ENOTSUP(board's MSI support is broken) 1279 * is a programming error */ 1280 assert(!ret || ret == -ENOTSUP); 1281 if (ret && s->msi == ON_OFF_AUTO_ON) { 1282 /* Can't satisfy user's explicit msi=on request, fail */ 1283 error_append_hint(&err, "You have to use msi=auto (default) or " 1284 "msi=off with this machine type.\n"); 1285 error_propagate(errp, err); 1286 return; 1287 } 1288 assert(!err || s->msi == ON_OFF_AUTO_AUTO); 1289 /* With msi=auto, we fall back to MSI off silently */ 1290 error_free(err); 1291 1292 /* Only used for migration. */ 1293 s->msi_in_use = (ret == 0); 1294 } 1295 1296 memory_region_init_io(&s->mmio_io, OBJECT(s), &mptsas_mmio_ops, s, 1297 "mptsas-mmio", 0x4000); 1298 memory_region_init_io(&s->port_io, OBJECT(s), &mptsas_port_ops, s, 1299 "mptsas-io", 256); 1300 memory_region_init_io(&s->diag_io, OBJECT(s), &mptsas_diag_ops, s, 1301 "mptsas-diag", 0x10000); 1302 1303 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->port_io); 1304 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY | 1305 PCI_BASE_ADDRESS_MEM_TYPE_32, &s->mmio_io); 1306 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY | 1307 PCI_BASE_ADDRESS_MEM_TYPE_32, &s->diag_io); 1308 1309 if (!s->sas_addr) { 1310 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) | 1311 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36; 1312 s->sas_addr |= (pci_dev_bus_num(dev) << 16); 1313 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8); 1314 s->sas_addr |= PCI_FUNC(dev->devfn); 1315 } 1316 s->max_devices = MPTSAS_NUM_PORTS; 1317 1318 s->request_bh = qemu_bh_new(mptsas_fetch_requests, s); 1319 1320 scsi_bus_init(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info); 1321 } 1322 1323 static void mptsas_scsi_uninit(PCIDevice *dev) 1324 { 1325 MPTSASState *s = MPT_SAS(dev); 1326 1327 qemu_bh_delete(s->request_bh); 1328 msi_uninit(dev); 1329 } 1330 1331 static void mptsas_reset(DeviceState *dev) 1332 { 1333 MPTSASState *s = MPT_SAS(dev); 1334 1335 mptsas_hard_reset(s); 1336 } 1337 1338 static int mptsas_post_load(void *opaque, int version_id) 1339 { 1340 MPTSASState *s = opaque; 1341 1342 if (s->doorbell_idx > s->doorbell_cnt || 1343 s->doorbell_cnt > ARRAY_SIZE(s->doorbell_msg) || 1344 s->doorbell_reply_idx > s->doorbell_reply_size || 1345 s->doorbell_reply_size > ARRAY_SIZE(s->doorbell_reply) || 1346 MPTSAS_FIFO_INVALID(s, request_post) || 1347 MPTSAS_FIFO_INVALID(s, reply_post) || 1348 MPTSAS_FIFO_INVALID(s, reply_free) || 1349 s->diagnostic_idx > 4) { 1350 return -EINVAL; 1351 } 1352 1353 return 0; 1354 } 1355 1356 static const VMStateDescription vmstate_mptsas = { 1357 .name = "mptsas", 1358 .version_id = 0, 1359 .minimum_version_id = 0, 1360 .minimum_version_id_old = 0, 1361 .post_load = mptsas_post_load, 1362 .fields = (VMStateField[]) { 1363 VMSTATE_PCI_DEVICE(dev, MPTSASState), 1364 VMSTATE_BOOL(msi_in_use, MPTSASState), 1365 VMSTATE_UINT32(state, MPTSASState), 1366 VMSTATE_UINT8(who_init, MPTSASState), 1367 VMSTATE_UINT8(doorbell_state, MPTSASState), 1368 VMSTATE_UINT32_ARRAY(doorbell_msg, MPTSASState, 256), 1369 VMSTATE_INT32(doorbell_idx, MPTSASState), 1370 VMSTATE_INT32(doorbell_cnt, MPTSASState), 1371 1372 VMSTATE_UINT16_ARRAY(doorbell_reply, MPTSASState, 256), 1373 VMSTATE_INT32(doorbell_reply_idx, MPTSASState), 1374 VMSTATE_INT32(doorbell_reply_size, MPTSASState), 1375 1376 VMSTATE_UINT32(diagnostic, MPTSASState), 1377 VMSTATE_UINT8(diagnostic_idx, MPTSASState), 1378 1379 VMSTATE_UINT32(intr_status, MPTSASState), 1380 VMSTATE_UINT32(intr_mask, MPTSASState), 1381 1382 VMSTATE_UINT32_ARRAY(request_post, MPTSASState, 1383 MPTSAS_REQUEST_QUEUE_DEPTH + 1), 1384 VMSTATE_UINT16(request_post_head, MPTSASState), 1385 VMSTATE_UINT16(request_post_tail, MPTSASState), 1386 1387 VMSTATE_UINT32_ARRAY(reply_post, MPTSASState, 1388 MPTSAS_REPLY_QUEUE_DEPTH + 1), 1389 VMSTATE_UINT16(reply_post_head, MPTSASState), 1390 VMSTATE_UINT16(reply_post_tail, MPTSASState), 1391 1392 VMSTATE_UINT32_ARRAY(reply_free, MPTSASState, 1393 MPTSAS_REPLY_QUEUE_DEPTH + 1), 1394 VMSTATE_UINT16(reply_free_head, MPTSASState), 1395 VMSTATE_UINT16(reply_free_tail, MPTSASState), 1396 1397 VMSTATE_UINT16(max_buses, MPTSASState), 1398 VMSTATE_UINT16(max_devices, MPTSASState), 1399 VMSTATE_UINT16(reply_frame_size, MPTSASState), 1400 VMSTATE_UINT64(host_mfa_high_addr, MPTSASState), 1401 VMSTATE_UINT64(sense_buffer_high_addr, MPTSASState), 1402 VMSTATE_END_OF_LIST() 1403 } 1404 }; 1405 1406 static Property mptsas_properties[] = { 1407 DEFINE_PROP_UINT64("sas_address", MPTSASState, sas_addr, 0), 1408 /* TODO: test MSI support under Windows */ 1409 DEFINE_PROP_ON_OFF_AUTO("msi", MPTSASState, msi, ON_OFF_AUTO_AUTO), 1410 DEFINE_PROP_END_OF_LIST(), 1411 }; 1412 1413 static void mptsas1068_class_init(ObjectClass *oc, void *data) 1414 { 1415 DeviceClass *dc = DEVICE_CLASS(oc); 1416 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc); 1417 1418 pc->realize = mptsas_scsi_realize; 1419 pc->exit = mptsas_scsi_uninit; 1420 pc->romfile = 0; 1421 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC; 1422 pc->device_id = PCI_DEVICE_ID_LSI_SAS1068; 1423 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC; 1424 pc->subsystem_id = 0x8000; 1425 pc->class_id = PCI_CLASS_STORAGE_SCSI; 1426 device_class_set_props(dc, mptsas_properties); 1427 dc->reset = mptsas_reset; 1428 dc->vmsd = &vmstate_mptsas; 1429 dc->desc = "LSI SAS 1068"; 1430 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1431 } 1432 1433 static const TypeInfo mptsas_info = { 1434 .name = TYPE_MPTSAS1068, 1435 .parent = TYPE_PCI_DEVICE, 1436 .instance_size = sizeof(MPTSASState), 1437 .class_init = mptsas1068_class_init, 1438 .interfaces = (InterfaceInfo[]) { 1439 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1440 { }, 1441 }, 1442 }; 1443 1444 static void mptsas_register_types(void) 1445 { 1446 type_register(&mptsas_info); 1447 } 1448 1449 type_init(mptsas_register_types) 1450