1 /* 2 * NetBSD header file, copied from 3 * http://gitorious.org/freebsd/freebsd/blobs/HEAD/sys/dev/mfi/mfireg.h 4 */ 5 /*- 6 * Copyright (c) 2006 IronPort Systems 7 * Copyright (c) 2007 LSI Corp. 8 * Copyright (c) 2007 Rajesh Prabhakaran. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #ifndef SCSI_MFI_H 34 #define SCSI_MFI_H 35 36 /* 37 * MegaRAID SAS MFI firmware definitions 38 */ 39 40 /* 41 * Start with the register set. All registers are 32 bits wide. 42 * The usual Intel IOP style setup. 43 */ 44 #define MFI_IMSG0 0x10 /* Inbound message 0 */ 45 #define MFI_IMSG1 0x14 /* Inbound message 1 */ 46 #define MFI_OMSG0 0x18 /* Outbound message 0 */ 47 #define MFI_OMSG1 0x1c /* Outbound message 1 */ 48 #define MFI_IDB 0x20 /* Inbound doorbell */ 49 #define MFI_ISTS 0x24 /* Inbound interrupt status */ 50 #define MFI_IMSK 0x28 /* Inbound interrupt mask */ 51 #define MFI_ODB 0x2c /* Outbound doorbell */ 52 #define MFI_OSTS 0x30 /* Outbound interrupt status */ 53 #define MFI_OMSK 0x34 /* Outbound interrupt mask */ 54 #define MFI_IQP 0x40 /* Inbound queue port */ 55 #define MFI_OQP 0x44 /* Outbound queue port */ 56 57 /* 58 * 1078 specific related register 59 */ 60 #define MFI_ODR0 0x9c /* outbound doorbell register0 */ 61 #define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */ 62 #define MFI_OSP0 0xb0 /* outbound scratch pad0 */ 63 #define MFI_OSP1 0xb4 /* outbound scratch pad1 */ 64 #define MFI_IQPL 0xc0 /* Inbound queue port (low bytes) */ 65 #define MFI_IQPH 0xc4 /* Inbound queue port (high bytes) */ 66 #define MFI_DIAG 0xf8 /* Host diag */ 67 #define MFI_SEQ 0xfc /* Sequencer offset */ 68 #define MFI_1078_EIM 0x80000004 /* 1078 enable interrupt mask */ 69 #define MFI_RMI 0x2 /* reply message interrupt */ 70 #define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */ 71 #define MFI_ODC 0x4 /* outbound doorbell change interrupt */ 72 73 /* 74 * gen2 specific changes 75 */ 76 #define MFI_GEN2_EIM 0x00000005 /* gen2 enable interrupt mask */ 77 #define MFI_GEN2_RM 0x00000001 /* reply gen2 message interrupt */ 78 79 /* 80 * skinny specific changes 81 */ 82 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 83 #define MFI_SKINNY_RM 0x00000001 /* reply skinny message interrupt */ 84 85 /* Bits for MFI_OSTS */ 86 #define MFI_OSTS_INTR_VALID 0x00000002 87 88 /* 89 * Firmware state values. Found in OMSG0 during initialization. 90 */ 91 #define MFI_FWSTATE_MASK 0xf0000000 92 #define MFI_FWSTATE_UNDEFINED 0x00000000 93 #define MFI_FWSTATE_BB_INIT 0x10000000 94 #define MFI_FWSTATE_FW_INIT 0x40000000 95 #define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000 96 #define MFI_FWSTATE_FW_INIT_2 0x70000000 97 #define MFI_FWSTATE_DEVICE_SCAN 0x80000000 98 #define MFI_FWSTATE_BOOT_MSG_PENDING 0x90000000 99 #define MFI_FWSTATE_FLUSH_CACHE 0xa0000000 100 #define MFI_FWSTATE_READY 0xb0000000 101 #define MFI_FWSTATE_OPERATIONAL 0xc0000000 102 #define MFI_FWSTATE_FAULT 0xf0000000 103 #define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000 104 #define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff 105 #define MFI_FWSTATE_MSIX_SUPPORTED 0x04000000 106 #define MFI_FWSTATE_HOSTMEMREQD_MASK 0x08000000 107 108 /* 109 * Control bits to drive the card to ready state. These go into the IDB 110 * register. 111 */ 112 #define MFI_FWINIT_ABORT 0x00000001 /* Abort all pending commands */ 113 #define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */ 114 #define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */ 115 #define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */ 116 #define MFI_FWINIT_HOTPLUG 0x00000010 117 #define MFI_FWINIT_STOP_ADP 0x00000020 /* Move to operational, stop */ 118 #define MFI_FWINIT_ADP_RESET 0x00000040 /* Reset ADP */ 119 120 /* 121 * Control bits for the DIAG register 122 */ 123 #define MFI_DIAG_WRITE_ENABLE 0x00000080 124 #define MFI_DIAG_RESET_ADP 0x00000004 125 126 /* MFI Commands */ 127 typedef enum { 128 MFI_CMD_INIT = 0x00, 129 MFI_CMD_LD_READ, 130 MFI_CMD_LD_WRITE, 131 MFI_CMD_LD_SCSI_IO, 132 MFI_CMD_PD_SCSI_IO, 133 MFI_CMD_DCMD, 134 MFI_CMD_ABORT, 135 MFI_CMD_SMP, 136 MFI_CMD_STP 137 } mfi_cmd_t; 138 139 /* Direct commands */ 140 typedef enum { 141 MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC = 0x0100e100, 142 MFI_DCMD_CTRL_GET_INFO = 0x01010000, 143 MFI_DCMD_CTRL_GET_PROPERTIES = 0x01020100, 144 MFI_DCMD_CTRL_SET_PROPERTIES = 0x01020200, 145 MFI_DCMD_CTRL_ALARM = 0x01030000, 146 MFI_DCMD_CTRL_ALARM_GET = 0x01030100, 147 MFI_DCMD_CTRL_ALARM_ENABLE = 0x01030200, 148 MFI_DCMD_CTRL_ALARM_DISABLE = 0x01030300, 149 MFI_DCMD_CTRL_ALARM_SILENCE = 0x01030400, 150 MFI_DCMD_CTRL_ALARM_TEST = 0x01030500, 151 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100, 152 MFI_DCMD_CTRL_EVENT_CLEAR = 0x01040200, 153 MFI_DCMD_CTRL_EVENT_GET = 0x01040300, 154 MFI_DCMD_CTRL_EVENT_COUNT = 0x01040400, 155 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500, 156 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000, 157 MFI_DCMD_HIBERNATE_STANDBY = 0x01060000, 158 MFI_DCMD_CTRL_GET_TIME = 0x01080101, 159 MFI_DCMD_CTRL_SET_TIME = 0x01080102, 160 MFI_DCMD_CTRL_BIOS_DATA_GET = 0x010c0100, 161 MFI_DCMD_CTRL_BIOS_DATA_SET = 0x010c0200, 162 MFI_DCMD_CTRL_FACTORY_DEFAULTS = 0x010d0000, 163 MFI_DCMD_CTRL_MFC_DEFAULTS_GET = 0x010e0201, 164 MFI_DCMD_CTRL_MFC_DEFAULTS_SET = 0x010e0202, 165 MFI_DCMD_CTRL_CACHE_FLUSH = 0x01101000, 166 MFI_DCMD_PD_GET_LIST = 0x02010000, 167 MFI_DCMD_PD_LIST_QUERY = 0x02010100, 168 MFI_DCMD_PD_GET_INFO = 0x02020000, 169 MFI_DCMD_PD_STATE_SET = 0x02030100, 170 MFI_DCMD_PD_REBUILD = 0x02040100, 171 MFI_DCMD_PD_BLINK = 0x02070100, 172 MFI_DCMD_PD_UNBLINK = 0x02070200, 173 MFI_DCMD_LD_GET_LIST = 0x03010000, 174 MFI_DCMD_LD_LIST_QUERY = 0x03010100, 175 MFI_DCMD_LD_GET_INFO = 0x03020000, 176 MFI_DCMD_LD_GET_PROP = 0x03030000, 177 MFI_DCMD_LD_SET_PROP = 0x03040000, 178 MFI_DCMD_LD_DELETE = 0x03090000, 179 MFI_DCMD_CFG_READ = 0x04010000, 180 MFI_DCMD_CFG_ADD = 0x04020000, 181 MFI_DCMD_CFG_CLEAR = 0x04030000, 182 MFI_DCMD_CFG_FOREIGN_READ = 0x04060100, 183 MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400, 184 MFI_DCMD_BBU_STATUS = 0x05010000, 185 MFI_DCMD_BBU_CAPACITY_INFO = 0x05020000, 186 MFI_DCMD_BBU_DESIGN_INFO = 0x05030000, 187 MFI_DCMD_BBU_PROP_GET = 0x05050100, 188 MFI_DCMD_CLUSTER = 0x08000000, 189 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100, 190 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200 191 } mfi_dcmd_t; 192 193 /* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */ 194 #define MFI_FLUSHCACHE_CTRL 0x01 195 #define MFI_FLUSHCACHE_DISK 0x02 196 197 /* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */ 198 #define MFI_SHUTDOWN_SPINDOWN 0x01 199 200 /* 201 * MFI Frame flags 202 */ 203 typedef enum { 204 MFI_FRAME_DONT_POST_IN_REPLY_QUEUE = 0x0001, 205 MFI_FRAME_SGL64 = 0x0002, 206 MFI_FRAME_SENSE64 = 0x0004, 207 MFI_FRAME_DIR_WRITE = 0x0008, 208 MFI_FRAME_DIR_READ = 0x0010, 209 MFI_FRAME_IEEE_SGL = 0x0020, 210 } mfi_frame_flags; 211 212 /* MFI Status codes */ 213 typedef enum { 214 MFI_STAT_OK = 0x00, 215 MFI_STAT_INVALID_CMD, 216 MFI_STAT_INVALID_DCMD, 217 MFI_STAT_INVALID_PARAMETER, 218 MFI_STAT_INVALID_SEQUENCE_NUMBER, 219 MFI_STAT_ABORT_NOT_POSSIBLE, 220 MFI_STAT_APP_HOST_CODE_NOT_FOUND, 221 MFI_STAT_APP_IN_USE, 222 MFI_STAT_APP_NOT_INITIALIZED, 223 MFI_STAT_ARRAY_INDEX_INVALID, 224 MFI_STAT_ARRAY_ROW_NOT_EMPTY, 225 MFI_STAT_CONFIG_RESOURCE_CONFLICT, 226 MFI_STAT_DEVICE_NOT_FOUND, 227 MFI_STAT_DRIVE_TOO_SMALL, 228 MFI_STAT_FLASH_ALLOC_FAIL, 229 MFI_STAT_FLASH_BUSY, 230 MFI_STAT_FLASH_ERROR = 0x10, 231 MFI_STAT_FLASH_IMAGE_BAD, 232 MFI_STAT_FLASH_IMAGE_INCOMPLETE, 233 MFI_STAT_FLASH_NOT_OPEN, 234 MFI_STAT_FLASH_NOT_STARTED, 235 MFI_STAT_FLUSH_FAILED, 236 MFI_STAT_HOST_CODE_NOT_FOUNT, 237 MFI_STAT_LD_CC_IN_PROGRESS, 238 MFI_STAT_LD_INIT_IN_PROGRESS, 239 MFI_STAT_LD_LBA_OUT_OF_RANGE, 240 MFI_STAT_LD_MAX_CONFIGURED, 241 MFI_STAT_LD_NOT_OPTIMAL, 242 MFI_STAT_LD_RBLD_IN_PROGRESS, 243 MFI_STAT_LD_RECON_IN_PROGRESS, 244 MFI_STAT_LD_WRONG_RAID_LEVEL, 245 MFI_STAT_MAX_SPARES_EXCEEDED, 246 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 247 MFI_STAT_MFC_HW_ERROR, 248 MFI_STAT_NO_HW_PRESENT, 249 MFI_STAT_NOT_FOUND, 250 MFI_STAT_NOT_IN_ENCL, 251 MFI_STAT_PD_CLEAR_IN_PROGRESS, 252 MFI_STAT_PD_TYPE_WRONG, 253 MFI_STAT_PR_DISABLED, 254 MFI_STAT_ROW_INDEX_INVALID, 255 MFI_STAT_SAS_CONFIG_INVALID_ACTION, 256 MFI_STAT_SAS_CONFIG_INVALID_DATA, 257 MFI_STAT_SAS_CONFIG_INVALID_PAGE, 258 MFI_STAT_SAS_CONFIG_INVALID_TYPE, 259 MFI_STAT_SCSI_DONE_WITH_ERROR, 260 MFI_STAT_SCSI_IO_FAILED, 261 MFI_STAT_SCSI_RESERVATION_CONFLICT, 262 MFI_STAT_SHUTDOWN_FAILED = 0x30, 263 MFI_STAT_TIME_NOT_SET, 264 MFI_STAT_WRONG_STATE, 265 MFI_STAT_LD_OFFLINE, 266 MFI_STAT_PEER_NOTIFICATION_REJECTED, 267 MFI_STAT_PEER_NOTIFICATION_FAILED, 268 MFI_STAT_RESERVATION_IN_PROGRESS, 269 MFI_STAT_I2C_ERRORS_DETECTED, 270 MFI_STAT_PCI_ERRORS_DETECTED, 271 MFI_STAT_DIAG_FAILED, 272 MFI_STAT_BOOT_MSG_PENDING, 273 MFI_STAT_FOREIGN_CONFIG_INCOMPLETE, 274 MFI_STAT_INVALID_SGL, 275 MFI_STAT_UNSUPPORTED_HW, 276 MFI_STAT_CC_SCHEDULE_DISABLED, 277 MFI_STAT_PD_COPYBACK_IN_PROGRESS, 278 MFI_STAT_MULTIPLE_PDS_IN_ARRAY = 0x40, 279 MFI_STAT_FW_DOWNLOAD_ERROR, 280 MFI_STAT_FEATURE_SECURITY_NOT_ENABLED, 281 MFI_STAT_LOCK_KEY_ALREADY_EXISTS, 282 MFI_STAT_LOCK_KEY_BACKUP_NOT_ALLOWED, 283 MFI_STAT_LOCK_KEY_VERIFY_NOT_ALLOWED, 284 MFI_STAT_LOCK_KEY_VERIFY_FAILED, 285 MFI_STAT_LOCK_KEY_REKEY_NOT_ALLOWED, 286 MFI_STAT_LOCK_KEY_INVALID, 287 MFI_STAT_LOCK_KEY_ESCROW_INVALID, 288 MFI_STAT_LOCK_KEY_BACKUP_REQUIRED, 289 MFI_STAT_SECURE_LD_EXISTS, 290 MFI_STAT_LD_SECURE_NOT_ALLOWED, 291 MFI_STAT_REPROVISION_NOT_ALLOWED, 292 MFI_STAT_PD_SECURITY_TYPE_WRONG, 293 MFI_STAT_LD_ENCRYPTION_TYPE_INVALID, 294 MFI_STAT_CONFIG_FDE_NON_FDE_MIX_NOT_ALLOWED = 0x50, 295 MFI_STAT_CONFIG_LD_ENCRYPTION_TYPE_MIX_NOT_ALLOWED, 296 MFI_STAT_SECRET_KEY_NOT_ALLOWED, 297 MFI_STAT_PD_HW_ERRORS_DETECTED, 298 MFI_STAT_LD_CACHE_PINNED, 299 MFI_STAT_POWER_STATE_SET_IN_PROGRESS, 300 MFI_STAT_POWER_STATE_SET_BUSY, 301 MFI_STAT_POWER_STATE_WRONG, 302 MFI_STAT_PR_NO_AVAILABLE_PD_FOUND, 303 MFI_STAT_CTRL_RESET_REQUIRED, 304 MFI_STAT_LOCK_KEY_EKM_NO_BOOT_AGENT, 305 MFI_STAT_SNAP_NO_SPACE, 306 MFI_STAT_SNAP_PARTIAL_FAILURE, 307 MFI_STAT_UPGRADE_KEY_INCOMPATIBLE, 308 MFI_STAT_PFK_INCOMPATIBLE, 309 MFI_STAT_PD_MAX_UNCONFIGURED, 310 MFI_STAT_IO_METRICS_DISABLED = 0x60, 311 MFI_STAT_AEC_NOT_STOPPED, 312 MFI_STAT_PI_TYPE_WRONG, 313 MFI_STAT_LD_PD_PI_INCOMPATIBLE, 314 MFI_STAT_PI_NOT_ENABLED, 315 MFI_STAT_LD_BLOCK_SIZE_MISMATCH, 316 MFI_STAT_INVALID_STATUS = 0xFF 317 } mfi_status_t; 318 319 /* Event classes */ 320 typedef enum { 321 MFI_EVT_CLASS_DEBUG = -2, 322 MFI_EVT_CLASS_PROGRESS = -1, 323 MFI_EVT_CLASS_INFO = 0, 324 MFI_EVT_CLASS_WARNING = 1, 325 MFI_EVT_CLASS_CRITICAL = 2, 326 MFI_EVT_CLASS_FATAL = 3, 327 MFI_EVT_CLASS_DEAD = 4 328 } mfi_evt_class_t; 329 330 /* Event locales */ 331 typedef enum { 332 MFI_EVT_LOCALE_LD = 0x0001, 333 MFI_EVT_LOCALE_PD = 0x0002, 334 MFI_EVT_LOCALE_ENCL = 0x0004, 335 MFI_EVT_LOCALE_BBU = 0x0008, 336 MFI_EVT_LOCALE_SAS = 0x0010, 337 MFI_EVT_LOCALE_CTRL = 0x0020, 338 MFI_EVT_LOCALE_CONFIG = 0x0040, 339 MFI_EVT_LOCALE_CLUSTER = 0x0080, 340 MFI_EVT_LOCALE_ALL = 0xffff 341 } mfi_evt_locale_t; 342 343 /* Event args */ 344 typedef enum { 345 MR_EVT_ARGS_NONE = 0x00, 346 MR_EVT_ARGS_CDB_SENSE, 347 MR_EVT_ARGS_LD, 348 MR_EVT_ARGS_LD_COUNT, 349 MR_EVT_ARGS_LD_LBA, 350 MR_EVT_ARGS_LD_OWNER, 351 MR_EVT_ARGS_LD_LBA_PD_LBA, 352 MR_EVT_ARGS_LD_PROG, 353 MR_EVT_ARGS_LD_STATE, 354 MR_EVT_ARGS_LD_STRIP, 355 MR_EVT_ARGS_PD, 356 MR_EVT_ARGS_PD_ERR, 357 MR_EVT_ARGS_PD_LBA, 358 MR_EVT_ARGS_PD_LBA_LD, 359 MR_EVT_ARGS_PD_PROG, 360 MR_EVT_ARGS_PD_STATE, 361 MR_EVT_ARGS_PCI, 362 MR_EVT_ARGS_RATE, 363 MR_EVT_ARGS_STR, 364 MR_EVT_ARGS_TIME, 365 MR_EVT_ARGS_ECC, 366 MR_EVT_ARGS_LD_PROP, 367 MR_EVT_ARGS_PD_SPARE, 368 MR_EVT_ARGS_PD_INDEX, 369 MR_EVT_ARGS_DIAG_PASS, 370 MR_EVT_ARGS_DIAG_FAIL, 371 MR_EVT_ARGS_PD_LBA_LBA, 372 MR_EVT_ARGS_PORT_PHY, 373 MR_EVT_ARGS_PD_MISSING, 374 MR_EVT_ARGS_PD_ADDRESS, 375 MR_EVT_ARGS_BITMAP, 376 MR_EVT_ARGS_CONNECTOR, 377 MR_EVT_ARGS_PD_PD, 378 MR_EVT_ARGS_PD_FRU, 379 MR_EVT_ARGS_PD_PATHINFO, 380 MR_EVT_ARGS_PD_POWER_STATE, 381 MR_EVT_ARGS_GENERIC, 382 } mfi_evt_args; 383 384 /* Event codes */ 385 #define MR_EVT_CFG_CLEARED 0x0004 386 #define MR_EVT_CTRL_SHUTDOWN 0x002a 387 #define MR_EVT_LD_STATE_CHANGE 0x0051 388 #define MR_EVT_PD_INSERTED 0x005b 389 #define MR_EVT_PD_REMOVED 0x0070 390 #define MR_EVT_PD_STATE_CHANGED 0x0072 391 #define MR_EVT_LD_CREATED 0x008a 392 #define MR_EVT_LD_DELETED 0x008b 393 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 394 #define MR_EVT_LD_OFFLINE 0x00fc 395 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 396 397 typedef enum { 398 MR_LD_CACHE_WRITE_BACK = 0x01, 399 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02, 400 MR_LD_CACHE_READ_AHEAD = 0x04, 401 MR_LD_CACHE_READ_ADAPTIVE = 0x08, 402 MR_LD_CACHE_WRITE_CACHE_BAD_BBU = 0x10, 403 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20, 404 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40 405 } mfi_ld_cache; 406 407 typedef enum { 408 MR_PD_CACHE_UNCHANGED = 0, 409 MR_PD_CACHE_ENABLE = 1, 410 MR_PD_CACHE_DISABLE = 2 411 } mfi_pd_cache; 412 413 typedef enum { 414 MR_PD_QUERY_TYPE_ALL = 0, 415 MR_PD_QUERY_TYPE_STATE = 1, 416 MR_PD_QUERY_TYPE_POWER_STATE = 2, 417 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 418 MR_PD_QUERY_TYPE_SPEED = 4, 419 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, /*query for system drives */ 420 } mfi_pd_query_type; 421 422 typedef enum { 423 MR_LD_QUERY_TYPE_ALL = 0, 424 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1, 425 MR_LD_QUERY_TYPE_USED_TGT_IDS = 2, 426 MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3, 427 MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4, 428 } mfi_ld_query_type; 429 430 /* 431 * Other propertities and definitions 432 */ 433 #define MFI_MAX_PD_CHANNELS 2 434 #define MFI_MAX_LD_CHANNELS 2 435 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 436 #define MFI_MAX_CHANNEL_DEVS 128 437 #define MFI_DEFAULT_ID -1 438 #define MFI_MAX_LUN 8 439 #define MFI_MAX_LD 64 440 441 #define MFI_FRAME_SIZE 64 442 #define MFI_MBOX_SIZE 12 443 444 /* Firmware flashing can take 40s */ 445 #define MFI_POLL_TIMEOUT_SECS 50 446 447 /* Allow for speedier math calculations */ 448 #define MFI_SECTOR_LEN 512 449 450 /* Scatter Gather elements */ 451 struct mfi_sg32 { 452 uint32_t addr; 453 uint32_t len; 454 } QEMU_PACKED; 455 456 struct mfi_sg64 { 457 uint64_t addr; 458 uint32_t len; 459 } QEMU_PACKED; 460 461 struct mfi_sg_skinny { 462 uint64_t addr; 463 uint32_t len; 464 uint32_t flag; 465 } QEMU_PACKED; 466 467 union mfi_sgl { 468 struct mfi_sg32 sg32[1]; 469 struct mfi_sg64 sg64[1]; 470 struct mfi_sg_skinny sg_skinny[1]; 471 } QEMU_PACKED; 472 473 /* Message frames. All messages have a common header */ 474 struct mfi_frame_header { 475 uint8_t frame_cmd; 476 uint8_t sense_len; 477 uint8_t cmd_status; 478 uint8_t scsi_status; 479 uint8_t target_id; 480 uint8_t lun_id; 481 uint8_t cdb_len; 482 uint8_t sge_count; 483 uint64_t context; 484 uint16_t flags; 485 uint16_t timeout; 486 uint32_t data_len; 487 } QEMU_PACKED; 488 489 struct mfi_init_frame { 490 struct mfi_frame_header header; 491 uint32_t qinfo_new_addr_lo; 492 uint32_t qinfo_new_addr_hi; 493 uint32_t qinfo_old_addr_lo; 494 uint32_t qinfo_old_addr_hi; 495 uint32_t reserved[6]; 496 }; 497 498 #define MFI_IO_FRAME_SIZE 40 499 struct mfi_io_frame { 500 struct mfi_frame_header header; 501 uint32_t sense_addr_lo; 502 uint32_t sense_addr_hi; 503 uint32_t lba_lo; 504 uint32_t lba_hi; 505 union mfi_sgl sgl; 506 } QEMU_PACKED; 507 508 #define MFI_PASS_FRAME_SIZE 48 509 struct mfi_pass_frame { 510 struct mfi_frame_header header; 511 uint32_t sense_addr_lo; 512 uint32_t sense_addr_hi; 513 uint8_t cdb[16]; 514 union mfi_sgl sgl; 515 } QEMU_PACKED; 516 517 #define MFI_DCMD_FRAME_SIZE 40 518 struct mfi_dcmd_frame { 519 struct mfi_frame_header header; 520 uint32_t opcode; 521 uint8_t mbox[MFI_MBOX_SIZE]; 522 union mfi_sgl sgl; 523 } QEMU_PACKED; 524 525 struct mfi_abort_frame { 526 struct mfi_frame_header header; 527 uint64_t abort_context; 528 uint32_t abort_mfi_addr_lo; 529 uint32_t abort_mfi_addr_hi; 530 uint32_t reserved1[6]; 531 } QEMU_PACKED; 532 533 struct mfi_smp_frame { 534 struct mfi_frame_header header; 535 uint64_t sas_addr; 536 union { 537 struct mfi_sg32 sg32[2]; 538 struct mfi_sg64 sg64[2]; 539 } sgl; 540 } QEMU_PACKED; 541 542 struct mfi_stp_frame { 543 struct mfi_frame_header header; 544 uint16_t fis[10]; 545 uint32_t stp_flags; 546 union { 547 struct mfi_sg32 sg32[2]; 548 struct mfi_sg64 sg64[2]; 549 } sgl; 550 } QEMU_PACKED; 551 552 union mfi_frame { 553 struct mfi_frame_header header; 554 struct mfi_init_frame init; 555 struct mfi_io_frame io; 556 struct mfi_pass_frame pass; 557 struct mfi_dcmd_frame dcmd; 558 struct mfi_abort_frame abort; 559 struct mfi_smp_frame smp; 560 struct mfi_stp_frame stp; 561 uint64_t raw[8]; 562 uint8_t bytes[MFI_FRAME_SIZE]; 563 }; 564 565 #define MFI_SENSE_LEN 128 566 struct mfi_sense { 567 uint8_t data[MFI_SENSE_LEN]; 568 }; 569 570 #define MFI_QUEUE_FLAG_CONTEXT64 0x00000002 571 572 /* The queue init structure that is passed with the init message */ 573 struct mfi_init_qinfo { 574 uint32_t flags; 575 uint32_t rq_entries; 576 uint32_t rq_addr_lo; 577 uint32_t rq_addr_hi; 578 uint32_t pi_addr_lo; 579 uint32_t pi_addr_hi; 580 uint32_t ci_addr_lo; 581 uint32_t ci_addr_hi; 582 } QEMU_PACKED; 583 584 /* Controller properties */ 585 struct mfi_ctrl_props { 586 uint16_t seq_num; 587 uint16_t pred_fail_poll_interval; 588 uint16_t intr_throttle_cnt; 589 uint16_t intr_throttle_timeout; 590 uint8_t rebuild_rate; 591 uint8_t patrol_read_rate; 592 uint8_t bgi_rate; 593 uint8_t cc_rate; 594 uint8_t recon_rate; 595 uint8_t cache_flush_interval; 596 uint8_t spinup_drv_cnt; 597 uint8_t spinup_delay; 598 uint8_t cluster_enable; 599 uint8_t coercion_mode; 600 uint8_t alarm_enable; 601 uint8_t disable_auto_rebuild; 602 uint8_t disable_battery_warn; 603 uint8_t ecc_bucket_size; 604 uint16_t ecc_bucket_leak_rate; 605 uint8_t restore_hotspare_on_insertion; 606 uint8_t expose_encl_devices; 607 uint8_t maintainPdFailHistory; 608 uint8_t disallowHostRequestReordering; 609 uint8_t abortCCOnError; 610 uint8_t loadBalanceMode; 611 uint8_t disableAutoDetectBackplane; 612 uint8_t snapVDSpace; 613 uint32_t OnOffProperties; 614 /* set TRUE to disable copyBack (0=copyback enabled) */ 615 #define MFI_CTRL_PROP_CopyBackDisabled (1 << 0) 616 #define MFI_CTRL_PROP_SMARTerEnabled (1 << 1) 617 #define MFI_CTRL_PROP_PRCorrectUnconfiguredAreas (1 << 2) 618 #define MFI_CTRL_PROP_UseFdeOnly (1 << 3) 619 #define MFI_CTRL_PROP_DisableNCQ (1 << 4) 620 #define MFI_CTRL_PROP_SSDSMARTerEnabled (1 << 5) 621 #define MFI_CTRL_PROP_SSDPatrolReadEnabled (1 << 6) 622 #define MFI_CTRL_PROP_EnableSpinDownUnconfigured (1 << 7) 623 #define MFI_CTRL_PROP_AutoEnhancedImport (1 << 8) 624 #define MFI_CTRL_PROP_EnableSecretKeyControl (1 << 9) 625 #define MFI_CTRL_PROP_DisableOnlineCtrlReset (1 << 10) 626 #define MFI_CTRL_PROP_AllowBootWithPinnedCache (1 << 11) 627 #define MFI_CTRL_PROP_DisableSpinDownHS (1 << 12) 628 #define MFI_CTRL_PROP_EnableJBOD (1 << 13) 629 630 uint8_t autoSnapVDSpace; /* % of source LD to be 631 * reserved for auto snapshot 632 * in snapshot repository, for 633 * metadata and user data 634 * 1=5%, 2=10%, 3=15% and so on 635 */ 636 uint8_t viewSpace; /* snapshot writable VIEWs 637 * capacity as a % of source LD 638 * capacity. 0=READ only 639 * 1=5%, 2=10%, 3=15% and so on 640 */ 641 uint16_t spinDownTime; /* # of idle minutes before device 642 * is spun down (0=use FW defaults) 643 */ 644 uint8_t reserved[24]; 645 } QEMU_PACKED; 646 647 /* PCI information about the card. */ 648 struct mfi_info_pci { 649 uint16_t vendor; 650 uint16_t device; 651 uint16_t subvendor; 652 uint16_t subdevice; 653 uint8_t reserved[24]; 654 } QEMU_PACKED; 655 656 /* Host (front end) interface information */ 657 struct mfi_info_host { 658 uint8_t type; 659 #define MFI_INFO_HOST_PCIX 0x01 660 #define MFI_INFO_HOST_PCIE 0x02 661 #define MFI_INFO_HOST_ISCSI 0x04 662 #define MFI_INFO_HOST_SAS3G 0x08 663 uint8_t reserved[6]; 664 uint8_t port_count; 665 uint64_t port_addr[8]; 666 } QEMU_PACKED; 667 668 /* Device (back end) interface information */ 669 struct mfi_info_device { 670 uint8_t type; 671 #define MFI_INFO_DEV_SPI 0x01 672 #define MFI_INFO_DEV_SAS3G 0x02 673 #define MFI_INFO_DEV_SATA1 0x04 674 #define MFI_INFO_DEV_SATA3G 0x08 675 #define MFI_INFO_DEV_PCIE 0x10 676 uint8_t reserved[6]; 677 uint8_t port_count; 678 uint64_t port_addr[8]; 679 } QEMU_PACKED; 680 681 /* Firmware component information */ 682 struct mfi_info_component { 683 char name[8]; 684 char version[32]; 685 char build_date[16]; 686 char build_time[16]; 687 } QEMU_PACKED; 688 689 /* Controller default settings */ 690 struct mfi_defaults { 691 uint64_t sas_addr; 692 uint8_t phy_polarity; 693 uint8_t background_rate; 694 uint8_t stripe_size; 695 uint8_t flush_time; 696 uint8_t write_back; 697 uint8_t read_ahead; 698 uint8_t cache_when_bbu_bad; 699 uint8_t cached_io; 700 uint8_t smart_mode; 701 uint8_t alarm_disable; 702 uint8_t coercion; 703 uint8_t zrc_config; 704 uint8_t dirty_led_shows_drive_activity; 705 uint8_t bios_continue_on_error; 706 uint8_t spindown_mode; 707 uint8_t allowed_device_types; 708 uint8_t allow_mix_in_enclosure; 709 uint8_t allow_mix_in_ld; 710 uint8_t allow_sata_in_cluster; 711 uint8_t max_chained_enclosures; 712 uint8_t disable_ctrl_r; 713 uint8_t enable_web_bios; 714 uint8_t phy_polarity_split; 715 uint8_t direct_pd_mapping; 716 uint8_t bios_enumerate_lds; 717 uint8_t restored_hot_spare_on_insertion; 718 uint8_t expose_enclosure_devices; 719 uint8_t maintain_pd_fail_history; 720 uint8_t disable_puncture; 721 uint8_t zero_based_enumeration; 722 uint8_t disable_preboot_cli; 723 uint8_t show_drive_led_on_activity; 724 uint8_t cluster_disable; 725 uint8_t sas_disable; 726 uint8_t auto_detect_backplane; 727 uint8_t fde_only; 728 uint8_t delay_during_post; 729 uint8_t resv[19]; 730 } QEMU_PACKED; 731 732 /* Controller default settings */ 733 struct mfi_bios_data { 734 uint16_t boot_target_id; 735 uint8_t do_not_int_13; 736 uint8_t continue_on_error; 737 uint8_t verbose; 738 uint8_t geometry; 739 uint8_t expose_all_drives; 740 uint8_t reserved[56]; 741 uint8_t check_sum; 742 } QEMU_PACKED; 743 744 /* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */ 745 struct mfi_ctrl_info { 746 struct mfi_info_pci pci; 747 struct mfi_info_host host; 748 struct mfi_info_device device; 749 750 /* Firmware components that are present and active. */ 751 uint32_t image_check_word; 752 uint32_t image_component_count; 753 struct mfi_info_component image_component[8]; 754 755 /* Firmware components that have been flashed but are inactive */ 756 uint32_t pending_image_component_count; 757 struct mfi_info_component pending_image_component[8]; 758 759 uint8_t max_arms; 760 uint8_t max_spans; 761 uint8_t max_arrays; 762 uint8_t max_lds; 763 char product_name[80]; 764 char serial_number[32]; 765 uint32_t hw_present; 766 #define MFI_INFO_HW_BBU 0x01 767 #define MFI_INFO_HW_ALARM 0x02 768 #define MFI_INFO_HW_NVRAM 0x04 769 #define MFI_INFO_HW_UART 0x08 770 #define MFI_INFO_HW_MEM 0x10 771 #define MFI_INFO_HW_FLASH 0x20 772 uint32_t current_fw_time; 773 uint16_t max_cmds; 774 uint16_t max_sg_elements; 775 uint32_t max_request_size; 776 uint16_t lds_present; 777 uint16_t lds_degraded; 778 uint16_t lds_offline; 779 uint16_t pd_present; 780 uint16_t pd_disks_present; 781 uint16_t pd_disks_pred_failure; 782 uint16_t pd_disks_failed; 783 uint16_t nvram_size; 784 uint16_t memory_size; 785 uint16_t flash_size; 786 uint16_t ram_correctable_errors; 787 uint16_t ram_uncorrectable_errors; 788 uint8_t cluster_allowed; 789 uint8_t cluster_active; 790 uint16_t max_strips_per_io; 791 792 uint32_t raid_levels; 793 #define MFI_INFO_RAID_0 0x01 794 #define MFI_INFO_RAID_1 0x02 795 #define MFI_INFO_RAID_5 0x04 796 #define MFI_INFO_RAID_1E 0x08 797 #define MFI_INFO_RAID_6 0x10 798 799 uint32_t adapter_ops; 800 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 801 #define MFI_INFO_AOPS_CC_RATE 0x0002 802 #define MFI_INFO_AOPS_BGI_RATE 0x0004 803 #define MFI_INFO_AOPS_RECON_RATE 0x0008 804 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 805 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 806 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 807 #define MFI_INFO_AOPS_BBU 0x0080 808 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 809 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 810 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 811 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 812 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 813 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 814 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 815 816 uint32_t ld_ops; 817 #define MFI_INFO_LDOPS_READ_POLICY 0x01 818 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 819 #define MFI_INFO_LDOPS_IO_POLICY 0x04 820 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 821 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 822 823 struct { 824 uint8_t min; 825 uint8_t max; 826 uint8_t reserved[2]; 827 } QEMU_PACKED stripe_sz_ops; 828 829 uint32_t pd_ops; 830 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 831 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 832 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 833 834 uint32_t pd_mix_support; 835 #define MFI_INFO_PDMIX_SAS 0x01 836 #define MFI_INFO_PDMIX_SATA 0x02 837 #define MFI_INFO_PDMIX_ENCL 0x04 838 #define MFI_INFO_PDMIX_LD 0x08 839 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 840 841 uint8_t ecc_bucket_count; 842 uint8_t reserved2[11]; 843 struct mfi_ctrl_props properties; 844 char package_version[0x60]; 845 uint8_t pad[0x800 - 0x6a0]; 846 } QEMU_PACKED; 847 848 /* keep track of an event. */ 849 union mfi_evt { 850 struct { 851 uint16_t locale; 852 uint8_t reserved; 853 int8_t class; 854 } members; 855 uint32_t word; 856 } QEMU_PACKED; 857 858 /* event log state. */ 859 struct mfi_evt_log_state { 860 uint32_t newest_seq_num; 861 uint32_t oldest_seq_num; 862 uint32_t clear_seq_num; 863 uint32_t shutdown_seq_num; 864 uint32_t boot_seq_num; 865 } QEMU_PACKED; 866 867 struct mfi_progress { 868 uint16_t progress; 869 uint16_t elapsed_seconds; 870 } QEMU_PACKED; 871 872 struct mfi_evt_ld { 873 uint16_t target_id; 874 uint8_t ld_index; 875 uint8_t reserved; 876 } QEMU_PACKED; 877 878 struct mfi_evt_pd { 879 uint16_t device_id; 880 uint8_t enclosure_index; 881 uint8_t slot_number; 882 } QEMU_PACKED; 883 884 /* event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */ 885 struct mfi_evt_detail { 886 uint32_t seq; 887 uint32_t time; 888 uint32_t code; 889 union mfi_evt class; 890 uint8_t arg_type; 891 uint8_t reserved1[15]; 892 893 union { 894 struct { 895 struct mfi_evt_pd pd; 896 uint8_t cdb_len; 897 uint8_t sense_len; 898 uint8_t reserved[2]; 899 uint8_t cdb[16]; 900 uint8_t sense[64]; 901 } cdb_sense; 902 903 struct mfi_evt_ld ld; 904 905 struct { 906 struct mfi_evt_ld ld; 907 uint64_t count; 908 } ld_count; 909 910 struct { 911 uint64_t lba; 912 struct mfi_evt_ld ld; 913 } ld_lba; 914 915 struct { 916 struct mfi_evt_ld ld; 917 uint32_t pre_owner; 918 uint32_t new_owner; 919 } ld_owner; 920 921 struct { 922 uint64_t ld_lba; 923 uint64_t pd_lba; 924 struct mfi_evt_ld ld; 925 struct mfi_evt_pd pd; 926 } ld_lba_pd_lba; 927 928 struct { 929 struct mfi_evt_ld ld; 930 struct mfi_progress prog; 931 } ld_prog; 932 933 struct { 934 struct mfi_evt_ld ld; 935 uint32_t prev_state; 936 uint32_t new_state; 937 } ld_state; 938 939 struct { 940 uint64_t strip; 941 struct mfi_evt_ld ld; 942 } ld_strip; 943 944 struct mfi_evt_pd pd; 945 946 struct { 947 struct mfi_evt_pd pd; 948 uint32_t err; 949 } pd_err; 950 951 struct { 952 uint64_t lba; 953 struct mfi_evt_pd pd; 954 } pd_lba; 955 956 struct { 957 uint64_t lba; 958 struct mfi_evt_pd pd; 959 struct mfi_evt_ld ld; 960 } pd_lba_ld; 961 962 struct { 963 struct mfi_evt_pd pd; 964 struct mfi_progress prog; 965 } pd_prog; 966 967 struct { 968 struct mfi_evt_pd ld; 969 uint32_t prev_state; 970 uint32_t new_state; 971 } pd_state; 972 973 struct { 974 uint16_t venderId; 975 uint16_t deviceId; 976 uint16_t subVenderId; 977 uint16_t subDeviceId; 978 } pci; 979 980 uint32_t rate; 981 982 char str[96]; 983 984 struct { 985 uint32_t rtc; 986 uint16_t elapsedSeconds; 987 } time; 988 989 struct { 990 uint32_t ecar; 991 uint32_t elog; 992 char str[64]; 993 } ecc; 994 995 uint8_t b[96]; 996 uint16_t s[48]; 997 uint32_t w[24]; 998 uint64_t d[12]; 999 } args; 1000 1001 char description[128]; 1002 } QEMU_PACKED; 1003 1004 struct mfi_evt_list { 1005 uint32_t count; 1006 uint32_t reserved; 1007 struct mfi_evt_detail event[1]; 1008 } QEMU_PACKED; 1009 1010 union mfi_pd_ref { 1011 struct { 1012 uint16_t device_id; 1013 uint16_t seq_num; 1014 } v; 1015 uint32_t ref; 1016 } QEMU_PACKED; 1017 1018 union mfi_pd_ddf_type { 1019 struct { 1020 uint16_t pd_type; 1021 #define MFI_PD_DDF_TYPE_FORCED_PD_GUID (1 << 0) 1022 #define MFI_PD_DDF_TYPE_IN_VD (1 << 1) 1023 #define MFI_PD_DDF_TYPE_IS_GLOBAL_SPARE (1 << 2) 1024 #define MFI_PD_DDF_TYPE_IS_SPARE (1 << 3) 1025 #define MFI_PD_DDF_TYPE_IS_FOREIGN (1 << 4) 1026 #define MFI_PD_DDF_TYPE_INTF_SPI (1 << 12) 1027 #define MFI_PD_DDF_TYPE_INTF_SAS (1 << 13) 1028 #define MFI_PD_DDF_TYPE_INTF_SATA1 (1 << 14) 1029 #define MFI_PD_DDF_TYPE_INTF_SATA3G (1 << 15) 1030 uint16_t reserved; 1031 } ddf; 1032 struct { 1033 uint32_t reserved; 1034 } non_disk; 1035 uint32_t type; 1036 } QEMU_PACKED; 1037 1038 struct mfi_pd_progress { 1039 uint32_t active; 1040 #define PD_PROGRESS_ACTIVE_REBUILD (1 << 0) 1041 #define PD_PROGRESS_ACTIVE_PATROL (1 << 1) 1042 #define PD_PROGRESS_ACTIVE_CLEAR (1 << 2) 1043 struct mfi_progress rbld; 1044 struct mfi_progress patrol; 1045 struct mfi_progress clear; 1046 struct mfi_progress reserved[4]; 1047 } QEMU_PACKED; 1048 1049 struct mfi_pd_info { 1050 union mfi_pd_ref ref; 1051 uint8_t inquiry_data[96]; 1052 uint8_t vpd_page83[64]; 1053 uint8_t not_supported; 1054 uint8_t scsi_dev_type; 1055 uint8_t connected_port_bitmap; 1056 uint8_t device_speed; 1057 uint32_t media_err_count; 1058 uint32_t other_err_count; 1059 uint32_t pred_fail_count; 1060 uint32_t last_pred_fail_event_seq_num; 1061 uint16_t fw_state; 1062 uint8_t disable_for_removal; 1063 uint8_t link_speed; 1064 union mfi_pd_ddf_type state; 1065 struct { 1066 uint8_t count; 1067 uint8_t is_path_broken; 1068 uint8_t reserved[6]; 1069 uint64_t sas_addr[4]; 1070 } path_info; 1071 uint64_t raw_size; 1072 uint64_t non_coerced_size; 1073 uint64_t coerced_size; 1074 uint16_t encl_device_id; 1075 uint8_t encl_index; 1076 uint8_t slot_number; 1077 struct mfi_pd_progress prog_info; 1078 uint8_t bad_block_table_full; 1079 uint8_t unusable_in_current_config; 1080 uint8_t vpd_page83_ext[64]; 1081 uint8_t reserved[512-358]; 1082 } QEMU_PACKED; 1083 1084 struct mfi_pd_address { 1085 uint16_t device_id; 1086 uint16_t encl_device_id; 1087 uint8_t encl_index; 1088 uint8_t slot_number; 1089 uint8_t scsi_dev_type; 1090 uint8_t connect_port_bitmap; 1091 uint64_t sas_addr[2]; 1092 } QEMU_PACKED; 1093 1094 #define MFI_MAX_SYS_PDS 240 1095 struct mfi_pd_list { 1096 uint32_t size; 1097 uint32_t count; 1098 struct mfi_pd_address addr[MFI_MAX_SYS_PDS]; 1099 } QEMU_PACKED; 1100 1101 union mfi_ld_ref { 1102 struct { 1103 uint8_t target_id; 1104 uint8_t reserved; 1105 uint16_t seq; 1106 } v; 1107 uint32_t ref; 1108 } QEMU_PACKED; 1109 1110 struct mfi_ld_list { 1111 uint32_t ld_count; 1112 uint32_t reserved1; 1113 struct { 1114 union mfi_ld_ref ld; 1115 uint8_t state; 1116 uint8_t reserved2[3]; 1117 uint64_t size; 1118 } ld_list[MFI_MAX_LD]; 1119 } QEMU_PACKED; 1120 1121 struct mfi_ld_targetid_list { 1122 uint32_t size; 1123 uint32_t ld_count; 1124 uint8_t pad[3]; 1125 uint8_t targetid[MFI_MAX_LD]; 1126 } QEMU_PACKED; 1127 1128 enum mfi_ld_access { 1129 MFI_LD_ACCESS_RW = 0, 1130 MFI_LD_ACCSSS_RO = 2, 1131 MFI_LD_ACCESS_BLOCKED = 3, 1132 }; 1133 #define MFI_LD_ACCESS_MASK 3 1134 1135 enum mfi_ld_state { 1136 MFI_LD_STATE_OFFLINE = 0, 1137 MFI_LD_STATE_PARTIALLY_DEGRADED = 1, 1138 MFI_LD_STATE_DEGRADED = 2, 1139 MFI_LD_STATE_OPTIMAL = 3 1140 }; 1141 1142 enum mfi_syspd_state { 1143 MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1144 MFI_PD_STATE_UNCONFIGURED_BAD = 0x01, 1145 MFI_PD_STATE_HOT_SPARE = 0x02, 1146 MFI_PD_STATE_OFFLINE = 0x10, 1147 MFI_PD_STATE_FAILED = 0x11, 1148 MFI_PD_STATE_REBUILD = 0x14, 1149 MFI_PD_STATE_ONLINE = 0x18, 1150 MFI_PD_STATE_COPYBACK = 0x20, 1151 MFI_PD_STATE_SYSTEM = 0x40 1152 }; 1153 1154 struct mfi_ld_props { 1155 union mfi_ld_ref ld; 1156 char name[16]; 1157 uint8_t default_cache_policy; 1158 uint8_t access_policy; 1159 uint8_t disk_cache_policy; 1160 uint8_t current_cache_policy; 1161 uint8_t no_bgi; 1162 uint8_t reserved[7]; 1163 } QEMU_PACKED; 1164 1165 struct mfi_ld_params { 1166 uint8_t primary_raid_level; 1167 uint8_t raid_level_qualifier; 1168 uint8_t secondary_raid_level; 1169 uint8_t stripe_size; 1170 uint8_t num_drives; 1171 uint8_t span_depth; 1172 uint8_t state; 1173 uint8_t init_state; 1174 uint8_t is_consistent; 1175 uint8_t reserved[23]; 1176 } QEMU_PACKED; 1177 1178 struct mfi_ld_progress { 1179 uint32_t active; 1180 #define MFI_LD_PROGRESS_CC (1<<0) 1181 #define MFI_LD_PROGRESS_BGI (1<<1) 1182 #define MFI_LD_PROGRESS_FGI (1<<2) 1183 #define MFI_LD_PORGRESS_RECON (1<<3) 1184 struct mfi_progress cc; 1185 struct mfi_progress bgi; 1186 struct mfi_progress fgi; 1187 struct mfi_progress recon; 1188 struct mfi_progress reserved[4]; 1189 } QEMU_PACKED; 1190 1191 struct mfi_span { 1192 uint64_t start_block; 1193 uint64_t num_blocks; 1194 uint16_t array_ref; 1195 uint8_t reserved[6]; 1196 } QEMU_PACKED; 1197 1198 #define MFI_MAX_SPAN_DEPTH 8 1199 struct mfi_ld_config { 1200 struct mfi_ld_props properties; 1201 struct mfi_ld_params params; 1202 struct mfi_span span[MFI_MAX_SPAN_DEPTH]; 1203 } QEMU_PACKED; 1204 1205 struct mfi_ld_info { 1206 struct mfi_ld_config ld_config; 1207 uint64_t size; 1208 struct mfi_ld_progress progress; 1209 uint16_t cluster_owner; 1210 uint8_t reconstruct_active; 1211 uint8_t reserved1[1]; 1212 uint8_t vpd_page83[64]; 1213 uint8_t reserved2[16]; 1214 } QEMU_PACKED; 1215 1216 union mfi_spare_type { 1217 uint8_t flags; 1218 #define MFI_SPARE_IS_DEDICATED (1 << 0) 1219 #define MFI_SPARE_IS_REVERTABLE (1 << 1) 1220 #define MFI_SPARE_IS_ENCL_AFFINITY (1 << 2) 1221 uint8_t type; 1222 } QEMU_PACKED; 1223 1224 #define MFI_MAX_ARRAYS 16 1225 struct mfi_spare { 1226 union mfi_pd_ref ref; 1227 union mfi_spare_type spare_type; 1228 uint8_t reserved[2]; 1229 uint8_t array_count; 1230 uint16_t array_refd[MFI_MAX_ARRAYS]; 1231 } QEMU_PACKED; 1232 1233 #define MFI_MAX_ROW_SIZE 32 1234 struct mfi_array { 1235 uint64_t size; 1236 uint8_t num_drives; 1237 uint8_t reserved; 1238 uint16_t array_ref; 1239 uint8_t pad[20]; 1240 struct { 1241 union mfi_pd_ref ref; 1242 uint16_t fw_state; /* enum mfi_syspd_state */ 1243 struct { 1244 uint8_t pd; 1245 uint8_t slot; 1246 } encl; 1247 } pd[MFI_MAX_ROW_SIZE]; 1248 } QEMU_PACKED; 1249 1250 struct mfi_config_data { 1251 uint32_t size; 1252 uint16_t array_count; 1253 uint16_t array_size; 1254 uint16_t log_drv_count; 1255 uint16_t log_drv_size; 1256 uint16_t spares_count; 1257 uint16_t spares_size; 1258 uint8_t reserved[16]; 1259 /* 1260 struct mfi_array array[]; 1261 struct mfi_ld_config ld[]; 1262 struct mfi_spare spare[]; 1263 */ 1264 } QEMU_PACKED; 1265 1266 #define MFI_SCSI_MAX_TARGETS 128 1267 #define MFI_SCSI_MAX_LUNS 8 1268 #define MFI_SCSI_INITIATOR_ID 255 1269 #define MFI_SCSI_MAX_CMDS 8 1270 #define MFI_SCSI_MAX_CDB_LEN 16 1271 1272 #endif /* SCSI_MFI_H */ 1273