1 /* 2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation 3 * Based on the linux driver code at drivers/scsi/megaraid 4 * 5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu-common.h" 23 #include "hw/pci/pci.h" 24 #include "hw/qdev-properties.h" 25 #include "sysemu/dma.h" 26 #include "sysemu/block-backend.h" 27 #include "hw/pci/msi.h" 28 #include "hw/pci/msix.h" 29 #include "qemu/iov.h" 30 #include "qemu/module.h" 31 #include "hw/scsi/scsi.h" 32 #include "scsi/constants.h" 33 #include "trace.h" 34 #include "qapi/error.h" 35 #include "mfi.h" 36 #include "migration/vmstate.h" 37 #include "qom/object.h" 38 39 #define MEGASAS_VERSION_GEN1 "1.70" 40 #define MEGASAS_VERSION_GEN2 "1.80" 41 #define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */ 42 #define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */ 43 #define MEGASAS_GEN2_DEFAULT_FRAMES 1008 /* Windows requires this */ 44 #define MEGASAS_MAX_SGE 128 /* Firmware limit */ 45 #define MEGASAS_DEFAULT_SGE 80 46 #define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */ 47 #define MEGASAS_MAX_ARRAYS 128 48 49 #define MEGASAS_HBA_SERIAL "QEMU123456" 50 #define NAA_LOCALLY_ASSIGNED_ID 0x3ULL 51 #define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400 52 53 #define MEGASAS_FLAG_USE_JBOD 0 54 #define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD) 55 #define MEGASAS_FLAG_USE_QUEUE64 1 56 #define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64) 57 58 typedef struct MegasasCmd { 59 uint32_t index; 60 uint16_t flags; 61 uint16_t count; 62 uint64_t context; 63 64 hwaddr pa; 65 hwaddr pa_size; 66 uint32_t dcmd_opcode; 67 union mfi_frame *frame; 68 SCSIRequest *req; 69 QEMUSGList qsg; 70 void *iov_buf; 71 size_t iov_size; 72 size_t iov_offset; 73 struct MegasasState *state; 74 } MegasasCmd; 75 76 struct MegasasState { 77 /*< private >*/ 78 PCIDevice parent_obj; 79 /*< public >*/ 80 81 MemoryRegion mmio_io; 82 MemoryRegion port_io; 83 MemoryRegion queue_io; 84 uint32_t frame_hi; 85 86 uint32_t fw_state; 87 uint32_t fw_sge; 88 uint32_t fw_cmds; 89 uint32_t flags; 90 uint32_t fw_luns; 91 uint32_t intr_mask; 92 uint32_t doorbell; 93 uint32_t busy; 94 uint32_t diag; 95 uint32_t adp_reset; 96 OnOffAuto msi; 97 OnOffAuto msix; 98 99 MegasasCmd *event_cmd; 100 uint16_t event_locale; 101 int event_class; 102 uint32_t event_count; 103 uint32_t shutdown_event; 104 uint32_t boot_event; 105 106 uint64_t sas_addr; 107 char *hba_serial; 108 109 uint64_t reply_queue_pa; 110 void *reply_queue; 111 uint16_t reply_queue_len; 112 uint32_t reply_queue_head; 113 uint32_t reply_queue_tail; 114 uint64_t consumer_pa; 115 uint64_t producer_pa; 116 117 MegasasCmd frames[MEGASAS_MAX_FRAMES]; 118 DECLARE_BITMAP(frame_map, MEGASAS_MAX_FRAMES); 119 SCSIBus bus; 120 }; 121 typedef struct MegasasState MegasasState; 122 123 struct MegasasBaseClass { 124 PCIDeviceClass parent_class; 125 const char *product_name; 126 const char *product_version; 127 int mmio_bar; 128 int ioport_bar; 129 int osts; 130 }; 131 typedef struct MegasasBaseClass MegasasBaseClass; 132 133 #define TYPE_MEGASAS_BASE "megasas-base" 134 #define TYPE_MEGASAS_GEN1 "megasas" 135 #define TYPE_MEGASAS_GEN2 "megasas-gen2" 136 137 DECLARE_OBJ_CHECKERS(MegasasState, MegasasBaseClass, 138 MEGASAS, TYPE_MEGASAS_BASE) 139 140 141 #define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF 142 143 static bool megasas_intr_enabled(MegasasState *s) 144 { 145 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) != 146 MEGASAS_INTR_DISABLED_MASK) { 147 return true; 148 } 149 return false; 150 } 151 152 static bool megasas_use_queue64(MegasasState *s) 153 { 154 return s->flags & MEGASAS_MASK_USE_QUEUE64; 155 } 156 157 static bool megasas_use_msix(MegasasState *s) 158 { 159 return s->msix != ON_OFF_AUTO_OFF; 160 } 161 162 static bool megasas_is_jbod(MegasasState *s) 163 { 164 return s->flags & MEGASAS_MASK_USE_JBOD; 165 } 166 167 static void megasas_frame_set_cmd_status(MegasasState *s, 168 unsigned long frame, uint8_t v) 169 { 170 PCIDevice *pci = &s->parent_obj; 171 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, cmd_status), 172 v, MEMTXATTRS_UNSPECIFIED); 173 } 174 175 static void megasas_frame_set_scsi_status(MegasasState *s, 176 unsigned long frame, uint8_t v) 177 { 178 PCIDevice *pci = &s->parent_obj; 179 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, scsi_status), 180 v, MEMTXATTRS_UNSPECIFIED); 181 } 182 183 static inline const char *mfi_frame_desc(unsigned int cmd) 184 { 185 static const char *mfi_frame_descs[] = { 186 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI", 187 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop" 188 }; 189 190 if (cmd < ARRAY_SIZE(mfi_frame_descs)) { 191 return mfi_frame_descs[cmd]; 192 } 193 194 return "Unknown"; 195 } 196 197 /* 198 * Context is considered opaque, but the HBA firmware is running 199 * in little endian mode. So convert it to little endian, too. 200 */ 201 static uint64_t megasas_frame_get_context(MegasasState *s, 202 unsigned long frame) 203 { 204 PCIDevice *pci = &s->parent_obj; 205 return ldq_le_pci_dma(pci, frame + offsetof(struct mfi_frame_header, context)); 206 } 207 208 static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd) 209 { 210 return cmd->flags & MFI_FRAME_IEEE_SGL; 211 } 212 213 static bool megasas_frame_is_sgl64(MegasasCmd *cmd) 214 { 215 return cmd->flags & MFI_FRAME_SGL64; 216 } 217 218 static bool megasas_frame_is_sense64(MegasasCmd *cmd) 219 { 220 return cmd->flags & MFI_FRAME_SENSE64; 221 } 222 223 static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd, 224 union mfi_sgl *sgl) 225 { 226 uint64_t addr; 227 228 if (megasas_frame_is_ieee_sgl(cmd)) { 229 addr = le64_to_cpu(sgl->sg_skinny->addr); 230 } else if (megasas_frame_is_sgl64(cmd)) { 231 addr = le64_to_cpu(sgl->sg64->addr); 232 } else { 233 addr = le32_to_cpu(sgl->sg32->addr); 234 } 235 return addr; 236 } 237 238 static uint32_t megasas_sgl_get_len(MegasasCmd *cmd, 239 union mfi_sgl *sgl) 240 { 241 uint32_t len; 242 243 if (megasas_frame_is_ieee_sgl(cmd)) { 244 len = le32_to_cpu(sgl->sg_skinny->len); 245 } else if (megasas_frame_is_sgl64(cmd)) { 246 len = le32_to_cpu(sgl->sg64->len); 247 } else { 248 len = le32_to_cpu(sgl->sg32->len); 249 } 250 return len; 251 } 252 253 static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd, 254 union mfi_sgl *sgl) 255 { 256 uint8_t *next = (uint8_t *)sgl; 257 258 if (megasas_frame_is_ieee_sgl(cmd)) { 259 next += sizeof(struct mfi_sg_skinny); 260 } else if (megasas_frame_is_sgl64(cmd)) { 261 next += sizeof(struct mfi_sg64); 262 } else { 263 next += sizeof(struct mfi_sg32); 264 } 265 266 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) { 267 return NULL; 268 } 269 return (union mfi_sgl *)next; 270 } 271 272 static void megasas_soft_reset(MegasasState *s); 273 274 static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl) 275 { 276 int i; 277 int iov_count = 0; 278 size_t iov_size = 0; 279 280 cmd->flags = le16_to_cpu(cmd->frame->header.flags); 281 iov_count = cmd->frame->header.sge_count; 282 if (!iov_count || iov_count > MEGASAS_MAX_SGE) { 283 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count, 284 MEGASAS_MAX_SGE); 285 return -1; 286 } 287 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count); 288 for (i = 0; i < iov_count; i++) { 289 dma_addr_t iov_pa, iov_size_p; 290 291 if (!sgl) { 292 trace_megasas_iovec_sgl_underflow(cmd->index, i); 293 goto unmap; 294 } 295 iov_pa = megasas_sgl_get_addr(cmd, sgl); 296 iov_size_p = megasas_sgl_get_len(cmd, sgl); 297 if (!iov_pa || !iov_size_p) { 298 trace_megasas_iovec_sgl_invalid(cmd->index, i, 299 iov_pa, iov_size_p); 300 goto unmap; 301 } 302 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p); 303 sgl = megasas_sgl_next(cmd, sgl); 304 iov_size += (size_t)iov_size_p; 305 } 306 if (cmd->iov_size > iov_size) { 307 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size); 308 goto unmap; 309 } else if (cmd->iov_size < iov_size) { 310 trace_megasas_iovec_underflow(cmd->index, iov_size, cmd->iov_size); 311 } 312 cmd->iov_offset = 0; 313 return 0; 314 unmap: 315 qemu_sglist_destroy(&cmd->qsg); 316 return -1; 317 } 318 319 /* 320 * passthrough sense and io sense are at the same offset 321 */ 322 static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr, 323 uint8_t sense_len) 324 { 325 PCIDevice *pcid = PCI_DEVICE(cmd->state); 326 uint32_t pa_hi = 0, pa_lo; 327 hwaddr pa; 328 int frame_sense_len; 329 330 frame_sense_len = cmd->frame->header.sense_len; 331 if (sense_len > frame_sense_len) { 332 sense_len = frame_sense_len; 333 } 334 if (sense_len) { 335 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo); 336 if (megasas_frame_is_sense64(cmd)) { 337 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi); 338 } 339 pa = ((uint64_t) pa_hi << 32) | pa_lo; 340 pci_dma_write(pcid, pa, sense_ptr, sense_len); 341 cmd->frame->header.sense_len = sense_len; 342 } 343 return sense_len; 344 } 345 346 static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense) 347 { 348 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE]; 349 uint8_t sense_len = 18; 350 351 memset(sense_buf, 0, sense_len); 352 sense_buf[0] = 0xf0; 353 sense_buf[2] = sense.key; 354 sense_buf[7] = 10; 355 sense_buf[12] = sense.asc; 356 sense_buf[13] = sense.ascq; 357 megasas_build_sense(cmd, sense_buf, sense_len); 358 } 359 360 static void megasas_copy_sense(MegasasCmd *cmd) 361 { 362 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE]; 363 uint8_t sense_len; 364 365 sense_len = scsi_req_get_sense(cmd->req, sense_buf, 366 SCSI_SENSE_BUF_SIZE); 367 megasas_build_sense(cmd, sense_buf, sense_len); 368 } 369 370 /* 371 * Format an INQUIRY CDB 372 */ 373 static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len) 374 { 375 memset(cdb, 0, 6); 376 cdb[0] = INQUIRY; 377 if (pg > 0) { 378 cdb[1] = 0x1; 379 cdb[2] = pg; 380 } 381 cdb[3] = (len >> 8) & 0xff; 382 cdb[4] = (len & 0xff); 383 return len; 384 } 385 386 /* 387 * Encode lba and len into a READ_16/WRITE_16 CDB 388 */ 389 static void megasas_encode_lba(uint8_t *cdb, uint64_t lba, 390 uint32_t len, bool is_write) 391 { 392 memset(cdb, 0x0, 16); 393 if (is_write) { 394 cdb[0] = WRITE_16; 395 } else { 396 cdb[0] = READ_16; 397 } 398 cdb[2] = (lba >> 56) & 0xff; 399 cdb[3] = (lba >> 48) & 0xff; 400 cdb[4] = (lba >> 40) & 0xff; 401 cdb[5] = (lba >> 32) & 0xff; 402 cdb[6] = (lba >> 24) & 0xff; 403 cdb[7] = (lba >> 16) & 0xff; 404 cdb[8] = (lba >> 8) & 0xff; 405 cdb[9] = (lba) & 0xff; 406 cdb[10] = (len >> 24) & 0xff; 407 cdb[11] = (len >> 16) & 0xff; 408 cdb[12] = (len >> 8) & 0xff; 409 cdb[13] = (len) & 0xff; 410 } 411 412 /* 413 * Utility functions 414 */ 415 static uint64_t megasas_fw_time(void) 416 { 417 struct tm curtime; 418 419 qemu_get_timedate(&curtime, 0); 420 return ((uint64_t)curtime.tm_sec & 0xff) << 48 | 421 ((uint64_t)curtime.tm_min & 0xff) << 40 | 422 ((uint64_t)curtime.tm_hour & 0xff) << 32 | 423 ((uint64_t)curtime.tm_mday & 0xff) << 24 | 424 ((uint64_t)curtime.tm_mon & 0xff) << 16 | 425 ((uint64_t)(curtime.tm_year + 1900) & 0xffff); 426 } 427 428 /* 429 * Default disk sata address 430 * 0x1221 is the magic number as 431 * present in real hardware, 432 * so use it here, too. 433 */ 434 static uint64_t megasas_get_sata_addr(uint16_t id) 435 { 436 uint64_t addr = (0x1221ULL << 48); 437 return addr | ((uint64_t)id << 24); 438 } 439 440 /* 441 * Frame handling 442 */ 443 static int megasas_next_index(MegasasState *s, int index, int limit) 444 { 445 index++; 446 if (index == limit) { 447 index = 0; 448 } 449 return index; 450 } 451 452 static MegasasCmd *megasas_lookup_frame(MegasasState *s, 453 hwaddr frame) 454 { 455 MegasasCmd *cmd = NULL; 456 int num = 0, index; 457 458 index = s->reply_queue_head; 459 460 while (num < s->fw_cmds && index < MEGASAS_MAX_FRAMES) { 461 if (s->frames[index].pa && s->frames[index].pa == frame) { 462 cmd = &s->frames[index]; 463 break; 464 } 465 index = megasas_next_index(s, index, s->fw_cmds); 466 num++; 467 } 468 469 return cmd; 470 } 471 472 static void megasas_unmap_frame(MegasasState *s, MegasasCmd *cmd) 473 { 474 PCIDevice *p = PCI_DEVICE(s); 475 476 if (cmd->pa_size) { 477 pci_dma_unmap(p, cmd->frame, cmd->pa_size, 0, 0); 478 } 479 cmd->frame = NULL; 480 cmd->pa = 0; 481 cmd->pa_size = 0; 482 qemu_sglist_destroy(&cmd->qsg); 483 clear_bit(cmd->index, s->frame_map); 484 } 485 486 /* 487 * This absolutely needs to be locked if 488 * qemu ever goes multithreaded. 489 */ 490 static MegasasCmd *megasas_enqueue_frame(MegasasState *s, 491 hwaddr frame, uint64_t context, int count) 492 { 493 PCIDevice *pcid = PCI_DEVICE(s); 494 MegasasCmd *cmd = NULL; 495 int frame_size = MEGASAS_MAX_SGE * sizeof(union mfi_sgl); 496 hwaddr frame_size_p = frame_size; 497 unsigned long index; 498 499 index = 0; 500 while (index < s->fw_cmds) { 501 index = find_next_zero_bit(s->frame_map, s->fw_cmds, index); 502 if (!s->frames[index].pa) 503 break; 504 /* Busy frame found */ 505 trace_megasas_qf_mapped(index); 506 } 507 if (index >= s->fw_cmds) { 508 /* All frames busy */ 509 trace_megasas_qf_busy(frame); 510 return NULL; 511 } 512 cmd = &s->frames[index]; 513 set_bit(index, s->frame_map); 514 trace_megasas_qf_new(index, frame); 515 516 cmd->pa = frame; 517 /* Map all possible frames */ 518 cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0); 519 if (!cmd->frame || frame_size_p != frame_size) { 520 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame); 521 if (cmd->frame) { 522 megasas_unmap_frame(s, cmd); 523 } 524 s->event_count++; 525 return NULL; 526 } 527 cmd->pa_size = frame_size_p; 528 cmd->context = context; 529 if (!megasas_use_queue64(s)) { 530 cmd->context &= (uint64_t)0xFFFFFFFF; 531 } 532 cmd->count = count; 533 cmd->dcmd_opcode = -1; 534 s->busy++; 535 536 if (s->consumer_pa) { 537 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa); 538 } 539 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context, 540 s->reply_queue_head, s->reply_queue_tail, s->busy); 541 542 return cmd; 543 } 544 545 static void megasas_complete_frame(MegasasState *s, uint64_t context) 546 { 547 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 548 PCIDevice *pci_dev = PCI_DEVICE(s); 549 int tail, queue_offset; 550 551 /* Decrement busy count */ 552 s->busy--; 553 if (s->reply_queue_pa) { 554 /* 555 * Put command on the reply queue. 556 * Context is opaque, but emulation is running in 557 * little endian. So convert it. 558 */ 559 if (megasas_use_queue64(s)) { 560 queue_offset = s->reply_queue_head * sizeof(uint64_t); 561 stq_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, 562 context, attrs); 563 } else { 564 queue_offset = s->reply_queue_head * sizeof(uint32_t); 565 stl_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, 566 context, attrs); 567 } 568 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa); 569 trace_megasas_qf_complete(context, s->reply_queue_head, 570 s->reply_queue_tail, s->busy); 571 } 572 573 if (megasas_intr_enabled(s)) { 574 /* Update reply queue pointer */ 575 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa); 576 tail = s->reply_queue_head; 577 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds); 578 trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail, 579 s->busy); 580 stl_le_pci_dma(pci_dev, s->producer_pa, s->reply_queue_head, attrs); 581 /* Notify HBA */ 582 if (msix_enabled(pci_dev)) { 583 trace_megasas_msix_raise(0); 584 msix_notify(pci_dev, 0); 585 } else if (msi_enabled(pci_dev)) { 586 trace_megasas_msi_raise(0); 587 msi_notify(pci_dev, 0); 588 } else { 589 s->doorbell++; 590 if (s->doorbell == 1) { 591 trace_megasas_irq_raise(); 592 pci_irq_assert(pci_dev); 593 } 594 } 595 } else { 596 trace_megasas_qf_complete_noirq(context); 597 } 598 } 599 600 static void megasas_complete_command(MegasasCmd *cmd) 601 { 602 cmd->iov_size = 0; 603 cmd->iov_offset = 0; 604 605 cmd->req->hba_private = NULL; 606 scsi_req_unref(cmd->req); 607 cmd->req = NULL; 608 609 megasas_unmap_frame(cmd->state, cmd); 610 megasas_complete_frame(cmd->state, cmd->context); 611 } 612 613 static void megasas_reset_frames(MegasasState *s) 614 { 615 int i; 616 MegasasCmd *cmd; 617 618 for (i = 0; i < s->fw_cmds; i++) { 619 cmd = &s->frames[i]; 620 if (cmd->pa) { 621 megasas_unmap_frame(s, cmd); 622 } 623 } 624 bitmap_zero(s->frame_map, MEGASAS_MAX_FRAMES); 625 } 626 627 static void megasas_abort_command(MegasasCmd *cmd) 628 { 629 /* Never abort internal commands. */ 630 if (cmd->dcmd_opcode != -1) { 631 return; 632 } 633 if (cmd->req != NULL) { 634 scsi_req_cancel(cmd->req); 635 } 636 } 637 638 static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd) 639 { 640 PCIDevice *pcid = PCI_DEVICE(s); 641 uint32_t pa_hi, pa_lo; 642 hwaddr iq_pa, initq_size = sizeof(struct mfi_init_qinfo); 643 struct mfi_init_qinfo *initq = NULL; 644 uint32_t flags; 645 int ret = MFI_STAT_OK; 646 647 if (s->reply_queue_pa) { 648 trace_megasas_initq_mapped(s->reply_queue_pa); 649 goto out; 650 } 651 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo); 652 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi); 653 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo); 654 trace_megasas_init_firmware((uint64_t)iq_pa); 655 initq = pci_dma_map(pcid, iq_pa, &initq_size, 0); 656 if (!initq || initq_size != sizeof(*initq)) { 657 trace_megasas_initq_map_failed(cmd->index); 658 s->event_count++; 659 ret = MFI_STAT_MEMORY_NOT_AVAILABLE; 660 goto out; 661 } 662 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF; 663 if (s->reply_queue_len > s->fw_cmds) { 664 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds); 665 s->event_count++; 666 ret = MFI_STAT_INVALID_PARAMETER; 667 goto out; 668 } 669 pa_lo = le32_to_cpu(initq->rq_addr_lo); 670 pa_hi = le32_to_cpu(initq->rq_addr_hi); 671 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo; 672 pa_lo = le32_to_cpu(initq->ci_addr_lo); 673 pa_hi = le32_to_cpu(initq->ci_addr_hi); 674 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo; 675 pa_lo = le32_to_cpu(initq->pi_addr_lo); 676 pa_hi = le32_to_cpu(initq->pi_addr_hi); 677 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo; 678 s->reply_queue_head = ldl_le_pci_dma(pcid, s->producer_pa); 679 s->reply_queue_head %= MEGASAS_MAX_FRAMES; 680 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa); 681 s->reply_queue_tail %= MEGASAS_MAX_FRAMES; 682 flags = le32_to_cpu(initq->flags); 683 if (flags & MFI_QUEUE_FLAG_CONTEXT64) { 684 s->flags |= MEGASAS_MASK_USE_QUEUE64; 685 } 686 trace_megasas_init_queue((unsigned long)s->reply_queue_pa, 687 s->reply_queue_len, s->reply_queue_head, 688 s->reply_queue_tail, flags); 689 megasas_reset_frames(s); 690 s->fw_state = MFI_FWSTATE_OPERATIONAL; 691 out: 692 if (initq) { 693 pci_dma_unmap(pcid, initq, initq_size, 0, 0); 694 } 695 return ret; 696 } 697 698 static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd) 699 { 700 dma_addr_t iov_pa, iov_size; 701 int iov_count; 702 703 cmd->flags = le16_to_cpu(cmd->frame->header.flags); 704 iov_count = cmd->frame->header.sge_count; 705 if (!iov_count) { 706 trace_megasas_dcmd_zero_sge(cmd->index); 707 cmd->iov_size = 0; 708 return 0; 709 } else if (iov_count > 1) { 710 trace_megasas_dcmd_invalid_sge(cmd->index, iov_count); 711 cmd->iov_size = 0; 712 return -EINVAL; 713 } 714 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl); 715 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl); 716 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1); 717 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size); 718 cmd->iov_size = iov_size; 719 return 0; 720 } 721 722 static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size) 723 { 724 trace_megasas_finish_dcmd(cmd->index, iov_size); 725 726 if (iov_size > cmd->iov_size) { 727 if (megasas_frame_is_ieee_sgl(cmd)) { 728 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size); 729 } else if (megasas_frame_is_sgl64(cmd)) { 730 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size); 731 } else { 732 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size); 733 } 734 } 735 } 736 737 static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd) 738 { 739 PCIDevice *pci_dev = PCI_DEVICE(s); 740 PCIDeviceClass *pci_class = PCI_DEVICE_GET_CLASS(pci_dev); 741 MegasasBaseClass *base_class = MEGASAS_GET_CLASS(s); 742 struct mfi_ctrl_info info; 743 size_t dcmd_size = sizeof(info); 744 BusChild *kid; 745 int num_pd_disks = 0; 746 747 memset(&info, 0x0, dcmd_size); 748 if (cmd->iov_size < dcmd_size) { 749 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, 750 dcmd_size); 751 return MFI_STAT_INVALID_PARAMETER; 752 } 753 754 info.pci.vendor = cpu_to_le16(pci_class->vendor_id); 755 info.pci.device = cpu_to_le16(pci_class->device_id); 756 info.pci.subvendor = cpu_to_le16(pci_class->subsystem_vendor_id); 757 info.pci.subdevice = cpu_to_le16(pci_class->subsystem_id); 758 759 /* 760 * For some reason the firmware supports 761 * only up to 8 device ports. 762 * Despite supporting a far larger number 763 * of devices for the physical devices. 764 * So just display the first 8 devices 765 * in the device port list, independent 766 * of how many logical devices are actually 767 * present. 768 */ 769 info.host.type = MFI_INFO_HOST_PCIE; 770 info.device.type = MFI_INFO_DEV_SAS3G; 771 info.device.port_count = 8; 772 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { 773 SCSIDevice *sdev = SCSI_DEVICE(kid->child); 774 uint16_t pd_id; 775 776 if (num_pd_disks < 8) { 777 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF); 778 info.device.port_addr[num_pd_disks] = 779 cpu_to_le64(megasas_get_sata_addr(pd_id)); 780 } 781 num_pd_disks++; 782 } 783 784 memcpy(info.product_name, base_class->product_name, 24); 785 snprintf(info.serial_number, 32, "%s", s->hba_serial); 786 snprintf(info.package_version, 0x60, "%s-QEMU", qemu_hw_version()); 787 memcpy(info.image_component[0].name, "APP", 3); 788 snprintf(info.image_component[0].version, 10, "%s-QEMU", 789 base_class->product_version); 790 memcpy(info.image_component[0].build_date, "Apr 1 2014", 11); 791 memcpy(info.image_component[0].build_time, "12:34:56", 8); 792 info.image_component_count = 1; 793 if (pci_dev->has_rom) { 794 uint8_t biosver[32]; 795 uint8_t *ptr; 796 797 ptr = memory_region_get_ram_ptr(&pci_dev->rom); 798 memcpy(biosver, ptr + 0x41, 31); 799 biosver[31] = 0; 800 memcpy(info.image_component[1].name, "BIOS", 4); 801 memcpy(info.image_component[1].version, biosver, 802 strlen((const char *)biosver)); 803 info.image_component_count++; 804 } 805 info.current_fw_time = cpu_to_le32(megasas_fw_time()); 806 info.max_arms = 32; 807 info.max_spans = 8; 808 info.max_arrays = MEGASAS_MAX_ARRAYS; 809 info.max_lds = MFI_MAX_LD; 810 info.max_cmds = cpu_to_le16(s->fw_cmds); 811 info.max_sg_elements = cpu_to_le16(s->fw_sge); 812 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS); 813 if (!megasas_is_jbod(s)) 814 info.lds_present = cpu_to_le16(num_pd_disks); 815 info.pd_present = cpu_to_le16(num_pd_disks); 816 info.pd_disks_present = cpu_to_le16(num_pd_disks); 817 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM | 818 MFI_INFO_HW_MEM | 819 MFI_INFO_HW_FLASH); 820 info.memory_size = cpu_to_le16(512); 821 info.nvram_size = cpu_to_le16(32); 822 info.flash_size = cpu_to_le16(16); 823 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0); 824 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE | 825 MFI_INFO_AOPS_SELF_DIAGNOSTIC | 826 MFI_INFO_AOPS_MIXED_ARRAY); 827 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY | 828 MFI_INFO_LDOPS_ACCESS_POLICY | 829 MFI_INFO_LDOPS_IO_POLICY | 830 MFI_INFO_LDOPS_WRITE_POLICY | 831 MFI_INFO_LDOPS_READ_POLICY); 832 info.max_strips_per_io = cpu_to_le16(s->fw_sge); 833 info.stripe_sz_ops.min = 3; 834 info.stripe_sz_ops.max = ctz32(MEGASAS_MAX_SECTORS + 1); 835 info.properties.pred_fail_poll_interval = cpu_to_le16(300); 836 info.properties.intr_throttle_cnt = cpu_to_le16(16); 837 info.properties.intr_throttle_timeout = cpu_to_le16(50); 838 info.properties.rebuild_rate = 30; 839 info.properties.patrol_read_rate = 30; 840 info.properties.bgi_rate = 30; 841 info.properties.cc_rate = 30; 842 info.properties.recon_rate = 30; 843 info.properties.cache_flush_interval = 4; 844 info.properties.spinup_drv_cnt = 2; 845 info.properties.spinup_delay = 6; 846 info.properties.ecc_bucket_size = 15; 847 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440); 848 info.properties.expose_encl_devices = 1; 849 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD); 850 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE | 851 MFI_INFO_PDOPS_FORCE_OFFLINE); 852 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS | 853 MFI_INFO_PDMIX_SATA | 854 MFI_INFO_PDMIX_LD); 855 856 cmd->iov_size -= dma_buf_read(&info, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED); 857 return MFI_STAT_OK; 858 } 859 860 static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd) 861 { 862 struct mfi_defaults info; 863 size_t dcmd_size = sizeof(struct mfi_defaults); 864 865 memset(&info, 0x0, dcmd_size); 866 if (cmd->iov_size < dcmd_size) { 867 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, 868 dcmd_size); 869 return MFI_STAT_INVALID_PARAMETER; 870 } 871 872 info.sas_addr = cpu_to_le64(s->sas_addr); 873 info.stripe_size = 3; 874 info.flush_time = 4; 875 info.background_rate = 30; 876 info.allow_mix_in_enclosure = 1; 877 info.allow_mix_in_ld = 1; 878 info.direct_pd_mapping = 1; 879 /* Enable for BIOS support */ 880 info.bios_enumerate_lds = 1; 881 info.disable_ctrl_r = 1; 882 info.expose_enclosure_devices = 1; 883 info.disable_preboot_cli = 1; 884 info.cluster_disable = 1; 885 886 cmd->iov_size -= dma_buf_read(&info, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED); 887 return MFI_STAT_OK; 888 } 889 890 static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd) 891 { 892 struct mfi_bios_data info; 893 size_t dcmd_size = sizeof(info); 894 895 memset(&info, 0x0, dcmd_size); 896 if (cmd->iov_size < dcmd_size) { 897 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, 898 dcmd_size); 899 return MFI_STAT_INVALID_PARAMETER; 900 } 901 info.continue_on_error = 1; 902 info.verbose = 1; 903 if (megasas_is_jbod(s)) { 904 info.expose_all_drives = 1; 905 } 906 907 cmd->iov_size -= dma_buf_read(&info, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED); 908 return MFI_STAT_OK; 909 } 910 911 static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd) 912 { 913 uint64_t fw_time; 914 size_t dcmd_size = sizeof(fw_time); 915 916 fw_time = cpu_to_le64(megasas_fw_time()); 917 918 cmd->iov_size -= dma_buf_read(&fw_time, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED); 919 return MFI_STAT_OK; 920 } 921 922 static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd) 923 { 924 uint64_t fw_time; 925 926 /* This is a dummy; setting of firmware time is not allowed */ 927 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time)); 928 929 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time); 930 fw_time = cpu_to_le64(megasas_fw_time()); 931 return MFI_STAT_OK; 932 } 933 934 static int megasas_event_info(MegasasState *s, MegasasCmd *cmd) 935 { 936 struct mfi_evt_log_state info; 937 size_t dcmd_size = sizeof(info); 938 939 memset(&info, 0, dcmd_size); 940 941 info.newest_seq_num = cpu_to_le32(s->event_count); 942 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event); 943 info.boot_seq_num = cpu_to_le32(s->boot_event); 944 945 cmd->iov_size -= dma_buf_read(&info, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED); 946 return MFI_STAT_OK; 947 } 948 949 static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd) 950 { 951 union mfi_evt event; 952 953 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) { 954 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, 955 sizeof(struct mfi_evt_detail)); 956 return MFI_STAT_INVALID_PARAMETER; 957 } 958 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]); 959 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]); 960 s->event_locale = event.members.locale; 961 s->event_class = event.members.class; 962 s->event_cmd = cmd; 963 /* Decrease busy count; event frame doesn't count here */ 964 s->busy--; 965 cmd->iov_size = sizeof(struct mfi_evt_detail); 966 return MFI_STAT_INVALID_STATUS; 967 } 968 969 static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd) 970 { 971 struct mfi_pd_list info; 972 size_t dcmd_size = sizeof(info); 973 BusChild *kid; 974 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks; 975 976 memset(&info, 0, dcmd_size); 977 offset = 8; 978 dcmd_limit = offset + sizeof(struct mfi_pd_address); 979 if (cmd->iov_size < dcmd_limit) { 980 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, 981 dcmd_limit); 982 return MFI_STAT_INVALID_PARAMETER; 983 } 984 985 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address); 986 if (max_pd_disks > MFI_MAX_SYS_PDS) { 987 max_pd_disks = MFI_MAX_SYS_PDS; 988 } 989 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { 990 SCSIDevice *sdev = SCSI_DEVICE(kid->child); 991 uint16_t pd_id; 992 993 if (num_pd_disks >= max_pd_disks) 994 break; 995 996 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF); 997 info.addr[num_pd_disks].device_id = cpu_to_le16(pd_id); 998 info.addr[num_pd_disks].encl_device_id = 0xFFFF; 999 info.addr[num_pd_disks].encl_index = 0; 1000 info.addr[num_pd_disks].slot_number = sdev->id & 0xFF; 1001 info.addr[num_pd_disks].scsi_dev_type = sdev->type; 1002 info.addr[num_pd_disks].connect_port_bitmap = 0x1; 1003 info.addr[num_pd_disks].sas_addr[0] = 1004 cpu_to_le64(megasas_get_sata_addr(pd_id)); 1005 num_pd_disks++; 1006 offset += sizeof(struct mfi_pd_address); 1007 } 1008 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks, 1009 max_pd_disks, offset); 1010 1011 info.size = cpu_to_le32(offset); 1012 info.count = cpu_to_le32(num_pd_disks); 1013 1014 cmd->iov_size -= dma_buf_read(&info, offset, &cmd->qsg, MEMTXATTRS_UNSPECIFIED); 1015 return MFI_STAT_OK; 1016 } 1017 1018 static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd) 1019 { 1020 uint16_t flags; 1021 1022 /* mbox0 contains flags */ 1023 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]); 1024 trace_megasas_dcmd_pd_list_query(cmd->index, flags); 1025 if (flags == MR_PD_QUERY_TYPE_ALL || 1026 megasas_is_jbod(s)) { 1027 return megasas_dcmd_pd_get_list(s, cmd); 1028 } 1029 1030 return MFI_STAT_OK; 1031 } 1032 1033 static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun, 1034 MegasasCmd *cmd) 1035 { 1036 struct mfi_pd_info *info = cmd->iov_buf; 1037 size_t dcmd_size = sizeof(struct mfi_pd_info); 1038 uint64_t pd_size; 1039 uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF); 1040 uint8_t cmdbuf[6]; 1041 size_t len, resid; 1042 1043 if (!cmd->iov_buf) { 1044 cmd->iov_buf = g_malloc0(dcmd_size); 1045 info = cmd->iov_buf; 1046 info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */ 1047 info->vpd_page83[0] = 0x7f; 1048 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data)); 1049 cmd->req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd); 1050 if (!cmd->req) { 1051 trace_megasas_dcmd_req_alloc_failed(cmd->index, 1052 "PD get info std inquiry"); 1053 g_free(cmd->iov_buf); 1054 cmd->iov_buf = NULL; 1055 return MFI_STAT_FLASH_ALLOC_FAIL; 1056 } 1057 trace_megasas_dcmd_internal_submit(cmd->index, 1058 "PD get info std inquiry", lun); 1059 len = scsi_req_enqueue(cmd->req); 1060 if (len > 0) { 1061 cmd->iov_size = len; 1062 scsi_req_continue(cmd->req); 1063 } 1064 return MFI_STAT_INVALID_STATUS; 1065 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) { 1066 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83)); 1067 cmd->req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd); 1068 if (!cmd->req) { 1069 trace_megasas_dcmd_req_alloc_failed(cmd->index, 1070 "PD get info vpd inquiry"); 1071 return MFI_STAT_FLASH_ALLOC_FAIL; 1072 } 1073 trace_megasas_dcmd_internal_submit(cmd->index, 1074 "PD get info vpd inquiry", lun); 1075 len = scsi_req_enqueue(cmd->req); 1076 if (len > 0) { 1077 cmd->iov_size = len; 1078 scsi_req_continue(cmd->req); 1079 } 1080 return MFI_STAT_INVALID_STATUS; 1081 } 1082 /* Finished, set FW state */ 1083 if ((info->inquiry_data[0] >> 5) == 0) { 1084 if (megasas_is_jbod(cmd->state)) { 1085 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM); 1086 } else { 1087 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE); 1088 } 1089 } else { 1090 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE); 1091 } 1092 1093 info->ref.v.device_id = cpu_to_le16(pd_id); 1094 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD| 1095 MFI_PD_DDF_TYPE_INTF_SAS); 1096 blk_get_geometry(sdev->conf.blk, &pd_size); 1097 info->raw_size = cpu_to_le64(pd_size); 1098 info->non_coerced_size = cpu_to_le64(pd_size); 1099 info->coerced_size = cpu_to_le64(pd_size); 1100 info->encl_device_id = 0xFFFF; 1101 info->slot_number = (sdev->id & 0xFF); 1102 info->path_info.count = 1; 1103 info->path_info.sas_addr[0] = 1104 cpu_to_le64(megasas_get_sata_addr(pd_id)); 1105 info->connected_port_bitmap = 0x1; 1106 info->device_speed = 1; 1107 info->link_speed = 1; 1108 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED); 1109 g_free(cmd->iov_buf); 1110 cmd->iov_size = dcmd_size - resid; 1111 cmd->iov_buf = NULL; 1112 return MFI_STAT_OK; 1113 } 1114 1115 static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd) 1116 { 1117 size_t dcmd_size = sizeof(struct mfi_pd_info); 1118 uint16_t pd_id; 1119 uint8_t target_id, lun_id; 1120 SCSIDevice *sdev = NULL; 1121 int retval = MFI_STAT_DEVICE_NOT_FOUND; 1122 1123 if (cmd->iov_size < dcmd_size) { 1124 return MFI_STAT_INVALID_PARAMETER; 1125 } 1126 1127 /* mbox0 has the ID */ 1128 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]); 1129 target_id = (pd_id >> 8) & 0xFF; 1130 lun_id = pd_id & 0xFF; 1131 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id); 1132 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id); 1133 1134 if (sdev) { 1135 /* Submit inquiry */ 1136 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd); 1137 } 1138 1139 return retval; 1140 } 1141 1142 static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd) 1143 { 1144 struct mfi_ld_list info; 1145 size_t dcmd_size = sizeof(info), resid; 1146 uint32_t num_ld_disks = 0, max_ld_disks; 1147 uint64_t ld_size; 1148 BusChild *kid; 1149 1150 memset(&info, 0, dcmd_size); 1151 if (cmd->iov_size > dcmd_size) { 1152 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, 1153 dcmd_size); 1154 return MFI_STAT_INVALID_PARAMETER; 1155 } 1156 1157 max_ld_disks = (cmd->iov_size - 8) / 16; 1158 if (megasas_is_jbod(s)) { 1159 max_ld_disks = 0; 1160 } 1161 if (max_ld_disks > MFI_MAX_LD) { 1162 max_ld_disks = MFI_MAX_LD; 1163 } 1164 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { 1165 SCSIDevice *sdev = SCSI_DEVICE(kid->child); 1166 1167 if (num_ld_disks >= max_ld_disks) { 1168 break; 1169 } 1170 /* Logical device size is in blocks */ 1171 blk_get_geometry(sdev->conf.blk, &ld_size); 1172 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id; 1173 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL; 1174 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size); 1175 num_ld_disks++; 1176 } 1177 info.ld_count = cpu_to_le32(num_ld_disks); 1178 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks); 1179 1180 resid = dma_buf_read(&info, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED); 1181 cmd->iov_size = dcmd_size - resid; 1182 return MFI_STAT_OK; 1183 } 1184 1185 static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd) 1186 { 1187 uint16_t flags; 1188 struct mfi_ld_targetid_list info; 1189 size_t dcmd_size = sizeof(info), resid; 1190 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns; 1191 BusChild *kid; 1192 1193 /* mbox0 contains flags */ 1194 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]); 1195 trace_megasas_dcmd_ld_list_query(cmd->index, flags); 1196 if (flags != MR_LD_QUERY_TYPE_ALL && 1197 flags != MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) { 1198 max_ld_disks = 0; 1199 } 1200 1201 memset(&info, 0, dcmd_size); 1202 if (cmd->iov_size < 12) { 1203 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, 1204 dcmd_size); 1205 return MFI_STAT_INVALID_PARAMETER; 1206 } 1207 dcmd_size = sizeof(uint32_t) * 2 + 3; 1208 max_ld_disks = cmd->iov_size - dcmd_size; 1209 if (megasas_is_jbod(s)) { 1210 max_ld_disks = 0; 1211 } 1212 if (max_ld_disks > MFI_MAX_LD) { 1213 max_ld_disks = MFI_MAX_LD; 1214 } 1215 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { 1216 SCSIDevice *sdev = SCSI_DEVICE(kid->child); 1217 1218 if (num_ld_disks >= max_ld_disks) { 1219 break; 1220 } 1221 info.targetid[num_ld_disks] = sdev->lun; 1222 num_ld_disks++; 1223 dcmd_size++; 1224 } 1225 info.ld_count = cpu_to_le32(num_ld_disks); 1226 info.size = dcmd_size; 1227 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks); 1228 1229 resid = dma_buf_read(&info, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED); 1230 cmd->iov_size = dcmd_size - resid; 1231 return MFI_STAT_OK; 1232 } 1233 1234 static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun, 1235 MegasasCmd *cmd) 1236 { 1237 struct mfi_ld_info *info = cmd->iov_buf; 1238 size_t dcmd_size = sizeof(struct mfi_ld_info); 1239 uint8_t cdb[6]; 1240 ssize_t len, resid; 1241 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF); 1242 uint64_t ld_size; 1243 1244 if (!cmd->iov_buf) { 1245 cmd->iov_buf = g_malloc0(dcmd_size); 1246 info = cmd->iov_buf; 1247 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83)); 1248 cmd->req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd); 1249 if (!cmd->req) { 1250 trace_megasas_dcmd_req_alloc_failed(cmd->index, 1251 "LD get info vpd inquiry"); 1252 g_free(cmd->iov_buf); 1253 cmd->iov_buf = NULL; 1254 return MFI_STAT_FLASH_ALLOC_FAIL; 1255 } 1256 trace_megasas_dcmd_internal_submit(cmd->index, 1257 "LD get info vpd inquiry", lun); 1258 len = scsi_req_enqueue(cmd->req); 1259 if (len > 0) { 1260 cmd->iov_size = len; 1261 scsi_req_continue(cmd->req); 1262 } 1263 return MFI_STAT_INVALID_STATUS; 1264 } 1265 1266 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL; 1267 info->ld_config.properties.ld.v.target_id = lun; 1268 info->ld_config.params.stripe_size = 3; 1269 info->ld_config.params.num_drives = 1; 1270 info->ld_config.params.is_consistent = 1; 1271 /* Logical device size is in blocks */ 1272 blk_get_geometry(sdev->conf.blk, &ld_size); 1273 info->size = cpu_to_le64(ld_size); 1274 memset(info->ld_config.span, 0, sizeof(info->ld_config.span)); 1275 info->ld_config.span[0].start_block = 0; 1276 info->ld_config.span[0].num_blocks = info->size; 1277 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id); 1278 1279 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED); 1280 g_free(cmd->iov_buf); 1281 cmd->iov_size = dcmd_size - resid; 1282 cmd->iov_buf = NULL; 1283 return MFI_STAT_OK; 1284 } 1285 1286 static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd) 1287 { 1288 struct mfi_ld_info info; 1289 size_t dcmd_size = sizeof(info); 1290 uint16_t ld_id; 1291 uint32_t max_ld_disks = s->fw_luns; 1292 SCSIDevice *sdev = NULL; 1293 int retval = MFI_STAT_DEVICE_NOT_FOUND; 1294 1295 if (cmd->iov_size < dcmd_size) { 1296 return MFI_STAT_INVALID_PARAMETER; 1297 } 1298 1299 /* mbox0 has the ID */ 1300 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]); 1301 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id); 1302 1303 if (megasas_is_jbod(s)) { 1304 return MFI_STAT_DEVICE_NOT_FOUND; 1305 } 1306 1307 if (ld_id < max_ld_disks) { 1308 sdev = scsi_device_find(&s->bus, 0, ld_id, 0); 1309 } 1310 1311 if (sdev) { 1312 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd); 1313 } 1314 1315 return retval; 1316 } 1317 1318 static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd) 1319 { 1320 uint8_t data[4096] = { 0 }; 1321 struct mfi_config_data *info; 1322 int num_pd_disks = 0, array_offset, ld_offset; 1323 BusChild *kid; 1324 1325 if (cmd->iov_size > 4096) { 1326 return MFI_STAT_INVALID_PARAMETER; 1327 } 1328 1329 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { 1330 num_pd_disks++; 1331 } 1332 info = (struct mfi_config_data *)&data; 1333 /* 1334 * Array mapping: 1335 * - One array per SCSI device 1336 * - One logical drive per SCSI device 1337 * spanning the entire device 1338 */ 1339 info->array_count = num_pd_disks; 1340 info->array_size = sizeof(struct mfi_array) * num_pd_disks; 1341 info->log_drv_count = num_pd_disks; 1342 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks; 1343 info->spares_count = 0; 1344 info->spares_size = sizeof(struct mfi_spare); 1345 info->size = sizeof(struct mfi_config_data) + info->array_size + 1346 info->log_drv_size; 1347 if (info->size > 4096) { 1348 return MFI_STAT_INVALID_PARAMETER; 1349 } 1350 1351 array_offset = sizeof(struct mfi_config_data); 1352 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks; 1353 1354 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { 1355 SCSIDevice *sdev = SCSI_DEVICE(kid->child); 1356 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF); 1357 struct mfi_array *array; 1358 struct mfi_ld_config *ld; 1359 uint64_t pd_size; 1360 int i; 1361 1362 array = (struct mfi_array *)(data + array_offset); 1363 blk_get_geometry(sdev->conf.blk, &pd_size); 1364 array->size = cpu_to_le64(pd_size); 1365 array->num_drives = 1; 1366 array->array_ref = cpu_to_le16(sdev_id); 1367 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id); 1368 array->pd[0].ref.v.seq_num = 0; 1369 array->pd[0].fw_state = MFI_PD_STATE_ONLINE; 1370 array->pd[0].encl.pd = 0xFF; 1371 array->pd[0].encl.slot = (sdev->id & 0xFF); 1372 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) { 1373 array->pd[i].ref.v.device_id = 0xFFFF; 1374 array->pd[i].ref.v.seq_num = 0; 1375 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD; 1376 array->pd[i].encl.pd = 0xFF; 1377 array->pd[i].encl.slot = 0xFF; 1378 } 1379 array_offset += sizeof(struct mfi_array); 1380 ld = (struct mfi_ld_config *)(data + ld_offset); 1381 memset(ld, 0, sizeof(struct mfi_ld_config)); 1382 ld->properties.ld.v.target_id = sdev->id; 1383 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD | 1384 MR_LD_CACHE_READ_ADAPTIVE; 1385 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD | 1386 MR_LD_CACHE_READ_ADAPTIVE; 1387 ld->params.state = MFI_LD_STATE_OPTIMAL; 1388 ld->params.stripe_size = 3; 1389 ld->params.num_drives = 1; 1390 ld->params.span_depth = 1; 1391 ld->params.is_consistent = 1; 1392 ld->span[0].start_block = 0; 1393 ld->span[0].num_blocks = cpu_to_le64(pd_size); 1394 ld->span[0].array_ref = cpu_to_le16(sdev_id); 1395 ld_offset += sizeof(struct mfi_ld_config); 1396 } 1397 1398 cmd->iov_size -= dma_buf_read(data, info->size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED); 1399 return MFI_STAT_OK; 1400 } 1401 1402 static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd) 1403 { 1404 struct mfi_ctrl_props info; 1405 size_t dcmd_size = sizeof(info); 1406 1407 memset(&info, 0x0, dcmd_size); 1408 if (cmd->iov_size < dcmd_size) { 1409 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, 1410 dcmd_size); 1411 return MFI_STAT_INVALID_PARAMETER; 1412 } 1413 info.pred_fail_poll_interval = cpu_to_le16(300); 1414 info.intr_throttle_cnt = cpu_to_le16(16); 1415 info.intr_throttle_timeout = cpu_to_le16(50); 1416 info.rebuild_rate = 30; 1417 info.patrol_read_rate = 30; 1418 info.bgi_rate = 30; 1419 info.cc_rate = 30; 1420 info.recon_rate = 30; 1421 info.cache_flush_interval = 4; 1422 info.spinup_drv_cnt = 2; 1423 info.spinup_delay = 6; 1424 info.ecc_bucket_size = 15; 1425 info.ecc_bucket_leak_rate = cpu_to_le16(1440); 1426 info.expose_encl_devices = 1; 1427 1428 cmd->iov_size -= dma_buf_read(&info, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED); 1429 return MFI_STAT_OK; 1430 } 1431 1432 static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd) 1433 { 1434 blk_drain_all(); 1435 return MFI_STAT_OK; 1436 } 1437 1438 static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd) 1439 { 1440 s->fw_state = MFI_FWSTATE_READY; 1441 return MFI_STAT_OK; 1442 } 1443 1444 /* Some implementations use CLUSTER RESET LD to simulate a device reset */ 1445 static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd) 1446 { 1447 uint16_t target_id; 1448 int i; 1449 1450 /* mbox0 contains the device index */ 1451 target_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]); 1452 trace_megasas_dcmd_reset_ld(cmd->index, target_id); 1453 for (i = 0; i < s->fw_cmds; i++) { 1454 MegasasCmd *tmp_cmd = &s->frames[i]; 1455 if (tmp_cmd->req && tmp_cmd->req->dev->id == target_id) { 1456 SCSIDevice *d = tmp_cmd->req->dev; 1457 qdev_reset_all(&d->qdev); 1458 } 1459 } 1460 return MFI_STAT_OK; 1461 } 1462 1463 static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd) 1464 { 1465 struct mfi_ctrl_props info; 1466 size_t dcmd_size = sizeof(info); 1467 1468 if (cmd->iov_size < dcmd_size) { 1469 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, 1470 dcmd_size); 1471 return MFI_STAT_INVALID_PARAMETER; 1472 } 1473 dma_buf_write(&info, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED); 1474 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size); 1475 return MFI_STAT_OK; 1476 } 1477 1478 static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd) 1479 { 1480 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size); 1481 return MFI_STAT_OK; 1482 } 1483 1484 static const struct dcmd_cmd_tbl_t { 1485 int opcode; 1486 const char *desc; 1487 int (*func)(MegasasState *s, MegasasCmd *cmd); 1488 } dcmd_cmd_tbl[] = { 1489 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC", 1490 megasas_dcmd_dummy }, 1491 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO", 1492 megasas_ctrl_get_info }, 1493 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES", 1494 megasas_dcmd_get_properties }, 1495 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES", 1496 megasas_dcmd_set_properties }, 1497 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET", 1498 megasas_dcmd_dummy }, 1499 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE", 1500 megasas_dcmd_dummy }, 1501 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE", 1502 megasas_dcmd_dummy }, 1503 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE", 1504 megasas_dcmd_dummy }, 1505 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST", 1506 megasas_dcmd_dummy }, 1507 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO", 1508 megasas_event_info }, 1509 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET", 1510 megasas_dcmd_dummy }, 1511 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT", 1512 megasas_event_wait }, 1513 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN", 1514 megasas_ctrl_shutdown }, 1515 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY", 1516 megasas_dcmd_dummy }, 1517 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME", 1518 megasas_dcmd_get_fw_time }, 1519 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME", 1520 megasas_dcmd_set_fw_time }, 1521 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET", 1522 megasas_dcmd_get_bios_info }, 1523 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS", 1524 megasas_dcmd_dummy }, 1525 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET", 1526 megasas_mfc_get_defaults }, 1527 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET", 1528 megasas_dcmd_dummy }, 1529 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH", 1530 megasas_cache_flush }, 1531 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST", 1532 megasas_dcmd_pd_get_list }, 1533 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY", 1534 megasas_dcmd_pd_list_query }, 1535 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO", 1536 megasas_dcmd_pd_get_info }, 1537 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET", 1538 megasas_dcmd_dummy }, 1539 { MFI_DCMD_PD_REBUILD, "PD_REBUILD", 1540 megasas_dcmd_dummy }, 1541 { MFI_DCMD_PD_BLINK, "PD_BLINK", 1542 megasas_dcmd_dummy }, 1543 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK", 1544 megasas_dcmd_dummy }, 1545 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST", 1546 megasas_dcmd_ld_get_list}, 1547 { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY", 1548 megasas_dcmd_ld_list_query }, 1549 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO", 1550 megasas_dcmd_ld_get_info }, 1551 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP", 1552 megasas_dcmd_dummy }, 1553 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP", 1554 megasas_dcmd_dummy }, 1555 { MFI_DCMD_LD_DELETE, "LD_DELETE", 1556 megasas_dcmd_dummy }, 1557 { MFI_DCMD_CFG_READ, "CFG_READ", 1558 megasas_dcmd_cfg_read }, 1559 { MFI_DCMD_CFG_ADD, "CFG_ADD", 1560 megasas_dcmd_dummy }, 1561 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR", 1562 megasas_dcmd_dummy }, 1563 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ", 1564 megasas_dcmd_dummy }, 1565 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT", 1566 megasas_dcmd_dummy }, 1567 { MFI_DCMD_BBU_STATUS, "BBU_STATUS", 1568 megasas_dcmd_dummy }, 1569 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO", 1570 megasas_dcmd_dummy }, 1571 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO", 1572 megasas_dcmd_dummy }, 1573 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET", 1574 megasas_dcmd_dummy }, 1575 { MFI_DCMD_CLUSTER, "CLUSTER", 1576 megasas_dcmd_dummy }, 1577 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL", 1578 megasas_dcmd_dummy }, 1579 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD", 1580 megasas_cluster_reset_ld }, 1581 { -1, NULL, NULL } 1582 }; 1583 1584 static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd) 1585 { 1586 int retval = 0; 1587 size_t len; 1588 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl; 1589 1590 cmd->dcmd_opcode = le32_to_cpu(cmd->frame->dcmd.opcode); 1591 trace_megasas_handle_dcmd(cmd->index, cmd->dcmd_opcode); 1592 if (megasas_map_dcmd(s, cmd) < 0) { 1593 return MFI_STAT_MEMORY_NOT_AVAILABLE; 1594 } 1595 while (cmdptr->opcode != -1 && cmdptr->opcode != cmd->dcmd_opcode) { 1596 cmdptr++; 1597 } 1598 len = cmd->iov_size; 1599 if (cmdptr->opcode == -1) { 1600 trace_megasas_dcmd_unhandled(cmd->index, cmd->dcmd_opcode, len); 1601 retval = megasas_dcmd_dummy(s, cmd); 1602 } else { 1603 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len); 1604 retval = cmdptr->func(s, cmd); 1605 } 1606 if (retval != MFI_STAT_INVALID_STATUS) { 1607 megasas_finish_dcmd(cmd, len); 1608 } 1609 return retval; 1610 } 1611 1612 static int megasas_finish_internal_dcmd(MegasasCmd *cmd, 1613 SCSIRequest *req, size_t resid) 1614 { 1615 int retval = MFI_STAT_OK; 1616 int lun = req->lun; 1617 1618 trace_megasas_dcmd_internal_finish(cmd->index, cmd->dcmd_opcode, lun); 1619 cmd->iov_size -= resid; 1620 switch (cmd->dcmd_opcode) { 1621 case MFI_DCMD_PD_GET_INFO: 1622 retval = megasas_pd_get_info_submit(req->dev, lun, cmd); 1623 break; 1624 case MFI_DCMD_LD_GET_INFO: 1625 retval = megasas_ld_get_info_submit(req->dev, lun, cmd); 1626 break; 1627 default: 1628 trace_megasas_dcmd_internal_invalid(cmd->index, cmd->dcmd_opcode); 1629 retval = MFI_STAT_INVALID_DCMD; 1630 break; 1631 } 1632 if (retval != MFI_STAT_INVALID_STATUS) { 1633 megasas_finish_dcmd(cmd, cmd->iov_size); 1634 } 1635 return retval; 1636 } 1637 1638 static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write) 1639 { 1640 int len; 1641 1642 len = scsi_req_enqueue(cmd->req); 1643 if (len < 0) { 1644 len = -len; 1645 } 1646 if (len > 0) { 1647 if (len > cmd->iov_size) { 1648 if (is_write) { 1649 trace_megasas_iov_write_overflow(cmd->index, len, 1650 cmd->iov_size); 1651 } else { 1652 trace_megasas_iov_read_overflow(cmd->index, len, 1653 cmd->iov_size); 1654 } 1655 } 1656 if (len < cmd->iov_size) { 1657 if (is_write) { 1658 trace_megasas_iov_write_underflow(cmd->index, len, 1659 cmd->iov_size); 1660 } else { 1661 trace_megasas_iov_read_underflow(cmd->index, len, 1662 cmd->iov_size); 1663 } 1664 cmd->iov_size = len; 1665 } 1666 scsi_req_continue(cmd->req); 1667 } 1668 return len; 1669 } 1670 1671 static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd, 1672 int frame_cmd) 1673 { 1674 uint8_t *cdb; 1675 int target_id, lun_id, cdb_len; 1676 bool is_write; 1677 struct SCSIDevice *sdev = NULL; 1678 bool is_logical = (frame_cmd == MFI_CMD_LD_SCSI_IO); 1679 1680 cdb = cmd->frame->pass.cdb; 1681 target_id = cmd->frame->header.target_id; 1682 lun_id = cmd->frame->header.lun_id; 1683 cdb_len = cmd->frame->header.cdb_len; 1684 1685 if (is_logical) { 1686 if (target_id >= MFI_MAX_LD || lun_id != 0) { 1687 trace_megasas_scsi_target_not_present( 1688 mfi_frame_desc(frame_cmd), is_logical, target_id, lun_id); 1689 return MFI_STAT_DEVICE_NOT_FOUND; 1690 } 1691 } 1692 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id); 1693 1694 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len); 1695 trace_megasas_handle_scsi(mfi_frame_desc(frame_cmd), is_logical, 1696 target_id, lun_id, sdev, cmd->iov_size); 1697 1698 if (!sdev || (megasas_is_jbod(s) && is_logical)) { 1699 trace_megasas_scsi_target_not_present( 1700 mfi_frame_desc(frame_cmd), is_logical, target_id, lun_id); 1701 return MFI_STAT_DEVICE_NOT_FOUND; 1702 } 1703 1704 if (cdb_len > 16) { 1705 trace_megasas_scsi_invalid_cdb_len( 1706 mfi_frame_desc(frame_cmd), is_logical, 1707 target_id, lun_id, cdb_len); 1708 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE)); 1709 cmd->frame->header.scsi_status = CHECK_CONDITION; 1710 s->event_count++; 1711 return MFI_STAT_SCSI_DONE_WITH_ERROR; 1712 } 1713 1714 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) { 1715 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE)); 1716 cmd->frame->header.scsi_status = CHECK_CONDITION; 1717 s->event_count++; 1718 return MFI_STAT_SCSI_DONE_WITH_ERROR; 1719 } 1720 1721 cmd->req = scsi_req_new(sdev, cmd->index, lun_id, cdb, cmd); 1722 if (!cmd->req) { 1723 trace_megasas_scsi_req_alloc_failed( 1724 mfi_frame_desc(frame_cmd), target_id, lun_id); 1725 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE)); 1726 cmd->frame->header.scsi_status = BUSY; 1727 s->event_count++; 1728 return MFI_STAT_SCSI_DONE_WITH_ERROR; 1729 } 1730 1731 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV); 1732 if (cmd->iov_size) { 1733 if (is_write) { 1734 trace_megasas_scsi_write_start(cmd->index, cmd->iov_size); 1735 } else { 1736 trace_megasas_scsi_read_start(cmd->index, cmd->iov_size); 1737 } 1738 } else { 1739 trace_megasas_scsi_nodata(cmd->index); 1740 } 1741 megasas_enqueue_req(cmd, is_write); 1742 return MFI_STAT_INVALID_STATUS; 1743 } 1744 1745 static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd, int frame_cmd) 1746 { 1747 uint32_t lba_count, lba_start_hi, lba_start_lo; 1748 uint64_t lba_start; 1749 bool is_write = (frame_cmd == MFI_CMD_LD_WRITE); 1750 uint8_t cdb[16]; 1751 int len; 1752 struct SCSIDevice *sdev = NULL; 1753 int target_id, lun_id, cdb_len; 1754 1755 lba_count = le32_to_cpu(cmd->frame->io.header.data_len); 1756 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo); 1757 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi); 1758 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo; 1759 1760 target_id = cmd->frame->header.target_id; 1761 lun_id = cmd->frame->header.lun_id; 1762 cdb_len = cmd->frame->header.cdb_len; 1763 1764 if (target_id < MFI_MAX_LD && lun_id == 0) { 1765 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id); 1766 } 1767 1768 trace_megasas_handle_io(cmd->index, 1769 mfi_frame_desc(frame_cmd), target_id, lun_id, 1770 (unsigned long)lba_start, (unsigned long)lba_count); 1771 if (!sdev) { 1772 trace_megasas_io_target_not_present(cmd->index, 1773 mfi_frame_desc(frame_cmd), target_id, lun_id); 1774 return MFI_STAT_DEVICE_NOT_FOUND; 1775 } 1776 1777 if (cdb_len > 16) { 1778 trace_megasas_scsi_invalid_cdb_len( 1779 mfi_frame_desc(frame_cmd), 1, target_id, lun_id, cdb_len); 1780 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE)); 1781 cmd->frame->header.scsi_status = CHECK_CONDITION; 1782 s->event_count++; 1783 return MFI_STAT_SCSI_DONE_WITH_ERROR; 1784 } 1785 1786 cmd->iov_size = lba_count * sdev->blocksize; 1787 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) { 1788 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE)); 1789 cmd->frame->header.scsi_status = CHECK_CONDITION; 1790 s->event_count++; 1791 return MFI_STAT_SCSI_DONE_WITH_ERROR; 1792 } 1793 1794 megasas_encode_lba(cdb, lba_start, lba_count, is_write); 1795 cmd->req = scsi_req_new(sdev, cmd->index, 1796 lun_id, cdb, cmd); 1797 if (!cmd->req) { 1798 trace_megasas_scsi_req_alloc_failed( 1799 mfi_frame_desc(frame_cmd), target_id, lun_id); 1800 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE)); 1801 cmd->frame->header.scsi_status = BUSY; 1802 s->event_count++; 1803 return MFI_STAT_SCSI_DONE_WITH_ERROR; 1804 } 1805 len = megasas_enqueue_req(cmd, is_write); 1806 if (len > 0) { 1807 if (is_write) { 1808 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len); 1809 } else { 1810 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len); 1811 } 1812 } 1813 return MFI_STAT_INVALID_STATUS; 1814 } 1815 1816 static QEMUSGList *megasas_get_sg_list(SCSIRequest *req) 1817 { 1818 MegasasCmd *cmd = req->hba_private; 1819 1820 if (cmd->dcmd_opcode != -1) { 1821 return NULL; 1822 } else { 1823 return &cmd->qsg; 1824 } 1825 } 1826 1827 static void megasas_xfer_complete(SCSIRequest *req, uint32_t len) 1828 { 1829 MegasasCmd *cmd = req->hba_private; 1830 uint8_t *buf; 1831 1832 trace_megasas_io_complete(cmd->index, len); 1833 1834 if (cmd->dcmd_opcode != -1) { 1835 scsi_req_continue(req); 1836 return; 1837 } 1838 1839 buf = scsi_req_get_buf(req); 1840 if (cmd->dcmd_opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) { 1841 struct mfi_pd_info *info = cmd->iov_buf; 1842 1843 if (info->inquiry_data[0] == 0x7f) { 1844 memset(info->inquiry_data, 0, sizeof(info->inquiry_data)); 1845 memcpy(info->inquiry_data, buf, len); 1846 } else if (info->vpd_page83[0] == 0x7f) { 1847 memset(info->vpd_page83, 0, sizeof(info->vpd_page83)); 1848 memcpy(info->vpd_page83, buf, len); 1849 } 1850 scsi_req_continue(req); 1851 } else if (cmd->dcmd_opcode == MFI_DCMD_LD_GET_INFO) { 1852 struct mfi_ld_info *info = cmd->iov_buf; 1853 1854 if (cmd->iov_buf) { 1855 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83)); 1856 scsi_req_continue(req); 1857 } 1858 } 1859 } 1860 1861 static void megasas_command_complete(SCSIRequest *req, size_t resid) 1862 { 1863 MegasasCmd *cmd = req->hba_private; 1864 uint8_t cmd_status = MFI_STAT_OK; 1865 1866 trace_megasas_command_complete(cmd->index, req->status, resid); 1867 1868 if (req->io_canceled) { 1869 return; 1870 } 1871 1872 if (cmd->dcmd_opcode != -1) { 1873 /* 1874 * Internal command complete 1875 */ 1876 cmd_status = megasas_finish_internal_dcmd(cmd, req, resid); 1877 if (cmd_status == MFI_STAT_INVALID_STATUS) { 1878 return; 1879 } 1880 } else { 1881 trace_megasas_scsi_complete(cmd->index, req->status, 1882 cmd->iov_size, req->cmd.xfer); 1883 if (req->status != GOOD) { 1884 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR; 1885 } 1886 if (req->status == CHECK_CONDITION) { 1887 megasas_copy_sense(cmd); 1888 } 1889 1890 cmd->frame->header.scsi_status = req->status; 1891 } 1892 cmd->frame->header.cmd_status = cmd_status; 1893 megasas_complete_command(cmd); 1894 } 1895 1896 static void megasas_command_cancelled(SCSIRequest *req) 1897 { 1898 MegasasCmd *cmd = req->hba_private; 1899 1900 if (!cmd) { 1901 return; 1902 } 1903 cmd->frame->header.cmd_status = MFI_STAT_SCSI_IO_FAILED; 1904 megasas_complete_command(cmd); 1905 } 1906 1907 static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd) 1908 { 1909 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context); 1910 hwaddr abort_addr, addr_hi, addr_lo; 1911 MegasasCmd *abort_cmd; 1912 1913 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi); 1914 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo); 1915 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo; 1916 1917 abort_cmd = megasas_lookup_frame(s, abort_addr); 1918 if (!abort_cmd) { 1919 trace_megasas_abort_no_cmd(cmd->index, abort_ctx); 1920 s->event_count++; 1921 return MFI_STAT_OK; 1922 } 1923 if (!megasas_use_queue64(s)) { 1924 abort_ctx &= (uint64_t)0xFFFFFFFF; 1925 } 1926 if (abort_cmd->context != abort_ctx) { 1927 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->context, 1928 abort_cmd->index); 1929 s->event_count++; 1930 return MFI_STAT_ABORT_NOT_POSSIBLE; 1931 } 1932 trace_megasas_abort_frame(cmd->index, abort_cmd->index); 1933 megasas_abort_command(abort_cmd); 1934 if (!s->event_cmd || abort_cmd != s->event_cmd) { 1935 s->event_cmd = NULL; 1936 } 1937 s->event_count++; 1938 return MFI_STAT_OK; 1939 } 1940 1941 static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr, 1942 uint32_t frame_count) 1943 { 1944 uint8_t frame_status = MFI_STAT_INVALID_CMD; 1945 uint64_t frame_context; 1946 int frame_cmd; 1947 MegasasCmd *cmd; 1948 1949 /* 1950 * Always read 64bit context, top bits will be 1951 * masked out if required in megasas_enqueue_frame() 1952 */ 1953 frame_context = megasas_frame_get_context(s, frame_addr); 1954 1955 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count); 1956 if (!cmd) { 1957 /* reply queue full */ 1958 trace_megasas_frame_busy(frame_addr); 1959 megasas_frame_set_scsi_status(s, frame_addr, BUSY); 1960 megasas_frame_set_cmd_status(s, frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR); 1961 megasas_complete_frame(s, frame_context); 1962 s->event_count++; 1963 return; 1964 } 1965 frame_cmd = cmd->frame->header.frame_cmd; 1966 switch (frame_cmd) { 1967 case MFI_CMD_INIT: 1968 frame_status = megasas_init_firmware(s, cmd); 1969 break; 1970 case MFI_CMD_DCMD: 1971 frame_status = megasas_handle_dcmd(s, cmd); 1972 break; 1973 case MFI_CMD_ABORT: 1974 frame_status = megasas_handle_abort(s, cmd); 1975 break; 1976 case MFI_CMD_PD_SCSI_IO: 1977 case MFI_CMD_LD_SCSI_IO: 1978 frame_status = megasas_handle_scsi(s, cmd, frame_cmd); 1979 break; 1980 case MFI_CMD_LD_READ: 1981 case MFI_CMD_LD_WRITE: 1982 frame_status = megasas_handle_io(s, cmd, frame_cmd); 1983 break; 1984 default: 1985 trace_megasas_unhandled_frame_cmd(cmd->index, frame_cmd); 1986 s->event_count++; 1987 break; 1988 } 1989 if (frame_status != MFI_STAT_INVALID_STATUS) { 1990 if (cmd->frame) { 1991 cmd->frame->header.cmd_status = frame_status; 1992 } else { 1993 megasas_frame_set_cmd_status(s, frame_addr, frame_status); 1994 } 1995 megasas_unmap_frame(s, cmd); 1996 megasas_complete_frame(s, cmd->context); 1997 } 1998 } 1999 2000 static uint64_t megasas_mmio_read(void *opaque, hwaddr addr, 2001 unsigned size) 2002 { 2003 MegasasState *s = opaque; 2004 PCIDevice *pci_dev = PCI_DEVICE(s); 2005 MegasasBaseClass *base_class = MEGASAS_GET_CLASS(s); 2006 uint32_t retval = 0; 2007 2008 switch (addr) { 2009 case MFI_IDB: 2010 retval = 0; 2011 trace_megasas_mmio_readl("MFI_IDB", retval); 2012 break; 2013 case MFI_OMSG0: 2014 case MFI_OSP0: 2015 retval = (msix_present(pci_dev) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) | 2016 (s->fw_state & MFI_FWSTATE_MASK) | 2017 ((s->fw_sge & 0xff) << 16) | 2018 (s->fw_cmds & 0xFFFF); 2019 trace_megasas_mmio_readl(addr == MFI_OMSG0 ? "MFI_OMSG0" : "MFI_OSP0", 2020 retval); 2021 break; 2022 case MFI_OSTS: 2023 if (megasas_intr_enabled(s) && s->doorbell) { 2024 retval = base_class->osts; 2025 } 2026 trace_megasas_mmio_readl("MFI_OSTS", retval); 2027 break; 2028 case MFI_OMSK: 2029 retval = s->intr_mask; 2030 trace_megasas_mmio_readl("MFI_OMSK", retval); 2031 break; 2032 case MFI_ODCR0: 2033 retval = s->doorbell ? 1 : 0; 2034 trace_megasas_mmio_readl("MFI_ODCR0", retval); 2035 break; 2036 case MFI_DIAG: 2037 retval = s->diag; 2038 trace_megasas_mmio_readl("MFI_DIAG", retval); 2039 break; 2040 case MFI_OSP1: 2041 retval = 15; 2042 trace_megasas_mmio_readl("MFI_OSP1", retval); 2043 break; 2044 default: 2045 trace_megasas_mmio_invalid_readl(addr); 2046 break; 2047 } 2048 return retval; 2049 } 2050 2051 static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d}; 2052 2053 static void megasas_mmio_write(void *opaque, hwaddr addr, 2054 uint64_t val, unsigned size) 2055 { 2056 MegasasState *s = opaque; 2057 PCIDevice *pci_dev = PCI_DEVICE(s); 2058 uint64_t frame_addr; 2059 uint32_t frame_count; 2060 int i; 2061 2062 switch (addr) { 2063 case MFI_IDB: 2064 trace_megasas_mmio_writel("MFI_IDB", val); 2065 if (val & MFI_FWINIT_ABORT) { 2066 /* Abort all pending cmds */ 2067 for (i = 0; i < s->fw_cmds; i++) { 2068 megasas_abort_command(&s->frames[i]); 2069 } 2070 } 2071 if (val & MFI_FWINIT_READY) { 2072 /* move to FW READY */ 2073 megasas_soft_reset(s); 2074 } 2075 if (val & MFI_FWINIT_MFIMODE) { 2076 /* discard MFIs */ 2077 } 2078 if (val & MFI_FWINIT_STOP_ADP) { 2079 /* Terminal error, stop processing */ 2080 s->fw_state = MFI_FWSTATE_FAULT; 2081 } 2082 break; 2083 case MFI_OMSK: 2084 trace_megasas_mmio_writel("MFI_OMSK", val); 2085 s->intr_mask = val; 2086 if (!megasas_intr_enabled(s) && 2087 !msi_enabled(pci_dev) && 2088 !msix_enabled(pci_dev)) { 2089 trace_megasas_irq_lower(); 2090 pci_irq_deassert(pci_dev); 2091 } 2092 if (megasas_intr_enabled(s)) { 2093 if (msix_enabled(pci_dev)) { 2094 trace_megasas_msix_enabled(0); 2095 } else if (msi_enabled(pci_dev)) { 2096 trace_megasas_msi_enabled(0); 2097 } else { 2098 trace_megasas_intr_enabled(); 2099 } 2100 } else { 2101 trace_megasas_intr_disabled(); 2102 megasas_soft_reset(s); 2103 } 2104 break; 2105 case MFI_ODCR0: 2106 trace_megasas_mmio_writel("MFI_ODCR0", val); 2107 s->doorbell = 0; 2108 if (megasas_intr_enabled(s)) { 2109 if (!msix_enabled(pci_dev) && !msi_enabled(pci_dev)) { 2110 trace_megasas_irq_lower(); 2111 pci_irq_deassert(pci_dev); 2112 } 2113 } 2114 break; 2115 case MFI_IQPH: 2116 trace_megasas_mmio_writel("MFI_IQPH", val); 2117 /* Received high 32 bits of a 64 bit MFI frame address */ 2118 s->frame_hi = val; 2119 break; 2120 case MFI_IQPL: 2121 trace_megasas_mmio_writel("MFI_IQPL", val); 2122 /* Received low 32 bits of a 64 bit MFI frame address */ 2123 /* Fallthrough */ 2124 case MFI_IQP: 2125 if (addr == MFI_IQP) { 2126 trace_megasas_mmio_writel("MFI_IQP", val); 2127 /* Received 64 bit MFI frame address */ 2128 s->frame_hi = 0; 2129 } 2130 frame_addr = (val & ~0x1F); 2131 /* Add possible 64 bit offset */ 2132 frame_addr |= ((uint64_t)s->frame_hi << 32); 2133 s->frame_hi = 0; 2134 frame_count = (val >> 1) & 0xF; 2135 megasas_handle_frame(s, frame_addr, frame_count); 2136 break; 2137 case MFI_SEQ: 2138 trace_megasas_mmio_writel("MFI_SEQ", val); 2139 /* Magic sequence to start ADP reset */ 2140 if (adp_reset_seq[s->adp_reset++] == val) { 2141 if (s->adp_reset == 6) { 2142 s->adp_reset = 0; 2143 s->diag = MFI_DIAG_WRITE_ENABLE; 2144 } 2145 } else { 2146 s->adp_reset = 0; 2147 s->diag = 0; 2148 } 2149 break; 2150 case MFI_DIAG: 2151 trace_megasas_mmio_writel("MFI_DIAG", val); 2152 /* ADP reset */ 2153 if ((s->diag & MFI_DIAG_WRITE_ENABLE) && 2154 (val & MFI_DIAG_RESET_ADP)) { 2155 s->diag |= MFI_DIAG_RESET_ADP; 2156 megasas_soft_reset(s); 2157 s->adp_reset = 0; 2158 s->diag = 0; 2159 } 2160 break; 2161 default: 2162 trace_megasas_mmio_invalid_writel(addr, val); 2163 break; 2164 } 2165 } 2166 2167 static const MemoryRegionOps megasas_mmio_ops = { 2168 .read = megasas_mmio_read, 2169 .write = megasas_mmio_write, 2170 .endianness = DEVICE_LITTLE_ENDIAN, 2171 .impl = { 2172 .min_access_size = 8, 2173 .max_access_size = 8, 2174 } 2175 }; 2176 2177 static uint64_t megasas_port_read(void *opaque, hwaddr addr, 2178 unsigned size) 2179 { 2180 return megasas_mmio_read(opaque, addr & 0xff, size); 2181 } 2182 2183 static void megasas_port_write(void *opaque, hwaddr addr, 2184 uint64_t val, unsigned size) 2185 { 2186 megasas_mmio_write(opaque, addr & 0xff, val, size); 2187 } 2188 2189 static const MemoryRegionOps megasas_port_ops = { 2190 .read = megasas_port_read, 2191 .write = megasas_port_write, 2192 .endianness = DEVICE_LITTLE_ENDIAN, 2193 .impl = { 2194 .min_access_size = 4, 2195 .max_access_size = 4, 2196 } 2197 }; 2198 2199 static uint64_t megasas_queue_read(void *opaque, hwaddr addr, 2200 unsigned size) 2201 { 2202 return 0; 2203 } 2204 2205 static void megasas_queue_write(void *opaque, hwaddr addr, 2206 uint64_t val, unsigned size) 2207 { 2208 return; 2209 } 2210 2211 static const MemoryRegionOps megasas_queue_ops = { 2212 .read = megasas_queue_read, 2213 .write = megasas_queue_write, 2214 .endianness = DEVICE_LITTLE_ENDIAN, 2215 .impl = { 2216 .min_access_size = 8, 2217 .max_access_size = 8, 2218 } 2219 }; 2220 2221 static void megasas_soft_reset(MegasasState *s) 2222 { 2223 int i; 2224 MegasasCmd *cmd; 2225 2226 trace_megasas_reset(s->fw_state); 2227 for (i = 0; i < s->fw_cmds; i++) { 2228 cmd = &s->frames[i]; 2229 megasas_abort_command(cmd); 2230 } 2231 if (s->fw_state == MFI_FWSTATE_READY) { 2232 BusChild *kid; 2233 2234 /* 2235 * The EFI firmware doesn't handle UA, 2236 * so we need to clear the Power On/Reset UA 2237 * after the initial reset. 2238 */ 2239 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { 2240 SCSIDevice *sdev = SCSI_DEVICE(kid->child); 2241 2242 sdev->unit_attention = SENSE_CODE(NO_SENSE); 2243 scsi_device_unit_attention_reported(sdev); 2244 } 2245 } 2246 megasas_reset_frames(s); 2247 s->reply_queue_len = s->fw_cmds; 2248 s->reply_queue_pa = 0; 2249 s->consumer_pa = 0; 2250 s->producer_pa = 0; 2251 s->fw_state = MFI_FWSTATE_READY; 2252 s->doorbell = 0; 2253 s->intr_mask = MEGASAS_INTR_DISABLED_MASK; 2254 s->frame_hi = 0; 2255 s->flags &= ~MEGASAS_MASK_USE_QUEUE64; 2256 s->event_count++; 2257 s->boot_event = s->event_count; 2258 } 2259 2260 static void megasas_scsi_reset(DeviceState *dev) 2261 { 2262 MegasasState *s = MEGASAS(dev); 2263 2264 megasas_soft_reset(s); 2265 } 2266 2267 static const VMStateDescription vmstate_megasas_gen1 = { 2268 .name = "megasas", 2269 .version_id = 0, 2270 .minimum_version_id = 0, 2271 .fields = (VMStateField[]) { 2272 VMSTATE_PCI_DEVICE(parent_obj, MegasasState), 2273 VMSTATE_MSIX(parent_obj, MegasasState), 2274 2275 VMSTATE_UINT32(fw_state, MegasasState), 2276 VMSTATE_UINT32(intr_mask, MegasasState), 2277 VMSTATE_UINT32(doorbell, MegasasState), 2278 VMSTATE_UINT64(reply_queue_pa, MegasasState), 2279 VMSTATE_UINT64(consumer_pa, MegasasState), 2280 VMSTATE_UINT64(producer_pa, MegasasState), 2281 VMSTATE_END_OF_LIST() 2282 } 2283 }; 2284 2285 static const VMStateDescription vmstate_megasas_gen2 = { 2286 .name = "megasas-gen2", 2287 .version_id = 0, 2288 .minimum_version_id = 0, 2289 .minimum_version_id_old = 0, 2290 .fields = (VMStateField[]) { 2291 VMSTATE_PCI_DEVICE(parent_obj, MegasasState), 2292 VMSTATE_MSIX(parent_obj, MegasasState), 2293 2294 VMSTATE_UINT32(fw_state, MegasasState), 2295 VMSTATE_UINT32(intr_mask, MegasasState), 2296 VMSTATE_UINT32(doorbell, MegasasState), 2297 VMSTATE_UINT64(reply_queue_pa, MegasasState), 2298 VMSTATE_UINT64(consumer_pa, MegasasState), 2299 VMSTATE_UINT64(producer_pa, MegasasState), 2300 VMSTATE_END_OF_LIST() 2301 } 2302 }; 2303 2304 static void megasas_scsi_uninit(PCIDevice *d) 2305 { 2306 MegasasState *s = MEGASAS(d); 2307 2308 if (megasas_use_msix(s)) { 2309 msix_uninit(d, &s->mmio_io, &s->mmio_io); 2310 } 2311 msi_uninit(d); 2312 } 2313 2314 static const struct SCSIBusInfo megasas_scsi_info = { 2315 .tcq = true, 2316 .max_target = MFI_MAX_LD, 2317 .max_lun = 255, 2318 2319 .transfer_data = megasas_xfer_complete, 2320 .get_sg_list = megasas_get_sg_list, 2321 .complete = megasas_command_complete, 2322 .cancel = megasas_command_cancelled, 2323 }; 2324 2325 static void megasas_scsi_realize(PCIDevice *dev, Error **errp) 2326 { 2327 MegasasState *s = MEGASAS(dev); 2328 MegasasBaseClass *b = MEGASAS_GET_CLASS(s); 2329 uint8_t *pci_conf; 2330 int i, bar_type; 2331 Error *err = NULL; 2332 int ret; 2333 2334 pci_conf = dev->config; 2335 2336 /* PCI latency timer = 0 */ 2337 pci_conf[PCI_LATENCY_TIMER] = 0; 2338 /* Interrupt pin 1 */ 2339 pci_conf[PCI_INTERRUPT_PIN] = 0x01; 2340 2341 if (s->msi != ON_OFF_AUTO_OFF) { 2342 ret = msi_init(dev, 0x50, 1, true, false, &err); 2343 /* Any error other than -ENOTSUP(board's MSI support is broken) 2344 * is a programming error */ 2345 assert(!ret || ret == -ENOTSUP); 2346 if (ret && s->msi == ON_OFF_AUTO_ON) { 2347 /* Can't satisfy user's explicit msi=on request, fail */ 2348 error_append_hint(&err, "You have to use msi=auto (default) or " 2349 "msi=off with this machine type.\n"); 2350 error_propagate(errp, err); 2351 return; 2352 } else if (ret) { 2353 /* With msi=auto, we fall back to MSI off silently */ 2354 s->msi = ON_OFF_AUTO_OFF; 2355 error_free(err); 2356 } 2357 } 2358 2359 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s, 2360 "megasas-mmio", 0x4000); 2361 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s, 2362 "megasas-io", 256); 2363 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s, 2364 "megasas-queue", 0x40000); 2365 2366 if (megasas_use_msix(s) && 2367 msix_init(dev, 15, &s->mmio_io, b->mmio_bar, 0x2000, 2368 &s->mmio_io, b->mmio_bar, 0x3800, 0x68, NULL)) { 2369 /* TODO: check msix_init's error, and should fail on msix=on */ 2370 s->msix = ON_OFF_AUTO_OFF; 2371 } 2372 2373 if (pci_is_express(dev)) { 2374 pcie_endpoint_cap_init(dev, 0xa0); 2375 } 2376 2377 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64; 2378 pci_register_bar(dev, b->ioport_bar, 2379 PCI_BASE_ADDRESS_SPACE_IO, &s->port_io); 2380 pci_register_bar(dev, b->mmio_bar, bar_type, &s->mmio_io); 2381 pci_register_bar(dev, 3, bar_type, &s->queue_io); 2382 2383 if (megasas_use_msix(s)) { 2384 msix_vector_use(dev, 0); 2385 } 2386 2387 s->fw_state = MFI_FWSTATE_READY; 2388 if (!s->sas_addr) { 2389 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) | 2390 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36; 2391 s->sas_addr |= pci_dev_bus_num(dev) << 16; 2392 s->sas_addr |= PCI_SLOT(dev->devfn) << 8; 2393 s->sas_addr |= PCI_FUNC(dev->devfn); 2394 } 2395 if (!s->hba_serial) { 2396 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL); 2397 } 2398 if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) { 2399 s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE; 2400 } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) { 2401 s->fw_sge = 128 - MFI_PASS_FRAME_SIZE; 2402 } else { 2403 s->fw_sge = 64 - MFI_PASS_FRAME_SIZE; 2404 } 2405 if (s->fw_cmds > MEGASAS_MAX_FRAMES) { 2406 s->fw_cmds = MEGASAS_MAX_FRAMES; 2407 } 2408 trace_megasas_init(s->fw_sge, s->fw_cmds, 2409 megasas_is_jbod(s) ? "jbod" : "raid"); 2410 2411 if (megasas_is_jbod(s)) { 2412 s->fw_luns = MFI_MAX_SYS_PDS; 2413 } else { 2414 s->fw_luns = MFI_MAX_LD; 2415 } 2416 s->producer_pa = 0; 2417 s->consumer_pa = 0; 2418 for (i = 0; i < s->fw_cmds; i++) { 2419 s->frames[i].index = i; 2420 s->frames[i].context = -1; 2421 s->frames[i].pa = 0; 2422 s->frames[i].state = s; 2423 } 2424 2425 scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &megasas_scsi_info); 2426 } 2427 2428 static Property megasas_properties_gen1[] = { 2429 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge, 2430 MEGASAS_DEFAULT_SGE), 2431 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds, 2432 MEGASAS_DEFAULT_FRAMES), 2433 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial), 2434 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0), 2435 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO), 2436 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO), 2437 DEFINE_PROP_BIT("use_jbod", MegasasState, flags, 2438 MEGASAS_FLAG_USE_JBOD, false), 2439 DEFINE_PROP_END_OF_LIST(), 2440 }; 2441 2442 static Property megasas_properties_gen2[] = { 2443 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge, 2444 MEGASAS_DEFAULT_SGE), 2445 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds, 2446 MEGASAS_GEN2_DEFAULT_FRAMES), 2447 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial), 2448 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0), 2449 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO), 2450 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO), 2451 DEFINE_PROP_BIT("use_jbod", MegasasState, flags, 2452 MEGASAS_FLAG_USE_JBOD, false), 2453 DEFINE_PROP_END_OF_LIST(), 2454 }; 2455 2456 typedef struct MegasasInfo { 2457 const char *name; 2458 const char *desc; 2459 const char *product_name; 2460 const char *product_version; 2461 uint16_t device_id; 2462 uint16_t subsystem_id; 2463 int ioport_bar; 2464 int mmio_bar; 2465 int osts; 2466 const VMStateDescription *vmsd; 2467 Property *props; 2468 InterfaceInfo *interfaces; 2469 } MegasasInfo; 2470 2471 static struct MegasasInfo megasas_devices[] = { 2472 { 2473 .name = TYPE_MEGASAS_GEN1, 2474 .desc = "LSI MegaRAID SAS 1078", 2475 .product_name = "LSI MegaRAID SAS 8708EM2", 2476 .product_version = MEGASAS_VERSION_GEN1, 2477 .device_id = PCI_DEVICE_ID_LSI_SAS1078, 2478 .subsystem_id = 0x1013, 2479 .ioport_bar = 2, 2480 .mmio_bar = 0, 2481 .osts = MFI_1078_RM | 1, 2482 .vmsd = &vmstate_megasas_gen1, 2483 .props = megasas_properties_gen1, 2484 .interfaces = (InterfaceInfo[]) { 2485 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 2486 { }, 2487 }, 2488 },{ 2489 .name = TYPE_MEGASAS_GEN2, 2490 .desc = "LSI MegaRAID SAS 2108", 2491 .product_name = "LSI MegaRAID SAS 9260-8i", 2492 .product_version = MEGASAS_VERSION_GEN2, 2493 .device_id = PCI_DEVICE_ID_LSI_SAS0079, 2494 .subsystem_id = 0x9261, 2495 .ioport_bar = 0, 2496 .mmio_bar = 1, 2497 .osts = MFI_GEN2_RM, 2498 .vmsd = &vmstate_megasas_gen2, 2499 .props = megasas_properties_gen2, 2500 .interfaces = (InterfaceInfo[]) { 2501 { INTERFACE_PCIE_DEVICE }, 2502 { } 2503 }, 2504 } 2505 }; 2506 2507 static void megasas_class_init(ObjectClass *oc, void *data) 2508 { 2509 DeviceClass *dc = DEVICE_CLASS(oc); 2510 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc); 2511 MegasasBaseClass *e = MEGASAS_CLASS(oc); 2512 const MegasasInfo *info = data; 2513 2514 pc->realize = megasas_scsi_realize; 2515 pc->exit = megasas_scsi_uninit; 2516 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC; 2517 pc->device_id = info->device_id; 2518 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC; 2519 pc->subsystem_id = info->subsystem_id; 2520 pc->class_id = PCI_CLASS_STORAGE_RAID; 2521 e->mmio_bar = info->mmio_bar; 2522 e->ioport_bar = info->ioport_bar; 2523 e->osts = info->osts; 2524 e->product_name = info->product_name; 2525 e->product_version = info->product_version; 2526 device_class_set_props(dc, info->props); 2527 dc->reset = megasas_scsi_reset; 2528 dc->vmsd = info->vmsd; 2529 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2530 dc->desc = info->desc; 2531 } 2532 2533 static const TypeInfo megasas_info = { 2534 .name = TYPE_MEGASAS_BASE, 2535 .parent = TYPE_PCI_DEVICE, 2536 .instance_size = sizeof(MegasasState), 2537 .class_size = sizeof(MegasasBaseClass), 2538 .abstract = true, 2539 }; 2540 2541 static void megasas_register_types(void) 2542 { 2543 int i; 2544 2545 type_register_static(&megasas_info); 2546 for (i = 0; i < ARRAY_SIZE(megasas_devices); i++) { 2547 const MegasasInfo *info = &megasas_devices[i]; 2548 TypeInfo type_info = {}; 2549 2550 type_info.name = info->name; 2551 type_info.parent = TYPE_MEGASAS_BASE; 2552 type_info.class_data = (void *)info; 2553 type_info.class_init = megasas_class_init; 2554 type_info.interfaces = info->interfaces; 2555 2556 type_register(&type_info); 2557 } 2558 } 2559 2560 type_init(megasas_register_types) 2561