1 /* 2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation 3 * Based on the linux driver code at drivers/scsi/megaraid 4 * 5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "hw/hw.h" 22 #include "hw/pci/pci.h" 23 #include "sysemu/dma.h" 24 #include "hw/pci/msix.h" 25 #include "qemu/iov.h" 26 #include "hw/scsi/scsi.h" 27 #include "block/scsi.h" 28 #include "trace.h" 29 30 #include "mfi.h" 31 32 #define MEGASAS_VERSION "1.70" 33 #define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */ 34 #define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */ 35 #define MEGASAS_MAX_SGE 128 /* Firmware limit */ 36 #define MEGASAS_DEFAULT_SGE 80 37 #define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */ 38 #define MEGASAS_MAX_ARRAYS 128 39 40 #define MEGASAS_HBA_SERIAL "QEMU123456" 41 #define NAA_LOCALLY_ASSIGNED_ID 0x3ULL 42 #define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400 43 44 #define MEGASAS_FLAG_USE_JBOD 0 45 #define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD) 46 #define MEGASAS_FLAG_USE_MSIX 1 47 #define MEGASAS_MASK_USE_MSIX (1 << MEGASAS_FLAG_USE_MSIX) 48 #define MEGASAS_FLAG_USE_QUEUE64 2 49 #define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64) 50 51 static const char *mfi_frame_desc[] = { 52 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI", 53 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"}; 54 55 typedef struct MegasasCmd { 56 uint32_t index; 57 uint16_t flags; 58 uint16_t count; 59 uint64_t context; 60 61 hwaddr pa; 62 hwaddr pa_size; 63 union mfi_frame *frame; 64 SCSIRequest *req; 65 QEMUSGList qsg; 66 void *iov_buf; 67 size_t iov_size; 68 size_t iov_offset; 69 struct MegasasState *state; 70 } MegasasCmd; 71 72 typedef struct MegasasState { 73 /*< private >*/ 74 PCIDevice parent_obj; 75 /*< public >*/ 76 77 MemoryRegion mmio_io; 78 MemoryRegion port_io; 79 MemoryRegion queue_io; 80 uint32_t frame_hi; 81 82 int fw_state; 83 uint32_t fw_sge; 84 uint32_t fw_cmds; 85 uint32_t flags; 86 int fw_luns; 87 int intr_mask; 88 int doorbell; 89 int busy; 90 91 MegasasCmd *event_cmd; 92 int event_locale; 93 int event_class; 94 int event_count; 95 int shutdown_event; 96 int boot_event; 97 98 uint64_t sas_addr; 99 char *hba_serial; 100 101 uint64_t reply_queue_pa; 102 void *reply_queue; 103 int reply_queue_len; 104 int reply_queue_head; 105 int reply_queue_tail; 106 uint64_t consumer_pa; 107 uint64_t producer_pa; 108 109 MegasasCmd frames[MEGASAS_MAX_FRAMES]; 110 111 SCSIBus bus; 112 } MegasasState; 113 114 #define TYPE_MEGASAS "megasas" 115 116 #define MEGASAS(obj) \ 117 OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS) 118 119 #define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF 120 121 static bool megasas_intr_enabled(MegasasState *s) 122 { 123 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) != 124 MEGASAS_INTR_DISABLED_MASK) { 125 return true; 126 } 127 return false; 128 } 129 130 static bool megasas_use_queue64(MegasasState *s) 131 { 132 return s->flags & MEGASAS_MASK_USE_QUEUE64; 133 } 134 135 static bool megasas_use_msix(MegasasState *s) 136 { 137 return s->flags & MEGASAS_MASK_USE_MSIX; 138 } 139 140 static bool megasas_is_jbod(MegasasState *s) 141 { 142 return s->flags & MEGASAS_MASK_USE_JBOD; 143 } 144 145 static void megasas_frame_set_cmd_status(unsigned long frame, uint8_t v) 146 { 147 stb_phys(&address_space_memory, 148 frame + offsetof(struct mfi_frame_header, cmd_status), v); 149 } 150 151 static void megasas_frame_set_scsi_status(unsigned long frame, uint8_t v) 152 { 153 stb_phys(&address_space_memory, 154 frame + offsetof(struct mfi_frame_header, scsi_status), v); 155 } 156 157 /* 158 * Context is considered opaque, but the HBA firmware is running 159 * in little endian mode. So convert it to little endian, too. 160 */ 161 static uint64_t megasas_frame_get_context(unsigned long frame) 162 { 163 return ldq_le_phys(&address_space_memory, 164 frame + offsetof(struct mfi_frame_header, context)); 165 } 166 167 static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd) 168 { 169 return cmd->flags & MFI_FRAME_IEEE_SGL; 170 } 171 172 static bool megasas_frame_is_sgl64(MegasasCmd *cmd) 173 { 174 return cmd->flags & MFI_FRAME_SGL64; 175 } 176 177 static bool megasas_frame_is_sense64(MegasasCmd *cmd) 178 { 179 return cmd->flags & MFI_FRAME_SENSE64; 180 } 181 182 static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd, 183 union mfi_sgl *sgl) 184 { 185 uint64_t addr; 186 187 if (megasas_frame_is_ieee_sgl(cmd)) { 188 addr = le64_to_cpu(sgl->sg_skinny->addr); 189 } else if (megasas_frame_is_sgl64(cmd)) { 190 addr = le64_to_cpu(sgl->sg64->addr); 191 } else { 192 addr = le32_to_cpu(sgl->sg32->addr); 193 } 194 return addr; 195 } 196 197 static uint32_t megasas_sgl_get_len(MegasasCmd *cmd, 198 union mfi_sgl *sgl) 199 { 200 uint32_t len; 201 202 if (megasas_frame_is_ieee_sgl(cmd)) { 203 len = le32_to_cpu(sgl->sg_skinny->len); 204 } else if (megasas_frame_is_sgl64(cmd)) { 205 len = le32_to_cpu(sgl->sg64->len); 206 } else { 207 len = le32_to_cpu(sgl->sg32->len); 208 } 209 return len; 210 } 211 212 static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd, 213 union mfi_sgl *sgl) 214 { 215 uint8_t *next = (uint8_t *)sgl; 216 217 if (megasas_frame_is_ieee_sgl(cmd)) { 218 next += sizeof(struct mfi_sg_skinny); 219 } else if (megasas_frame_is_sgl64(cmd)) { 220 next += sizeof(struct mfi_sg64); 221 } else { 222 next += sizeof(struct mfi_sg32); 223 } 224 225 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) { 226 return NULL; 227 } 228 return (union mfi_sgl *)next; 229 } 230 231 static void megasas_soft_reset(MegasasState *s); 232 233 static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl) 234 { 235 int i; 236 int iov_count = 0; 237 size_t iov_size = 0; 238 239 cmd->flags = le16_to_cpu(cmd->frame->header.flags); 240 iov_count = cmd->frame->header.sge_count; 241 if (iov_count > MEGASAS_MAX_SGE) { 242 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count, 243 MEGASAS_MAX_SGE); 244 return iov_count; 245 } 246 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count); 247 for (i = 0; i < iov_count; i++) { 248 dma_addr_t iov_pa, iov_size_p; 249 250 if (!sgl) { 251 trace_megasas_iovec_sgl_underflow(cmd->index, i); 252 goto unmap; 253 } 254 iov_pa = megasas_sgl_get_addr(cmd, sgl); 255 iov_size_p = megasas_sgl_get_len(cmd, sgl); 256 if (!iov_pa || !iov_size_p) { 257 trace_megasas_iovec_sgl_invalid(cmd->index, i, 258 iov_pa, iov_size_p); 259 goto unmap; 260 } 261 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p); 262 sgl = megasas_sgl_next(cmd, sgl); 263 iov_size += (size_t)iov_size_p; 264 } 265 if (cmd->iov_size > iov_size) { 266 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size); 267 } else if (cmd->iov_size < iov_size) { 268 trace_megasas_iovec_underflow(cmd->iov_size, iov_size, cmd->iov_size); 269 } 270 cmd->iov_offset = 0; 271 return 0; 272 unmap: 273 qemu_sglist_destroy(&cmd->qsg); 274 return iov_count - i; 275 } 276 277 static void megasas_unmap_sgl(MegasasCmd *cmd) 278 { 279 qemu_sglist_destroy(&cmd->qsg); 280 cmd->iov_offset = 0; 281 } 282 283 /* 284 * passthrough sense and io sense are at the same offset 285 */ 286 static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr, 287 uint8_t sense_len) 288 { 289 uint32_t pa_hi = 0, pa_lo; 290 hwaddr pa; 291 292 if (sense_len > cmd->frame->header.sense_len) { 293 sense_len = cmd->frame->header.sense_len; 294 } 295 if (sense_len) { 296 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo); 297 if (megasas_frame_is_sense64(cmd)) { 298 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi); 299 } 300 pa = ((uint64_t) pa_hi << 32) | pa_lo; 301 cpu_physical_memory_write(pa, sense_ptr, sense_len); 302 cmd->frame->header.sense_len = sense_len; 303 } 304 return sense_len; 305 } 306 307 static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense) 308 { 309 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE]; 310 uint8_t sense_len = 18; 311 312 memset(sense_buf, 0, sense_len); 313 sense_buf[0] = 0xf0; 314 sense_buf[2] = sense.key; 315 sense_buf[7] = 10; 316 sense_buf[12] = sense.asc; 317 sense_buf[13] = sense.ascq; 318 megasas_build_sense(cmd, sense_buf, sense_len); 319 } 320 321 static void megasas_copy_sense(MegasasCmd *cmd) 322 { 323 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE]; 324 uint8_t sense_len; 325 326 sense_len = scsi_req_get_sense(cmd->req, sense_buf, 327 SCSI_SENSE_BUF_SIZE); 328 megasas_build_sense(cmd, sense_buf, sense_len); 329 } 330 331 /* 332 * Format an INQUIRY CDB 333 */ 334 static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len) 335 { 336 memset(cdb, 0, 6); 337 cdb[0] = INQUIRY; 338 if (pg > 0) { 339 cdb[1] = 0x1; 340 cdb[2] = pg; 341 } 342 cdb[3] = (len >> 8) & 0xff; 343 cdb[4] = (len & 0xff); 344 return len; 345 } 346 347 /* 348 * Encode lba and len into a READ_16/WRITE_16 CDB 349 */ 350 static void megasas_encode_lba(uint8_t *cdb, uint64_t lba, 351 uint32_t len, bool is_write) 352 { 353 memset(cdb, 0x0, 16); 354 if (is_write) { 355 cdb[0] = WRITE_16; 356 } else { 357 cdb[0] = READ_16; 358 } 359 cdb[2] = (lba >> 56) & 0xff; 360 cdb[3] = (lba >> 48) & 0xff; 361 cdb[4] = (lba >> 40) & 0xff; 362 cdb[5] = (lba >> 32) & 0xff; 363 cdb[6] = (lba >> 24) & 0xff; 364 cdb[7] = (lba >> 16) & 0xff; 365 cdb[8] = (lba >> 8) & 0xff; 366 cdb[9] = (lba) & 0xff; 367 cdb[10] = (len >> 24) & 0xff; 368 cdb[11] = (len >> 16) & 0xff; 369 cdb[12] = (len >> 8) & 0xff; 370 cdb[13] = (len) & 0xff; 371 } 372 373 /* 374 * Utility functions 375 */ 376 static uint64_t megasas_fw_time(void) 377 { 378 struct tm curtime; 379 uint64_t bcd_time; 380 381 qemu_get_timedate(&curtime, 0); 382 bcd_time = ((uint64_t)curtime.tm_sec & 0xff) << 48 | 383 ((uint64_t)curtime.tm_min & 0xff) << 40 | 384 ((uint64_t)curtime.tm_hour & 0xff) << 32 | 385 ((uint64_t)curtime.tm_mday & 0xff) << 24 | 386 ((uint64_t)curtime.tm_mon & 0xff) << 16 | 387 ((uint64_t)(curtime.tm_year + 1900) & 0xffff); 388 389 return bcd_time; 390 } 391 392 /* 393 * Default disk sata address 394 * 0x1221 is the magic number as 395 * present in real hardware, 396 * so use it here, too. 397 */ 398 static uint64_t megasas_get_sata_addr(uint16_t id) 399 { 400 uint64_t addr = (0x1221ULL << 48); 401 return addr & (id << 24); 402 } 403 404 /* 405 * Frame handling 406 */ 407 static int megasas_next_index(MegasasState *s, int index, int limit) 408 { 409 index++; 410 if (index == limit) { 411 index = 0; 412 } 413 return index; 414 } 415 416 static MegasasCmd *megasas_lookup_frame(MegasasState *s, 417 hwaddr frame) 418 { 419 MegasasCmd *cmd = NULL; 420 int num = 0, index; 421 422 index = s->reply_queue_head; 423 424 while (num < s->fw_cmds) { 425 if (s->frames[index].pa && s->frames[index].pa == frame) { 426 cmd = &s->frames[index]; 427 break; 428 } 429 index = megasas_next_index(s, index, s->fw_cmds); 430 num++; 431 } 432 433 return cmd; 434 } 435 436 static MegasasCmd *megasas_next_frame(MegasasState *s, 437 hwaddr frame) 438 { 439 MegasasCmd *cmd = NULL; 440 int num = 0, index; 441 442 cmd = megasas_lookup_frame(s, frame); 443 if (cmd) { 444 trace_megasas_qf_found(cmd->index, cmd->pa); 445 return cmd; 446 } 447 index = s->reply_queue_head; 448 num = 0; 449 while (num < s->fw_cmds) { 450 if (!s->frames[index].pa) { 451 cmd = &s->frames[index]; 452 break; 453 } 454 index = megasas_next_index(s, index, s->fw_cmds); 455 num++; 456 } 457 if (!cmd) { 458 trace_megasas_qf_failed(frame); 459 } 460 trace_megasas_qf_new(index, cmd); 461 return cmd; 462 } 463 464 static MegasasCmd *megasas_enqueue_frame(MegasasState *s, 465 hwaddr frame, uint64_t context, int count) 466 { 467 MegasasCmd *cmd = NULL; 468 int frame_size = MFI_FRAME_SIZE * 16; 469 hwaddr frame_size_p = frame_size; 470 471 cmd = megasas_next_frame(s, frame); 472 /* All frames busy */ 473 if (!cmd) { 474 return NULL; 475 } 476 if (!cmd->pa) { 477 cmd->pa = frame; 478 /* Map all possible frames */ 479 cmd->frame = cpu_physical_memory_map(frame, &frame_size_p, 0); 480 if (frame_size_p != frame_size) { 481 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame); 482 if (cmd->frame) { 483 cpu_physical_memory_unmap(cmd->frame, frame_size_p, 0, 0); 484 cmd->frame = NULL; 485 cmd->pa = 0; 486 } 487 s->event_count++; 488 return NULL; 489 } 490 cmd->pa_size = frame_size_p; 491 cmd->context = context; 492 if (!megasas_use_queue64(s)) { 493 cmd->context &= (uint64_t)0xFFFFFFFF; 494 } 495 } 496 cmd->count = count; 497 s->busy++; 498 499 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context, 500 s->reply_queue_head, s->busy); 501 502 return cmd; 503 } 504 505 static void megasas_complete_frame(MegasasState *s, uint64_t context) 506 { 507 PCIDevice *pci_dev = PCI_DEVICE(s); 508 int tail, queue_offset; 509 510 /* Decrement busy count */ 511 s->busy--; 512 513 if (s->reply_queue_pa) { 514 /* 515 * Put command on the reply queue. 516 * Context is opaque, but emulation is running in 517 * little endian. So convert it. 518 */ 519 tail = s->reply_queue_head; 520 if (megasas_use_queue64(s)) { 521 queue_offset = tail * sizeof(uint64_t); 522 stq_le_phys(&address_space_memory, 523 s->reply_queue_pa + queue_offset, context); 524 } else { 525 queue_offset = tail * sizeof(uint32_t); 526 stl_le_phys(&address_space_memory, 527 s->reply_queue_pa + queue_offset, context); 528 } 529 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds); 530 trace_megasas_qf_complete(context, tail, queue_offset, 531 s->busy, s->doorbell); 532 } 533 534 if (megasas_intr_enabled(s)) { 535 /* Notify HBA */ 536 s->doorbell++; 537 if (s->doorbell == 1) { 538 if (msix_enabled(pci_dev)) { 539 trace_megasas_msix_raise(0); 540 msix_notify(pci_dev, 0); 541 } else { 542 trace_megasas_irq_raise(); 543 pci_irq_assert(pci_dev); 544 } 545 } 546 } else { 547 trace_megasas_qf_complete_noirq(context); 548 } 549 } 550 551 static void megasas_reset_frames(MegasasState *s) 552 { 553 int i; 554 MegasasCmd *cmd; 555 556 for (i = 0; i < s->fw_cmds; i++) { 557 cmd = &s->frames[i]; 558 if (cmd->pa) { 559 cpu_physical_memory_unmap(cmd->frame, cmd->pa_size, 0, 0); 560 cmd->frame = NULL; 561 cmd->pa = 0; 562 } 563 } 564 } 565 566 static void megasas_abort_command(MegasasCmd *cmd) 567 { 568 if (cmd->req) { 569 scsi_req_cancel(cmd->req); 570 cmd->req = NULL; 571 } 572 } 573 574 static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd) 575 { 576 uint32_t pa_hi, pa_lo; 577 hwaddr iq_pa, initq_size; 578 struct mfi_init_qinfo *initq; 579 uint32_t flags; 580 int ret = MFI_STAT_OK; 581 582 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo); 583 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi); 584 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo); 585 trace_megasas_init_firmware((uint64_t)iq_pa); 586 initq_size = sizeof(*initq); 587 initq = cpu_physical_memory_map(iq_pa, &initq_size, 0); 588 if (!initq || initq_size != sizeof(*initq)) { 589 trace_megasas_initq_map_failed(cmd->index); 590 s->event_count++; 591 ret = MFI_STAT_MEMORY_NOT_AVAILABLE; 592 goto out; 593 } 594 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF; 595 if (s->reply_queue_len > s->fw_cmds) { 596 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds); 597 s->event_count++; 598 ret = MFI_STAT_INVALID_PARAMETER; 599 goto out; 600 } 601 pa_lo = le32_to_cpu(initq->rq_addr_lo); 602 pa_hi = le32_to_cpu(initq->rq_addr_hi); 603 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo; 604 pa_lo = le32_to_cpu(initq->ci_addr_lo); 605 pa_hi = le32_to_cpu(initq->ci_addr_hi); 606 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo; 607 pa_lo = le32_to_cpu(initq->pi_addr_lo); 608 pa_hi = le32_to_cpu(initq->pi_addr_hi); 609 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo; 610 s->reply_queue_head = ldl_le_phys(&address_space_memory, s->producer_pa); 611 s->reply_queue_tail = ldl_le_phys(&address_space_memory, s->consumer_pa); 612 flags = le32_to_cpu(initq->flags); 613 if (flags & MFI_QUEUE_FLAG_CONTEXT64) { 614 s->flags |= MEGASAS_MASK_USE_QUEUE64; 615 } 616 trace_megasas_init_queue((unsigned long)s->reply_queue_pa, 617 s->reply_queue_len, s->reply_queue_head, 618 s->reply_queue_tail, flags); 619 megasas_reset_frames(s); 620 s->fw_state = MFI_FWSTATE_OPERATIONAL; 621 out: 622 if (initq) { 623 cpu_physical_memory_unmap(initq, initq_size, 0, 0); 624 } 625 return ret; 626 } 627 628 static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd) 629 { 630 dma_addr_t iov_pa, iov_size; 631 632 cmd->flags = le16_to_cpu(cmd->frame->header.flags); 633 if (!cmd->frame->header.sge_count) { 634 trace_megasas_dcmd_zero_sge(cmd->index); 635 cmd->iov_size = 0; 636 return 0; 637 } else if (cmd->frame->header.sge_count > 1) { 638 trace_megasas_dcmd_invalid_sge(cmd->index, 639 cmd->frame->header.sge_count); 640 cmd->iov_size = 0; 641 return -1; 642 } 643 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl); 644 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl); 645 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1); 646 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size); 647 cmd->iov_size = iov_size; 648 return cmd->iov_size; 649 } 650 651 static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size) 652 { 653 trace_megasas_finish_dcmd(cmd->index, iov_size); 654 655 if (cmd->frame->header.sge_count) { 656 qemu_sglist_destroy(&cmd->qsg); 657 } 658 if (iov_size > cmd->iov_size) { 659 if (megasas_frame_is_ieee_sgl(cmd)) { 660 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size); 661 } else if (megasas_frame_is_sgl64(cmd)) { 662 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size); 663 } else { 664 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size); 665 } 666 } 667 cmd->iov_size = 0; 668 } 669 670 static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd) 671 { 672 PCIDevice *pci_dev = PCI_DEVICE(s); 673 struct mfi_ctrl_info info; 674 size_t dcmd_size = sizeof(info); 675 BusChild *kid; 676 int num_ld_disks = 0; 677 uint16_t sdev_id; 678 679 memset(&info, 0x0, cmd->iov_size); 680 if (cmd->iov_size < dcmd_size) { 681 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, 682 dcmd_size); 683 return MFI_STAT_INVALID_PARAMETER; 684 } 685 686 info.pci.vendor = cpu_to_le16(PCI_VENDOR_ID_LSI_LOGIC); 687 info.pci.device = cpu_to_le16(PCI_DEVICE_ID_LSI_SAS1078); 688 info.pci.subvendor = cpu_to_le16(PCI_VENDOR_ID_LSI_LOGIC); 689 info.pci.subdevice = cpu_to_le16(0x1013); 690 691 /* 692 * For some reason the firmware supports 693 * only up to 8 device ports. 694 * Despite supporting a far larger number 695 * of devices for the physical devices. 696 * So just display the first 8 devices 697 * in the device port list, independent 698 * of how many logical devices are actually 699 * present. 700 */ 701 info.host.type = MFI_INFO_HOST_PCIE; 702 info.device.type = MFI_INFO_DEV_SAS3G; 703 info.device.port_count = 8; 704 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { 705 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child); 706 707 if (num_ld_disks < 8) { 708 sdev_id = ((sdev->id & 0xFF) >> 8) | (sdev->lun & 0xFF); 709 info.device.port_addr[num_ld_disks] = 710 cpu_to_le64(megasas_get_sata_addr(sdev_id)); 711 } 712 num_ld_disks++; 713 } 714 715 memcpy(info.product_name, "MegaRAID SAS 8708EM2", 20); 716 snprintf(info.serial_number, 32, "%s", s->hba_serial); 717 snprintf(info.package_version, 0x60, "%s-QEMU", QEMU_VERSION); 718 memcpy(info.image_component[0].name, "APP", 3); 719 memcpy(info.image_component[0].version, MEGASAS_VERSION "-QEMU", 9); 720 memcpy(info.image_component[0].build_date, __DATE__, 11); 721 memcpy(info.image_component[0].build_time, __TIME__, 8); 722 info.image_component_count = 1; 723 if (pci_dev->has_rom) { 724 uint8_t biosver[32]; 725 uint8_t *ptr; 726 727 ptr = memory_region_get_ram_ptr(&pci_dev->rom); 728 memcpy(biosver, ptr + 0x41, 31); 729 memcpy(info.image_component[1].name, "BIOS", 4); 730 memcpy(info.image_component[1].version, biosver, 731 strlen((const char *)biosver)); 732 info.image_component_count++; 733 } 734 info.current_fw_time = cpu_to_le32(megasas_fw_time()); 735 info.max_arms = 32; 736 info.max_spans = 8; 737 info.max_arrays = MEGASAS_MAX_ARRAYS; 738 info.max_lds = s->fw_luns; 739 info.max_cmds = cpu_to_le16(s->fw_cmds); 740 info.max_sg_elements = cpu_to_le16(s->fw_sge); 741 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS); 742 info.lds_present = cpu_to_le16(num_ld_disks); 743 info.pd_present = cpu_to_le16(num_ld_disks); 744 info.pd_disks_present = cpu_to_le16(num_ld_disks); 745 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM | 746 MFI_INFO_HW_MEM | 747 MFI_INFO_HW_FLASH); 748 info.memory_size = cpu_to_le16(512); 749 info.nvram_size = cpu_to_le16(32); 750 info.flash_size = cpu_to_le16(16); 751 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0); 752 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE | 753 MFI_INFO_AOPS_SELF_DIAGNOSTIC | 754 MFI_INFO_AOPS_MIXED_ARRAY); 755 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY | 756 MFI_INFO_LDOPS_ACCESS_POLICY | 757 MFI_INFO_LDOPS_IO_POLICY | 758 MFI_INFO_LDOPS_WRITE_POLICY | 759 MFI_INFO_LDOPS_READ_POLICY); 760 info.max_strips_per_io = cpu_to_le16(s->fw_sge); 761 info.stripe_sz_ops.min = 3; 762 info.stripe_sz_ops.max = ffs(MEGASAS_MAX_SECTORS + 1) - 1; 763 info.properties.pred_fail_poll_interval = cpu_to_le16(300); 764 info.properties.intr_throttle_cnt = cpu_to_le16(16); 765 info.properties.intr_throttle_timeout = cpu_to_le16(50); 766 info.properties.rebuild_rate = 30; 767 info.properties.patrol_read_rate = 30; 768 info.properties.bgi_rate = 30; 769 info.properties.cc_rate = 30; 770 info.properties.recon_rate = 30; 771 info.properties.cache_flush_interval = 4; 772 info.properties.spinup_drv_cnt = 2; 773 info.properties.spinup_delay = 6; 774 info.properties.ecc_bucket_size = 15; 775 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440); 776 info.properties.expose_encl_devices = 1; 777 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD); 778 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE | 779 MFI_INFO_PDOPS_FORCE_OFFLINE); 780 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS | 781 MFI_INFO_PDMIX_SATA | 782 MFI_INFO_PDMIX_LD); 783 784 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg); 785 return MFI_STAT_OK; 786 } 787 788 static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd) 789 { 790 struct mfi_defaults info; 791 size_t dcmd_size = sizeof(struct mfi_defaults); 792 793 memset(&info, 0x0, dcmd_size); 794 if (cmd->iov_size < dcmd_size) { 795 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, 796 dcmd_size); 797 return MFI_STAT_INVALID_PARAMETER; 798 } 799 800 info.sas_addr = cpu_to_le64(s->sas_addr); 801 info.stripe_size = 3; 802 info.flush_time = 4; 803 info.background_rate = 30; 804 info.allow_mix_in_enclosure = 1; 805 info.allow_mix_in_ld = 1; 806 info.direct_pd_mapping = 1; 807 /* Enable for BIOS support */ 808 info.bios_enumerate_lds = 1; 809 info.disable_ctrl_r = 1; 810 info.expose_enclosure_devices = 1; 811 info.disable_preboot_cli = 1; 812 info.cluster_disable = 1; 813 814 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg); 815 return MFI_STAT_OK; 816 } 817 818 static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd) 819 { 820 struct mfi_bios_data info; 821 size_t dcmd_size = sizeof(info); 822 823 memset(&info, 0x0, dcmd_size); 824 if (cmd->iov_size < dcmd_size) { 825 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, 826 dcmd_size); 827 return MFI_STAT_INVALID_PARAMETER; 828 } 829 info.continue_on_error = 1; 830 info.verbose = 1; 831 if (megasas_is_jbod(s)) { 832 info.expose_all_drives = 1; 833 } 834 835 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg); 836 return MFI_STAT_OK; 837 } 838 839 static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd) 840 { 841 uint64_t fw_time; 842 size_t dcmd_size = sizeof(fw_time); 843 844 fw_time = cpu_to_le64(megasas_fw_time()); 845 846 cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg); 847 return MFI_STAT_OK; 848 } 849 850 static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd) 851 { 852 uint64_t fw_time; 853 854 /* This is a dummy; setting of firmware time is not allowed */ 855 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time)); 856 857 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time); 858 fw_time = cpu_to_le64(megasas_fw_time()); 859 return MFI_STAT_OK; 860 } 861 862 static int megasas_event_info(MegasasState *s, MegasasCmd *cmd) 863 { 864 struct mfi_evt_log_state info; 865 size_t dcmd_size = sizeof(info); 866 867 memset(&info, 0, dcmd_size); 868 869 info.newest_seq_num = cpu_to_le32(s->event_count); 870 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event); 871 info.boot_seq_num = cpu_to_le32(s->boot_event); 872 873 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg); 874 return MFI_STAT_OK; 875 } 876 877 static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd) 878 { 879 union mfi_evt event; 880 881 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) { 882 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, 883 sizeof(struct mfi_evt_detail)); 884 return MFI_STAT_INVALID_PARAMETER; 885 } 886 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]); 887 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]); 888 s->event_locale = event.members.locale; 889 s->event_class = event.members.class; 890 s->event_cmd = cmd; 891 /* Decrease busy count; event frame doesn't count here */ 892 s->busy--; 893 cmd->iov_size = sizeof(struct mfi_evt_detail); 894 return MFI_STAT_INVALID_STATUS; 895 } 896 897 static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd) 898 { 899 struct mfi_pd_list info; 900 size_t dcmd_size = sizeof(info); 901 BusChild *kid; 902 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks; 903 uint16_t sdev_id; 904 905 memset(&info, 0, dcmd_size); 906 offset = 8; 907 dcmd_limit = offset + sizeof(struct mfi_pd_address); 908 if (cmd->iov_size < dcmd_limit) { 909 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, 910 dcmd_limit); 911 return MFI_STAT_INVALID_PARAMETER; 912 } 913 914 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address); 915 if (max_pd_disks > s->fw_luns) { 916 max_pd_disks = s->fw_luns; 917 } 918 919 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { 920 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child); 921 922 sdev_id = ((sdev->id & 0xFF) >> 8) | (sdev->lun & 0xFF); 923 info.addr[num_pd_disks].device_id = cpu_to_le16(sdev_id); 924 info.addr[num_pd_disks].encl_device_id = 0xFFFF; 925 info.addr[num_pd_disks].encl_index = 0; 926 info.addr[num_pd_disks].slot_number = (sdev->id & 0xFF); 927 info.addr[num_pd_disks].scsi_dev_type = sdev->type; 928 info.addr[num_pd_disks].connect_port_bitmap = 0x1; 929 info.addr[num_pd_disks].sas_addr[0] = 930 cpu_to_le64(megasas_get_sata_addr(sdev_id)); 931 num_pd_disks++; 932 offset += sizeof(struct mfi_pd_address); 933 } 934 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks, 935 max_pd_disks, offset); 936 937 info.size = cpu_to_le32(offset); 938 info.count = cpu_to_le32(num_pd_disks); 939 940 cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg); 941 return MFI_STAT_OK; 942 } 943 944 static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd) 945 { 946 uint16_t flags; 947 948 /* mbox0 contains flags */ 949 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]); 950 trace_megasas_dcmd_pd_list_query(cmd->index, flags); 951 if (flags == MR_PD_QUERY_TYPE_ALL || 952 megasas_is_jbod(s)) { 953 return megasas_dcmd_pd_get_list(s, cmd); 954 } 955 956 return MFI_STAT_OK; 957 } 958 959 static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun, 960 MegasasCmd *cmd) 961 { 962 struct mfi_pd_info *info = cmd->iov_buf; 963 size_t dcmd_size = sizeof(struct mfi_pd_info); 964 BlockConf *conf = &sdev->conf; 965 uint64_t pd_size; 966 uint16_t sdev_id = ((sdev->id & 0xFF) >> 8) | (lun & 0xFF); 967 uint8_t cmdbuf[6]; 968 SCSIRequest *req; 969 size_t len, resid; 970 971 if (!cmd->iov_buf) { 972 cmd->iov_buf = g_malloc(dcmd_size); 973 memset(cmd->iov_buf, 0, dcmd_size); 974 info = cmd->iov_buf; 975 info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */ 976 info->vpd_page83[0] = 0x7f; 977 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data)); 978 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd); 979 if (!req) { 980 trace_megasas_dcmd_req_alloc_failed(cmd->index, 981 "PD get info std inquiry"); 982 g_free(cmd->iov_buf); 983 cmd->iov_buf = NULL; 984 return MFI_STAT_FLASH_ALLOC_FAIL; 985 } 986 trace_megasas_dcmd_internal_submit(cmd->index, 987 "PD get info std inquiry", lun); 988 len = scsi_req_enqueue(req); 989 if (len > 0) { 990 cmd->iov_size = len; 991 scsi_req_continue(req); 992 } 993 return MFI_STAT_INVALID_STATUS; 994 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) { 995 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83)); 996 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd); 997 if (!req) { 998 trace_megasas_dcmd_req_alloc_failed(cmd->index, 999 "PD get info vpd inquiry"); 1000 return MFI_STAT_FLASH_ALLOC_FAIL; 1001 } 1002 trace_megasas_dcmd_internal_submit(cmd->index, 1003 "PD get info vpd inquiry", lun); 1004 len = scsi_req_enqueue(req); 1005 if (len > 0) { 1006 cmd->iov_size = len; 1007 scsi_req_continue(req); 1008 } 1009 return MFI_STAT_INVALID_STATUS; 1010 } 1011 /* Finished, set FW state */ 1012 if ((info->inquiry_data[0] >> 5) == 0) { 1013 if (megasas_is_jbod(cmd->state)) { 1014 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM); 1015 } else { 1016 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE); 1017 } 1018 } else { 1019 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE); 1020 } 1021 1022 info->ref.v.device_id = cpu_to_le16(sdev_id); 1023 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD| 1024 MFI_PD_DDF_TYPE_INTF_SAS); 1025 bdrv_get_geometry(conf->bs, &pd_size); 1026 info->raw_size = cpu_to_le64(pd_size); 1027 info->non_coerced_size = cpu_to_le64(pd_size); 1028 info->coerced_size = cpu_to_le64(pd_size); 1029 info->encl_device_id = 0xFFFF; 1030 info->slot_number = (sdev->id & 0xFF); 1031 info->path_info.count = 1; 1032 info->path_info.sas_addr[0] = 1033 cpu_to_le64(megasas_get_sata_addr(sdev_id)); 1034 info->connected_port_bitmap = 0x1; 1035 info->device_speed = 1; 1036 info->link_speed = 1; 1037 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg); 1038 g_free(cmd->iov_buf); 1039 cmd->iov_size = dcmd_size - resid; 1040 cmd->iov_buf = NULL; 1041 return MFI_STAT_OK; 1042 } 1043 1044 static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd) 1045 { 1046 size_t dcmd_size = sizeof(struct mfi_pd_info); 1047 uint16_t pd_id; 1048 SCSIDevice *sdev = NULL; 1049 int retval = MFI_STAT_DEVICE_NOT_FOUND; 1050 1051 if (cmd->iov_size < dcmd_size) { 1052 return MFI_STAT_INVALID_PARAMETER; 1053 } 1054 1055 /* mbox0 has the ID */ 1056 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]); 1057 sdev = scsi_device_find(&s->bus, 0, pd_id, 0); 1058 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id); 1059 1060 if (sdev) { 1061 /* Submit inquiry */ 1062 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd); 1063 } 1064 1065 return retval; 1066 } 1067 1068 static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd) 1069 { 1070 struct mfi_ld_list info; 1071 size_t dcmd_size = sizeof(info), resid; 1072 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns; 1073 uint64_t ld_size; 1074 BusChild *kid; 1075 1076 memset(&info, 0, dcmd_size); 1077 if (cmd->iov_size < dcmd_size) { 1078 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, 1079 dcmd_size); 1080 return MFI_STAT_INVALID_PARAMETER; 1081 } 1082 1083 if (megasas_is_jbod(s)) { 1084 max_ld_disks = 0; 1085 } 1086 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { 1087 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child); 1088 BlockConf *conf = &sdev->conf; 1089 1090 if (num_ld_disks >= max_ld_disks) { 1091 break; 1092 } 1093 /* Logical device size is in blocks */ 1094 bdrv_get_geometry(conf->bs, &ld_size); 1095 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id; 1096 info.ld_list[num_ld_disks].ld.v.lun_id = sdev->lun; 1097 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL; 1098 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size); 1099 num_ld_disks++; 1100 } 1101 info.ld_count = cpu_to_le32(num_ld_disks); 1102 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks); 1103 1104 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg); 1105 cmd->iov_size = dcmd_size - resid; 1106 return MFI_STAT_OK; 1107 } 1108 1109 static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun, 1110 MegasasCmd *cmd) 1111 { 1112 struct mfi_ld_info *info = cmd->iov_buf; 1113 size_t dcmd_size = sizeof(struct mfi_ld_info); 1114 uint8_t cdb[6]; 1115 SCSIRequest *req; 1116 ssize_t len, resid; 1117 BlockConf *conf = &sdev->conf; 1118 uint16_t sdev_id = ((sdev->id & 0xFF) >> 8) | (lun & 0xFF); 1119 uint64_t ld_size; 1120 1121 if (!cmd->iov_buf) { 1122 cmd->iov_buf = g_malloc(dcmd_size); 1123 memset(cmd->iov_buf, 0x0, dcmd_size); 1124 info = cmd->iov_buf; 1125 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83)); 1126 req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd); 1127 if (!req) { 1128 trace_megasas_dcmd_req_alloc_failed(cmd->index, 1129 "LD get info vpd inquiry"); 1130 g_free(cmd->iov_buf); 1131 cmd->iov_buf = NULL; 1132 return MFI_STAT_FLASH_ALLOC_FAIL; 1133 } 1134 trace_megasas_dcmd_internal_submit(cmd->index, 1135 "LD get info vpd inquiry", lun); 1136 len = scsi_req_enqueue(req); 1137 if (len > 0) { 1138 cmd->iov_size = len; 1139 scsi_req_continue(req); 1140 } 1141 return MFI_STAT_INVALID_STATUS; 1142 } 1143 1144 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL; 1145 info->ld_config.properties.ld.v.target_id = lun; 1146 info->ld_config.params.stripe_size = 3; 1147 info->ld_config.params.num_drives = 1; 1148 info->ld_config.params.is_consistent = 1; 1149 /* Logical device size is in blocks */ 1150 bdrv_get_geometry(conf->bs, &ld_size); 1151 info->size = cpu_to_le64(ld_size); 1152 memset(info->ld_config.span, 0, sizeof(info->ld_config.span)); 1153 info->ld_config.span[0].start_block = 0; 1154 info->ld_config.span[0].num_blocks = info->size; 1155 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id); 1156 1157 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg); 1158 g_free(cmd->iov_buf); 1159 cmd->iov_size = dcmd_size - resid; 1160 cmd->iov_buf = NULL; 1161 return MFI_STAT_OK; 1162 } 1163 1164 static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd) 1165 { 1166 struct mfi_ld_info info; 1167 size_t dcmd_size = sizeof(info); 1168 uint16_t ld_id; 1169 uint32_t max_ld_disks = s->fw_luns; 1170 SCSIDevice *sdev = NULL; 1171 int retval = MFI_STAT_DEVICE_NOT_FOUND; 1172 1173 if (cmd->iov_size < dcmd_size) { 1174 return MFI_STAT_INVALID_PARAMETER; 1175 } 1176 1177 /* mbox0 has the ID */ 1178 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]); 1179 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id); 1180 1181 if (megasas_is_jbod(s)) { 1182 return MFI_STAT_DEVICE_NOT_FOUND; 1183 } 1184 1185 if (ld_id < max_ld_disks) { 1186 sdev = scsi_device_find(&s->bus, 0, ld_id, 0); 1187 } 1188 1189 if (sdev) { 1190 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd); 1191 } 1192 1193 return retval; 1194 } 1195 1196 static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd) 1197 { 1198 uint8_t data[4096]; 1199 struct mfi_config_data *info; 1200 int num_pd_disks = 0, array_offset, ld_offset; 1201 BusChild *kid; 1202 1203 if (cmd->iov_size > 4096) { 1204 return MFI_STAT_INVALID_PARAMETER; 1205 } 1206 1207 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { 1208 num_pd_disks++; 1209 } 1210 info = (struct mfi_config_data *)&data; 1211 /* 1212 * Array mapping: 1213 * - One array per SCSI device 1214 * - One logical drive per SCSI device 1215 * spanning the entire device 1216 */ 1217 info->array_count = num_pd_disks; 1218 info->array_size = sizeof(struct mfi_array) * num_pd_disks; 1219 info->log_drv_count = num_pd_disks; 1220 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks; 1221 info->spares_count = 0; 1222 info->spares_size = sizeof(struct mfi_spare); 1223 info->size = sizeof(struct mfi_config_data) + info->array_size + 1224 info->log_drv_size; 1225 if (info->size > 4096) { 1226 return MFI_STAT_INVALID_PARAMETER; 1227 } 1228 1229 array_offset = sizeof(struct mfi_config_data); 1230 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks; 1231 1232 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { 1233 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child); 1234 BlockConf *conf = &sdev->conf; 1235 uint16_t sdev_id = ((sdev->id & 0xFF) >> 8) | (sdev->lun & 0xFF); 1236 struct mfi_array *array; 1237 struct mfi_ld_config *ld; 1238 uint64_t pd_size; 1239 int i; 1240 1241 array = (struct mfi_array *)(data + array_offset); 1242 bdrv_get_geometry(conf->bs, &pd_size); 1243 array->size = cpu_to_le64(pd_size); 1244 array->num_drives = 1; 1245 array->array_ref = cpu_to_le16(sdev_id); 1246 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id); 1247 array->pd[0].ref.v.seq_num = 0; 1248 array->pd[0].fw_state = MFI_PD_STATE_ONLINE; 1249 array->pd[0].encl.pd = 0xFF; 1250 array->pd[0].encl.slot = (sdev->id & 0xFF); 1251 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) { 1252 array->pd[i].ref.v.device_id = 0xFFFF; 1253 array->pd[i].ref.v.seq_num = 0; 1254 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD; 1255 array->pd[i].encl.pd = 0xFF; 1256 array->pd[i].encl.slot = 0xFF; 1257 } 1258 array_offset += sizeof(struct mfi_array); 1259 ld = (struct mfi_ld_config *)(data + ld_offset); 1260 memset(ld, 0, sizeof(struct mfi_ld_config)); 1261 ld->properties.ld.v.target_id = (sdev->id & 0xFF); 1262 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD | 1263 MR_LD_CACHE_READ_ADAPTIVE; 1264 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD | 1265 MR_LD_CACHE_READ_ADAPTIVE; 1266 ld->params.state = MFI_LD_STATE_OPTIMAL; 1267 ld->params.stripe_size = 3; 1268 ld->params.num_drives = 1; 1269 ld->params.span_depth = 1; 1270 ld->params.is_consistent = 1; 1271 ld->span[0].start_block = 0; 1272 ld->span[0].num_blocks = cpu_to_le64(pd_size); 1273 ld->span[0].array_ref = cpu_to_le16(sdev_id); 1274 ld_offset += sizeof(struct mfi_ld_config); 1275 } 1276 1277 cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg); 1278 return MFI_STAT_OK; 1279 } 1280 1281 static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd) 1282 { 1283 struct mfi_ctrl_props info; 1284 size_t dcmd_size = sizeof(info); 1285 1286 memset(&info, 0x0, dcmd_size); 1287 if (cmd->iov_size < dcmd_size) { 1288 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, 1289 dcmd_size); 1290 return MFI_STAT_INVALID_PARAMETER; 1291 } 1292 info.pred_fail_poll_interval = cpu_to_le16(300); 1293 info.intr_throttle_cnt = cpu_to_le16(16); 1294 info.intr_throttle_timeout = cpu_to_le16(50); 1295 info.rebuild_rate = 30; 1296 info.patrol_read_rate = 30; 1297 info.bgi_rate = 30; 1298 info.cc_rate = 30; 1299 info.recon_rate = 30; 1300 info.cache_flush_interval = 4; 1301 info.spinup_drv_cnt = 2; 1302 info.spinup_delay = 6; 1303 info.ecc_bucket_size = 15; 1304 info.ecc_bucket_leak_rate = cpu_to_le16(1440); 1305 info.expose_encl_devices = 1; 1306 1307 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg); 1308 return MFI_STAT_OK; 1309 } 1310 1311 static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd) 1312 { 1313 bdrv_drain_all(); 1314 return MFI_STAT_OK; 1315 } 1316 1317 static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd) 1318 { 1319 s->fw_state = MFI_FWSTATE_READY; 1320 return MFI_STAT_OK; 1321 } 1322 1323 static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd) 1324 { 1325 return MFI_STAT_INVALID_DCMD; 1326 } 1327 1328 static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd) 1329 { 1330 struct mfi_ctrl_props info; 1331 size_t dcmd_size = sizeof(info); 1332 1333 if (cmd->iov_size < dcmd_size) { 1334 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, 1335 dcmd_size); 1336 return MFI_STAT_INVALID_PARAMETER; 1337 } 1338 dma_buf_write((uint8_t *)&info, cmd->iov_size, &cmd->qsg); 1339 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size); 1340 return MFI_STAT_OK; 1341 } 1342 1343 static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd) 1344 { 1345 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size); 1346 return MFI_STAT_OK; 1347 } 1348 1349 static const struct dcmd_cmd_tbl_t { 1350 int opcode; 1351 const char *desc; 1352 int (*func)(MegasasState *s, MegasasCmd *cmd); 1353 } dcmd_cmd_tbl[] = { 1354 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC", 1355 megasas_dcmd_dummy }, 1356 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO", 1357 megasas_ctrl_get_info }, 1358 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES", 1359 megasas_dcmd_get_properties }, 1360 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES", 1361 megasas_dcmd_set_properties }, 1362 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET", 1363 megasas_dcmd_dummy }, 1364 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE", 1365 megasas_dcmd_dummy }, 1366 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE", 1367 megasas_dcmd_dummy }, 1368 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE", 1369 megasas_dcmd_dummy }, 1370 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST", 1371 megasas_dcmd_dummy }, 1372 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO", 1373 megasas_event_info }, 1374 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET", 1375 megasas_dcmd_dummy }, 1376 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT", 1377 megasas_event_wait }, 1378 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN", 1379 megasas_ctrl_shutdown }, 1380 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY", 1381 megasas_dcmd_dummy }, 1382 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME", 1383 megasas_dcmd_get_fw_time }, 1384 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME", 1385 megasas_dcmd_set_fw_time }, 1386 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET", 1387 megasas_dcmd_get_bios_info }, 1388 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS", 1389 megasas_dcmd_dummy }, 1390 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET", 1391 megasas_mfc_get_defaults }, 1392 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET", 1393 megasas_dcmd_dummy }, 1394 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH", 1395 megasas_cache_flush }, 1396 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST", 1397 megasas_dcmd_pd_get_list }, 1398 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY", 1399 megasas_dcmd_pd_list_query }, 1400 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO", 1401 megasas_dcmd_pd_get_info }, 1402 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET", 1403 megasas_dcmd_dummy }, 1404 { MFI_DCMD_PD_REBUILD, "PD_REBUILD", 1405 megasas_dcmd_dummy }, 1406 { MFI_DCMD_PD_BLINK, "PD_BLINK", 1407 megasas_dcmd_dummy }, 1408 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK", 1409 megasas_dcmd_dummy }, 1410 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST", 1411 megasas_dcmd_ld_get_list}, 1412 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO", 1413 megasas_dcmd_ld_get_info }, 1414 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP", 1415 megasas_dcmd_dummy }, 1416 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP", 1417 megasas_dcmd_dummy }, 1418 { MFI_DCMD_LD_DELETE, "LD_DELETE", 1419 megasas_dcmd_dummy }, 1420 { MFI_DCMD_CFG_READ, "CFG_READ", 1421 megasas_dcmd_cfg_read }, 1422 { MFI_DCMD_CFG_ADD, "CFG_ADD", 1423 megasas_dcmd_dummy }, 1424 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR", 1425 megasas_dcmd_dummy }, 1426 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ", 1427 megasas_dcmd_dummy }, 1428 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT", 1429 megasas_dcmd_dummy }, 1430 { MFI_DCMD_BBU_STATUS, "BBU_STATUS", 1431 megasas_dcmd_dummy }, 1432 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO", 1433 megasas_dcmd_dummy }, 1434 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO", 1435 megasas_dcmd_dummy }, 1436 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET", 1437 megasas_dcmd_dummy }, 1438 { MFI_DCMD_CLUSTER, "CLUSTER", 1439 megasas_dcmd_dummy }, 1440 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL", 1441 megasas_dcmd_dummy }, 1442 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD", 1443 megasas_cluster_reset_ld }, 1444 { -1, NULL, NULL } 1445 }; 1446 1447 static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd) 1448 { 1449 int opcode, len; 1450 int retval = 0; 1451 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl; 1452 1453 opcode = le32_to_cpu(cmd->frame->dcmd.opcode); 1454 trace_megasas_handle_dcmd(cmd->index, opcode); 1455 len = megasas_map_dcmd(s, cmd); 1456 if (len < 0) { 1457 return MFI_STAT_MEMORY_NOT_AVAILABLE; 1458 } 1459 while (cmdptr->opcode != -1 && cmdptr->opcode != opcode) { 1460 cmdptr++; 1461 } 1462 if (cmdptr->opcode == -1) { 1463 trace_megasas_dcmd_unhandled(cmd->index, opcode, len); 1464 retval = megasas_dcmd_dummy(s, cmd); 1465 } else { 1466 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len); 1467 retval = cmdptr->func(s, cmd); 1468 } 1469 if (retval != MFI_STAT_INVALID_STATUS) { 1470 megasas_finish_dcmd(cmd, len); 1471 } 1472 return retval; 1473 } 1474 1475 static int megasas_finish_internal_dcmd(MegasasCmd *cmd, 1476 SCSIRequest *req) 1477 { 1478 int opcode; 1479 int retval = MFI_STAT_OK; 1480 int lun = req->lun; 1481 1482 opcode = le32_to_cpu(cmd->frame->dcmd.opcode); 1483 scsi_req_unref(req); 1484 trace_megasas_dcmd_internal_finish(cmd->index, opcode, lun); 1485 switch (opcode) { 1486 case MFI_DCMD_PD_GET_INFO: 1487 retval = megasas_pd_get_info_submit(req->dev, lun, cmd); 1488 break; 1489 case MFI_DCMD_LD_GET_INFO: 1490 retval = megasas_ld_get_info_submit(req->dev, lun, cmd); 1491 break; 1492 default: 1493 trace_megasas_dcmd_internal_invalid(cmd->index, opcode); 1494 retval = MFI_STAT_INVALID_DCMD; 1495 break; 1496 } 1497 if (retval != MFI_STAT_INVALID_STATUS) { 1498 megasas_finish_dcmd(cmd, cmd->iov_size); 1499 } 1500 return retval; 1501 } 1502 1503 static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write) 1504 { 1505 int len; 1506 1507 len = scsi_req_enqueue(cmd->req); 1508 if (len < 0) { 1509 len = -len; 1510 } 1511 if (len > 0) { 1512 if (len > cmd->iov_size) { 1513 if (is_write) { 1514 trace_megasas_iov_write_overflow(cmd->index, len, 1515 cmd->iov_size); 1516 } else { 1517 trace_megasas_iov_read_overflow(cmd->index, len, 1518 cmd->iov_size); 1519 } 1520 } 1521 if (len < cmd->iov_size) { 1522 if (is_write) { 1523 trace_megasas_iov_write_underflow(cmd->index, len, 1524 cmd->iov_size); 1525 } else { 1526 trace_megasas_iov_read_underflow(cmd->index, len, 1527 cmd->iov_size); 1528 } 1529 cmd->iov_size = len; 1530 } 1531 scsi_req_continue(cmd->req); 1532 } 1533 return len; 1534 } 1535 1536 static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd, 1537 bool is_logical) 1538 { 1539 uint8_t *cdb; 1540 int len; 1541 bool is_write; 1542 struct SCSIDevice *sdev = NULL; 1543 1544 cdb = cmd->frame->pass.cdb; 1545 1546 if (cmd->frame->header.target_id < s->fw_luns) { 1547 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id, 1548 cmd->frame->header.lun_id); 1549 } 1550 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len); 1551 trace_megasas_handle_scsi(mfi_frame_desc[cmd->frame->header.frame_cmd], 1552 is_logical, cmd->frame->header.target_id, 1553 cmd->frame->header.lun_id, sdev, cmd->iov_size); 1554 1555 if (!sdev || (megasas_is_jbod(s) && is_logical)) { 1556 trace_megasas_scsi_target_not_present( 1557 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical, 1558 cmd->frame->header.target_id, cmd->frame->header.lun_id); 1559 return MFI_STAT_DEVICE_NOT_FOUND; 1560 } 1561 1562 if (cmd->frame->header.cdb_len > 16) { 1563 trace_megasas_scsi_invalid_cdb_len( 1564 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical, 1565 cmd->frame->header.target_id, cmd->frame->header.lun_id, 1566 cmd->frame->header.cdb_len); 1567 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE)); 1568 cmd->frame->header.scsi_status = CHECK_CONDITION; 1569 s->event_count++; 1570 return MFI_STAT_SCSI_DONE_WITH_ERROR; 1571 } 1572 1573 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) { 1574 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE)); 1575 cmd->frame->header.scsi_status = CHECK_CONDITION; 1576 s->event_count++; 1577 return MFI_STAT_SCSI_DONE_WITH_ERROR; 1578 } 1579 1580 cmd->req = scsi_req_new(sdev, cmd->index, 1581 cmd->frame->header.lun_id, cdb, cmd); 1582 if (!cmd->req) { 1583 trace_megasas_scsi_req_alloc_failed( 1584 mfi_frame_desc[cmd->frame->header.frame_cmd], 1585 cmd->frame->header.target_id, cmd->frame->header.lun_id); 1586 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE)); 1587 cmd->frame->header.scsi_status = BUSY; 1588 s->event_count++; 1589 return MFI_STAT_SCSI_DONE_WITH_ERROR; 1590 } 1591 1592 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV); 1593 len = megasas_enqueue_req(cmd, is_write); 1594 if (len > 0) { 1595 if (is_write) { 1596 trace_megasas_scsi_write_start(cmd->index, len); 1597 } else { 1598 trace_megasas_scsi_read_start(cmd->index, len); 1599 } 1600 } else { 1601 trace_megasas_scsi_nodata(cmd->index); 1602 } 1603 return MFI_STAT_INVALID_STATUS; 1604 } 1605 1606 static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd) 1607 { 1608 uint32_t lba_count, lba_start_hi, lba_start_lo; 1609 uint64_t lba_start; 1610 bool is_write = (cmd->frame->header.frame_cmd == MFI_CMD_LD_WRITE); 1611 uint8_t cdb[16]; 1612 int len; 1613 struct SCSIDevice *sdev = NULL; 1614 1615 lba_count = le32_to_cpu(cmd->frame->io.header.data_len); 1616 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo); 1617 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi); 1618 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo; 1619 1620 if (cmd->frame->header.target_id < s->fw_luns) { 1621 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id, 1622 cmd->frame->header.lun_id); 1623 } 1624 1625 trace_megasas_handle_io(cmd->index, 1626 mfi_frame_desc[cmd->frame->header.frame_cmd], 1627 cmd->frame->header.target_id, 1628 cmd->frame->header.lun_id, 1629 (unsigned long)lba_start, (unsigned long)lba_count); 1630 if (!sdev) { 1631 trace_megasas_io_target_not_present(cmd->index, 1632 mfi_frame_desc[cmd->frame->header.frame_cmd], 1633 cmd->frame->header.target_id, cmd->frame->header.lun_id); 1634 return MFI_STAT_DEVICE_NOT_FOUND; 1635 } 1636 1637 if (cmd->frame->header.cdb_len > 16) { 1638 trace_megasas_scsi_invalid_cdb_len( 1639 mfi_frame_desc[cmd->frame->header.frame_cmd], 1, 1640 cmd->frame->header.target_id, cmd->frame->header.lun_id, 1641 cmd->frame->header.cdb_len); 1642 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE)); 1643 cmd->frame->header.scsi_status = CHECK_CONDITION; 1644 s->event_count++; 1645 return MFI_STAT_SCSI_DONE_WITH_ERROR; 1646 } 1647 1648 cmd->iov_size = lba_count * sdev->blocksize; 1649 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) { 1650 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE)); 1651 cmd->frame->header.scsi_status = CHECK_CONDITION; 1652 s->event_count++; 1653 return MFI_STAT_SCSI_DONE_WITH_ERROR; 1654 } 1655 1656 megasas_encode_lba(cdb, lba_start, lba_count, is_write); 1657 cmd->req = scsi_req_new(sdev, cmd->index, 1658 cmd->frame->header.lun_id, cdb, cmd); 1659 if (!cmd->req) { 1660 trace_megasas_scsi_req_alloc_failed( 1661 mfi_frame_desc[cmd->frame->header.frame_cmd], 1662 cmd->frame->header.target_id, cmd->frame->header.lun_id); 1663 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE)); 1664 cmd->frame->header.scsi_status = BUSY; 1665 s->event_count++; 1666 return MFI_STAT_SCSI_DONE_WITH_ERROR; 1667 } 1668 len = megasas_enqueue_req(cmd, is_write); 1669 if (len > 0) { 1670 if (is_write) { 1671 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len); 1672 } else { 1673 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len); 1674 } 1675 } 1676 return MFI_STAT_INVALID_STATUS; 1677 } 1678 1679 static int megasas_finish_internal_command(MegasasCmd *cmd, 1680 SCSIRequest *req, size_t resid) 1681 { 1682 int retval = MFI_STAT_INVALID_CMD; 1683 1684 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) { 1685 cmd->iov_size -= resid; 1686 retval = megasas_finish_internal_dcmd(cmd, req); 1687 } 1688 return retval; 1689 } 1690 1691 static QEMUSGList *megasas_get_sg_list(SCSIRequest *req) 1692 { 1693 MegasasCmd *cmd = req->hba_private; 1694 1695 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) { 1696 return NULL; 1697 } else { 1698 return &cmd->qsg; 1699 } 1700 } 1701 1702 static void megasas_xfer_complete(SCSIRequest *req, uint32_t len) 1703 { 1704 MegasasCmd *cmd = req->hba_private; 1705 uint8_t *buf; 1706 uint32_t opcode; 1707 1708 trace_megasas_io_complete(cmd->index, len); 1709 1710 if (cmd->frame->header.frame_cmd != MFI_CMD_DCMD) { 1711 scsi_req_continue(req); 1712 return; 1713 } 1714 1715 buf = scsi_req_get_buf(req); 1716 opcode = le32_to_cpu(cmd->frame->dcmd.opcode); 1717 if (opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) { 1718 struct mfi_pd_info *info = cmd->iov_buf; 1719 1720 if (info->inquiry_data[0] == 0x7f) { 1721 memset(info->inquiry_data, 0, sizeof(info->inquiry_data)); 1722 memcpy(info->inquiry_data, buf, len); 1723 } else if (info->vpd_page83[0] == 0x7f) { 1724 memset(info->vpd_page83, 0, sizeof(info->vpd_page83)); 1725 memcpy(info->vpd_page83, buf, len); 1726 } 1727 scsi_req_continue(req); 1728 } else if (opcode == MFI_DCMD_LD_GET_INFO) { 1729 struct mfi_ld_info *info = cmd->iov_buf; 1730 1731 if (cmd->iov_buf) { 1732 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83)); 1733 scsi_req_continue(req); 1734 } 1735 } 1736 } 1737 1738 static void megasas_command_complete(SCSIRequest *req, uint32_t status, 1739 size_t resid) 1740 { 1741 MegasasCmd *cmd = req->hba_private; 1742 uint8_t cmd_status = MFI_STAT_OK; 1743 1744 trace_megasas_command_complete(cmd->index, status, resid); 1745 1746 if (cmd->req != req) { 1747 /* 1748 * Internal command complete 1749 */ 1750 cmd_status = megasas_finish_internal_command(cmd, req, resid); 1751 if (cmd_status == MFI_STAT_INVALID_STATUS) { 1752 return; 1753 } 1754 } else { 1755 req->status = status; 1756 trace_megasas_scsi_complete(cmd->index, req->status, 1757 cmd->iov_size, req->cmd.xfer); 1758 if (req->status != GOOD) { 1759 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR; 1760 } 1761 if (req->status == CHECK_CONDITION) { 1762 megasas_copy_sense(cmd); 1763 } 1764 1765 megasas_unmap_sgl(cmd); 1766 cmd->frame->header.scsi_status = req->status; 1767 scsi_req_unref(cmd->req); 1768 cmd->req = NULL; 1769 } 1770 cmd->frame->header.cmd_status = cmd_status; 1771 megasas_complete_frame(cmd->state, cmd->context); 1772 } 1773 1774 static void megasas_command_cancel(SCSIRequest *req) 1775 { 1776 MegasasCmd *cmd = req->hba_private; 1777 1778 if (cmd) { 1779 megasas_abort_command(cmd); 1780 } else { 1781 scsi_req_unref(req); 1782 } 1783 } 1784 1785 static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd) 1786 { 1787 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context); 1788 hwaddr abort_addr, addr_hi, addr_lo; 1789 MegasasCmd *abort_cmd; 1790 1791 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi); 1792 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo); 1793 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo; 1794 1795 abort_cmd = megasas_lookup_frame(s, abort_addr); 1796 if (!abort_cmd) { 1797 trace_megasas_abort_no_cmd(cmd->index, abort_ctx); 1798 s->event_count++; 1799 return MFI_STAT_OK; 1800 } 1801 if (!megasas_use_queue64(s)) { 1802 abort_ctx &= (uint64_t)0xFFFFFFFF; 1803 } 1804 if (abort_cmd->context != abort_ctx) { 1805 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->index, 1806 abort_cmd->context); 1807 s->event_count++; 1808 return MFI_STAT_ABORT_NOT_POSSIBLE; 1809 } 1810 trace_megasas_abort_frame(cmd->index, abort_cmd->index); 1811 megasas_abort_command(abort_cmd); 1812 if (!s->event_cmd || abort_cmd != s->event_cmd) { 1813 s->event_cmd = NULL; 1814 } 1815 s->event_count++; 1816 return MFI_STAT_OK; 1817 } 1818 1819 static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr, 1820 uint32_t frame_count) 1821 { 1822 uint8_t frame_status = MFI_STAT_INVALID_CMD; 1823 uint64_t frame_context; 1824 MegasasCmd *cmd; 1825 1826 /* 1827 * Always read 64bit context, top bits will be 1828 * masked out if required in megasas_enqueue_frame() 1829 */ 1830 frame_context = megasas_frame_get_context(frame_addr); 1831 1832 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count); 1833 if (!cmd) { 1834 /* reply queue full */ 1835 trace_megasas_frame_busy(frame_addr); 1836 megasas_frame_set_scsi_status(frame_addr, BUSY); 1837 megasas_frame_set_cmd_status(frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR); 1838 megasas_complete_frame(s, frame_context); 1839 s->event_count++; 1840 return; 1841 } 1842 switch (cmd->frame->header.frame_cmd) { 1843 case MFI_CMD_INIT: 1844 frame_status = megasas_init_firmware(s, cmd); 1845 break; 1846 case MFI_CMD_DCMD: 1847 frame_status = megasas_handle_dcmd(s, cmd); 1848 break; 1849 case MFI_CMD_ABORT: 1850 frame_status = megasas_handle_abort(s, cmd); 1851 break; 1852 case MFI_CMD_PD_SCSI_IO: 1853 frame_status = megasas_handle_scsi(s, cmd, 0); 1854 break; 1855 case MFI_CMD_LD_SCSI_IO: 1856 frame_status = megasas_handle_scsi(s, cmd, 1); 1857 break; 1858 case MFI_CMD_LD_READ: 1859 case MFI_CMD_LD_WRITE: 1860 frame_status = megasas_handle_io(s, cmd); 1861 break; 1862 default: 1863 trace_megasas_unhandled_frame_cmd(cmd->index, 1864 cmd->frame->header.frame_cmd); 1865 s->event_count++; 1866 break; 1867 } 1868 if (frame_status != MFI_STAT_INVALID_STATUS) { 1869 if (cmd->frame) { 1870 cmd->frame->header.cmd_status = frame_status; 1871 } else { 1872 megasas_frame_set_cmd_status(frame_addr, frame_status); 1873 } 1874 megasas_complete_frame(s, cmd->context); 1875 } 1876 } 1877 1878 static uint64_t megasas_mmio_read(void *opaque, hwaddr addr, 1879 unsigned size) 1880 { 1881 MegasasState *s = opaque; 1882 uint32_t retval = 0; 1883 1884 switch (addr) { 1885 case MFI_IDB: 1886 retval = 0; 1887 break; 1888 case MFI_OMSG0: 1889 case MFI_OSP0: 1890 retval = (megasas_use_msix(s) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) | 1891 (s->fw_state & MFI_FWSTATE_MASK) | 1892 ((s->fw_sge & 0xff) << 16) | 1893 (s->fw_cmds & 0xFFFF); 1894 break; 1895 case MFI_OSTS: 1896 if (megasas_intr_enabled(s) && s->doorbell) { 1897 retval = MFI_1078_RM | 1; 1898 } 1899 break; 1900 case MFI_OMSK: 1901 retval = s->intr_mask; 1902 break; 1903 case MFI_ODCR0: 1904 retval = s->doorbell; 1905 break; 1906 default: 1907 trace_megasas_mmio_invalid_readl(addr); 1908 break; 1909 } 1910 trace_megasas_mmio_readl(addr, retval); 1911 return retval; 1912 } 1913 1914 static void megasas_mmio_write(void *opaque, hwaddr addr, 1915 uint64_t val, unsigned size) 1916 { 1917 MegasasState *s = opaque; 1918 PCIDevice *pci_dev = PCI_DEVICE(s); 1919 uint64_t frame_addr; 1920 uint32_t frame_count; 1921 int i; 1922 1923 trace_megasas_mmio_writel(addr, val); 1924 switch (addr) { 1925 case MFI_IDB: 1926 if (val & MFI_FWINIT_ABORT) { 1927 /* Abort all pending cmds */ 1928 for (i = 0; i < s->fw_cmds; i++) { 1929 megasas_abort_command(&s->frames[i]); 1930 } 1931 } 1932 if (val & MFI_FWINIT_READY) { 1933 /* move to FW READY */ 1934 megasas_soft_reset(s); 1935 } 1936 if (val & MFI_FWINIT_MFIMODE) { 1937 /* discard MFIs */ 1938 } 1939 break; 1940 case MFI_OMSK: 1941 s->intr_mask = val; 1942 if (!megasas_intr_enabled(s) && !msix_enabled(pci_dev)) { 1943 trace_megasas_irq_lower(); 1944 pci_irq_deassert(pci_dev); 1945 } 1946 if (megasas_intr_enabled(s)) { 1947 trace_megasas_intr_enabled(); 1948 } else { 1949 trace_megasas_intr_disabled(); 1950 } 1951 break; 1952 case MFI_ODCR0: 1953 s->doorbell = 0; 1954 if (s->producer_pa && megasas_intr_enabled(s)) { 1955 /* Update reply queue pointer */ 1956 trace_megasas_qf_update(s->reply_queue_head, s->busy); 1957 stl_le_phys(&address_space_memory, 1958 s->producer_pa, s->reply_queue_head); 1959 if (!msix_enabled(pci_dev)) { 1960 trace_megasas_irq_lower(); 1961 pci_irq_deassert(pci_dev); 1962 } 1963 } 1964 break; 1965 case MFI_IQPH: 1966 /* Received high 32 bits of a 64 bit MFI frame address */ 1967 s->frame_hi = val; 1968 break; 1969 case MFI_IQPL: 1970 /* Received low 32 bits of a 64 bit MFI frame address */ 1971 case MFI_IQP: 1972 /* Received 32 bit MFI frame address */ 1973 frame_addr = (val & ~0x1F); 1974 /* Add possible 64 bit offset */ 1975 frame_addr |= ((uint64_t)s->frame_hi << 32); 1976 s->frame_hi = 0; 1977 frame_count = (val >> 1) & 0xF; 1978 megasas_handle_frame(s, frame_addr, frame_count); 1979 break; 1980 default: 1981 trace_megasas_mmio_invalid_writel(addr, val); 1982 break; 1983 } 1984 } 1985 1986 static const MemoryRegionOps megasas_mmio_ops = { 1987 .read = megasas_mmio_read, 1988 .write = megasas_mmio_write, 1989 .endianness = DEVICE_LITTLE_ENDIAN, 1990 .impl = { 1991 .min_access_size = 8, 1992 .max_access_size = 8, 1993 } 1994 }; 1995 1996 static uint64_t megasas_port_read(void *opaque, hwaddr addr, 1997 unsigned size) 1998 { 1999 return megasas_mmio_read(opaque, addr & 0xff, size); 2000 } 2001 2002 static void megasas_port_write(void *opaque, hwaddr addr, 2003 uint64_t val, unsigned size) 2004 { 2005 megasas_mmio_write(opaque, addr & 0xff, val, size); 2006 } 2007 2008 static const MemoryRegionOps megasas_port_ops = { 2009 .read = megasas_port_read, 2010 .write = megasas_port_write, 2011 .endianness = DEVICE_LITTLE_ENDIAN, 2012 .impl = { 2013 .min_access_size = 4, 2014 .max_access_size = 4, 2015 } 2016 }; 2017 2018 static uint64_t megasas_queue_read(void *opaque, hwaddr addr, 2019 unsigned size) 2020 { 2021 return 0; 2022 } 2023 2024 static const MemoryRegionOps megasas_queue_ops = { 2025 .read = megasas_queue_read, 2026 .endianness = DEVICE_LITTLE_ENDIAN, 2027 .impl = { 2028 .min_access_size = 8, 2029 .max_access_size = 8, 2030 } 2031 }; 2032 2033 static void megasas_soft_reset(MegasasState *s) 2034 { 2035 int i; 2036 MegasasCmd *cmd; 2037 2038 trace_megasas_reset(); 2039 for (i = 0; i < s->fw_cmds; i++) { 2040 cmd = &s->frames[i]; 2041 megasas_abort_command(cmd); 2042 } 2043 megasas_reset_frames(s); 2044 s->reply_queue_len = s->fw_cmds; 2045 s->reply_queue_pa = 0; 2046 s->consumer_pa = 0; 2047 s->producer_pa = 0; 2048 s->fw_state = MFI_FWSTATE_READY; 2049 s->doorbell = 0; 2050 s->intr_mask = MEGASAS_INTR_DISABLED_MASK; 2051 s->frame_hi = 0; 2052 s->flags &= ~MEGASAS_MASK_USE_QUEUE64; 2053 s->event_count++; 2054 s->boot_event = s->event_count; 2055 } 2056 2057 static void megasas_scsi_reset(DeviceState *dev) 2058 { 2059 MegasasState *s = MEGASAS(dev); 2060 2061 megasas_soft_reset(s); 2062 } 2063 2064 static const VMStateDescription vmstate_megasas = { 2065 .name = "megasas", 2066 .version_id = 0, 2067 .minimum_version_id = 0, 2068 .minimum_version_id_old = 0, 2069 .fields = (VMStateField[]) { 2070 VMSTATE_PCI_DEVICE(parent_obj, MegasasState), 2071 2072 VMSTATE_INT32(fw_state, MegasasState), 2073 VMSTATE_INT32(intr_mask, MegasasState), 2074 VMSTATE_INT32(doorbell, MegasasState), 2075 VMSTATE_UINT64(reply_queue_pa, MegasasState), 2076 VMSTATE_UINT64(consumer_pa, MegasasState), 2077 VMSTATE_UINT64(producer_pa, MegasasState), 2078 VMSTATE_END_OF_LIST() 2079 } 2080 }; 2081 2082 static void megasas_scsi_uninit(PCIDevice *d) 2083 { 2084 MegasasState *s = MEGASAS(d); 2085 2086 #ifdef USE_MSIX 2087 msix_uninit(d, &s->mmio_io); 2088 #endif 2089 memory_region_destroy(&s->mmio_io); 2090 memory_region_destroy(&s->port_io); 2091 memory_region_destroy(&s->queue_io); 2092 } 2093 2094 static const struct SCSIBusInfo megasas_scsi_info = { 2095 .tcq = true, 2096 .max_target = MFI_MAX_LD, 2097 .max_lun = 255, 2098 2099 .transfer_data = megasas_xfer_complete, 2100 .get_sg_list = megasas_get_sg_list, 2101 .complete = megasas_command_complete, 2102 .cancel = megasas_command_cancel, 2103 }; 2104 2105 static int megasas_scsi_init(PCIDevice *dev) 2106 { 2107 DeviceState *d = DEVICE(dev); 2108 MegasasState *s = MEGASAS(dev); 2109 uint8_t *pci_conf; 2110 int i, bar_type; 2111 Error *err = NULL; 2112 2113 pci_conf = dev->config; 2114 2115 /* PCI latency timer = 0 */ 2116 pci_conf[PCI_LATENCY_TIMER] = 0; 2117 /* Interrupt pin 1 */ 2118 pci_conf[PCI_INTERRUPT_PIN] = 0x01; 2119 2120 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s, 2121 "megasas-mmio", 0x4000); 2122 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s, 2123 "megasas-io", 256); 2124 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s, 2125 "megasas-queue", 0x40000); 2126 2127 #ifdef USE_MSIX 2128 /* MSI-X support is currently broken */ 2129 if (megasas_use_msix(s) && 2130 msix_init(dev, 15, &s->mmio_io, 0, 0x2000)) { 2131 s->flags &= ~MEGASAS_MASK_USE_MSIX; 2132 } 2133 #else 2134 s->flags &= ~MEGASAS_MASK_USE_MSIX; 2135 #endif 2136 2137 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64; 2138 pci_register_bar(dev, 0, bar_type, &s->mmio_io); 2139 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &s->port_io); 2140 pci_register_bar(dev, 3, bar_type, &s->queue_io); 2141 2142 if (megasas_use_msix(s)) { 2143 msix_vector_use(dev, 0); 2144 } 2145 2146 if (!s->sas_addr) { 2147 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) | 2148 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36; 2149 s->sas_addr |= (pci_bus_num(dev->bus) << 16); 2150 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8); 2151 s->sas_addr |= PCI_FUNC(dev->devfn); 2152 } 2153 if (!s->hba_serial) { 2154 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL); 2155 } 2156 if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) { 2157 s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE; 2158 } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) { 2159 s->fw_sge = 128 - MFI_PASS_FRAME_SIZE; 2160 } else { 2161 s->fw_sge = 64 - MFI_PASS_FRAME_SIZE; 2162 } 2163 if (s->fw_cmds > MEGASAS_MAX_FRAMES) { 2164 s->fw_cmds = MEGASAS_MAX_FRAMES; 2165 } 2166 trace_megasas_init(s->fw_sge, s->fw_cmds, 2167 megasas_use_msix(s) ? "MSI-X" : "INTx", 2168 megasas_is_jbod(s) ? "jbod" : "raid"); 2169 s->fw_luns = (MFI_MAX_LD > MAX_SCSI_DEVS) ? 2170 MAX_SCSI_DEVS : MFI_MAX_LD; 2171 s->producer_pa = 0; 2172 s->consumer_pa = 0; 2173 for (i = 0; i < s->fw_cmds; i++) { 2174 s->frames[i].index = i; 2175 s->frames[i].context = -1; 2176 s->frames[i].pa = 0; 2177 s->frames[i].state = s; 2178 } 2179 2180 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev), 2181 &megasas_scsi_info, NULL); 2182 if (!d->hotplugged) { 2183 scsi_bus_legacy_handle_cmdline(&s->bus, &err); 2184 if (err != NULL) { 2185 error_free(err); 2186 return -1; 2187 } 2188 } 2189 return 0; 2190 } 2191 2192 static Property megasas_properties[] = { 2193 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge, 2194 MEGASAS_DEFAULT_SGE), 2195 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds, 2196 MEGASAS_DEFAULT_FRAMES), 2197 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial), 2198 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0), 2199 #ifdef USE_MSIX 2200 DEFINE_PROP_BIT("use_msix", MegasasState, flags, 2201 MEGASAS_FLAG_USE_MSIX, false), 2202 #endif 2203 DEFINE_PROP_BIT("use_jbod", MegasasState, flags, 2204 MEGASAS_FLAG_USE_JBOD, false), 2205 DEFINE_PROP_END_OF_LIST(), 2206 }; 2207 2208 static void megasas_class_init(ObjectClass *oc, void *data) 2209 { 2210 DeviceClass *dc = DEVICE_CLASS(oc); 2211 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc); 2212 2213 pc->init = megasas_scsi_init; 2214 pc->exit = megasas_scsi_uninit; 2215 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC; 2216 pc->device_id = PCI_DEVICE_ID_LSI_SAS1078; 2217 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC; 2218 pc->subsystem_id = 0x1013; 2219 pc->class_id = PCI_CLASS_STORAGE_RAID; 2220 dc->props = megasas_properties; 2221 dc->reset = megasas_scsi_reset; 2222 dc->vmsd = &vmstate_megasas; 2223 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2224 dc->desc = "LSI MegaRAID SAS 1078"; 2225 } 2226 2227 static const TypeInfo megasas_info = { 2228 .name = TYPE_MEGASAS, 2229 .parent = TYPE_PCI_DEVICE, 2230 .instance_size = sizeof(MegasasState), 2231 .class_init = megasas_class_init, 2232 }; 2233 2234 static void megasas_register_types(void) 2235 { 2236 type_register_static(&megasas_info); 2237 } 2238 2239 type_init(megasas_register_types) 2240