1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/pci/pci.h" 28 #include "hw/irq.h" 29 #include "hw/nvram/eeprom93xx.h" 30 #include "hw/scsi/esp.h" 31 #include "migration/vmstate.h" 32 #include "trace.h" 33 #include "qapi/error.h" 34 #include "qemu/log.h" 35 #include "qemu/module.h" 36 37 #define TYPE_AM53C974_DEVICE "am53c974" 38 39 #define PCI_ESP(obj) \ 40 OBJECT_CHECK(PCIESPState, (obj), TYPE_AM53C974_DEVICE) 41 42 #define DMA_CMD 0x0 43 #define DMA_STC 0x1 44 #define DMA_SPA 0x2 45 #define DMA_WBC 0x3 46 #define DMA_WAC 0x4 47 #define DMA_STAT 0x5 48 #define DMA_SMDLA 0x6 49 #define DMA_WMAC 0x7 50 51 #define DMA_CMD_MASK 0x03 52 #define DMA_CMD_DIAG 0x04 53 #define DMA_CMD_MDL 0x10 54 #define DMA_CMD_INTE_P 0x20 55 #define DMA_CMD_INTE_D 0x40 56 #define DMA_CMD_DIR 0x80 57 58 #define DMA_STAT_PWDN 0x01 59 #define DMA_STAT_ERROR 0x02 60 #define DMA_STAT_ABORT 0x04 61 #define DMA_STAT_DONE 0x08 62 #define DMA_STAT_SCSIINT 0x10 63 #define DMA_STAT_BCMBLT 0x20 64 65 #define SBAC_STATUS (1 << 24) 66 67 typedef struct PCIESPState { 68 /*< private >*/ 69 PCIDevice parent_obj; 70 /*< public >*/ 71 72 MemoryRegion io; 73 uint32_t dma_regs[8]; 74 uint32_t sbac; 75 ESPState esp; 76 } PCIESPState; 77 78 static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val) 79 { 80 trace_esp_pci_dma_idle(val); 81 esp_dma_enable(&pci->esp, 0, 0); 82 } 83 84 static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val) 85 { 86 trace_esp_pci_dma_blast(val); 87 qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n"); 88 } 89 90 static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val) 91 { 92 trace_esp_pci_dma_abort(val); 93 if (pci->esp.current_req) { 94 scsi_req_cancel(pci->esp.current_req); 95 } 96 } 97 98 static void esp_pci_handle_start(PCIESPState *pci, uint32_t val) 99 { 100 trace_esp_pci_dma_start(val); 101 102 pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC]; 103 pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA]; 104 pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA]; 105 106 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT 107 | DMA_STAT_DONE | DMA_STAT_ABORT 108 | DMA_STAT_ERROR | DMA_STAT_PWDN); 109 110 esp_dma_enable(&pci->esp, 0, 1); 111 } 112 113 static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val) 114 { 115 trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val); 116 switch (saddr) { 117 case DMA_CMD: 118 pci->dma_regs[saddr] = val; 119 switch (val & DMA_CMD_MASK) { 120 case 0x0: /* IDLE */ 121 esp_pci_handle_idle(pci, val); 122 break; 123 case 0x1: /* BLAST */ 124 esp_pci_handle_blast(pci, val); 125 break; 126 case 0x2: /* ABORT */ 127 esp_pci_handle_abort(pci, val); 128 break; 129 case 0x3: /* START */ 130 esp_pci_handle_start(pci, val); 131 break; 132 default: /* can't happen */ 133 abort(); 134 } 135 break; 136 case DMA_STC: 137 case DMA_SPA: 138 case DMA_SMDLA: 139 pci->dma_regs[saddr] = val; 140 break; 141 case DMA_STAT: 142 if (pci->sbac & SBAC_STATUS) { 143 /* clear some bits on write */ 144 uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE; 145 pci->dma_regs[DMA_STAT] &= ~(val & mask); 146 } 147 break; 148 default: 149 trace_esp_pci_error_invalid_write_dma(val, saddr); 150 return; 151 } 152 } 153 154 static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr) 155 { 156 uint32_t val; 157 158 val = pci->dma_regs[saddr]; 159 if (saddr == DMA_STAT) { 160 if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) { 161 val |= DMA_STAT_SCSIINT; 162 } 163 if (!(pci->sbac & SBAC_STATUS)) { 164 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT | 165 DMA_STAT_DONE); 166 } 167 } 168 169 trace_esp_pci_dma_read(saddr, val); 170 return val; 171 } 172 173 static void esp_pci_io_write(void *opaque, hwaddr addr, 174 uint64_t val, unsigned int size) 175 { 176 PCIESPState *pci = opaque; 177 178 if (size < 4 || addr & 3) { 179 /* need to upgrade request: we only support 4-bytes accesses */ 180 uint32_t current = 0, mask; 181 int shift; 182 183 if (addr < 0x40) { 184 current = pci->esp.wregs[addr >> 2]; 185 } else if (addr < 0x60) { 186 current = pci->dma_regs[(addr - 0x40) >> 2]; 187 } else if (addr < 0x74) { 188 current = pci->sbac; 189 } 190 191 shift = (4 - size) * 8; 192 mask = (~(uint32_t)0 << shift) >> shift; 193 194 shift = ((4 - (addr & 3)) & 3) * 8; 195 val <<= shift; 196 val |= current & ~(mask << shift); 197 addr &= ~3; 198 size = 4; 199 } 200 g_assert(size >= 4); 201 202 if (addr < 0x40) { 203 /* SCSI core reg */ 204 esp_reg_write(&pci->esp, addr >> 2, val); 205 } else if (addr < 0x60) { 206 /* PCI DMA CCB */ 207 esp_pci_dma_write(pci, (addr - 0x40) >> 2, val); 208 } else if (addr == 0x70) { 209 /* DMA SCSI Bus and control */ 210 trace_esp_pci_sbac_write(pci->sbac, val); 211 pci->sbac = val; 212 } else { 213 trace_esp_pci_error_invalid_write((int)addr); 214 } 215 } 216 217 static uint64_t esp_pci_io_read(void *opaque, hwaddr addr, 218 unsigned int size) 219 { 220 PCIESPState *pci = opaque; 221 uint32_t ret; 222 223 if (addr < 0x40) { 224 /* SCSI core reg */ 225 ret = esp_reg_read(&pci->esp, addr >> 2); 226 } else if (addr < 0x60) { 227 /* PCI DMA CCB */ 228 ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2); 229 } else if (addr == 0x70) { 230 /* DMA SCSI Bus and control */ 231 trace_esp_pci_sbac_read(pci->sbac); 232 ret = pci->sbac; 233 } else { 234 /* Invalid region */ 235 trace_esp_pci_error_invalid_read((int)addr); 236 ret = 0; 237 } 238 239 /* give only requested data */ 240 ret >>= (addr & 3) * 8; 241 ret &= ~(~(uint64_t)0 << (8 * size)); 242 243 return ret; 244 } 245 246 static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len, 247 DMADirection dir) 248 { 249 dma_addr_t addr; 250 DMADirection expected_dir; 251 252 if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) { 253 expected_dir = DMA_DIRECTION_FROM_DEVICE; 254 } else { 255 expected_dir = DMA_DIRECTION_TO_DEVICE; 256 } 257 258 if (dir != expected_dir) { 259 trace_esp_pci_error_invalid_dma_direction(); 260 return; 261 } 262 263 if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) { 264 qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n"); 265 } 266 267 addr = pci->dma_regs[DMA_SPA]; 268 if (pci->dma_regs[DMA_WBC] < len) { 269 len = pci->dma_regs[DMA_WBC]; 270 } 271 272 pci_dma_rw(PCI_DEVICE(pci), addr, buf, len, dir); 273 274 /* update status registers */ 275 pci->dma_regs[DMA_WBC] -= len; 276 pci->dma_regs[DMA_WAC] += len; 277 if (pci->dma_regs[DMA_WBC] == 0) { 278 pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE; 279 } 280 } 281 282 static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len) 283 { 284 PCIESPState *pci = opaque; 285 esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE); 286 } 287 288 static void esp_pci_dma_memory_write(void *opaque, uint8_t *buf, int len) 289 { 290 PCIESPState *pci = opaque; 291 esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE); 292 } 293 294 static const MemoryRegionOps esp_pci_io_ops = { 295 .read = esp_pci_io_read, 296 .write = esp_pci_io_write, 297 .endianness = DEVICE_LITTLE_ENDIAN, 298 .impl = { 299 .min_access_size = 1, 300 .max_access_size = 4, 301 }, 302 }; 303 304 static void esp_pci_hard_reset(DeviceState *dev) 305 { 306 PCIESPState *pci = PCI_ESP(dev); 307 esp_hard_reset(&pci->esp); 308 pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_INTE_P 309 | DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK); 310 pci->dma_regs[DMA_WBC] &= ~0xffff; 311 pci->dma_regs[DMA_WAC] = 0xffffffff; 312 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT 313 | DMA_STAT_DONE | DMA_STAT_ABORT 314 | DMA_STAT_ERROR); 315 pci->dma_regs[DMA_WMAC] = 0xfffffffd; 316 } 317 318 static const VMStateDescription vmstate_esp_pci_scsi = { 319 .name = "pciespscsi", 320 .version_id = 1, 321 .minimum_version_id = 1, 322 .fields = (VMStateField[]) { 323 VMSTATE_PCI_DEVICE(parent_obj, PCIESPState), 324 VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)), 325 VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState), 326 VMSTATE_END_OF_LIST() 327 } 328 }; 329 330 static void esp_pci_command_complete(SCSIRequest *req, uint32_t status, 331 size_t resid) 332 { 333 ESPState *s = req->hba_private; 334 PCIESPState *pci = container_of(s, PCIESPState, esp); 335 336 esp_command_complete(req, status, resid); 337 pci->dma_regs[DMA_WBC] = 0; 338 pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE; 339 } 340 341 static const struct SCSIBusInfo esp_pci_scsi_info = { 342 .tcq = false, 343 .max_target = ESP_MAX_DEVS, 344 .max_lun = 7, 345 346 .transfer_data = esp_transfer_data, 347 .complete = esp_pci_command_complete, 348 .cancel = esp_request_cancelled, 349 }; 350 351 static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp) 352 { 353 PCIESPState *pci = PCI_ESP(dev); 354 DeviceState *d = DEVICE(dev); 355 ESPState *s = &pci->esp; 356 uint8_t *pci_conf; 357 358 pci_conf = dev->config; 359 360 /* Interrupt pin A */ 361 pci_conf[PCI_INTERRUPT_PIN] = 0x01; 362 363 s->dma_memory_read = esp_pci_dma_memory_read; 364 s->dma_memory_write = esp_pci_dma_memory_write; 365 s->dma_opaque = pci; 366 s->chip_id = TCHI_AM53C974; 367 memory_region_init_io(&pci->io, OBJECT(pci), &esp_pci_io_ops, pci, 368 "esp-io", 0x80); 369 370 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io); 371 s->irq = pci_allocate_irq(dev); 372 373 scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL); 374 } 375 376 static void esp_pci_scsi_uninit(PCIDevice *d) 377 { 378 PCIESPState *pci = PCI_ESP(d); 379 380 qemu_free_irq(pci->esp.irq); 381 } 382 383 static void esp_pci_class_init(ObjectClass *klass, void *data) 384 { 385 DeviceClass *dc = DEVICE_CLASS(klass); 386 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 387 388 k->realize = esp_pci_scsi_realize; 389 k->exit = esp_pci_scsi_uninit; 390 k->vendor_id = PCI_VENDOR_ID_AMD; 391 k->device_id = PCI_DEVICE_ID_AMD_SCSI; 392 k->revision = 0x10; 393 k->class_id = PCI_CLASS_STORAGE_SCSI; 394 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 395 dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter"; 396 dc->reset = esp_pci_hard_reset; 397 dc->vmsd = &vmstate_esp_pci_scsi; 398 } 399 400 static const TypeInfo esp_pci_info = { 401 .name = TYPE_AM53C974_DEVICE, 402 .parent = TYPE_PCI_DEVICE, 403 .instance_size = sizeof(PCIESPState), 404 .class_init = esp_pci_class_init, 405 .interfaces = (InterfaceInfo[]) { 406 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 407 { }, 408 }, 409 }; 410 411 typedef struct { 412 PCIESPState pci; 413 eeprom_t *eeprom; 414 } DC390State; 415 416 #define TYPE_DC390_DEVICE "dc390" 417 #define DC390(obj) \ 418 OBJECT_CHECK(DC390State, obj, TYPE_DC390_DEVICE) 419 420 #define EE_ADAPT_SCSI_ID 64 421 #define EE_MODE2 65 422 #define EE_DELAY 66 423 #define EE_TAG_CMD_NUM 67 424 #define EE_ADAPT_OPTIONS 68 425 #define EE_BOOT_SCSI_ID 69 426 #define EE_BOOT_SCSI_LUN 70 427 #define EE_CHKSUM1 126 428 #define EE_CHKSUM2 127 429 430 #define EE_ADAPT_OPTION_F6_F8_AT_BOOT 0x01 431 #define EE_ADAPT_OPTION_BOOT_FROM_CDROM 0x02 432 #define EE_ADAPT_OPTION_INT13 0x04 433 #define EE_ADAPT_OPTION_SCAM_SUPPORT 0x08 434 435 436 static uint32_t dc390_read_config(PCIDevice *dev, uint32_t addr, int l) 437 { 438 DC390State *pci = DC390(dev); 439 uint32_t val; 440 441 val = pci_default_read_config(dev, addr, l); 442 443 if (addr == 0x00 && l == 1) { 444 /* First byte of address space is AND-ed with EEPROM DO line */ 445 if (!eeprom93xx_read(pci->eeprom)) { 446 val &= ~0xff; 447 } 448 } 449 450 return val; 451 } 452 453 static void dc390_write_config(PCIDevice *dev, 454 uint32_t addr, uint32_t val, int l) 455 { 456 DC390State *pci = DC390(dev); 457 if (addr == 0x80) { 458 /* EEPROM write */ 459 int eesk = val & 0x80 ? 1 : 0; 460 int eedi = val & 0x40 ? 1 : 0; 461 eeprom93xx_write(pci->eeprom, 1, eesk, eedi); 462 } else if (addr == 0xc0) { 463 /* EEPROM CS low */ 464 eeprom93xx_write(pci->eeprom, 0, 0, 0); 465 } else { 466 pci_default_write_config(dev, addr, val, l); 467 } 468 } 469 470 static void dc390_scsi_realize(PCIDevice *dev, Error **errp) 471 { 472 DC390State *pci = DC390(dev); 473 Error *err = NULL; 474 uint8_t *contents; 475 uint16_t chksum = 0; 476 int i; 477 478 /* init base class */ 479 esp_pci_scsi_realize(dev, &err); 480 if (err) { 481 error_propagate(errp, err); 482 return; 483 } 484 485 /* EEPROM */ 486 pci->eeprom = eeprom93xx_new(DEVICE(dev), 64); 487 488 /* set default eeprom values */ 489 contents = (uint8_t *)eeprom93xx_data(pci->eeprom); 490 491 for (i = 0; i < 16; i++) { 492 contents[i * 2] = 0x57; 493 contents[i * 2 + 1] = 0x00; 494 } 495 contents[EE_ADAPT_SCSI_ID] = 7; 496 contents[EE_MODE2] = 0x0f; 497 contents[EE_TAG_CMD_NUM] = 0x04; 498 contents[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT 499 | EE_ADAPT_OPTION_BOOT_FROM_CDROM 500 | EE_ADAPT_OPTION_INT13; 501 502 /* update eeprom checksum */ 503 for (i = 0; i < EE_CHKSUM1; i += 2) { 504 chksum += contents[i] + (((uint16_t)contents[i + 1]) << 8); 505 } 506 chksum = 0x1234 - chksum; 507 contents[EE_CHKSUM1] = chksum & 0xff; 508 contents[EE_CHKSUM2] = chksum >> 8; 509 } 510 511 static void dc390_class_init(ObjectClass *klass, void *data) 512 { 513 DeviceClass *dc = DEVICE_CLASS(klass); 514 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 515 516 k->realize = dc390_scsi_realize; 517 k->config_read = dc390_read_config; 518 k->config_write = dc390_write_config; 519 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 520 dc->desc = "Tekram DC-390 SCSI adapter"; 521 } 522 523 static const TypeInfo dc390_info = { 524 .name = "dc390", 525 .parent = TYPE_AM53C974_DEVICE, 526 .instance_size = sizeof(DC390State), 527 .class_init = dc390_class_init, 528 }; 529 530 static void esp_pci_register_types(void) 531 { 532 type_register_static(&esp_pci_info); 533 type_register_static(&dc390_info); 534 } 535 536 type_init(esp_pci_register_types) 537